A task bypass method based on absolute physical rules

Abstract

This invention discloses a task dispatch method based on absolute physical rules, applied to a heterogeneous processing system containing both high- and low-power dual arithmetic units. The core scheme involves a pure hardware detection circuit acquiring the physical characteristic parameters of the task to be executed. When the physical characteristic parameters meet preset absolute physical rules, the task is bypassed and executed by the low-power second arithmetic unit, while the high-power first arithmetic unit remains dormant. The rule determination relies solely on the independent physical characteristics of the current task, and the entire process is executed by pure hardware circuitry without software instruction intervention. This invention solves the problems of high latency, high computational power consumption, and high patent risk associated with existing software task scheduling, achieving low-power execution of small tasks, significantly reducing overall system power consumption, and ensuring complete autonomy and controllability.

Description

Technical Field

[0001] This invention relates to the field of heterogeneous computing and power management technology, and in particular to a task bypass method based on absolute physical rules for parallel computing processing chips applied to large-scale parallel computing clusters. Background Technology

[0002] In massively parallel computing inference tasks, over 30% of the tasks are lightweight computational tasks such as small-sized operators, filling, and outlier handling. These tasks require minimal computing resources but need to wake up the entire high-power parallel computing core for execution, resulting in over 90% of power consumption being wasted. This is one of the core reasons for the low energy efficiency of computing cluster chips. Existing task scheduling schemes generally suffer from the following core defects: 1. High software scheduling latency and high computational resource consumption: Existing task offloading and bypass scheduling are all executed by host-side software or chip firmware, with scheduling latency of tens of microseconds, which cannot be adapted to the microsecond-level execution cycle of small tasks. At the same time, the scheduling process consumes a large amount of core computing resources, further reducing the effective computing power utilization. 2. High patent risk due to reliance on complex graph analysis and contextual dependencies: The core of existing intelligent task scheduling solutions is a scheduling algorithm based on computational graph analysis and multi-task contextual dependencies. Patent layout in this field is highly concentrated, and leading manufacturers have formed complete patent barriers. Independent solutions are very likely to trigger patent infringement risks and cannot achieve commercial application. 3. The scheduling logic is easily tampered with and has poor stability: the software scheduling path is easily tampered with or bypassed by malicious programs, which can lead to abnormal task scheduling, abnormal chip power consumption, business errors, or even system crashes. 4. Lack of hardware pass-through and bypass, resulting in significant waste of power consumption: Even for invalid filling tasks, existing solutions still require waking up at least some computing cores to execute, making it impossible to achieve pure hardware pass-through and bypass, and thus the waste power consumption cannot be completely eliminated.

[0003] Currently, some hardware-assisted task scheduling solutions have emerged in the industry, but the core scheduling decisions are still made by software algorithms, which cannot fundamentally solve the above-mentioned defects, and there is still a serious risk of patent infringement. Summary of the Invention

[0004] I. Technical problems to be solved The purpose of this invention is to overcome the above-mentioned defects of the prior art and provide a task bypass method that is purely hardware-based, without software instruction intervention, and based solely on absolute physical rules. This method enables low-power bypass execution of lightweight tasks, fundamentally solves the problem of wasted power consumption, and completely avoids the risk of third-party patents, thus achieving independent and controllable commercial application. Technical solution

[0005] To achieve the above objectives, the present invention adopts the following technical solution: A task bypass method based on absolute physical rules, applied to a heterogeneous processing system including a first computing unit and a second computing unit, wherein the power consumption of the first computing unit is higher than that of the second computing unit, includes the following steps: S1. The pure hardware detection circuit acquires the physical characteristic parameters of the task to be executed; S2. When the physical characteristic parameters meet the preset absolute physical rules, the task is bypassed to the second computing unit for execution, and the first computing unit remains in a dormant state. S3. When the physical characteristic parameters do not meet the absolute physical rules, the task is normally scheduled to be executed by the first computing unit. The determination of the absolute physical rules relies solely on the independent physical characteristics of the current task, without requiring context information from other tasks; all steps are executed by pure hardware circuitry, without the intervention of software instructions.

[0006] Furthermore, the physical feature parameters include the number of task operation elements; the absolute physical rule is: when the number of operation elements is less than a preset size threshold, the rule is deemed to be satisfied.

[0007] Furthermore, the preset size threshold is fixed once during manufacturing and cannot be modified during operation.

[0008] Furthermore, the physical characteristic parameters include whether the task data block conforms to a preset invalid data pattern; the absolute physical rule is: when the task data block is detected to conform to the preset invalid data pattern, it is determined that the rule is met, and the corresponding result is directly returned by the hardware circuit without starting any computing unit.

[0009] Furthermore, the preset invalid data mode includes all task data being zero, in which case the hardware circuit directly returns a result of all zeros.

[0010] Furthermore, the preset invalid data mode includes tasks containing non-numerical data identifiers, in which case the hardware circuit directly returns an invalid value flag.

[0011] Furthermore, the first operation unit is a tensor operation core or an arithmetic logic operation unit array, and the second operation unit is a scalar operation core.

[0012] Furthermore, the task that is bypassed to the second computing unit is transparent to the upper-layer software in terms of its execution result.

[0013] Furthermore, the pure hardware detection circuit is automatically triggered when a task arrives and automatically enters a low-power standby state after the task is completed.

[0014] Furthermore, the control logic circuit of the pure hardware circuit itself does not contain any executable firmware, microcode, software instructions, or programmable logic configuration data, and its logic function is permanently fixed during manufacturing and cannot be reconfigured. Beneficial effects

[0015] Compared with the prior art, the present invention has the following significant advantages: 1. Extremely reduce ineffective power consumption and significantly improve energy efficiency: This invention bypasses small-sized operator tasks to low-power computing units through pure hardware task bypass, and bypasses ineffective filling tasks through pure hardware pass-through, which can greatly reduce the ineffective power consumption of chips in inference scenarios and significantly reduce the operating cost of computing clusters. 2. Microsecond-level real-time response, zero computing power consumption: The entire process is executed by pure hardware circuits without multi-layer software interaction. The task bypass decision latency is <100ns, which is fully adapted to the microsecond-level execution cycle of small tasks. At the same time, it does not occupy any core computing power resources, and the effective computing power utilization of the chip is effectively improved. 3. No complex scheduling algorithms, zero patent risk: The bypass decision of this invention is based solely on the independent absolute physical characteristics of the current task, without the need for computation graph analysis or multi-task context dependencies. It completely avoids the core protection scope of task scheduling patents in the industry, achieving complete independent control, with no risk of third-party patent infringement, and can be directly commercialized. 4. High reliability, tamper-proof, and maximum stability: All logic is permanently fixed during chip manufacturing, with no software intervention path, making it impossible to tamper with or bypass. Driver failures and system crashes do not affect the execution of bypass functions, ensuring stable operation throughout the chip's entire lifecycle. 5. Unaware of upper-layer software and highly adaptable: The execution results of the bypass task are completely transparent to the upper-layer software. No modification is required to the computational inference framework or business code. It is directly compatible with all existing computing cluster hardware and software architectures, resulting in extremely low deployment costs. Detailed Implementation

[0016] The present invention will be further described in detail below with reference to specific embodiments.

[0017] This embodiment provides a task bypass method based on absolute physical rules, applied to a parallel computing processing chip in a computing cluster. The chip includes heterogeneous dual computing units: the first computing unit is a high-power parallel computing core with a peak power consumption of 200W, used for heavy computational tasks such as large-size matrix multiplication and convolution; the second computing unit is a low-power serial computing core with a peak power consumption of <1W, used for small-size operators and lightweight computational tasks.

[0018] The method in this embodiment is executed entirely by pure hardware circuitry embedded in the chip, without any software instructions. All control logic is permanently fixed during chip manufacturing via mask programming, and contains no executable firmware, microcode, software instructions, or programmable logic configuration data. It cannot be reconfigured during operation. The specific implementation steps are as follows: Step 1: Hardware extraction of task physical feature parameters When a task enters the chip instruction queue, a dedicated pure hardware detection circuit extracts two core physical characteristic parameters of the current task in real time within one clock cycle: 1. Number of task operation elements: Extract the tensor dimension and total number of elements of the operator from the fixed fields of the task instruction; 2. Task data block characteristics: Detect whether the task input data block is all zero data and whether it contains non-numerical data identifiers.

[0019] The entire extraction process is performed without software involvement, relying solely on the independent physical characteristics of the current task. It does not require obtaining context information from other tasks, nor does it involve any computational graph analysis or dependency parsing operations.

[0020] Step 2: Determining Absolute Physical Rules and Task Distribution The hardware circuitry performs task allocation and determination based on absolute physical rules permanently fixed in a one-time programmable non-volatile memory unit during chip manufacturing. The rules are as follows: 1. First type of rule: When the number of task operation elements is less than the preset size threshold (64 elements by default), it is determined that the bypass rule is met, and the task is bypassed to the low-power serial computing core for execution, while the high-power parallel computing core remains in sleep state; 2. Second type of rule: When the task data block is detected to be filled with all zeros or contains non-numerical identifiers, it is determined that the pass-through bypass rule is met. No processing unit needs to be started, and the corresponding result is returned directly by the dedicated hardware circuit. 3. Tasks that do not meet the above rules will be scheduled to be executed on high-power parallel computing cores.

[0021] The preset size threshold is locked once during chip manufacturing, and no software can modify the path during operation, completely avoiding patent risks.

[0022] Step 3: Task Execution and Result Return 1. Tasks bypassed to the serial processing core are calculated by the serial core and the result is written back to the target register. This is completely transparent to the upper-layer software and requires no modification to any business code. 2. For all-zero tasks with direct bypass, the hardware circuit directly returns all-zero results; for non-numerical exception tasks, it directly returns an invalid value flag. No computing unit is powered on throughout the process, significantly reducing standby power consumption. 3. Tasks normally scheduled to the parallel computing core are woken up to complete the computation and return the results.

[0023] Step 4: Low-power standby control The pure hardware detection circuit is automatically triggered when a task arrives. After the task is completed, it automatically enters a low-power standby state, turns off the internal clock, and retains only the edge detection circuit, further reducing static power consumption.

[0024] When the method of this embodiment is applied to a large-scale parallel computing scenario, a large number of lightweight computing tasks are directly bypassed to low-power computing cores for execution, and invalid padding tasks are implemented through pure hardware pass-through bypass. The overall power consumption of the system is significantly reduced while the computing accuracy remains unchanged. At the same time, it is fully compatible with existing mainstream computing frameworks, requires no modification to upper-layer business code, and is easy to deploy.

[0025] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A task bypass method based on absolute physical rules, applied to a heterogeneous processing system comprising a first computing unit and a second computing unit, wherein the power consumption of the first computing unit is higher than that of the second computing unit, characterized in that, Includes the following steps: S1. The pure hardware detection circuit acquires the physical characteristic parameters of the task to be executed; S2. When the physical characteristic parameters meet the preset absolute physical rules, the task is bypassed to the second computing unit for execution, and the first computing unit remains in a dormant state. S3. When the physical characteristic parameters do not meet the absolute physical rules, the task is normally scheduled to be executed by the first computing unit. The determination of the absolute physical rules relies solely on the independent physical characteristics of the current task, without requiring context information from other tasks; all steps are executed by pure hardware circuitry, without the intervention of software instructions.

2. The method according to claim 1, characterized in that, The physical characteristic parameters include the number of task operation elements; the absolute physical rule is: when the number of operation elements is less than a preset size threshold, the rule is deemed to be satisfied.

3. The method according to claim 2, characterized in that, The preset size threshold is fixed once during manufacturing and cannot be modified during operation.

4. The method according to claim 1, characterized in that, The physical characteristic parameters include whether the task data block conforms to the preset invalid data pattern; the absolute physical rule is: when the task data block is detected to conform to the preset invalid data pattern, it is determined that the rule is met, and the corresponding result is directly returned by the hardware circuit without starting any computing unit.

5. The method according to claim 4, characterized in that, The preset invalid data mode includes situations where all task data is zero, in which case the hardware circuit directly returns a result of all zeros.

6. The method according to claim 4, characterized in that, The preset invalid data mode includes tasks containing non-numerical data identifiers, in which case the hardware circuit directly returns an invalid value flag.

7. The method according to claim 1, characterized in that, The first operation unit is a tensor operation core or an arithmetic logic operation unit array, and the second operation unit is a scalar operation core.

8. The method according to claim 1, characterized in that, The task that is bypassed to the second processing unit is transparent to the upper-level software.

9. The method according to claim 1, characterized in that, The pure hardware detection circuit is automatically triggered when a task arrives and automatically enters a low-power standby state after the task is completed.

10. The method according to claim 1, characterized in that, The control logic circuit of the pure hardware circuit itself does not contain any executable firmware, microcode, software instructions, or programmable logic configuration data. Its logic function is permanently fixed during manufacturing and cannot be reconfigured.