A pure hardware lookup table-based dynamic voltage and frequency regulation method and circuit

Abstract

This invention discloses a pure hardware lookup table-based dynamic voltage and frequency regulation method and circuit. The core of the method is: a pure hardware state machine collects the current operating state parameters in real time, uses the collected parameters as an index, and determines the target frequency level and target voltage level by looking up a table according to a preset mapping relationship, then performs level switching. The entire process is executed by the pure hardware state machine without software instruction intervention, and the level switching decision does not rely on any closed-loop feedback algorithm. This invention solves the problems of high latency, susceptibility to tampering, and patent risks associated with relying on closed-loop algorithms in existing software regulation schemes. It achieves chip-level low-latency, high-reliability dynamic voltage and frequency regulation, significantly reduces the overall power consumption of the chip, and is completely autonomous and controllable, effectively avoiding third-party patent risks.

Description

Technical Field

[0001] This invention relates to the field of chip power and clock management technology, and in particular to a pure hardware lookup table-based dynamic voltage and frequency adjustment method and circuit for parallel computing processing chips applied to large-scale parallel computing clusters. Background Technology

[0002] Dynamic voltage and frequency regulation is a core technology for reducing chip power consumption. Its core principle is to dynamically adjust the core operating frequency and supply voltage based on the chip's load status, minimizing power consumption while meeting performance requirements. Current regulation schemes for parallel processing chips in computing clusters generally suffer from the following core shortcomings: 1. Software-driven management, high latency and slow response: Existing solutions are all driven by host-side software, which requires multiple layers of interaction between the operating system, driver layer and hardware layer. The adjustment latency is tens of milliseconds, which cannot adapt to the real-time requirements of the tidal load changes of computing business. In light load scenarios, it is not possible to reduce frequency and voltage in time, resulting in serious waste of power consumption. 2. Reliance on closed-loop feedback algorithms carries extremely high patent risks: The core of existing solutions is a closed-loop feedback adjustment algorithm based on performance, latency, and temperature. Patent layouts in this field are highly concentrated, and leading manufacturers have formed patent barriers. Independent solutions are extremely prone to patent infringement risks and cannot achieve commercialization. 3. Easily tampered with and poorly stable: The software adjustment path is easily tampered with by malicious programs. Overclocking and undervoltage operations will directly cause the chip to crash or be permanently damaged. At the same time, driver failure will cause the adjustment function to completely fail. 4. Poor adjustment accuracy and low energy efficiency ratio: Software adjustment can only achieve coarse-grained gear adjustment, which cannot adapt to microsecond-level load fluctuations. At the same time, in order to ensure performance margin, there is a common problem of voltage over-design, which makes it impossible to achieve the optimal energy efficiency ratio.

[0003] Currently, some hardware-assisted adjustment solutions have emerged in the industry, but the core adjustment decisions are still made by software closed-loop algorithms, which cannot fundamentally solve the above-mentioned defects, and there is still a serious risk of patent infringement. Summary of the Invention

[0004] I. Technical problems to be solved The purpose of this invention is to overcome the above-mentioned defects of the prior art and provide a dynamic voltage and frequency regulation method and circuit that is purely hardware-based, without software instruction intervention, and does not rely on any closed-loop feedback algorithm. This enables chip-level low-latency, high-reliability, and high-precision voltage and frequency regulation, fundamentally solving the problem of ineffective power consumption waste, while effectively avoiding third-party patent risks and achieving independent and controllable commercial application. Technical solution

[0005] To achieve the above objectives, the present invention adopts the following technical solution: Methodological approach: A pure hardware lookup table-based dynamic voltage and frequency regulation method, comprising the following steps: S1. Pure hardware state machine collects current operating status parameters in real time; S2. Based on the preset mapping relationship, the target frequency range and target voltage range are determined by looking up the table using the collected operating status parameters as an index. S3, Execute gear shift; All steps are executed by a pure hardware state machine without the intervention of software instructions; gear shifting decisions do not rely on any closed-loop feedback algorithm.

[0006] Furthermore, in step S3, the gear switching is performed in the order of first adjusting the voltage and then increasing the frequency, and first decreasing the frequency and then adjusting the voltage.

[0007] Furthermore, the operating status parameters include at least one of the following: operating mode information, temperature data, and load utilization rate data.

[0008] Furthermore, the preset mapping relationship includes at least three levels, each corresponding to a different working mode, with each level having a preset frequency value and voltage value.

[0009] Furthermore, step S3 also includes: during the switching process, first turn off the gating of the old clock domain, wait for a preset number of clock cycles, and then turn on the gating of the new clock domain to eliminate clock glitches; after the gear switching is completed, start a preset hysteresis period, during which gear switching is prohibited again.

[0010] Furthermore, it also includes: a timing margin monitoring circuit that monitors the timing of critical paths in real time, and triggers emergency frequency reduction protection only when the timing margin is lower than a preset threshold; the output of the timing margin monitoring circuit does not participate in daily frequency switching decisions; when the temperature exceeds a preset temperature threshold, the hardware automatically limits the highest selectable frequency level.

[0011] Furthermore, it also includes: the hardware load monitoring circuit real-time acquisition of at least one load indicator among the computing unit utilization rate, pipeline idle state, cache hit rate, and memory access bandwidth utilization rate of the processing unit, and writes it into the independent reporting cache at fixed intervals; the gear switching control state machine determines the target gear by looking up the table based on the load indicators.

[0012] Furthermore, it also includes: when acquiring external cooling medium temperature data, automatically adjusting the upper limit of power consumption according to a preset temperature-power consumption mapping relationship.

[0013] Furthermore, the control logic circuit of the pure hardware state machine itself does not contain any executable firmware, microcode, software instructions, or programmable logic configuration data, and its logic function is permanently fixed during manufacturing and cannot be reconfigured.

[0014] Circuit-side solution: A pure hardware lookup table-based dynamic voltage and frequency adjustment circuit, comprising: an operating status acquisition interface, a mapping relationship storage unit, a gear switching control state machine, and a glitch-free clock interlock circuit; the mapping relationship storage unit pre-stores multiple sets of frequency-voltage mapping relationships; the gear switching control state machine determines the target gear by looking up the table based on the operating status parameters obtained from the operating status acquisition interface, and outputs voltage and frequency adjustment signals according to a preset timing sequence; the glitch-free clock interlock circuit first disables the old clock domain gate during gear switching, waits for a preset period, and then enables the new clock domain gate; wherein, the circuit does not contain any executable firmware, microcode, software instructions, or programmable logic configuration data. Beneficial effects

[0015] Compared with the prior art, the present invention has the following significant advantages: 1. Microsecond-level real-time response and significantly improved energy efficiency: The entire process is executed by a pure hardware state machine without multi-layered software interaction. The gear switching delay can be controlled within 1 microsecond, which is fully adapted to the tidal load fluctuation of computing business. The chip power consumption is significantly reduced in light load and training scenarios, greatly improving the chip's energy efficiency. 2. No closed-loop feedback algorithm, effectively avoiding patent risks: The core of this invention is a pure hardware lookup table fixed mapping adjustment, which does not rely on any closed-loop feedback optimization algorithm. This effectively avoids the core protection scope of related patents in the industry, achieves complete independent control, has no risk of third-party patent infringement, and can be directly commercialized. 3. High reliability, tamper-proof, and chip security safeguards: All logic is permanently fixed during chip manufacturing, with no software intervention path, making it impossible to be maliciously tampered with, overclocked / undervoltaged, or affected by driver failures or system crashes. The chip operates safely and stably throughout its entire lifecycle. 4. High-precision adjustment without performance loss: The preset mapping relationship can realize fine-grained adjustment of multiple levels. At the same time, through glitch-free clock interlocking and timing margin emergency protection, it ensures that there is no performance loss or timing violation when switching levels, and fully meets the performance requirements of computation training and inference. 5. Zero computing power consumption, no impact on business operations: The entire process is executed by dedicated hardware circuits, which does not occupy the core computing power resources of the chip and has no computing power overhead from software scheduling, ensuring that computing power resources are fully utilized. Detailed Implementation

[0016] The present invention will be further described in detail below with reference to specific embodiments.

[0017] This embodiment provides a pure hardware lookup table-based dynamic voltage and frequency adjustment method and circuit, which is applied to the parallel computing processing chip of the computing cluster. The chip is manufactured using mature technology, and the core power domain supports 5 levels of frequency-voltage adjustment, adapting to three core business modes: computing training, online inference, and standby idle.

[0018] I. Circuit Hardware Architecture The pure hardware lookup table-based dynamic voltage and frequency adjustment circuit in this embodiment is integrated into the chip's global control module, and specifically includes: 1. Operational Status Acquisition Interface: Supports real-time acquisition of chip operating mode information, core temperature data, arithmetic unit load utilization data, pipeline idle status, cache hit rate, memory access bandwidth utilization, cooling medium temperature and other operational status parameters; 2. Mapping relationship storage unit: It adopts a one-time programmable non-volatile storage unit, which pre-stores 5 sets of frequency-voltage mapping relationship tables, as well as temperature-power consumption mapping table and cooling medium temperature-power consumption mapping table. It is permanently fixed once during chip manufacturing and cannot be modified during operation. 3. Gear switching control state machine: It adopts a pure hardware state machine with one-hot encoding, without any software instruction intervention. It uses the collected operating status parameters as an index to look up the table to determine the target gear, and outputs voltage and frequency modulation signals according to the preset timing sequence. The gear switching decision does not depend on any closed-loop feedback algorithm. 4. Glitch-free clock interlock circuit: used for clock domain switching during gear shifting. First, the old clock domain gate is closed, and after waiting for 2 clock cycles, the new clock domain gate is opened, completely eliminating clock glitches. 5. Timing margin monitoring circuit: Real-time monitoring of the timing margin of the chip's critical path. Emergency frequency reduction protection is triggered only when the timing margin is lower than a preset threshold. Its output does not participate in daily frequency reduction decisions. 6. Hardware load monitoring circuit: Real-time acquisition of load indicators of the computing unit, written to an independent reporting cache at fixed intervals for level lookup and upper-level operation and maintenance reading.

[0019] All circuit logic is permanently fixed during chip manufacturing through mask programming, containing no executable firmware, microcode, software instructions, or programmable logic configuration data, and cannot be reconfigured during operation.

[0020] II. Specific Implementation Steps of the Method The adjustment method in this embodiment is executed entirely by the aforementioned pure hardware circuit, without any software instruction intervention. The specific steps are as follows: Step 1: Real-time acquisition of operating status parameters The gear shifting control state machine collects real-time operating status parameters such as the chip's current working mode, core temperature, and computing unit load utilization through the operating status acquisition interface. The acquisition cycle is 1 microsecond, and no software is involved.

[0021] Step 2: Determine the target gear by referring to the table. The state machine uses the collected operating state parameters as an index to look up the target frequency range and target voltage range in a preset mapping table in the non-volatile memory. The preset mapping table is as follows: Gear settings, operating modes, core frequency, core voltage, applicable scenarios Training mode 1.2GHz 0.85V computational training Level 2 Training Medium 1.0GHz 0.78V Light Load Training 3-level inference mode, 800MHz, 0.70V online inference. 4-speed inference low-end 500MHz 0.60V light-load inference 5-level idle mode, 200MHz, 0.55V, standby idle. The gear shifting decision is based solely on a preset fixed mapping table and does not rely on any closed-loop feedback optimization algorithm, effectively avoiding patent risks.

[0022] Step 3: Execute burr-free gear shifting. The state machine performs gear switching according to a fixed timing sequence of "adjusting voltage first and then increasing frequency, and decreasing frequency first and then adjusting voltage". At the same time, the glitch-free clock interlock circuit first closes the old clock domain gate during the switching process, waits for 2 clock cycles, and then opens the new clock domain gate to completely eliminate clock glitches. After the gear switching is completed, a 10-cycle hysteresis cycle is started, during which gear switching is prohibited to avoid frequent oscillations.

[0023] Step 4: Anomaly Protection and Extended Functions 1. Timing margin emergency protection: The timing margin monitoring circuit monitors the critical path in real time and triggers emergency frequency reduction protection only when the timing margin is lower than the threshold. It does not participate in the daily frequency reduction decision. 2. Temperature-linked protection: When the core chip temperature exceeds 85℃, the hardware automatically limits the highest frequency setting to prevent the chip from overheating; 3. Cooling scenario adaptation: When the temperature data of the cooling medium is obtained, the chip power consumption limit is automatically adjusted according to the preset mapping table to adapt to the needs of liquid-cooled computing clusters; 4. Load data reporting: The hardware load monitoring circuit collects load indicators at fixed intervals and writes them to an independent reporting cache for upper-level operation and maintenance to read. It does not participate in the level decision.

[0024] In this embodiment, all logic is executed purely in hardware without any software instructions. The total latency for gear switching is less than 1μs, far superior to the tens of milliseconds latency of existing software solutions. When applied to online inference and training scenarios in computing clusters, this embodiment significantly reduces overall chip power consumption while maintaining hardware accuracy and training performance. It also effectively avoids third-party patent risks, meeting the requirements for commercial deployment.

[0025] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A purely hardware lookup table-based dynamic voltage and frequency regulation method, characterized in that, Includes the following steps: S1. Pure hardware state machine collects current operating status parameters in real time; S2. Based on the preset mapping relationship, the target frequency range and target voltage range are determined by looking up the table using the collected operating status parameters as an index. S3, Execute gear shift; All steps are executed by a pure hardware state machine without the intervention of software instructions; gear shifting decisions do not rely on any closed-loop feedback algorithm.

2. The method according to claim 1, characterized in that, In step S3, the gear switching is performed in the order of first adjusting the voltage and then increasing the frequency, and first decreasing the frequency and then adjusting the voltage.

3. The method according to claim 1, characterized in that, The operating status parameters include at least one of the following: operating mode information, temperature data, and load utilization rate data.

4. The method according to claim 1, characterized in that, The preset mapping relationship includes at least three levels, each corresponding to a different working mode, with each level having a preset frequency and voltage value.

5. The method according to claim 2, characterized in that, Step S3 also includes: during the switching process, first turn off the gating of the old clock domain, wait for a preset number of clock cycles, and then turn on the gating of the new clock domain to eliminate clock glitches; after the gear switching is completed, start a preset hysteresis period, during which gear switching is prohibited again.

6. The method according to claim 1, characterized in that, Also includes: The timing margin monitoring circuit monitors the timing of critical paths in real time and triggers emergency frequency reduction protection only when the timing margin is lower than a preset threshold. The output of the timing margin monitoring circuit does not participate in daily frequency switching decisions. When the temperature exceeds a preset temperature threshold, the hardware automatically limits the highest selectable frequency level.

7. The method according to claim 1, characterized in that, Also includes: The hardware load monitoring circuit collects at least one load indicator from the processing unit, including the computing unit utilization rate, pipeline idle status, cache hit rate, and memory access bandwidth utilization rate, and writes it to an independent reporting cache at fixed intervals; the gear switching control state machine determines the target gear by looking up the table based on the load indicators.

8. The method according to claim 1, characterized in that, Also includes: When acquiring external cooling medium temperature data, the power consumption limit is automatically adjusted according to the preset temperature-power consumption mapping relationship.

9. The method according to claim 1, characterized in that, The control logic circuit of the pure hardware state machine itself does not contain any executable firmware, microcode, software instructions, or programmable logic configuration data. Its logic function is permanently fixed during manufacturing and cannot be reconfigured.

10. A purely hardware lookup table-based dynamic voltage and frequency regulation circuit, characterized in that, include: Operating status acquisition interface, mapping relationship storage unit, gear switching control state machine, and glitch-free clock interlock circuit; The mapping relationship storage unit pre-stores multiple sets of frequency-voltage mapping relationships; the gear switching control state machine determines the target gear by looking up the operating status parameters obtained from the operating status acquisition interface, and outputs voltage and frequency modulation signals according to a preset timing sequence; the glitch-free clock interlock circuit first closes the old clock domain gate during gear switching, waits for a preset period, and then opens the new clock domain gate; wherein, the circuit does not contain any executable firmware, microcode, software instructions, or programmable logic configuration data.