Weighted distributed access in memory space

Abstract

This application relates to weighted distributed access over memory space. It can receive multiple commands. The multiple commands may include a first command associated with a first memory space of a first priority among a plurality of priorities allocated in the memory system, a second command associated with a second memory space of a second priority among the plurality of priorities allocated in the memory system, and a third command associated with a third memory space of a third priority among the plurality of priorities allocated in the memory system. The multiple commands can be executed using an interleaved mode based on memory space priorities.

Description

[0001] Cross-referencing

[0002] This patent application claims priority to U.S. Patent Application No. 19 / 215,432, entitled “Weighted Distributed-Access Across Memory Spaces”, filed May 22, 2025, by Porzio et al., and U.S. Provisional Patent Application No. 63 / 656,003, entitled “Weighted Distributed-Access Across Memory Spaces”, filed June 4, 2024, by Porzio et al., each of which is assigned to the assignee, and each of which is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The technical field relates to weighted distributed access in memory space. Background Technology

[0004] Memory devices are widely used to store information in devices such as computers, user devices, wireless communication devices, cameras, digital displays, and so on. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed to support one of two states, typically represented as logic 1 or logic 0. In some instances, a single memory cell can support more than two states, either of which can be stored. To access the stored information, the memory device can read (e.g., sense, detect, retrieve, determine) the state from the memory cell. To store information, the memory device can write (e.g., program, set, assign) states to the memory cell.

[0005] Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), auto-select memory, chalcogenide memory technology, NOR and NAND memory devices, and so on. Memory cells can be described in terms of volatile or non-volatile configurations. Memory cells configured in a non-volatile configuration can maintain their stored logical state for a long time, even in the absence of external power. Memory cells configured in a volatile configuration may lose their stored state when disconnected from external power. Summary of the Invention

[0006] A memory system is described. The memory system may include one or more memory devices; and a processing circuitry system coupled to the one or more memory devices and configured to cause the memory system to: receive a plurality of commands, including a first command associated with a first memory space of a first priority assigned to a plurality of priorities in the memory system, a second command associated with a second memory space of a second priority assigned to a plurality of priorities in the memory system, and a third command associated with a third memory space of a third priority assigned to a plurality of priorities in the memory system; and, upon receiving the plurality of commands, execute the plurality of commands using an interleaved mode according to the first priority, the second priority, and the third priority.

[0007] A non-transitory computer-readable medium storing code is described. The transitory computer-readable medium storing code may include instructions executable by a processing circuitry of a memory system to cause the memory system to: receive a plurality of commands, including a first command associated with a first memory space of a first priority assigned to a plurality of priorities in the memory system, a second command associated with a second memory space of a second priority assigned to a plurality of priorities in the memory system, and a third command associated with a third memory space of a third priority assigned to a plurality of priorities in the memory system; and, upon receiving the plurality of commands, execute the plurality of commands using an interleaved pattern according to the first priority, the second priority, and the third priority.

[0008] A method performed by a memory system is described. The method may include: receiving a plurality of commands, including a first command associated with a first memory space of a first priority among a plurality of priorities allocated in the memory system, a second command associated with a second memory space of a second priority among the plurality of priorities allocated in the memory system, and a third command associated with a third memory space of a third priority among the plurality of priorities allocated in the memory system; and executing the plurality of commands in an interleaved mode according to the received plurality of commands. Attached Figure Description

[0009] Figure 1 Examples of systems supporting weighted distributed access over memory space are shown, based on the examples disclosed herein.

[0010] Figure 2 Examples of a set of operations for weighted distributed access in memory space are shown, based on the examples disclosed herein.

[0011] Figure 3 This illustrates instance queue operations for weighted distributed access in memory space, based on the examples disclosed herein.

[0012] Figure 4 A block diagram is shown of a memory system supporting weighted distributed access over memory space, based on an example disclosed herein.

[0013] Figure 5 The flowcharts shown below illustrate one or more methods for supporting weighted distributed access over memory space, based on examples disclosed herein. Detailed Implementation

[0014] One or more host systems (e.g., navigation systems, autonomous driving systems, entertainment systems, diagnostic systems, wireless communication systems, etc.) access the memory system. Similarly, one or more applications installed on the one or more host systems access the memory system. Therefore, the memory system can be shared by multiple host systems and / or multiple applications. Data can be stored in multiple memory spaces (e.g., logical units) of the memory system for one or more host systems / applications. In such cases, the host systems / applications can access data stored in multiple memory spaces during operation.

[0015] In some instances, host systems and / or applications may send an excessive number of read and / or write requests, thereby monopolizing the bandwidth of the storage device (e.g., communication bandwidth and / or processing bandwidth). This can cause other applications attempting to access the storage device (e.g., another storage space on the storage device) to access it with reduced performance, or in some cases, to be unable to fully access the storage device. Therefore, mechanisms (e.g., methods, systems, devices, technologies, configurations, components) may be needed to ensure that every host system can access and / or every application on a host system (e.g., installed on or running on the host system) can access the data stored in the storage system, and that its throughput exceeds a throughput threshold.

[0016] To ensure that each host system and / or each application on the host system can access data stored in the storage device system with the lowest throughput, a set of relative priorities can be assigned to the memory spaces in the storage device. The assigned priorities of the memory spaces can be used to implement a priority-weighted memory space access pattern, while also ensuring that each memory space can be accessed according to a minimum throughput threshold.

[0017] Beyond the memory systems described herein, techniques for providing access to memory space in a distributed manner, weighted according to memory space priority while ensuring minimum access throughput, can typically be implemented to improve the performance of various electronic devices and systems, including artificial intelligence (AI) applications, augmented reality (AR) applications, virtual reality (VR) applications, and games. Some electronic device applications, including high-performance applications such as AI, AR, VR, and games, can be associated with relatively high processing demands to meet user expectations. Therefore, increasing the processing power of electronic devices by reducing response time, improving power consumption, reducing complexity, increasing data throughput or access speed, reducing communication time, or increasing memory capacity or density, as well as other performance indicators, can improve user experience or appeal. Implementing the techniques described herein can improve the performance of electronic devices by favoring access to (relatively) higher-priority memory spaces and preventing (relatively) lower-priority applications from monopolizing the memory system, while ensuring fair access throughput to all memory spaces. This improves the user experience of systems and applications while still prioritizing the operation of the most important systems and applications, and other benefits.

[0018] Figure 1 An example of a system 100 supporting weighted distributed access over memory space is shown, according to the examples disclosed herein. System 100 may include a memory system 110 configured to store data received from host system 105 and to send data to host system 105 if requested by host system 105 using an access command (e.g., a read command or a write command).

[0019] The memory system 110 may include one or more memory devices 140 for storing data transferred between the memory system 110 and the host system 105 (e.g., in response to receiving an access command from the host system 105). For example, the memory device 140 may include NAND memory, PCM, self-select memory, 3D cross-point or other chalcogenide-based memory, FERAM, MRAM, NOR (e.g., NOR flash) memory, STT-MRAM, CBRAM, RRAM or OxRAM, and other examples.

[0020] Memory system 110 may include a memory controller 130 for controlling the transfer of data directly to and from memory device 140 (e.g., for storing data, retrieving data, determining memory locations where data is stored, and retrieving data from). The memory controller 130 may communicate directly with memory device 140 or via a bus (not shown), which may include protocols specific to each type of memory device 140. In some cases, a single memory controller 130 may be used to control multiple memory devices 140 of the same or different types. In some cases, memory system 110 may include multiple memory controllers 130 (e.g., the memory controller 130 is different for each type of memory device 140).

[0021] The memory system 110 may include an interface 120 for communicating with the host system 105, and a buffer 125 for temporarily storing data transferred between the host system 105 and the memory device 140. The interface 120, buffer 125, and memory controller 130 may support the transfer of data between the host system 105 and the memory device 140 (e.g., as shown by data path 150), and may be collectively referred to as the data path component.

[0022] Using buffer 125 to temporarily store data during transmission allows data to be buffered while commands are being processed, which reduces latency between commands and can support arbitrary data sizes associated with commands. This also allows for handling command bursts, and buffered data can be stored or transmitted, or both (e.g., after the burst stops). Buffer 125 may contain relatively fast memory (e.g., some type of volatile memory such as SRAM or DRAM), or hardware accelerators, or both, to allow for fast storage of data into and retrieval of data from buffer 125. Buffer 125 may contain data path switching components for bidirectional data transfer between buffer 125 and other components.

[0023] Temporary data storage in buffer 125 can refer to data being stored in buffer 125 during the execution of an access command. For example, after an access command completes, the associated data may no longer be maintained in buffer 125 (e.g., it can be overwritten with data for additional access commands). In some instances, buffer 125 can be a non-cached buffer. For example, data can be read directly from buffer 125 without going through host system 105. In some instances, read commands can be added to a queue without requiring an address to be matched against an address already in buffer 125 (e.g., no cached address matching or lookup operation is needed).

[0024] The memory system 110 may also include a memory system controller 115 for executing commands received from the host system 105, which may include controlling data path components to move data. The bus 135 can be used for communication between system components.

[0025] In some cases, one or more queues (e.g., command queue 160, buffer queue 165, storage queue 170) can be used to control the processing of access commands and the movement of corresponding data. This can be advantageous, for example, if the memory system 110 processes more than one access command from the host system 105 in parallel. As an example of a possible implementation, command queue 160, buffer queue 165, and storage queue 170 are depicted at interface 120, memory system controller 115, and storage controller 130, respectively. However, if implemented, the queues can be located anywhere within the memory system 110.

[0026] Data transferred between host system 105 and memory device 140 can be transmitted within memory system 110 along paths different from those for non-data information (e.g., commands, status information). For example, system components in memory system 110 can communicate with each other using bus 135, while data can be transmitted via data path 150 through data path components instead of bus 135. By communicating with data path components via bus 135 (e.g., using a memory system 110-specific protocol), memory system controller 115 can control how and whether data is transferred between host system 105 and memory device 140.

[0027] If host system 105 transmits an access command to memory system 110, the command can be received by interface 120 (e.g., according to a protocol such as UFS or eMMC). Therefore, interface 120 can be considered the front end of memory system 110. After receiving each access command, interface 120 can forward the command to memory system controller 115 (e.g., via bus 135). In some cases, each command can be added to command queue 160 for interface 120 to forward to memory system controller 115.

[0028] The memory system controller 115 can determine that an access command has been received based on communication from interface 120. In some cases, the memory system controller 115 can determine that a command has been received by retrieving the access command from command queue 160. The command can be removed from command queue 160 after retrieval (e.g., via memory system controller 115). In some cases, the memory system controller 115 can remove the command from command queue 160 via interface 120 (e.g., via bus 135).

[0029] After determining that an access command has been received, the memory system controller 115 can execute the access command. For a read command, this may involve obtaining data from one or more memory devices 140 and transferring the data to the host system 105. For a write command, this may involve receiving data from the host system 105 and moving the data to one or more memory devices 140. In either case, the memory system controller 115 may use a buffer 125 for, among other things, temporarily storing data received from or sent to the host system 105. The buffer 125 can be considered as an intermediate part of the memory system 110. In some cases, buffer address management (e.g., pointers to address locations in the buffer 125) may be performed by hardware (e.g., dedicated circuitry) in the interface 120, the buffer 125, or the memory controller 130.

[0030] In order to process a write command received from host system 105, memory system controller 115 may determine whether buffer 125 has sufficient available space to store the data associated with the command. For example, memory system controller 115 may determine (e.g., via firmware, via controller firmware) the amount of space within buffer 125 available to store the data associated with the write command.

[0031] In some cases, buffer queue 165 can be used to control the flow of commands associated with data stored in buffer 125, including write commands. Buffer queue 165 may contain access commands associated with data currently stored in buffer 125. In some cases, commands in command queue 160 can be moved to buffer queue 165 via memory system controller 115 and can remain in buffer queue 165 while the associated data is stored in buffer 125. In some cases, each command in buffer queue 165 may be associated with an address at buffer 125. For example, a pointer indicating the location in buffer 125 where the data associated with each command is stored can be maintained. Using buffer queue 165, multiple access commands can be received sequentially from host system 105, and at least some of the access commands can be processed in parallel.

[0032] If buffer 125 has sufficient space to store the write data, memory system controller 115 can cause interface 120 to transmit an availability indication to host system 105 (e.g., a "ready to deliver" indication), which can be performed according to a protocol (e.g., UFS protocol, eMMC protocol). When interface 120 receives data associated with a write command from host system 105, interface 120 can use data path 150 to deliver the data to buffer 125 for temporary storage. In some cases, interface 120 can obtain the location of the stored data within buffer 125 (e.g., from buffer 125, from buffer queue 165). Interface 120 can indicate to memory system controller 115 (e.g., via bus 135) whether the data delivery to buffer 125 has been completed.

[0033] After data is written and stored in buffer 125 via interface 120, the data can be transferred from buffer 125 and stored in memory device 140, which may involve the operation of memory controller 130. For example, memory system controller 115 may cause memory controller 130 to retrieve data from buffer 125 using data path 150 and transfer the data to memory device 140. Memory controller 130 can be considered as the back end of memory system 110. Memory controller 130 may (e.g., via bus 135) indicate to memory system controller 115 whether data transfer to one or more memory devices 140 has been completed.

[0034] In some cases, memory queue 170 may support the transfer of write data. For example, memory system controller 115 may (e.g., via bus 135) push write commands from buffer queue 165 to memory queue 170 for processing. Memory queue 170 may contain entries for each access command. In some instances, memory queue 170 may additionally contain: a buffer pointer (e.g., an address) indicating the location in buffer 125 where the data associated with the command is stored; and a memory pointer (e.g., an address) indicating the location in memory device 140 associated with the data. In some cases, memory controller 130 may (e.g., from buffer 125, from buffer queue 165, from memory queue 170) obtain the location of the data retrieved from buffer 125. Memory controller 130 may manage the location of stored data in memory device 140 (e.g., perform wear leveling, perform garbage collection). Entries may be added to memory queue 170 (e.g., via memory system controller 115). Entries can be removed from storage queue 170 after data transfer is complete (e.g., via storage controller 130, via memory system controller 115).

[0035] In order to process a read command received from host system 105, memory system controller 115 may determine whether buffer 125 has sufficient available space to store the data associated with the command. For example, memory system controller 115 may determine (e.g., via firmware, via controller firmware) the amount of space within buffer 125 available to store the data associated with the read command.

[0036] In some cases, buffer queue 165 can support buffered storage of data associated with read commands in a manner similar to that discussed with respect to write commands. For example, if buffer 125 has sufficient space to store read data, then memory system controller 115 can cause memory controller 130 to retrieve the data associated with the read command from memory device 140 using data path 150 and store the data in buffer 125 for temporary storage. Memory controller 130 can (e.g., via bus 135) indicate to memory system controller 115 when data transfer to buffer 125 is complete.

[0037] In some cases, the storage queue 170 can be used to facilitate data transfer. For example, the memory system controller 115 can push a read command to the storage queue 170 for processing. In some cases, the storage controller 130 can obtain (e.g., from buffer 125, from storage queue 170) the location from which data is retrieved within one or more memory devices 140. In some cases, the storage controller 130 can obtain (e.g., from buffer queue 165) the location where data is stored in buffer 125. In some cases, the storage controller 130 can obtain (e.g., from storage queue 170) the location where data is stored in buffer 125. In some cases, the memory system controller 115 can move a command processed by the storage queue 170 back to the command queue 160.

[0038] After data is stored in buffer 125 by storage controller 130, the data can be transferred from buffer 125 and sent to host system 105. For example, memory system controller 115 may enable interface 120 to retrieve data from buffer 125 using data path 150 and transfer the data to host system 105 (e.g., according to a protocol such as UFS or eMMC). For example, interface 120 may process commands from command queue 160 and may (e.g., via bus 135) indicate to memory system controller 115 that the data transfer to host system 105 has been completed.

[0039] The memory system controller 115 can execute received commands in a sequential order (e.g., first-in-first-out, according to the order of command queue 160). For each command, the memory system controller 115 can shift data corresponding to the command into and out of buffer 125, as discussed herein. While data is shifted into and stored in buffer 125, the command can remain in buffer queue 165. If the processing of the command has been completed (e.g., if the data corresponding to the access command has been passed out of buffer 125), then the command can be removed from buffer queue 165 (e.g., via memory system controller 115). If a command is removed from buffer queue 165, then the address where data associated with said command was previously stored can be used to store data associated with the new command.

[0040] In some instances, memory system controller 115 may be configured for operations associated with one or more memory devices 140. For example, memory system controller 115 may perform or manage operations such as wear leveling, garbage collection, error control such as error detection or error correction, encryption, caching, media management, background refresh, health monitoring, and address translation between logical addresses (e.g., LBAs) associated with commands from host system 105 and physical addresses (e.g., physical block addresses) associated with memory cells within memory device 140. For example, host system 105 may issue commands indicating one or more LBAs, and memory system controller 115 may recognize one or more physical block addresses indicated by the LBAs. In some cases, one or more consecutive LBAs may correspond to non-consecutive physical block addresses. In some cases, memory controller 130 may be configured to perform one or more of the operations in conjunction with or in place of memory system controller 115. In some cases, memory system controller 115 may perform the functions of memory controller 130, and memory controller 130 may be omitted.

[0041] System 100 may include any number of non-transitory computer-readable media that support weighted distributed access over memory space. For example, host system 105 or memory system 110 may include or otherwise have access to one or more non-transitory computer-readable media storing instructions (e.g., firmware) for performing the functions belonging to host system 105 or memory system 110 herein. For example, such instructions, when executed by host system 105 (e.g., host system controller) or by memory system (e.g., memory system controller), may cause host system 105 or memory system 110 to perform the associated functions described herein.

[0042] The memory supported by a memory system (e.g., with a capacity of 1TB) can consist of memory regions (also known as volumes). In some instances, memory regions can be further divided into memory sub-regions (also known as partitions). In some cases, both memory regions and memory sub-regions can be collectively referred to as memory space.

[0043] In some instances, memory regions can be implemented as logical units (LUs), which can be identified using logical unit numbers (LUNs). In some instances, a logical unit can be referred to or identified by its LUN. In some instances, a logical unit can be a logical disk. Logical units can have different sizes and can be used to store different types of data. For example, a first logical unit (with a first LUN) can be represented as a code execution unit and used to store executable code for an operating system and / or applications installed on a host system, and a second logical unit (with a second LUN) can be represented as a mass storage unit and used to store user-level data.

[0044] In some instances, one or more LUNs at the memory system can be designated as high-priority LUNs. A logical unit with a high-priority LUN can be used to store a specific type of data (e.g., system-level and application-level executable code). In some instances, device descriptor parameters can designate the one or more LUNs at the memory system as high-priority LUNs. In some instances, the memory system is configured to represent a single LUN as a high-priority LUN.

[0045] In some instances, commands received at the memory system addressing a high-priority LUN can be processed first, followed by any other commands currently awaiting execution at the memory system and / or any commands received after the high-priority LUN. In some instances, the commands received at the memory system can themselves indicate priority; for example, a command received as a queue head command (e.g., according to the Small Computer System Interface (SCSI) protocol) may have a higher priority than other commands received as regular mode commands (e.g., according to the SCSI protocol). In still other instances, a command can indicate its priority by setting a UPIU command priority flag in the Universal Flash Storage (UFS) Protocol Information Unit (UPIU) containing the command. In some cases, commands for a high-priority LUN can be executed before all other high-priority commands (e.g., queue head commands, commands with a UPIU high-priority flag, etc.).

[0046] In some instances, a memory system may contain a high-priority command queue for executing commands associated with high-priority operations, and one or more normal-priority queues for executing other commands. In such cases, commands entering the high-priority queue can be executed as quickly as possible, while the execution of commands in the normal-priority queues can be paused until all commands in the high-priority queues have been executed.

[0047] One or more host systems (e.g., navigation systems, autonomous driving systems, entertainment systems, diagnostic systems, wireless communication systems, etc.) can access the memory system. Similarly, one or more applications installed on the one or more host systems can access the memory system. Data for one or more host systems / applications can be stored in one or more memory spaces (e.g., one or more logical units) of the memory system. In some instances, data for each host system and / or application can be stored in a dedicated memory space. In other instances, data for each host system and / or application can be stored in one or more shared memory spaces. In some instances, some data for each host system and / or application (e.g., executable code) can be stored in one memory space, while other data (e.g., user data) can be stored in another memory space. In such cases, the host system / application can access the data stored in one or more memory spaces during operation.

[0048] In some instances, host systems and / or applications may send an excessive number of read and / or write requests, thereby monopolizing storage bandwidth. This can cause other applications attempting to access the storage device (e.g., another memory space of the storage device) to access the storage device with reduced performance, or in some cases, to be unable to fully access the storage device. Therefore, mechanisms (e.g., methods, systems, devices, technologies, configurations, components) may be needed to ensure that every host system can access and / or every application at the host system (e.g., installed at or running on the host system) can access the data stored in the storage system, and that its throughput exceeds a throughput threshold.

[0049] To ensure that each host system and / or each application on the host system can access data stored in the storage device system with the lowest throughput, a set of relative priorities can be assigned to the memory spaces in the storage device. The assigned priorities of the memory spaces can be used to implement a priority-weighted memory space access pattern, while also ensuring that each memory space can be accessed according to a minimum throughput threshold.

[0050] Memory system 110 (e.g., via memory system controller 115) can be configured to receive a sequence of commands, including commands for multiple memory spaces of memory system 110. For example, memory system 110 (e.g., via memory system controller 115) can receive a sequence of commands over a period of time, including a first command for a first memory space of memory system 110 (e.g., a first logical unit, a first partition of the first logical unit), a second command for a second memory space of memory system 110 (e.g., a second logical unit, a second partition of the first logical unit), and a third command for a third memory space of memory system 110 (e.g., a third logical unit, a third partition of the first logical unit). The first memory space may be associated with a first priority, the second memory space may be associated with a second priority, and the third memory space may be associated with a third priority. In some instances, the first priority is higher than the second priority, and the second priority is higher than the third priority. The relative priority of memory spaces can indicate that commands for higher-priority memory spaces will take precedence over commands for lower-priority memory spaces (e.g., executed first, executed at higher throughput, or a combination thereof). In some instances, the first, second, and third commands can be stored simultaneously in command queue 160.

[0051] Memory system 110 (e.g., via memory system controller 115) can be configured to execute a sequence of commands according to an interleaving pattern based on relative priorities associated with the command sequence. In some instances, the interleaving pattern is a weighted interleaving pattern implemented to prioritize commands for higher-priority memory spaces while also ensuring at least a minimum access throughput for lower-priority memory spaces. For example, for the first, second, and third commands in command queue 160, the interleaving pattern can interleave the first, second, and third commands such that higher-priority commands are executed with higher access throughput (e.g., greater frequency, larger batch size, etc.) compared to lower-priority commands, while also ensuring that lower-priority commands are executed with minimum access throughput. In some instances, memory system 110 (e.g., via memory system controller 115) loads commands from command queue 160 into storage queue 170 according to the interleaving pattern and then executes the commands in storage queue 170 in an ordered manner (e.g., starting at the beginning of storage queue 170).

[0052] By executing commands for different memory spaces according to a priority-weighted pattern (e.g., interleaved circular pattern) based on the priority allocated to the memory space, while ensuring the minimum access throughput of the memory space, commands can be executed in a manner that tends to point to higher priority memory spaces, while ensuring that the execution of lower priority commands pointing to lower priority memory spaces is not completely blocked (for an excessively long period of time) (e.g., ensuring the minimum throughput of lower priority commands pointing to lower priority memory spaces).

[0053] Figure 2 Examples of a set of operations for weighted distributed access in memory space are shown, based on the examples disclosed herein.

[0054] Process flow 200 may be executed by one or more host systems (e.g., including host system 205) and memory system 210, which may be the host systems described herein (e.g., ...). Figure 1 The host system 105) and the memory system (e.g., Figure 1 An example of a memory system 110. In some instances, process flow 200 illustrates a set of instance operations executed to support weighted distributed access over memory spaces. For example, process flow 200 may include operations for executing a sequence of commands (containing commands for different memory spaces in the memory system) according to a weighted interleaving pattern that favors higher-priority commands while ensuring minimum execution throughput for lower-priority commands.

[0055] At point 202, multiple memory spaces can be configured at memory system 210, for example, during an initial or pre-deployment configuration procedure. As part of configuring the memory spaces, the memory of memory system 210 can be divided into multiple memory spaces, each of which can be configured to have a specific size (e.g., x gigabytes). In some instances, memory spaces are logical units. In other instances, memory spaces are partitions within logical units.

[0056] During the configuration process, one of the memory spaces can be represented as a high-priority memory space (e.g., a LUN is represented as one or more memory spaces as a high-priority LUN). Commands received for a high-priority memory space can be loaded into a high-priority memory queue and executed before commands stored in a low-priority memory queue. In some instances, a high-priority LUN can be specified in response to a command received during the configuration process. The identity of the high-priority LUN can be stored at memory system 210 and can be transmitted to the host system in the device descriptor UPIU. In particular, the identity of the high-priority LUN can be indicated in the bHighPriorityLUN field at offset 0Bh of the device descriptor UPIU, for example, by indicating the value of the LUN corresponding to the logical cell represented as a high-priority LUN. In some instances, the bHighPriorityLUN parameter defines the high-priority logical cell, wherein the valid values ​​of the bHighPriorityLUN parameter are in the range from zero (0) to the number of logical cells specified by the bMaxNumberLU parameter. In some instances, the bHighPriorityLUN parameter can be set to hex:7F to indicate that all memory spaces have the same priority (e.g., there is no high-priority LUN).

[0057] As mentioned above, parameters for each memory space can be specified during the configuration process. These parameters may include the number of allocation units assigned to the logical unit, the logical block size of the memory space, the type of memory in the memory space, and so on. Parameters may also include memory space-level priority parameters (which may be called priorities, or bLUNPriorityScore). For example, during the configuration process, configured memory spaces can be assigned different priorities, for example, in response to one or more configuration commands. For example, a first memory space may be assigned a first priority, a second memory space may be assigned a second priority, and a third memory space may be assigned a third priority. In some instances, the assigned priority is selected from a set of available priority values ​​(e.g., 0 to 255, where 255 can be the highest priority). In some instances, the memory system may contain a fourth logical unit, but may not receive configuration commands for the fourth logical unit. In such cases, the memory system may assign the fourth memory space the lowest priority (e.g., 0) based on not receiving configuration commands for the fourth logical unit.

[0058] The priority assigned to each memory space can be independent of the high-priority memory space representation. Therefore, in some cases, a memory space represented as a high-priority memory space can also be assigned a memory space-level priority. In some instances, the priority assigned to a memory space-level priority can be lower than the highest memory space-level priority. In such cases, the high-priority memory space representation can override the memory space-level priorities described herein.

[0059] At point 206, the priority of the memory space can be indicated to the host system 205. In some instances, the priority of the memory space can be indicated to the host system 205 in response to a request from the host system 205 for a cell descriptor UPIU (e.g., in the bLUNPriorityScore field of the cell descriptor UPIU, which may be located at offset 30h of the cell descriptor UPIU). In some instances, the host system 205 can be configured to store different data in different memory spaces based on different priorities. For example, the host system 205 can be configured to store higher priority data (e.g., operationally critical data, safety-critical data) in a memory space represented as a higher priority, relative to lower priority data (e.g., media) stored in a memory space represented as a lower priority.

[0060] At 209, a command sequence can be received from host system 205. The command sequence may contain multiple sets of commands for multiple memory spaces. In some instances, the command sequence includes a first command associated with a first memory space having a first priority, a second command associated with a second memory space having a second priority, and a third command associated with a third memory space having a third priority.

[0061] At 212, the sequence of commands received from host system 205 can be loaded into the command queue at memory system 210 (e.g., according to reference herein). Figure 1 (Similar to the method described in command queue 160). In some instances, the command sequence is loaded into the command queue in the order in which the commands in the command sequence are received at memory system 210. In some instances, the commands in the command sequence stored in the command queue include a first command associated with a first memory space having a first priority, a second command associated with a second memory space having a second priority, and a third command associated with a third memory space having a third priority.

[0062] At point 216, interleaving mode can be activated to execute commands in the command queue. In some instances, interleaving mode is activated based on an identifier that commands stored in the command queue target multiple memory spaces. Alternatively, interleaving mode can be activated based on an identifier that the number of commands in the command queue exceeds a threshold. In some instances, a transition from normal mode, where commands in the command queue are executed according to the order in which they were loaded into the command queue, to interleaving mode can be made (but commands targeting high-priority memory spaces can be loaded into high-priority memory queues, and other commands in the command queue and / or normal-priority memory queues are executed before them).

[0063] At point 219, commands in the command queue can be passed to the storage queue (e.g., as referenced in this article). Figure 1 (Similar to the storage queue 170 described above). Commands in the command queue can be loaded into the storage queue according to an interleaving mode (e.g., based on the interleaving mode being activated). In such cases, the order in which commands are loaded into the storage queue may differ from the order in which commands are loaded into the command queue. In some instances, the interleaving mode is an interleaving cyclic algorithm that weights commands in the command queue according to their respective priorities, while being configured to maintain a lower bound on the access throughput of the memory space of the memory system. Therefore, in some instances, commands associated with higher-priority memory spaces can be loaded into the storage queue more frequently and in larger batches than commands associated with lower-priority memory spaces, while still ensuring that lower-priority commands are served promptly.

[0064] At position 222, commands loaded into the storage queue can be executed, for example, according to interleaved mode. In some instances, commands in the storage queue can be executed in the order they were loaded into the storage queue.

[0065] At 226, commands associated with a memory space represented as a high-priority memory space can be received at memory system 210. In some instances, commands associated with a high-priority memory space can be automatically assigned the highest priority in this set of priorities (if not already assigned).

[0066] At point 229, commands associated with high-priority memory spaces can be loaded into the storage queue according to an interleaving mode. For example, the interleaving mode may favor commands associated with high-priority memory spaces over commands from other memory spaces. In some instances, commands associated with high-priority memory spaces may be loaded into a high-priority storage queue, separate from the interleaving mode. In some instances, commands in the high-priority storage queue may be executed before commands in the normal-priority storage queue; for example, the execution of commands in the normal-priority storage queue may be paused until all commands in the high-priority storage queue have been executed.

[0067] Various aspects of process flow 200 can be implemented by corresponding controllers at corresponding devices. Alternatively, aspects of process flow 200 can be implemented at corresponding devices as instructions stored in memory (e.g., firmware stored in memory coupled to the controller). For example, when executed by a controller at one of the corresponding devices, the instructions can cause the controller to perform the operation of process flow 200 performed by the device. Similarly, when executed by a controller at another corresponding device, the instructions can cause the controller to perform the operation of process flow 200 performed by the device.

[0068] One or more operations described in process flow 200 may be performed earlier or later, omitted, replaced, supplemented, or combined with another operation. Furthermore, additional operations described herein may replace, supplement, or combine with one or more operations described in process flow 200.

[0069] Figure 3 This illustrates instance queue operations for weighted distributed access in memory space, based on the examples disclosed herein.

[0070] Queue operation 300 describes the command flow through the memory system's command queue 360, high-priority storage queue 371, and normal-priority storage queue 372. In some instances, command queue 360 ​​may be the command queue described herein (e.g., Figure 1 An instance of command queue 160. In some instances, high-priority storage queue 371 and normal-priority storage queue 372 may be the storage queues described herein (e.g., Figure 1 This refers to a portion of the storage queue 170. In some instances, commands in the command queue 360 ​​can be retrieved in top-to-bottom order. In other instances, commands in the command queue 360 ​​can be retrieved in any order desired by the memory system. In some instances, commands in the high-priority storage queue 371 and the normal-priority storage queue 372 can be executed in right-to-left order.

[0071] In some instances, the host system may load command queue 360 ​​with commands for accessing data stored in the memory system. As described herein, commands may include a first command for a first memory space (e.g., a priority 0 command), a second command for a second memory space (e.g., a priority 1 command), and a third command for a third memory space (e.g., a priority 2 command). In some instances, commands may also include a fourth command for a memory space in the memory system that is represented as a high-priority memory space.

[0072] As described herein, in some instances, an application or host system can "fill" a command queue with priority 0 commands for accessing data in the memory system. In some instances, priority 0 commands are for lower-priority data stored in logical units with lower-priority LUNs (e.g., latency-resilient data, data that does not affect the operation of the application on the host system, data that does not affect the operation of the host system's operating system, etc.). Meanwhile, other applications or host systems may attempt to access the memory system. For example, an application or host system may send a priority 1 command for accessing data in the memory system. Priority 1 commands may be for data with a higher priority than the data associated with priority 0 commands (e.g., the data addressed by a priority 1 command may be latency-sensitive). Additionally, an application or host system may send a priority 2 command for accessing data in the memory system. Priority 2 commands may be for data with a higher priority than the data associated with priority 0 and 1 commands (e.g., the data addressed by a priority 2 command may be operationally critical to the application or host system, or may be associated with safety-critical data). Furthermore, an application or host system may send high-priority LUN commands. High-priority LUN commands can be directed to data with a priority higher than that of commands with priorities 0, 1, and 2 (for example, the data addressed by a high-priority LUN command can be safety-critical, such as data or code used to support autonomous driving).

[0073] As described herein, to support the proper execution of commands in command queue 360 ​​without leaving any part of the application "lacking" access to the memory system, the memory system can load commands into normal priority storage queue 372 according to a weighted interleaving pattern. However, in some instances, high-priority LUN commands can be loaded into high-priority storage queue 371, separate from other commands of different priorities stored in command queue 360. The weighted interleaving pattern ensures that the execution of higher-priority commands takes precedence over the execution of lower-priority commands (e.g., by scheduling higher-priority commands in larger batches compared to lower-priority commands), while also ensuring that lower-priority commands are executed with the lowest possible throughput.

[0074] Figure 4 A block diagram 400 illustrates a memory system 420 supporting weighted distributed access over memory space, according to an example disclosed herein. The memory system 420 may be a reference... Figures 1 to 3Examples of various aspects of the described memory system. Memory system 420 or its various components may be examples of constructs for performing various aspects of weighted distributed access over memory space as described herein. For example, memory system 420 may include command receiving component 425, command execution component 430, command storage component 435, priority component 440, or any combination thereof. Each of these components or components of its sub-components (e.g., one or more processors, one or more memories) may communicate directly or indirectly with each other (e.g., via one or more buses).

[0075] Command receiving component 425 may be configured or otherwise supported to receive a plurality of commands, the plurality of commands including a first command associated with a first memory space of a first priority in a memory system, a second command associated with a second memory space of a second priority in a memory system, and a third command associated with a third memory space of a third priority in a memory system. Command execution component 430 may be configured or otherwise supported to execute the plurality of commands using an interleaved mode according to the first priority, second priority, and third priority, based on the received plurality of commands.

[0076] In some instances, the command storage component 435 may be configured or otherwise support a means for storing the plurality of commands into a queue based on the received plurality of commands, wherein the plurality of commands are in an interleaved pattern and wherein the plurality of commands are executed using the order in which the plurality of commands are in the queue.

[0077] In some instances, command storage component 435 may be configured or otherwise support components for storing the plurality of commands in a second queue in the order in which the plurality of commands were received, before storing the plurality of commands in a queue, wherein the order in which the plurality of commands were received is different from the order in which the plurality of commands are in the queue.

[0078] In some instances, command receiving component 425 may be configured or otherwise support the following: upon receiving the plurality of commands, receiving a fourth command associated with a fourth memory space that is assigned the fourth priority among the plurality of priorities and represented as a high-priority memory space in the memory system. In some instances, priority component 440 may be configured or otherwise support the following: upon receiving the fourth command, for an interleaved mode, using the highest priority among the plurality of priorities for the fourth command, instead of using the fourth priority among the plurality of priorities.

[0079] In some instances, command execution component 430 may be configured or otherwise support components for: upon receiving the plurality of commands, identifying that the plurality of commands are associated with a plurality of memory spaces while in a first mode for executing commands, wherein the commands are executed in the order of receipt according to the first mode for executing commands. In some instances, command execution component 430 may be configured or otherwise support components for: upon receiving the plurality of commands and associating them with the plurality of memory spaces, activating a second mode for executing commands, wherein the plurality of commands are executed using an interleaved mode upon activation of the second mode for executing commands.

[0080] In some instances, command execution component 430 may be configured or otherwise support components for: recognizing, based on the received plurality of commands, that the number of the plurality of commands in the queue is greater than a threshold, wherein a second mode for executing commands is activated based on the number of the plurality of commands in the queue being greater than the threshold.

[0081] In some instances, the priority component 440 may be configured or otherwise support components for: receiving one or more commands during an initial configuration procedure, prior to receiving the plurality of commands, for configuring a first priority of a first memory space, a second priority of a second memory space, and a third priority of a third memory space. In some instances, the priority component 440 may be configured or otherwise support components for: assigning a first priority, a second priority, and a third priority to the first memory space, the second memory space, and the third memory space, respectively, using the corresponding commands from the one or more commands received.

[0082] In some instances, priority component 440 may be configured or otherwise support a component for allocating the lowest priority among the plurality of priorities to a fourth memory space prior to receiving the plurality of commands, based on the failure to receive a command for configuring the fourth priority among the plurality of priorities for the fourth memory space during the initial configuration procedure.

[0083] In some instances, priority component 440 may be configured or otherwise support components for indicating the appropriate priorities of multiple memory spaces of a memory system to one or more host systems prior to receiving the plurality of commands, the plurality of memory spaces including a first memory space, a second memory space, and a third memory space.

[0084] In some instances, the interleaved pattern is based on an interleaved loop algorithm that uses weighted averages of first, second, and third priorities.

[0085] In some instances, a memory system comprises multiple memory spaces, which contain one or more logical units, one or more partitions, or both.

[0086] In some instances, interleaved mode configuration serves as a lower bound for the memory space sustaining access throughput of the memory system.

[0087] In some instances, the second priority differs from the first priority, and the third priority differs from the first and second priorities.

[0088] In some instances, the described functionality of memory system 420 or its various components may be supported by at least one processor or may refer to at least a portion of at least one processor, wherein such at least one processor may comprise one or more processing elements (e.g., a controller, microprocessor, microcontroller, digital signal processor, state machine, discrete gate logic, discrete transistor logic, discrete hardware component, or any combination of one or more of such elements). In some instances, the described functionality of memory system 420 or its various components may be implemented at least in part by instructions executable by such at least one processor (e.g., stored in memory, non-transitory computer-readable medium).

[0089] Figure 5 A flowchart illustrating an example disclosed herein demonstrates a method 500 for supporting weighted distributed access over memory space. Operation of method 500 can be implemented by the memory system or its components described herein. For example, operation of method 500 can be provided by reference to... Figures 1 to 4 The described memory system performs the function. In some instances, the memory system can execute a set of instructions, and the functional elements of the control device perform the function. Alternatively, the memory system can use dedicated hardware to perform aspects of the function.

[0090] At 505, the method may include receiving a plurality of commands, including a first command associated with a first memory space of a first priority among a plurality of priorities allocated in a memory system, a second command associated with a second memory space of a second priority among the plurality of priorities allocated in a memory system, and a third command associated with a third memory space of a third priority among the plurality of priorities allocated in a memory system. In some instances, aspects of operation 505 may be referenced from [reference needed]. Figure 4 The command described is executed by receiving component 425.

[0091] At point 510, the method may include executing the plurality of commands using an interleaved pattern according to a first priority, a second priority, and a third priority, based on the received plurality of commands. In some instances, aspects of operation 510 may be referenced. Figure 4 The command execution component 430 described is executed.

[0092] In some instances, the device described herein may perform one or more methods, such as method 500. The device may include features, circuitry, logic, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) or any combination thereof for performing aspects of this disclosure:

[0093] Aspect 1: A method, apparatus, or non-transitory computer-readable medium comprising operations, features, circuitry, logic, components, or instructions, or any combination thereof, for: receiving a plurality of commands, each comprising a first command associated with a first memory space of a first priority assigned to a plurality of priorities in the memory system, a second command associated with a second memory space of a second priority assigned to a plurality of priorities in the memory system, and a third command associated with a third memory space of a third priority assigned to a plurality of priorities in the memory system; and, upon receiving the plurality of commands, executing the plurality of commands using an interleaving mode according to the first priority, the second priority, and the third priority.

[0094] Aspect 2: The method, apparatus, or non-transitory computer-readable medium according to aspect 1 further comprises an operation, feature, circuit system, logic, component, or instruction or any combination thereof for: storing the plurality of commands in a queue upon receiving the plurality of commands, wherein the order of the plurality of commands in the queue is using the interleaved mode, and wherein the plurality of commands are executed using the order of the plurality of commands in the queue.

[0095] Aspect 3: The method, apparatus, or non-transitory computer-readable medium according to aspect 2 further comprises an operation, feature, circuit system, logic, component, or instruction, or any combination thereof, for: storing the plurality of commands in a second queue in the order in which the plurality of commands are received, prior to storing the plurality of commands in the queue, wherein the order in which the plurality of commands are received is different from the order in which the plurality of commands are in the queue.

[0096] Aspect 4: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 3 further comprises an operation, feature, circuit system, logic, component, or instruction, or any combination thereof, for: receiving, upon receiving, a fourth command among the plurality of commands associated with a fourth memory space assigned a fourth priority among the plurality of priorities and represented as a high-priority memory space in the memory system; and, upon receiving, for the interleaving mode, using the highest priority among the plurality of priorities for the fourth command, instead of using the fourth priority among the plurality of priorities.

[0097] Aspect 5: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 4, further comprising an operation, feature, circuit system, logic, component, or instruction, or any combination thereof, for: upon receiving the plurality of commands, identifying the plurality of commands associated with a plurality of memory spaces while in a first mode for executing commands, wherein the commands are executed in the order of receipt according to the first mode for executing commands being activated; and activating a second mode for executing commands according to the plurality of commands being associated with the plurality of memory spaces, wherein the plurality of commands are executed using the interleaved mode according to the second mode for executing commands being activated.

[0098] Aspect 6: The method, device, or non-transitory computer-readable medium according to aspect 5 further includes an operation, feature, circuit system, logic, component, or instruction or any combination thereof for: identifying, upon receiving the plurality of commands, that the number of the plurality of commands in the queue is greater than a threshold, wherein the second mode for executing the commands is activated based on the number of the plurality of commands in the queue being greater than the threshold.

[0099] Aspect 7: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 6 further comprises an operation, feature, circuit system, logic, component, or instruction, or any combination thereof, for: receiving, during an initial configuration procedure, one or more commands for configuring a first priority of the first memory space, a second priority of the second memory space, and a third priority of the third memory space, prior to receiving the plurality of commands; and, based on receiving the one or more commands, assigning the first priority, the second priority, and the third priority to the first memory space, the second memory space, and the third memory space, respectively, using the corresponding command among the one or more commands.

[0100] Aspect 8: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 7 further comprises an operation, feature, circuit system, logic, component, or instruction or any combination thereof for: prior to receiving the plurality of commands, assigning the lowest priority of the plurality of priorities to the fourth memory space based on the failure to receive a command for configuring the fourth priority of the plurality of priorities for the fourth memory space during an initial configuration procedure.

[0101] Aspect 9: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 8 further comprises an operation, feature, circuit system, logic, component, or instruction or any combination thereof for: indicating to one or more host systems, prior to receiving the plurality of commands, the respective priorities of a plurality of memory spaces of the memory system, the plurality of memory spaces including the first memory space, the second memory space, and the third memory space.

[0102] Aspect 10: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 9, wherein the interleaving mode is based on an interleaving loop algorithm weighted using the first priority, the second priority, and the third priority.

[0103] Aspect 11: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 10, wherein the memory system comprises a plurality of memory spaces, which include one or more logical units, one or more partitions, or both.

[0104] Aspect 12: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 11, wherein the interleaving mode is configured as a lower limit for the memory space maintenance access throughput of the memory system.

[0105] Aspect 13: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 12, wherein the second priority is different from the first priority, and the third priority is different from both the first priority and the second priority.

[0106] It should be noted that the technology includes possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, two or more parts from the methods can be combined.

[0107] The information and signals described herein can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, or signaling symbols that may be referenced throughout the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof. Some diagrams may show a signal as a single signal; however, the signal may represent a signal bus, where the bus may have multiple bit widths.

[0108] The terms "electronic connectivity," "conductive contact," "connection," and "coupling" can refer to a relationship between components that supports the flow of signals between them. Components are considered electronically connected (or electrically contacting, connected, or coupled) to each other if any conductive path exists between them that supports the flow of signals at any given time. At any given time, the conductive path between components that are electronically connected (or electrically contacting, connected, or coupled) can be open or closed, depending on the operation of the device containing the connected components. The conductive path between connected components can be a direct conductive path between components, or an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some instances, the signal flow between connected components may be interrupted for a period of time, for example, using one or more intermediate components such as switches or transistors.

[0109] The term "coupling" (e.g., "electrical coupling") can refer to a condition that shifts from an open-circuit relationship between components to a closed-circuit relationship, in which a signal is currently unable to travel between components via a conductive path, and in which a signal can travel between components via a conductive path. If, for example, one component of a controller couples other components together, then that component triggers a change that allows signals to flow between those other components via conductive paths that were previously not permitted to allow signal flow.

[0110] The term "isolation" refers to a relationship between components where signals cannot currently flow between them. If there is an open circuit between components, they are isolated from each other. For example, components separated by a switch positioned between two components are isolated from each other when the switch is open. If a controller isolates two components, the controller achieves the following change: preventing signals from flowing between the components using previously permitted conductive paths.

[0111] As used in this article, the term “substantially” means that the modified feature (e.g., a verb or adjective modified by the term “substantially”) does not have to be absolute but is close enough to obtain the advantage of the feature.

[0112] The terms “if,” “when,” “based on,” or “at least partially based on” are used interchangeably. In some instances, these terms are used interchangeably if they describe the connection between conditional actions, conditional processes, or process parts.

[0113] The term "in response to" can refer to a condition or action that occurs at least partially (if not completely) as a result of a preceding condition or action. For example, a first condition or action may be executed and a second condition or action may occur at least partially as a result of the occurrence of a preceding condition or action (whether it occurs directly after or after one or more other intermediate conditions or actions that occur after the first condition or action).

[0114] Additionally, the terms "directly in response to" or "directly responding to" can refer to a condition or action that occurs as a direct result of a previous condition or action. In some instances, a first condition or action may be performed, and a second condition or action may occur directly as a result of a previous condition or action, regardless of whether other conditions or actions occur. In some instances, a first condition or action may be performed, and a second condition or action may occur directly as a result of a previous condition or action, such that no other intermediate conditions or actions occur between the earlier condition or action and the second condition or action, or a limited number of one or more intermediate steps or actions occur between the earlier condition or action and the second condition or action. Unless otherwise specified, any condition or action described herein as being performed "based on," "at least in part based on," or "in response to" a certain other step, action, event, or condition may additionally or alternatively (e.g., in alternative instances) be performed "directly in response to" or "directly responding to" such other conditions or actions.

[0115] The devices containing memory arrays discussed herein can be formed on semiconductor substrates, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some instances, the substrate is a semiconductor wafer. In other instances, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemicals containing (but not limited to) phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate, either by ion implantation or by any other doping method.

[0116] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include three-terminal devices comprising a source, drain, and gate. Terminals may be connected to other electronic components via a conductive material (e.g., a metal). The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or channels. If the channel is n-type (i.e., the majority of carriers are electrons), then the FET may be called an n-type FET. If the channel is p-type (i.e., the majority of carriers are holes), then the FET may be called a p-type FET. The channel may be end-capped by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can cause the channel to become conductive. If a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, then the transistor may be "on" or "activated." If a voltage less than the transistor's threshold voltage is applied to the transistor's gate, then the transistor may be "off" or "deactivated."

[0117] The description herein, illustrated with reference to the accompanying drawings, describes exemplary configurations and does not represent all instances that can be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description" and is not "preferred" or "advantageous" over other instances. The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques can be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described instances.

[0118] In the accompanying drawings, similar components or features may have the same reference numerals. Furthermore, various components of the same type can be distinguished by a hyphen following the reference numeral and a second numeral to differentiate them. If only the first reference numeral is used in the specification, the description applies to any of the similar components having the same first reference numeral, regardless of the second reference numeral.

[0119] The functions described herein can be implemented by hardware or software executed by a processing system (e.g., one or more processors, one or more controllers, control circuitry, processing circuitry, logic circuitry), firmware, or any combination thereof. If implemented as software executed by a processing system, the functions can be stored on a computer-readable medium or transmitted via a computer-readable medium as one or more instructions (e.g., code). Due to the nature of software, the functions described herein can be implemented using software executed by a processing system, hardware, firmware, hardwired, or any combination thereof. The features implementing the functions can be physically located in various locations, including distributed implementations, such that different parts of the functions are implemented at different physical locations.

[0120] The illustrative blocks and modules described herein may be implemented or executed by one or more processors designed to perform the functions described herein, such as DSPs, ASICs, FPGAs, discrete gate logic, discrete transistor logic, discrete hardware components, other programmable logic devices, or any combination thereof. The processor may be an instance of a microprocessor, controller, microcontroller, state machine, or other type of processor. The processor may also be implemented as at least one of one or more computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors incorporating a DSP chip, or any other such configuration).

[0121] As used herein (included in the claims), the word "or" in a list of items (e.g., a list of items ending with a phrase such as "at least one of" or "one or more of") indicates an inclusive list, such that a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase "based on" should not be construed as a reference to a set of closing conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "at least partially based on".

[0122] As used herein, including in the claims, the prefix "a" preceding a noun is open-ended and can be understood to mean "at least one" or "one or more" of these nouns. Therefore, the terms "a," "at least one," "one or more," and "at least one of one or more" are interchangeable. For example, if a claim states a "component" performing one or more functions, then each individual function can be performed by a single component or by any combination of multiple components. Therefore, the term "component having a characteristic or performing a function" can refer to "at least one of one or more components" having a particular characteristic or performing a particular function. Subsequent use of the term "the / said" to refer to a component introduced with the article "a" can refer to any one or all of the one or more components. For example, a component introduced with the article "a" can be understood as "one or more components," and subsequent reference to "the / said" in a claim can be understood as equivalent to referring to "at least one of the one or more components." Similarly, subsequent use of the term "the / said" to refer to a component as "one or more components" can refer to any one or all of the one or more components. For example, reference to "the one or more components" in the subsequent claims can be understood as equivalent to reference to "at least one of the one or more components".

[0123] Computer-readable media includes both non-transitory computer storage media and communication media, with communication media encompassing any media that facilitates the transfer of a computer program from one place to another. Non-transitory storage media can be any available media that can be accessed by a general-purpose or special-purpose computer. For example, and without limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), optical disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code components in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Furthermore, any connection is appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of media. As used herein, disks and optical discs include CDs, laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs, where disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of these items are also included within the scope of computer-readable media.

[0124] The description provided herein enables those skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein can be applied to other variations without departing from the scope of this disclosure. Therefore, the invention is not limited to the examples and designs described herein, but is given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A memory system comprising: One or more memory devices; as well as A processing circuitry system coupled to and configured to cause the memory system to: Receive multiple commands, including a first command associated with a first memory space of a first priority among multiple priorities allocated in the memory system, a second command associated with a second memory space of a second priority among multiple priorities allocated in the memory system, and a third command associated with a third memory space of a third priority among multiple priorities allocated in the memory system. as well as Upon receiving the plurality of commands, the plurality of commands are executed using an interleaved mode based on the first priority, the second priority, and the third priority.

2. The memory system of claim 1, wherein the processing circuitry is further configured to cause the memory system to: Upon receiving the plurality of commands, the plurality of commands are stored in a queue, wherein the order of the plurality of commands in the queue uses the interleaved pattern, and wherein the plurality of commands are executed using the order of the plurality of commands in the queue.

3. The memory system of claim 2, wherein the processing circuitry is further configured to cause the memory system to: Before storing the plurality of commands into the queue, the plurality of commands are stored into a second queue in the order in which they were received, the order in which the plurality of commands were received being different from the order in which the plurality of commands were in the queue.

4. The memory system of claim 1, wherein the processing circuitry is further configured to cause the memory system to: Based on the received plurality of commands, a fourth command among the plurality of commands is received that is associated with a fourth memory space that is assigned the fourth priority among the plurality of priorities and is represented as a high-priority memory space in the memory system; and Upon receiving the fourth command, for the interleaved mode, the highest priority among the plurality of priorities is used for the fourth command, instead of the fourth priority among the plurality of priorities.

5. The memory system of claim 1, wherein the processing circuitry is further configured to cause the memory system to: Based on the received plurality of commands, while in a first mode for executing commands, the plurality of commands are identified as being associated with a plurality of memory spaces, wherein the commands are executed in the order of receipt, having been activated according to the first mode for executing commands; and Based on the association of the plurality of commands with the plurality of memory spaces, a second mode for executing commands is activated, wherein the plurality of commands are executed using the interleaved mode based on the activation of the second mode for executing commands.

6. The memory system of claim 5, wherein the processing circuitry is further configured to cause the memory system to: Based on the received plurality of commands, the number of the plurality of commands in the queue is identified as being greater than a threshold, wherein the second mode for executing the commands is activated based on the number of the plurality of commands in the queue being greater than the threshold.

7. The memory system of claim 1, wherein the processing circuitry is further configured to cause the memory system to: Before receiving the plurality of commands, during the initial configuration procedure, one or more commands are received for configuring the first priority of the first memory space, the second priority of the second memory space, and the third priority of the third memory space; and Based on the received one or more commands, the first priority, the second priority, and the third priority are allocated to the first memory space, the second memory space, and the third memory space respectively using the corresponding commands among the one or more commands.

8. The memory system of claim 1, wherein the processing circuitry is further configured to cause the memory system to: Before receiving the plurality of commands, the lowest priority among the plurality of priorities is assigned to the fourth memory space based on the failure to receive a command for configuring the fourth priority among the plurality of priorities for the fourth memory space during the initial configuration procedure.

9. The memory system of claim 1, wherein the processing circuitry is further configured to cause the memory system to: Before receiving the plurality of commands, the respective priorities of a plurality of memory spaces of the memory system are indicated to one or more host systems, the plurality of memory spaces including the first memory space, the second memory space and the third memory space.

10. The memory system of claim 1, wherein the interleaving mode is based on an interleaving loop algorithm weighted by the first priority, the second priority, and the third priority.

11. The memory system of claim 1, wherein the memory system comprises a plurality of memory spaces, which include one or more logical units, one or more partitions, or both.

12. The memory system of claim 1, wherein the interleaving mode is configured as a lower limit for the memory space maintenance access throughput of the memory system.

13. The memory system of claim 1, wherein the second priority is different from the first priority, and the third priority is different from both the first priority and the second priority.

14. A non-transitory computer-readable medium storing code, the code comprising instructions executable by a processing circuitry of a memory system to cause the memory system to: Receive multiple commands, including a first command associated with a first memory space of a first priority among a plurality of priorities allocated in the memory system, a second command associated with a second memory space of a second priority among the plurality of priorities allocated in the memory system, and a third command associated with a third memory space of a third priority among the plurality of priorities allocated in the memory system; and Upon receiving the plurality of commands, the plurality of commands are executed using an interleaved mode based on the first priority, the second priority, and the third priority.

15. The non-transitory computer-readable medium of claim 14, wherein the instructions are further executable by the processing circuitry to cause the memory system to: Upon receiving the plurality of commands, the plurality of commands are stored in a queue, wherein the order of the plurality of commands in the queue uses the interleaved pattern, and wherein the plurality of commands are executed using the order of the plurality of commands in the queue.

16. The non-transitory computer-readable medium of claim 14, wherein the instructions are further executable by the processing circuitry to cause the memory system to: Based on the received plurality of commands, a fourth command among the plurality of commands is received that is associated with a fourth memory space that is assigned the fourth priority among the plurality of priorities and is represented as a high-priority memory space in the memory system; and Upon receiving the fourth command, for the interleaved mode, the highest priority among the plurality of priorities is used for the fourth command, instead of the fourth priority among the plurality of priorities.

17. The non-transitory computer-readable medium of claim 14, wherein the instructions are further executable by the processing circuitry to cause the memory system to: Based on the received plurality of commands, while in a first mode for executing commands, the plurality of commands are identified as being associated with a plurality of memory spaces, wherein the commands are executed in the order of receipt, having been activated according to the first mode for executing commands; and Based on the association of the plurality of commands with the plurality of memory spaces, a second mode for executing commands is activated, wherein the plurality of commands are executed using the interleaved mode based on the activation of the second mode for executing commands.

18. The non-transitory computer-readable medium of claim 14, wherein the instructions are further executable by the processing circuitry to cause the memory system to: Before receiving the plurality of commands, during the initial configuration procedure, one or more commands are received for configuring the first priority of the first memory space, the second priority of the second memory space, and the third priority of the third memory space; and Based on the received one or more commands, the first priority, the second priority, and the third priority are allocated to the first memory space, the second memory space, and the third memory space respectively using the corresponding commands among the one or more commands.

19. The non-transitory computer-readable medium of claim 14, wherein the instructions are further executable by the processing circuitry to cause the memory system to: Before receiving the plurality of commands, the lowest priority among the plurality of priorities is assigned to the fourth memory space based on the failure to receive a command for configuring the fourth priority among the plurality of priorities for the fourth memory space during the initial configuration procedure.

20. The non-transitory computer-readable medium of claim 14, wherein the instructions are further executable by the processing circuitry to cause the memory system to: Before receiving the plurality of commands, the respective priorities of a plurality of memory spaces of the memory system are indicated to one or more host systems, the plurality of memory spaces including the first memory space, the second memory space and the third memory space.

21. A method performed by a memory system, comprising: Receive multiple commands, including a first command associated with a first memory space of a first priority among multiple priorities allocated in the memory system, a second command associated with a second memory space of a second priority among multiple priorities allocated in the memory system, and a third command associated with a third memory space of a third priority among multiple priorities allocated in the memory system. as well as Upon receiving the plurality of commands, the plurality of commands are executed using an interleaved mode based on the first priority, the second priority, and the third priority.

22. The method of claim 21, further comprising: Upon receiving the plurality of commands, the plurality of commands are stored in a queue, wherein the order of the plurality of commands in the queue uses the interleaved pattern, and wherein the plurality of commands are executed using the order of the plurality of commands in the queue.

23. The method of claim 21, further comprising: According to the received plurality of commands, a fourth command is received that is associated with a fourth memory space that is assigned the fourth priority among the plurality of priorities and is represented as a high-priority memory space in the memory system; as well as Upon receiving the fourth command, for the interleaved mode, the highest priority among the plurality of priorities is used for the fourth command, instead of the fourth priority among the plurality of priorities.

24. The method of claim 21, further comprising: Based on the received plurality of commands, when in a first mode for executing commands, the plurality of commands are identified as being associated with a plurality of memory spaces, wherein the commands are executed in the order of receipt based on the activation of the first mode for executing commands; as well as Based on the association of the plurality of commands with the plurality of memory spaces, a second mode for executing commands is activated, wherein the plurality of commands are executed using the interleaved mode based on the activation of the second mode for executing commands.

25. The method of claim 21, further comprising: Before receiving the plurality of commands, during the initial configuration procedure, one or more commands are received for configuring the first priority of the first memory space, the second priority of the second memory space, and the third priority of the third memory space; as well as Based on the received one or more commands, the first priority, the second priority, and the third priority are allocated to the first memory space, the second memory space, and the third memory space respectively using the corresponding commands among the one or more commands.

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