Memory system and memory controller

Abstract

This invention provides a memory system capable of appropriately controlling the write mode. According to an embodiment, the memory system includes a non-volatile memory and a memory controller for controlling the non-volatile memory. The memory controller is configured to: as a mode for writing data to the non-volatile memory, corresponding to a first write mode that writes 1 bit of data to each memory cell and a second write mode that writes N bits of data to each memory cell, when the capacity of the write data is below a threshold related to the execution of garbage collection, write the write data to the non-volatile memory using the first write mode; when the capacity of the write data exceeds the threshold, write at least (the amount exceeding the threshold) + ((the amount exceeding the threshold) / (N-1)) of the write data to the non-volatile memory using the second write mode, and write the remaining write data to the non-volatile memory using the first write mode.

Description

Technical Field

[0001] Embodiments of the present invention relate to a memory system and a memory controller. Background Technology

[0002] In recent years, flash memory systems have become widely used. Currently, memory systems, such as TLC (Triple Level Cell) products, support both TLC and SLC (Single Level Cell) writing methods. Additionally, QLC (Quad Level Cell) products support both QLC and SLC writing methods.

[0003] Compared to TLC or QLC writing, SLC writing offers higher sequential write performance. Therefore, some TLC or QLC products also include features like WB (Write Booster) to effectively utilize the superior sequential write performance of SLC when needed.

[0004] However, there are also concerns about SLC writing, such as a deterioration in WAF (Write Amplification Factor) and performance degradation caused by GC (Garbage Collection) due to the limited physical capacity of flash memory. Summary of the Invention

[0005] The present invention provides a memory system and a memory controller capable of appropriately controlling the writing mode.

[0006] According to one embodiment, the memory system includes non-volatile memory and a memory controller. The non-volatile memory has multiple blocks, each containing multiple memory cells. The memory controller can be connected to a host computer and control the non-volatile memory. The memory controller is configured to: as a method of writing data to non-volatile memory, there are a first write method that writes 1 bit of data to each memory cell and a second write method that writes N (N is a natural number greater than 2) bits of data to each memory cell. When a write command is received from the host to use the first write method, it determines whether the capacity of the write data exceeds a threshold obtained by subtracting a predetermined value from the remaining capacity of the non-volatile memory. The predetermined value represents the remaining capacity of the non-volatile memory after garbage collection to increase the remaining capacity of the non-volatile memory. When the capacity of the write data is below the threshold, the write data is written to the non-volatile memory using the first write method. When the capacity of the write data exceeds the threshold, at least (the excess amount of the threshold) + ((the excess amount of the threshold) / (N-1)) of the write data is written to the non-volatile memory using the second write method, and the remaining write data is written to the non-volatile memory using the first write method. Attached Figure Description

[0007] Figure 1 This is a diagram illustrating a configuration example of the memory system according to the first embodiment.

[0008] Figure 2 This is a graph showing an example of a comparison between write times using SLC (with GC) and write times using MLC (without GC).

[0009] Figure 3 This is a flowchart illustrating the data write process of the memory system in the first embodiment.

[0010] Figure 4 This is a diagram illustrating a configuration example of the memory system according to the second embodiment.

[0011] Figure 5 This is a flowchart illustrating the data write process of the memory system in the second embodiment.

[0012] Figure 6 This is a diagram illustrating a configuration example of the memory system according to the third embodiment.

[0013] Figure 7 This diagram illustrates an example of a flash memory writing method defined by the first flag (fWriteBoosterEn flag) and the second flag (fWriteBoosterMLC flag) in the memory system of the third embodiment.

[0014] Figure 8This is a flowchart illustrating the data write process of the memory system in the third embodiment.

[0015] Figure 9 This is a diagram illustrating a configuration example of the memory system according to the fourth embodiment.

[0016] Figure 10 This is a diagram illustrating an example of a table for selecting the write mode of the memory system in the fourth embodiment.

[0017] Figure 11 It is a graph representing the transfer performance of elements for each HS-GEAR as defined by the UFS (Universal Flash Storage) 4.0 standard.

[0018] Figure 12 This is a graph representing the maximum write performance for each performance level.

[0019] Figure 13 It is a graph that shows the write performance of each level in each write mode.

[0020] Figure 14 This is a flowchart illustrating the data write processing flow of the memory system in the fourth embodiment.

[0021] Figure 15 This is a flowchart illustrating a variation of the data write process of the memory system in the fourth embodiment.

[0022] Figure 16 This is a flowchart illustrating the data write process of the memory system in the fifth embodiment. Detailed Implementation

[0023] Hereinafter, the embodiments will be described with reference to the accompanying drawings.

[0024] (First Embodiment)

[0025] First, the first embodiment will be described.

[0026] Figure 1 This is a diagram illustrating a configuration example of the memory system 1 according to the first embodiment. Figure 1 The diagram shows a memory system 1 connected to a host 2 and forming an information processing system together with the host 2. The host 2 is an information processing device such as a personal computer or a server.

[0027] The memory system 1 has a controller (memory controller) 10 and flash memory 20.

[0028] Controller 10 is a device for controlling flash memory 20. Specifically, controller 10 controls the writing process of data to flash memory 20 or the reading process of data from flash memory 20 according to commands from host 2. In order to manage flash memory 20, regardless of the commands from host 2, controller 10 may spontaneously control the writing process of data to flash memory 20 or the reading process of data from flash memory 20. Controller 10 is implemented in the form of SoC (System on a Chip) or similar.

[0029] Flash memory 20 is a non-volatile storage medium, meaning data cannot be overwritten to areas where data has already been written. Therefore, updating data stored in flash memory 20 is achieved by invalidating the old data and writing new data to other areas. Areas storing invalidated data are erased and become reusable. Flash memory 20 has multiple blocks, each containing multiple memory cells. Erasing is performed on a block-by-block basis. A block that becomes writable after erasing is called a free block, etc. Furthermore, data is written to flash memory 20 on a page-by-page basis, with each block containing a predetermined number of pages.

[0030] The flash memory 20, under the control of the controller 10, is divided into a system data storage area 21 and a user data storage area 22. The host 2 is provided with the user data storage area 22. The system data storage area 21 stores data used by the controller 10 to control the memory system 1 as a whole.

[0031] The controller 10 includes a host interface unit (host I / F unit) 11, a memory interface unit (memory I / F unit) 12, a read / write processing unit (RW processing unit) 13, a memory region management unit 14, and a GC processing unit 15. Here, it is illustrated that the host I / F unit 11 and the memory I / F unit 12 of the controller 10 are implemented by hardware such as circuitry. Furthermore, the RW processing unit 13, the memory region management unit 14, and the GC processing unit 15 are implemented by the CPU (Central Processing Unit) 100 built into the controller 10, executing a program called firmware. The RW processing unit 13, the memory region management unit 14, and the GC processing unit 15 may also be implemented by hardware such as circuitry, similar to the host I / F unit 11 or the memory I / F unit 12.

[0032] The host I / F unit 11, for example, performs control in order to transmit data via PCIe. TM The standard interface connects to host 2, and conforms to NVMe standards. TM The standard protocol is used to communicate with host 2.

[0033] The memory I / F section 12 controls the writing of data to the flash memory 20 and the reading of data from the flash memory 20.

[0034] When the RW processing unit 13 receives a read command through the host I / F unit 11, it reads the requested data (read data) from the flash memory 20 via the memory I / F unit 12. The RW processing unit 13 then sends the read data read from the flash memory 20 via the memory I / F unit 12 to the host 2 via the host I / F unit 11.

[0035] Furthermore, when the RW processing unit 13 receives a write command through the host I / F unit 11, it writes the requested data (write data) to the flash memory 20 via the memory I / F unit 12. When the write data to the flash memory 20 is successfully written, the RW processing unit 13 notifies the host 2 of the write completion via the host I / F unit 11.

[0036] The RW processing unit 13 has a WB unit 131. The WB unit 131 is a module set up to implement the WB function and manages the first flag (fWriteBoosterEn flag) indicating the writing method to be used by the RW processing unit 13. The first flag is a flag according to the current WB specification.

[0037] The flash memory 20 has multiple blocks, each containing multiple memory cells. The RW processing unit 13, in cooperation with the memory I / F unit 12, can perform both SLC (Single-Level Cell) writes (writing 1 bit of data) and MLC (Multi-Level Cell) writes (writing 2 bits of data) to each memory cell of the flash memory 20. During the period when the first flag is on, the RW processing unit 13 writes the data to the flash memory 20 in an SLC manner. When the first flag is off, the RW processing unit 13 writes the data to the flash memory 20 in an MLC manner. Hereinafter, an example is shown where the memory system 1 of the embodiment supports both SLC and MLC writes, but it is not limited to this. For example, it may also support SLC writes and TLC writes (writing 3 bits of data to each memory cell). Alternatively, it may support all three: SLC writes, MLC writes, and TLC writes. Hereinafter, the SLC write performed when the first flag is on will sometimes be referred to as a write using WB, etc.

[0038] Additionally, the write performance for each write method is set as follows: SLC write 3800 MiBps, MLC write 2500 MiBps, TLC write 835 MiBps, and QLC write 69 MiBps. The write performance of a write method refers to its write capability per fixed time interval.

[0039] The first flag managed by WB section 131 can be toggled on / off via a command called QUERY REQUEST. In other words, host 2 can specify whether to use SLC or MLC writing to write data to flash memory 20. Specifically, host 2 can select SLC writing when needed by toggling the first flag to on.

[0040] SLC writing offers higher sequential write performance compared to MLC writing. However, SLC writing consumes twice the storage area of ​​MLC writing and may experience performance degradation due to garbage collection (GC). Therefore, in the first embodiment of the memory system 1, where SLC writing is specified during the period when the first flag is enabled, writing all data in SLC mode may actually lead to performance degradation. In this case, performance degradation is suppressed by spontaneously changing part or all of the data writing to MLC writing. This aspect will be described below.

[0041] The memory region management unit 14 manages the status of the flash memory 20. As information indicating the status of the flash memory 20, the memory region management unit 14 manages, for example, the remaining capacity of the flash memory 20.

[0042] When the remaining capacity of the flash memory 20 managed by the memory region management unit 14 is lower than a predetermined value, the GC processing unit 15 performs GC processing to generate free blocks. GC processing generates, for example, a free block (number of source blocks) by moving valid data from two or more blocks where the proportion of regions storing invalid data is relatively large to one block. Information related to the proportion of regions storing invalid data in each block is managed by the memory region management unit 14.

[0043] As described above, the memory region management unit 14 manages the remaining capacity of the flash memory 20. Therefore, it can calculate how much region will be consumed afterward to reduce the remaining capacity of the flash memory 20 below a predetermined value. When the RW processing unit 13 writes data to the flash memory 20 in SLC mode during the period when the first flag is enabled, it first subtracts a predetermined value from the remaining capacity of the flash memory 20 to calculate a threshold representing the amount of data that can be written in SLC without GC. Next, the RW processing unit 13 determines whether the calculated threshold does not exceed the amount of data to be written. If the amount of data to be written exceeds the threshold, the RW processing unit 13 decides to perform SLC writing and MLC writing in a combined manner to maximize SLC writing within the range of GC without GC.

[0044] Specifically, the RW processing unit 13 performs MLC writing on twice the amount of written data that exceeds the threshold, and performs SLC writing on the remaining amount. The order of MLC writing and SLC writing is not important. By changing a portion to MLC writing to avoid GC, the memory system 1 of the first embodiment can suppress performance degradation compared to the case where all written data is written by SLC as specified.

[0045] Through the above controls, if GC can be performed and completed after the write data is written to flash memory 20 without GC, and before the next write command is received from host 2, then GC will not occur during the writing of the next write data, thereby suppressing performance degradation. Even if the next write command is received from host 2 during GC, the impact of GC can be mitigated.

[0046] Figure 2 This is a graph showing an example of a comparison between write times using SLC (with GC) and write times using MLC (without GC).

[0047] Here, we consider a situation where, during a 5 GiB write operation, writing up to 4 GiB using the SLC method would exceed the threshold for garbage collection (GC). In this case, in the memory system 1 of the first embodiment, for example, 3 GiB is written using SLC, and the remaining 2 GiB is written using MLC. Figure 2 (Symbol a1). In the case shown by symbol a2, where all 5 GiB is written using SLC, GC will occur, which will lead to a decrease in performance.

[0048] Furthermore, when the memory system 1 in the first embodiment supports both SLC writing and TLC writing, the RW processing unit 13 only needs to perform TLC writing on the data to be written (the amount exceeding the threshold) + ((the amount exceeding the threshold) / 2). In other words, when the memory system 1 in the first embodiment supports both SLC writing and writing N bits of data to each storage cell of the flash memory 20, the RW processing unit 13 only needs to write the data to be written using the latter method, by adding ((the amount exceeding the threshold) / N-1).

[0049] Figure 3 This is a flowchart illustrating the data write process of the memory system 1 in the first embodiment.

[0050] RW processing unit 13 determines whether the first flag (fWriteBoosterEn flag) is enabled (S101). If the first flag is disabled (S101: No), RW processing unit 13 writes all write data to flash memory 20 in MLC mode (S102). In addition, even if the first flag is disabled, SLC writing may be performed by meeting other conditions that should be met for SLC writing, but here we only focus on WB.

[0051] When the first flag is enabled (S101: YES), the RW processing unit 13 determines whether the amount of data to be written exceeds the threshold (S103). The threshold is the amount of data that can be written in SLC without GC. If the amount of data to be written does not exceed the threshold (S103: No), the RW processing unit 13 writes all the data to the flash memory 20 in SLC mode (S104).

[0052] If the amount of data written exceeds the threshold (S103: Yes), the RW processing unit 13 writes twice the amount of data to the flash memory 20 in MLC mode (S105), and writes the remaining data to the flash memory 20 in SLC mode (S106). The order of MLC writing in S105 and SLC writing in S106 can also be reversed.

[0053] As described above, in the first embodiment of the memory system 1, if all write data is written in SLC during the period when the first flag is enabled, the performance may be reduced. In this case, the performance reduction is suppressed by changing part or all of the write data to MLC write.

[0054] In other words, the memory system 1 of the first embodiment can appropriately control the writing mode.

[0055] (Second Implementation)

[0056] Next, the second embodiment will be described.

[0057] Figure 4 This is a diagram illustrating a configuration example of the memory system 1-2 according to the second embodiment. The same reference numerals are used for the same components as in the memory system 1 of the first embodiment, and their descriptions are omitted.

[0058] The controller 10-2 of the second embodiment, in addition to having the configuration of the controller 10 of the first embodiment, also has a command analysis unit 16. Here, an example is shown in which the command analysis unit 16 is implemented by the CPU 100 executing a program such as firmware, but the command analysis unit 16 may also be implemented by hardware such as circuitry.

[0059] When the command analysis unit 16 receives a write command from the host 2, it analyzes the write command or the functions associated with it to determine whether SLC writing should be used. In the memory system 1 of the first embodiment, the determination of whether to use SLC writing for the write command from the host 2 is based on whether the first flag (fWriteBoosterEn flag) is enabled. In contrast, in the memory system 1-2 of the second embodiment, when the first flag is disabled, the command analysis unit 16 further determines whether to use SLC writing for the write command from the host 2.

[0060] For example, FUA (Force Unit Access) is a parameter that instructs the write data not to be stored in the cache, thus quickly making it non-volatile. Specifically, by attaching FUA set to "1" with a write command, the write data can be quickly made non-volatile. The command analysis unit 16 determines that an SLC write should be performed on the write command that is accompanied by FUA set to "1". In addition to FUA, the command analysis unit 16 can also store various determination conditions.

[0061] If the command analysis unit 16 determines that SLC writing should be used, similar to the memory system 1 of the first embodiment, the RW processing unit 13-2 determines whether the amount of data to be written in the write command does not exceed a threshold. If the amount of data to be written does not exceed the threshold, the RW processing unit 13 decides to perform SLC writing on all the data. On the other hand, if the amount of data to be written exceeds the threshold, the RW processing unit 13 decides to perform SLC writing and MLC writing in a combined manner to maximize SLC writing without causing garbage collection (GC). The write amounts for SLC and MLC are calculated in the same manner as in the memory system 1 of the first embodiment.

[0062] Figure 5 This is a flowchart illustrating the data write process of the memory system 1-2 in the second embodiment. Here, the example is taken where the memory system 1-2 in the second embodiment supports both SLC write and MLC write.

[0063] Command analysis unit 16 analyzes the write command from host 2 (S201). If command analysis unit 16 determines that SLC writing should not be used (S202: No), RW processing unit 13 writes all write data to flash memory 20 in MLC mode (S203).

[0064] If the analysis indicates that SLC writing should be used (S202: Yes), the RW processing unit 13 determines whether the amount of data to be written exceeds a threshold (S204). The threshold is the amount of data that can be written using SLC without GC. If the amount of data to be written does not exceed the threshold (S204: No), the RW processing unit 13 writes all the data to the flash memory 20 using SLC (S205).

[0065] If the amount of data written exceeds the threshold (S204: Yes), the RW processing unit 13 writes twice the amount of data exceeding the threshold to the flash memory 20 in MLC mode (S206), and writes the remaining data to the flash memory 20 in SLC mode (S207). The order of the TLC writing in S206 and the SLC writing in S207 can also be reversed.

[0066] As described above, when the memory system 1-2 of the second embodiment receives a write command that should be performed by SLC writing, if all the write data is written by SLC, it may actually lead to a performance reduction. In this case, similar to the memory system 1 of the first embodiment, the performance reduction is suppressed by changing part or all of the write data to MLC writing.

[0067] In other words, the memory system 1-2 of the second embodiment can also appropriately control the writing method.

[0068] (Third Implementation)

[0069] Next, the third embodiment will be described.

[0070] Figure 6 This is a diagram illustrating a configuration example of the memory system 1-3 according to the third embodiment. The same reference numerals are used for the same components as in the memory system 1 of the first embodiment, and their descriptions are omitted.

[0071] In the controller 10-3 of the third embodiment, the RW processing unit 13-3 further includes an extended WB unit 132. The extended WB unit 132 is a module provided to extend the WB functionality implemented by the WB unit 131, and manages the second flag (fWriteBoosterMLC flag). The second flag is not present in the current WB specification and is a flag independently added to the memory system 1-3 of the third embodiment.

[0072] The second flag functions when the first flag (fWriteBoosterEn flag) is enabled. When the first flag is disabled, the second flag is also disabled. Like the first flag, the second flag can also be toggled on / off via commands from host 2.

[0073] With the first flag enabled and the second flag disabled, the RW processing unit 13-3 writes the write data requested by the write command to the flash memory 20 via SLC writing, in accordance with the current WB specification.

[0074] On the other hand, when both the first and second flags are enabled, the RW processing unit 13-3 writes the write data requested by the write command to the flash memory 20 via MLC write. That is, in the memory system 1-3 of the third embodiment, the host 2 can instruct not only SLC write but also MLC write.

[0075] With the first flag off, the RW processing unit 13-3 basically writes the write data requested by the write command to the flash memory 20 via MLC write. However, there are no specification limitations; the RW processing unit 13-2 can also perform SLC write, and if TLC write is supported, it can also perform TLC write.

[0076] In addition, Figure 6 In this embodiment, the memory region management unit 14 and the GC processing unit 15 are omitted. This does not mean that the controller 10-3 in the third embodiment does not have the memory region management unit 14 and the GC processing unit 15.

[0077] Figure 7 This is a diagram illustrating an example of the write mode of the flash memory 20 as defined by the first flag (fWriteBoosterEn flag) and the second flag (fWriteBoosterMLC flag).

[0078] With the first flag on (FLG_ON) and the second flag off (FLG_OFF), the RW processing unit 13-2 writes the write data requested by the write command to the flash memory 20 in SLC mode (SLC fixed).

[0079] In addition, when both the first and second flags are enabled, the RW processing unit 13-2 performs MLC writing (MLC fixed).

[0080] With the first flag off, the RW processing unit 13-2 writes the write data to the flash memory 20 using arbitrary write mode (arbitrary write mode).

[0081] Figure 8 This is a flowchart illustrating the data write process of the memory system 1-3 in the third embodiment.

[0082] RW processing unit 13 determines whether the first flag (fWriteBoosterEn flag) is turned on (S301). If the first flag is turned on (S301: Yes), RW processing unit 13 then determines whether the second flag (fWriteBoosterMLC flag) is turned on (S302).

[0083] When the second flag is enabled (S301: Yes), the RW processing unit 13 writes the write data to the flash memory 20 in MLC mode (S303). On the other hand, when the second flag is disabled (S301: No), the RW processing unit 13 writes the write data to the flash memory 20 in SLC mode (S303).

[0084] In addition, when the first flag is off (S301: NO), the RW processing unit 13 writes the write data to the flash memory 20 using an arbitrary write mode (S305).

[0085] As described above, in the memory system 1-3 of the third embodiment, the host 2 can instruct not only SLC writing but also MLC writing.

[0086] In other words, the memory system 1-3 of the third embodiment can also appropriately control the writing method.

[0087] (Fourth implementation)

[0088] Next, the fourth embodiment will be described.

[0089] Figure 9 This is a diagram illustrating a configuration example of the memory system 1-4 according to the fourth embodiment. The same reference numerals are used for the same components as in the memory system 1-2 of the second embodiment, and their descriptions are omitted.

[0090] The data transfer speed between host 2 and memory systems 1-4 depends on the transfer rate set between host 2 and memory systems 1-4. For example, even if SLC writing is performed in pursuit of higher SLC performance, the performance can only be equal to or lower than that of MLC, depending on the transfer rate.

[0091] Therefore, the controller 10-4 in the fourth embodiment includes a write performance determination unit 17. The write performance determination unit 17 determines, based on the transfer rate, whether the write mode specified by the host 2 can achieve the maximum write performance achievable by that write mode. Furthermore, the write performance determination unit 17 determines the write mode with the best WAF (Write-Off Function) among those write modes that can achieve maximum write performance using that transfer rate. In other words, the write performance determination unit 17 determines the write mode with superior write capability per fixed time. If, due to the transfer rate limitation, the write capability per unit time of each write mode is not different, the write performance determination unit 17 determines the write mode with the lowest WAF. The RW processing unit 13 in the memory system 1-4 of the fourth embodiment implements changes to the write mode as needed based on the determination result of the write performance determination unit 17.

[0092] For example, in MIPI TM In the Mobile Industry Processor Interface (MIMI) standard, transmission rates are referred to as tiers, etc. The UFS (Universal Flash Storage) 4.0 standard specifies five transmission rates: HS-GEAR1 to HS-GEAR5. HS-GEAR1 is the lowest transmission rate, and HS-GEAR5 is the highest transmission rate.

[0093] In addition, the controller 10-4 of the fourth embodiment has a writing mode selection table 31. Figure 10 This is a diagram showing an example of the write mode selection using Table 31.

[0094] The write mode selection table 31 is, for example, set in the SRAM (Static RAM [Random Access Memory]) built into the controller 10-4. The write mode selection table 31 is a table referred to by the write performance determination unit 17 to determine the write mode that can achieve the maximum write performance based on the transfer rate.

[0095] like Figure 10 As shown in Table 31, the write mode selection is configured by setting the vertical axis to a gear and the horizontal axis to the write mode specified by the host 2, saving the data obtained by configuring numbers 1 to 4 in a matrix. For example, 1 represents SLC write, 2 represents MLC write, 3 represents TLC write, and 4 represents QLC write.

[0096] For example, when the gear is HS-GEAR1 and the write mode specified by the host 2 is SLC or MLC, maximum write performance cannot be achieved in SLC or MLC writes; TLC writes achieve maximum write performance. Therefore, the write performance determination unit 17, after referring to the write mode selection table 31, decides to change the write mode from SLC or MLC to TLC. In the case of TLC or QLC, since maximum write performance can be achieved, the write performance determination unit 17, after referring to the write mode selection table 31, decides not to change the write mode.

[0097] In other words, Table 31 stores information (1-4) indicating the actual write mode to be used for each combination of the file position and the write mode specified by the host 2.

[0098] When the gear is HS-GEAR2, just like HS-GEAR1, SLC and MLC cannot achieve the maximum write performance of these write methods. The write methods that can achieve the maximum write performance are TLC and QLC. Therefore, if the specified write method is SLC or MLC, change it to TLC. If the specified write method is TLC or QLC, do not change it.

[0099] With the gear settings HS-GEAR3 and HS-GEAR4, MLC becomes the write mode that can achieve the maximum write performance. Therefore, you only need to change to TLC if the specified write mode is SLC. No change is needed if the settings are MLC, TLC or QLC.

[0100] When the gear is set to HS-GEAR5, SLC becomes the write mode that can achieve the maximum write performance, and this will not change even if any write mode is specified.

[0101] Figure 11 This is a graph showing the transmission performance of components for each gear (HS-GEAR) as defined by the UFS 4.0 standard. Additionally, it shows an example of a 2-lane component with a REF_CLK frequency value of 38.4MHz in the Rate B series.

[0102] Due to system updates or header overhead, SLC's write performance is 3800 MiBps, so its overhead is assumed to be 0.1467s. The maximum write performance for each tier is as follows: Figure 12 As shown. Figure 12 This is a graph representing the maximum write performance for each performance level.

[0103] in addition, Figure 13It is a graph that shows the write performance of each level in each write mode.

[0104] For example, looking at the HS-GEAR4, we know that the write performance of SLC and MLC is the same, and the write performance is limited by the level. In this case, even if SLC is used for writing, it can only achieve the same performance as MLC, and the WAF is worse than MLC, so MLC is chosen for writing.

[0105] Specifically, when the gear is HS-GEAR4 and the write mode specified by the host 2 is SLC, the write performance determination unit 17 selects MLC as the write mode according to the write mode selection table 31.

[0106] Figure 14 This is a flowchart illustrating the data write processing flow of the memory system in the fourth embodiment.

[0107] The write performance determination unit 17 determines, according to the write mode selection table 31, whether the write mode specified by the host 2 can achieve the maximum write performance at this time (S401). If the maximum write performance can be achieved (S401: Yes), the RW processing unit 13 writes the write data to the flash memory 20 using the specified write mode (S402).

[0108] If maximum write performance cannot be achieved (S401: No), the write performance determination unit 17 determines the optimal write mode for WAF among the write modes that can achieve maximum write performance at this time, based on the write mode selection table 31 (S403). The RW processing unit 13 writes the write data to the flash memory 20 using the determined write mode (S404).

[0109] Furthermore, the above example illustrates how, when the maximum write performance of the specified write mode cannot be achieved regardless of which write mode is chosen by host 2, the write mode that achieves the maximum write performance and is optimal for WAF within the same range is selected. As a variation, for example, when a write mode is specified by host 2, that write mode can be followed; when no write mode is specified, the write mode that achieves the maximum write performance and is optimal for WAF can be selected.

[0110] Figure 15 This is a flowchart illustrating a variation of the data write process of the memory system in the fourth embodiment.

[0111] RW processing unit 13 determines whether the host 2 has specified a write mode (S501). If specified (S501: Yes), RW processing unit 13 writes the write data to flash memory 20 using the specified write mode (S502).

[0112] When the host 2 does not specify a write mode (S501: No), the write performance determination unit 17 determines the write mode that can achieve the maximum write performance according to the write mode selection table 31 (S503). The RW processing unit 13 writes the write data to the flash memory 20 using the determined write mode (S504).

[0113] As described above, the memory system 1-4 of the fourth embodiment focuses on the limitation of write performance by the level. When the write mode specified by the host 2 cannot achieve the maximum write performance of the write mode, it is changed to the write mode that can achieve the maximum write performance at that level and is the best write mode of WAF among the write modes that can achieve the maximum write performance.

[0114] In other words, the memory systems 1-4 of the fourth embodiment can also appropriately control the writing method.

[0115] (Fifth Embodiment)

[0116] Next, the fifth embodiment will be described.

[0117] The fifth embodiment is an application example of the memory system 1-2 of the second embodiment. In the second embodiment, an example is shown in which all write data is written to the flash memory 20 without GC by changing a portion of the write data from SLC to MLC.

[0118] In contrast, in the fifth embodiment, if GC occurs even after changing from SLC to MLC, the occurrence of GC is further delayed by utilizing TLC writes.

[0119] This write mode control is designed to prevent write performance degradation due to garbage collection (GC). Therefore, depending on the situation, all write operations can be changed to MLC. If GC still occurs even after changing all write operations to MLC, the occurrence of GC can be delayed by changing all write operations to TLC.

[0120] Figure 16 This is a flowchart illustrating the data write process of the memory system in the fifth embodiment.

[0121] RW processing unit 13 determines whether the amount of written data exceeds the threshold (S601). If the amount of written data does not exceed the threshold (S601: No), RW processing unit 13 writes all written data to flash memory 20 in SLC mode (S602).

[0122] If the amount of data written exceeds the threshold (S601: Yes), the RW processing unit 13 then determines whether half of the amount of data written exceeds the threshold (S603). If half of the amount of data written does not exceed the threshold (S603: No), the RW processing unit 13 writes twice the amount of data exceeding the threshold to the flash memory 20 in MLC mode (S604), and writes the remaining data to the flash memory 20 in SLC mode (S605). The order of the MLC write in S604 and the SLC write in S605 can also be reversed.

[0123] If half of the written data exceeds the threshold (S603: Yes), the RW processing unit 13 writes all the written data TLC to the flash memory 20 (S606).

[0124] As described above, the memory system 1-2 of the fifth embodiment further delays the occurrence of GC by utilizing TLC writing.

[0125] In other words, the memory system 1-2 of the fifth embodiment can also appropriately control the writing method.

[0126] Several embodiments of the present invention have been described, but these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments or variations thereof are included in the scope or spirit of the invention, and are included in the scope of the invention as set forth in the claims and its equivalents.

[0127] [Explanation of Symbols]

[0128] 1: Memory System

[0129] 2: Host

[0130] 10: Controller

[0131] 11: Mainframe I / F Section

[0132] 12: Memory I / F Section

[0133] 13: RW Processing Department

[0134] 14: Memory Area Management Department

[0135] 15: GC Processing Department

[0136] 16: Command Analysis Department

[0137] 17: Write Performance Determination Section

[0138] 20: Flash Memory

[0139] 21: System Data Storage Area

[0140] 22: User data storage area

[0141] 31: Select table as the writing method

[0142] 100: CPU

[0143] 131: WB Department

[0144] 132: Extended WB section.

Claims

1. A memory system having Non-volatile memory having multiple blocks, each containing multiple memory cells; and A memory controller is available to connect to a host computer and control the non-volatile memory. The memory controller is configured as follows: As methods of writing data to the non-volatile memory, there are two corresponding methods: a first method of writing 1 bit of data to each memory cell, and a second method of writing N (N is a natural number greater than 2) bits of data to each memory cell. When a write command is received from the host indicating that the first write method should be used... Determine whether the amount of data written exceeds a threshold obtained by subtracting a predetermined value from the remaining capacity of the non-volatile memory, where the predetermined value represents the remaining capacity of the non-volatile memory at which garbage collection has occurred to increase its remaining capacity. When the capacity of the written data is below the threshold, the written data is written to the non-volatile memory using the first writing method. When the volume of the written data exceeds the threshold The second write method is used to write at least (the excess amount of the threshold) + ((the excess amount of the threshold) / (the N-1)) of the write data to the non-volatile memory, and the first write method is used to write the remaining write data to the non-volatile memory.

2. The memory system according to claim 1, wherein The memory controller is configured as follows: The administrator can toggle the first flag on / off based on commands from the host. During the period when the first flag is enabled, it is determined that the first write mode should be used for the write command received from the host.

3. The memory system according to claim 2, wherein The memory controller is configured as follows: Furthermore, it manages the ability to toggle the second flag on / off based on commands from the host. During the period when the first flag is open, if the second flag is closed, it is determined that the first write mode should be used for the write command received from the host; if the second flag is open, it is determined that the second write mode should be used for the write command received from the host.

4. The memory system according to claim 2, wherein The memory controller is configured as follows: If the write command received from the host is a write command that should use the first write method, and if, based on the transmission rate used in the communication with the host, it is estimated that the write performance of the first write method for the non-volatile memory is equal to or lower than the write performance of the second write method for the non-volatile memory, then it is determined that the second write method should be used for the write command received from the host.

5. The memory system according to claim 1, wherein The memory controller is configured as follows: As a method of writing data to the non-volatile memory, this corresponds to a third writing method that writes K bits of data (K is a natural number greater than N) to each memory cell. If the capacity of the written data exceeds the threshold, and even if all the written data is written to the non-volatile memory using the second writing method, the remaining capacity of the non-volatile memory is still lower than the specified value, then all the written data is written to the non-volatile memory using the third writing method.

6. A memory controller capable of connecting to a host computer and controlling a non-volatile memory having multiple blocks each containing multiple memory cells, the memory controller being configured as follows: As methods of writing data to the non-volatile memory, there are two corresponding methods: a first method of writing 1 bit of data to each memory cell, and a second method of writing N (N is a natural number greater than 2) bits of data to each memory cell. When a write command is received from the host indicating that the first write method should be used... Determine whether the amount of data written exceeds a threshold obtained by subtracting a predetermined value from the remaining capacity of the non-volatile memory, where the predetermined value represents the remaining capacity of the non-volatile memory at which garbage collection has occurred to increase its remaining capacity. When the capacity of the written data is below the threshold, the written data is written to the non-volatile memory using the first writing method. When the volume of the written data exceeds the threshold The second write method is used to write at least (the excess amount of the threshold) + ((the excess amount of the threshold) / (the N-1)) of the write data to the non-volatile memory, and the first write method is used to write the remaining write data to the non-volatile memory.

7. The memory controller according to claim 6, wherein the configuration is as follows: The administrator can toggle the first flag on / off based on commands from the host. During the period when the first flag is enabled, it is determined that the first write mode should be used for the write command received from the host.

8. The memory controller according to claim 7, wherein the configuration is as follows: Furthermore, it manages the ability to toggle the second flag on / off based on commands from the host. During the period when the first flag is open, if the second flag is closed, it is determined that the first write mode should be used for the write command received from the host; if the second flag is open, it is determined that the second write mode should be used for the write command received from the host.

9. The memory controller according to claim 7, wherein the configuration is as follows: If the write command received from the host is a write command that should use the first write method, and if, based on the transmission rate used in the communication with the host, it is estimated that the write performance of the first write method for the non-volatile memory is equal to or lower than the write performance of the second write method for the non-volatile memory, then it is determined that the second write method should be used for the write command received from the host.

10. The memory controller according to claim 6, wherein the configuration is as follows: As a method of writing data to the non-volatile memory, this corresponds to a third writing method that writes K bits of data (K is a natural number greater than N) to each memory cell. If the capacity of the written data exceeds the threshold, and even if all the written data is written to the non-volatile memory using the second writing method, the remaining capacity of the non-volatile memory is still lower than the specified value, then all the written data is written to the non-volatile memory using the third writing method.

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