CXL Memory System and Its Operation Method

Abstract

This application provides a CXL memory system and its operation method. The CXL memory system may include: a storage device configured to store data; a memory device configured to cache the data stored in the storage device; and a CXL controller configured to receive a read request for target data from a host via a CXL interface. The CXL controller is also configured to determine whether to send a response message to the host, the response message including information related to the read latency required to read the target data.

Description

Cross-references to related applications

[0001] This application claims priority to Korean Patent Application No. 10-2025-0017906, filed on February 12, 2025, and Korean Patent Application No. 10-2025-0054196, filed on April 25, 2025, which are incorporated herein by reference in their entirety. Technical Field

[0002] Embodiments of this disclosure relate to a high-speed computing link (CXL) memory system and a method of operating the same. Background Technology

[0003] Existing host computers use memory via dual in-line memory modules (DIMMs), but the maximum capacity of the memory is limited due to the limited number of pins in the central processing unit (CPU) and chipset.

[0004] To address this limitation, a High-Speed ​​Compute Link (CXL) memory system employing CXL technology can be used. CXL technology is an open standard for accelerating the performance of CPU devices and memory, and it is a standard for cache coherency and memory expansion. Through CXL technology, the host can utilize the CXL memory system as a buffer memory.

[0005] The CXL memory system supports CXL sub-protocols such as the CXL.mem sub-protocol and can provide additional memory capacity to the host by connecting to the host without any physical limitation on the number of pins. Summary of the Invention

[0006] Embodiments of this disclosure aim to provide a CXL memory system and a method of operating thereof, which can improve the task processing performance of a host by sending information related to the latency required to read data to the host.

[0007] The purposes of the embodiments disclosed herein are not limited to those described herein, and other purposes not mentioned will be apparent to those skilled in the art from the following description.

[0008] In an embodiment, a high-speed computing link (CXL) memory system may include: a storage device configured to store data; a memory device configured to cache the data stored in the storage device; and a CXL controller configured to receive a read request for target data from a host via a CXL interface and determine whether to send a response message to the host, the response message including information related to the read latency required to read the target data.

[0009] In an embodiment, a method for operating a high-speed computing link (CXL) memory system including a storage device, a memory device, and a CXL controller may include: receiving a read request for target data from a host via a CXL interface by the CXL controller; calculating a read latency required to read the target data from the storage device or the memory device by the CXL controller; and determining, based on the read latency, whether to send a response message to the host, the response message including information related to the read latency.

[0010] In an embodiment, a memory system may include: a storage device configured to store data; a memory device configured to cache the data stored in the storage device; and a controller configured to communicate with a host via a preset interface and control the storage device and the memory device. The controller may be configured to receive a read request from the host for target data in the storage device or the memory device, and may determine whether to send a response message to the host, the response message including information related to the read latency required to read the target data.

[0011] The effects of this disclosure are not limited to the foregoing objectives, and other effects will be apparent to those skilled in the art from the following detailed description. Attached Figure Description

[0012] This disclosure will be more fully understood through the following detailed description and accompanying drawings, which are provided for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0013] Figure 1 This is a schematic configuration diagram of a CXL memory system according to an embodiment of the present disclosure.

[0014] Figure 2 This is a diagram illustrating the schematic operation of a CXL memory system according to an embodiment of the present disclosure.

[0015] Figure 3 This is a diagram illustrating an example of the operation of a CXL memory system determining whether to send a response message according to an embodiment of the present disclosure.

[0016] Figure 4 This is a diagram illustrating another example of the operation of a CXL memory system determining whether to send a response message according to an embodiment of the present disclosure.

[0017] Figure 5 and Figure 6 This is a diagram illustrating an example of how a CXL memory system processes a read request according to an embodiment of the present disclosure.

[0018] Figure 7 and Figure 8This is a diagram illustrating another example of how a CXL memory system processes a read request according to an embodiment of the present disclosure.

[0019] Figure 9 This is a flowchart illustrating a method of operating a CXL memory system according to an embodiment of the present disclosure. Detailed Implementation

[0020] Embodiments of the present disclosure are described in detail below with reference to the accompanying drawings. Throughout the specification, references to "embodiment," "another embodiment," etc., do not necessarily refer to only one embodiment, and different references to any such phrases are not necessarily limited to the same embodiment. The term "embodiment" as used herein does not necessarily refer to all embodiments.

[0021] Various embodiments of the present disclosure are described in more detail below with reference to the accompanying drawings. However, the present disclosure may be implemented in different forms and variations and should not be construed as limited to the embodiments set forth herein. Rather, the described embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the contents of the disclosure to those skilled in the art to which it pertains. Throughout the present disclosure, the same reference numerals refer to the same parts throughout the various figures and embodiments.

[0022] The methods, processes, and / or operations described herein can be performed by code or instructions that run on a computer, processor, controller, or other signal processing device. This computer, processor, controller, or other signal processing device can be those described herein, or it can be an element other than those described herein. Because the algorithms that form the basis of the method (or the operation of the computer, processor, controller, or other signal processing device) are described in detail, the code or instructions for implementing embodiments of the method can convert the computer, processor, controller, or other signal processing device into a dedicated processor for performing the methods herein.

[0023] When implemented at least in part as software, controllers, processors, devices, modules, units, multiplexers, logic, interfaces, decoders, drivers, generators, and other signal generation and signal processing features may include, for example, memory or other storage devices for storing code or instructions that will be executed by, for example, a computer, processor, microprocessor, controller, or other signal processing device.

[0024] Figure 1 This is a schematic configuration diagram of a CXL memory system 100 according to an embodiment of the present disclosure.

[0025] Reference Figure 1The CXL memory system 100 may include a storage device 110, a storage device 120, and a CXL controller 130.

[0026] Storage device 110 can store data. For example, storage device 110 can be a device (e.g., a solid-state drive (SSD)) that includes non-volatile memory (e.g., NAND flash, MRAM, or PRAM) for storing data. Storage device 110 can store large amounts of data and can operate at a lower speed (e.g., relative to storage device 120).

[0027] Memory device 120 can cache data stored in memory device 110. The storage capacity of memory device 120 can be smaller than that of memory device 110, and it can operate at a higher speed (e.g., relative to memory device 110). Therefore, by caching data from memory device 110 to memory device 120, CXL memory system 100 can handle read requests from external sources more quickly.

[0028] When cached data in memory device 120 is modified and becomes dirty (e.g., the cached data in memory device 120 is modified and is different from the data stored in memory device 110), CXL memory system 100 can flush the cached data in memory device 120 to memory device 110.

[0029] The memory device 120 can be implemented in a variety of ways. For example, the memory device 120 can be volatile memory (e.g., dynamic random access memory (DRAM) or static random access memory (SRAM)).

[0030] The CXL controller 130 can control the storage device 110 and the memory device 120, and can communicate with the host via the CXL interface. This allows the host to increase available memory capacity and bandwidth without needing to add a separate memory channel.

[0031] The CXL interface can operate based on the High-Speed ​​Peripheral Component Interconnect (PCIe). In embodiments of this disclosure, the CXL interface can operate based on the CXL.mem subprotocol.

[0032] Figure 2 This is a diagram illustrating the schematic operation of a CXL memory system 100 according to an embodiment of the present disclosure.

[0033] Reference Figure 2The host can generate a read request RD_REQ (S210) for target data stored in the CXL memory system 100 (e.g., storage device 110 or storage device 120).

[0034] The host can send a read request RD_REQ (S220) to the CXL controller 130 of the CXL memory system 100 via the CXL interface.

[0035] Upon receiving the read request RD_REQ, the CXL controller 130 can determine whether to send a response message RESP_MSG to the host for the read request RD_REQ (S230).

[0036] The response message RESP_MSG may include information related to the read latency required to read the target data. For example, the read latency may represent the time between the time when the CXL controller 130 receives the read request RD_REQ and the time when the CXL controller 130 sends the target data to the host in response to the read request RD_REQ.

[0037] At the point in time the host sends a read request RD_REQ to the CXL memory system 100, the host may not be able to determine (e.g., be unaware) the time it will take to read the target data. This is because the read latency may vary depending on whether the target data is cached in memory device 120 (or another location such as storage device 110). In other words, the host may not know whether the target data is stored in memory device 120 or storage device 110.

[0038] The process used (or utilized) by the host to handle a task can vary depending on the read latency. This task can be a job, process, thread, etc., processed by the host's CPU.

[0039] In instances with high read latency, it is advantageous for the host to run another task instead of continuing to wait for the target data. On the other hand, in instances with low read latency, it is advantageous for the host to wait for the target data from the CXL memory system 100 to avoid the overhead of task switching.

[0040] Therefore, in order for the host to determine whether to wait for target data or perform a task switch to improve task processing performance, the CXL controller 130 can send a response message RESP_MSG to the host, which includes information related to read latency.

[0041] Figure 3This is a diagram illustrating an example of the operation of a CXL memory system 100 according to an embodiment of the present disclosure to determine whether to send a response message RESP_MSG.

[0042] Reference Figure 3 The host can generate a read request RD_REQ (S310) for the target data. The read request RD_REQ may include the response flag RESP_FLG.

[0043] The response flag RESP_FLG can indicate whether the sending of the aforementioned response message RESP_MSG to the host is enabled. For example, as a 1-bit flag, the response flag RESP_FLG can have a first value (e.g., 1) or a second value (e.g., 0).

[0044] The host can send a read request RD_REQ (including the response flag RESP_FLG) to the CXL controller 130 of the CXL memory system 100 via the CXL interface (S320).

[0045] Upon receiving the read request RD_REQ, the CXL controller 130 can determine whether to send a response message RESP_MSG to the host based on the response flag RESP_FLG included in the read request RD_REQ (S330).

[0046] In an instance where the response flag RESP_FLG indicates that sending the response message RESP_MSG to the host is enabled, the CXL controller 130 can send the response message RESP_MSG to the host.

[0047] On the other hand, in instances where the response flag RESP_FLG indicates that sending the response message RESP_MSG to the host is not enabled, the CXL controller 130 may not send the response message RESP_MSG to the host.

[0048] Figure 4 This is a diagram illustrating another example of the operation of a CXL memory system 100, according to an embodiment of the present disclosure, in determining whether to send a response message RESP_MSG.

[0049] Reference Figure 4 The host can generate a read request RD_REQ (S410) for the target data.

[0050] The host can send a read request RD_REQ (S420) to the CXL controller 130 of the CXL memory system 100 via the CXL interface.

[0051] Upon receiving the read request RD_REQ, the CXL controller 130 can determine whether to send a response message RESP_MSG to the host based on the target field TGT_FIELD of the control register CTRL_REG included in the CXL controller 130 (S430).

[0052] The control register CTRL_REG can be implemented in several ways. For example, the control register CTRL_REG can be the CXL timeout and isolation control register defined in the CXL standard. The destination field TGT_FIELD can be a specific bit of the control register CTRL_REG (e.g., the fifth bit).

[0053] The CXL controller 130 may additionally store configuration information related to whether the operation of determining whether to send a response message RESP_MSG to the host is supported. For example, this configuration information may be a specific bit (e.g., the seventh bit) of the CXL timeout and isolation performance register as defined in the CXL standard.

[0054] When the configuration information indicates that the operation of determining whether to send a response message RESP_MSG to the host is supported, the CXL controller 130 can determine whether to send a response message RESP_MSG to the host based on the target field TGT_FIELD of the control register CTRL_REG.

[0055] As described above, the CXL controller 130 can determine whether to send a response message RESP_MSG to the host, including information about the read latency required to read the target data.

[0056] Therefore, the CXL controller 130 can calculate the read latency (required to read the target data). The CXL controller 130 can calculate the read latency in a variety of ways.

[0057] For example, the CXL controller 130 can calculate the read latency based on at least one of the following: whether the target data is cached in the memory device 120, and the depth of the read queue in which read commands for the memory device 110 are queued.

[0058] In the instance where the target data is cached in memory device 120, since memory device 120 operates at a faster speed than memory device 110, CXL controller 130 can determine that the read latency is less than the read latency if the target data is not cached in memory device 120.

[0059] On the other hand, as the depth of the read queue increases, the time that the command (requesting to read target data from storage device 110) waits in the read queue also increases. Therefore, the CXL controller 130 can determine that the read latency is large.

[0060] Figure 5 and Figure 6 This is a diagram illustrating an example of how a CXL memory system 100, according to an embodiment of the present disclosure, processes a read request RD_REQ.

[0061] Reference Figure 5 The host can generate a read request RD_REQ (S510) for the target data TGT_DATA.

[0062] The host can send a read request RD_REQ (S520) to the CXL controller 130 of the CXL memory system 100 via the CXL interface.

[0063] After receiving the read request RD_REQ, the CXL controller 130 can send the target data TGT_DATA to the host (S530). For example... Figure 5 As shown, because the target data TGT_DATA is cached in the memory device 120, the read latency required from the time the CXL controller 130 receives the read request RD_REQ to the time the CXL controller 130 reads the target data TGT_DATA is small.

[0064] Therefore, after sending a read request RD_REQ to the CXL controller 130, the host can wait for the target data TGT_DATA. This is because the overhead of the host waiting for the target data TGT_DATA is less than the overhead of the host performing a task switch.

[0065] In the following text, reference will be made to Figure 6 To describe the above references in more detail Figure 5 Examples of the described operations.

[0066] Reference Figure 6 The host can generate a read request RD_REQ (S610) for the target data TGT_DATA.

[0067] The host can send a read request RD_REQ (S620) to the CXL controller 130 of the CXL memory system 100 via the CXL interface.

[0068] In an instance where the target data TGT_DATA is cached in memory device 120, CXL controller 130 may determine not to send a response message RESP_MSG to the host (S630). This is because the read latency required for CXL controller 130 to send the target data TGT_DATA in response to read request RD_REQ is short, and the target data TGT_DATA can be sent to the host immediately without needing to send a separate response message RESP_MSG.

[0069] CXL controller 130 may read target data TGT_DATA from memory device 120 in response to read request RD_REQ (S640). Memory device 120 may send target data TGT_DATA to CXL controller 130 in response to a request from CXL controller 130 (S650).

[0070] The CXL controller 130 can send target data TGT_DATA (S660) to the host. (See above for reference.) Figure 5 After sending a read request RD_REQ to the CXL controller 130, the host waits for the target data TGT_DATA. The host can immediately receive the target data TGT_DATA from the CXL controller 130.

[0071] Figure 7 and Figure 8 This is a diagram illustrating another example of how a CXL memory system 100, according to an embodiment of the present disclosure, processes a read request RD_REQ.

[0072] Reference Figure 7 The host can generate a read request RD_REQ (S710) for the target data TGT_DATA.

[0073] The host can send a read request RD_REQ (S720) to the CXL controller 130 of the CXL memory system 100 via the CXL interface.

[0074] Before sending the target data TGT_DATA to the host, the CXL controller 130 may send a response message RESP_MSG (S730) to the host, which includes information related to the read latency.

[0075] The response message RESP_MSG can be an NDR (No Data Response) message that does not include the target data TGT_DATA. The response message RESP_MSG may include operator codes that indicate that the response message includes information related to read latency.

[0076] Upon receiving the response message RESP_MSG, the host can perform a task switch to execute another task instead of continuing to wait for the target data TGT_DATA. The host can also stop the currently running task and execute another task.

[0077] like Figure 7 As shown, because the target data TGT_DATA is not cached in memory device 120, the read latency required for the CXL controller 130 to read the target data TGT_DATA from memory device 110 is relatively large. In this case, the performance degradation caused by the host waiting for the target data TGT_DATA outweighs the overhead of task switching.

[0078] Therefore, the CXL controller 130 can first send a response message RESP_MSG to the host to notify the host that it does not need to continue waiting for the target data TGT_DATA.

[0079] After receiving the response message RESP_MSG, because the latency required to read the target data TGT_DATA is relatively large, the host can execute another task without continuing to wait for the target data TGT_DATA, thereby improving task processing performance.

[0080] In the following description, the CXL controller 130 can read the target data TGT_DATA from the storage device 110 and send the target data TGT_DATA to the host (S740). In order to process the received target data TGT_DATA, the host can perform a task switch again to execute the original task (i.e., the task that generates the read request RD_REQ for the target data TGT_DATA).

[0081] In the following text, reference will be made to Figure 8 For a more detailed description of the above references Figure 7 Examples of the described operations.

[0082] Reference Figure 8 The host can generate a read request RD_REQ (S810) for the target data TGT_DATA.

[0083] The host can send a read request RD_REQ (S820) to the CXL controller 130 of the CXL memory system 100 via the CXL interface.

[0084] In an instance where the target data TGT_DATA is not cached in the memory device 120, the CXL controller 130 may determine to send a response message RESP_MSG to the host (S830).

[0085] Therefore, the CXL controller 130 can send a response message RESP_MSG (S840) to the host in response to the read request RD_REQ. This is consistent with the above description regarding... Figure 7 The process described is similar; upon receiving the response message RESP_MSG, the host can perform a task switch to execute another task instead of continuing to wait for the target data TGT_DATA. The host can stop the currently running task and execute another task.

[0086] The CXL controller 130 may read the target data TGT_DATA from the storage device 110 (S850). The storage device 110 may send the target data TGT_DATA to the CXL controller 130 in response to a request from the CXL controller 130 (S860).

[0087] The CXL controller 130 can send target data TGT_DATA (S870) to the host. This is consistent with the above description regarding... Figure 7 The process described is similar. In order to process the received target data TGT_DATA, the host can perform a task switch again to execute the original task (i.e., the task that generates the read request RD_REQ for the target data TGT_DATA).

[0088] The information related to read latency included in the response message RESP_MSG can be configured in a variety of ways.

[0089] For example, information related to read latency can indicate whether the read latency is greater than or equal to a preset threshold latency. When the read latency is greater than or equal to the threshold latency, the information related to read latency can be set to a first value (e.g., 1). When the read latency is less than the threshold latency, the read latency information can be set to a second value (e.g., 0).

[0090] The CXL controller 130 may store the value of the threshold delay therein. For example, the CXL controller 130 may store the value of the threshold delay in M ​​bits (M is a natural number of 2 or greater) included in the aforementioned CXL timeout and isolation control register.

[0091] For example, information related to read latency can indicate the magnitude of the read latency. This information can be represented using N bits (where N is a natural number of 2 or greater).

[0092] For example, the read latency can be one of K candidate values ​​(K is a natural number of 2 or greater), and each candidate value can correspond to a specific range of read latency sizes.

[0093] The operation of the CXL memory system 100 has been described above. However, the above operation is not limited to the CXL memory system 100, and can also be applied to general-purpose memory systems that communicate with the host via an interface other than the CXL interface.

[0094] For example, a memory system may include the memory device 110 and memory device 120 described above, as well as a separate controller. (Referring to the above...) Figures 1 to 8 The method described allows the controller to receive read requests for target data from the host and determine whether to send a response message to the host including information about the read latency required to read the target data.

[0095] Figure 9 This is a flowchart illustrating a method 900 for operating a CXL memory system 100 according to an embodiment of the present disclosure.

[0096] Reference Figure 9 The method 900 for operating the CXL memory system 100 may include operation S910: receiving a read request RD_REQ for target data TGT_DATA from the host HOST via the CXL interface.

[0097] The method 900 for operating the CXL memory system 100 may include operation S920: calculating the read latency required to read the target data TGT_DATA.

[0098] For example, operation S920 can calculate the read latency based on at least one of the following: whether the target data TGT_DATA is cached in memory device 120, and the depth of the read queue, in which read commands for memory device 110 are queued.

[0099] The method 900 for operating the CXL memory system 100 may include operation S930: determining whether to send a response message RESP_MSG, which includes information related to read latency, to the host.

[0100] For example, a read request RD_REQ may include a response flag RESP_FLG, which indicates whether sending the response message RESP_MSG to the host is enabled. In an instance where the response flag RESP_FLG indicates that sending the response message RESP_MSG to the host is enabled, operation S930 can determine that the response message RESP_MSG is sent to the host. On the other hand, in an instance where the response flag RESP_FLG indicates that sending the response message RESP_MSG to the host is not enabled, operation S930 can determine that the response message RESP_MSG is not sent to the host.

[0101] For example, the CXL memory system 100 may include a control register CTRL_REG. Operation S930 may determine whether to send a response message RESP_MSG to the host based on the target field TGT_FIELD of the control register CTRL_REG.

[0102] For example, when the target data TGT_DATA is cached in the memory device 120, operation S930 can determine not to send a response message RESP_MSG to the host.

[0103] According to another embodiment, in an instance where the target data TGT_DATA is not cached in the memory device 120, operation S930 may determine to send a response message RESP_MSG to the host host before sending the target data to the host host.

[0104] The information related to read latency included in the response message RESP_MSG can indicate whether the read latency is greater than or equal to a preset threshold latency. This information can also indicate the magnitude of the read latency.

[0105] Although exemplary embodiments of this disclosure have been described for illustrative purposes, those skilled in the art will understand that various modifications, additions, and substitutions can be made without departing from the scope and spirit of this disclosure. Therefore, the embodiments disclosed above and in the accompanying drawings should be considered descriptive only and not limiting of the scope of the technology. The technical scope of this disclosure is not limited to the embodiments and the accompanying drawings. The spirit and scope of this disclosure should be interpreted in conjunction with the claims and cover all equivalent solutions falling within the scope of the claims.

Claims

1. A high-speed computing link memory system, namely a CXL memory system, comprising: Storage device, for storing data; A memory device for caching data stored in the memory device; as well as CXL controller: Receive read requests for target data from the host via the CXL interface, and Determine whether to send a response message to the host, the response message including information about the read latency required to read the target data.

2. The CXL memory system according to claim 1, wherein, The read request includes a response flag indicating whether sending the response message to the host is enabled. When the response flag indicates that sending the response message to the host is enabled, the CXL controller determines to send the response message to the host, and When the response flag indicates that sending the response message to the host is not enabled, the CXL controller determines not to send the response message to the host.

3. The CXL memory system according to claim 1, wherein, The CXL controller includes control registers, and The CXL controller determines whether to send the response message to the host based on the target field of the control register.

4. The CXL memory system according to claim 1, wherein, The CXL controller calculates the read latency based on at least one of the following: whether the target data is cached in the memory device, and the depth of the read queue in which read commands for the memory device are queued.

5. The CXL memory system according to claim 1, wherein, When the target data is cached in the memory device, the CXL controller determines not to send the response message to the host.

6. The CXL memory system according to claim 1, wherein, In response to determining that the target data is not cached in the memory device, the CXL controller determines to send the response message to the host before sending the target data to the host.

7. The CXL memory system according to claim 6, wherein, Information related to the read latency indicates that the read latency is greater than or equal to a preset threshold latency.

8. The CXL memory system according to claim 6, wherein, Information related to the read latency indicates the magnitude of the read latency.

9. A method for operating a high-speed computing link memory system, i.e., a CXL memory system, the CXL memory system comprising a storage device, a memory device, and a CXL controller, the method comprising: The CXL controller receives a read request for the target data from the host via the CXL interface; The CXL controller calculates the read latency required to read the target data from the storage device or the memory device; as well as The CXL controller determines whether to send a response message to the host based on the read latency, the response message including information related to the read latency.

10. The method of claim 9, wherein, The read request includes a response flag indicating whether sending the response message to the host is enabled. Determining whether to send a response message to the host includes: in response to determining that the response flag indicates enabling the sending of the response message to the host, determining to send the response message to the host, and Determining whether to send a response message to the host includes: in response to determining that the response flag indicates that sending the response message to the host is not enabled, determining not to send the response message to the host.

11. The method of claim 9, wherein, The CXL memory system includes control registers, and Determining whether to send a response message to the host includes: determining whether to send the response message to the host based on the target field of the control register.

12. The method according to claim 9, wherein, Calculating the read latency includes calculating the read latency based on at least one of the following: whether the target data is cached in the memory device, and the depth of the read queue in which read commands for the memory device are queued.

13. The method according to claim 9, wherein, When the target data is cached in the memory device, determining whether to send a response message to the host includes: determining not to send the response message to the host.

14. The method according to claim 9, wherein, When the target data is not cached in the memory device, determining whether to send a response message to the host includes: determining whether to send the response message to the host before sending the target data to the host.

15. The method according to claim 14, wherein, Information related to the read latency indicates whether the read latency is greater than or equal to a preset threshold latency.

16. The method of claim 14, wherein, Information related to the read latency indicates the magnitude of the read latency.

17. A memory system comprising: Storage device, for storing data; A memory device for caching data stored in the memory device; as well as The controller communicates with the host via a preset interface and controls the storage device and the memory device. The controller receives a read request from the host for target data in the storage device or memory device, and determines whether to send a response message to the host, the response message including information related to the read latency required to read the target data.

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