An asynchronous memory processing scheduling method based on historical access popularity
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-04-17
- Publication Date
- 2026-08-14
AI Technical Summary
[0007]有鉴于此，本申请提供了一种基于历史访问热度的异步内存处理调度方法，以解决现有技术中因缺乏对内存访问局部性的感知而导致的调度效率低下、写停顿现象频发、系统长尾延迟严重的问题，从而在保证数据一致性的前提下最小化应用程序的等待时间，提升系统在高负载下的整体吞吐量和稳定性
[0016]经由上述技术方案可知，本发明通过引入一种基于位运算的高效热度评分模型，利用位移操作模拟热度随时间的自然衰减，并通过置位操作累加当前访问事件的热度权重，从而量化内存页框的访问紧迫程度。基于该实时热度评分，系统构建优先级感知的调度队列替代传统的先进先出队列，动态调整后台任务的处理顺序，确保高热度页面被优先处理，使得热点页面能以最快速度解除写保护，在主线程再次访问之前“抢跑”完成处理。
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Abstract
Description
Technical Field
[0001] This invention relates to the field of memory management technology, and in particular to an asynchronous memory processing scheduling method based on historical access frequency. Background Technology
[0002] In modern high-performance computing systems, database systems, and operating systems, an asynchronous architecture that decouples computation and I / O resources is typically used to improve system throughput and reduce latency. In this architecture, the main computing thread handles business logic processing, while background threads handle asynchronous processing of in-memory data, such as data persistence, migrating memory pages to slower media, memory compression, or remote synchronization.
[0003] To ensure data consistency and integrity, the system typically imposes access constraints on specific memory page frames during background thread processing, such as write protection, locking, or freezing. When the main computing thread attempts to access a protected memory page that is in a "background processing" state, the hardware memory management unit triggers a page fault. After catching this exception, the system kernel checks the state of the target page. If the page is still in the background processing queue, to prevent new data from overwriting old data and causing consistency issues such as write tearing, the system must suspend the main computing thread, putting it into a sleep state or spinning it until the background thread completes processing the page and releases the constraint. This passive waiting phenomenon is called "write pause" or "access blocking."
[0004] In existing asynchronous memory processing mechanisms, background task queues typically employ simple first-in-first-out (FIFO) or physical address-based scheduling strategies. These strategies assume all pending memory pages have the same processing priority, ignoring the spatiotemporal locality of memory access by applications. According to the principle of temporal locality, if a memory location has just been accessed, it is likely to be accessed again in the near future. Under write-intensive loads, some "hot pages" are frequently modified, while other "cold pages" rarely change.
[0005] In real-world high-concurrency or write-intensive workloads, traditional first-in-first-out (FIFO) scheduling can easily lead to "head-of-queue blocking": "Hot pages" that the application urgently needs to access again are unfortunately placed at the end of the background processing queue, and must wait for a large number of "cold data pages" at the front of the queue to be processed before they can be released. This blocking caused by improper scheduling order results in unpredictable long-tail delays for the main computing thread, severely causing system performance fluctuations, negating the performance advantages of asynchronous architecture, and failing to meet the real-time requirements of business applications.
[0006] In summary, existing technologies suffer from problems such as low scheduling efficiency, frequent write pauses, and severe long-tail latency due to a lack of awareness of memory access locality, which limits the throughput ceiling of multi-core asynchronous architectures under write-intensive loads. Summary of the Invention
[0007] In view of this, this application provides an asynchronous memory processing scheduling method based on historical access popularity to solve the problems of low scheduling efficiency, frequent write pauses, and severe long-tail latency caused by the lack of awareness of memory access locality in the prior art. This method minimizes the waiting time of the application while ensuring data consistency and improves the overall throughput and stability of the system under high load.
[0008] To achieve the above objectives, this application provides the following technical solution:
[0009] This invention provides an asynchronous memory processing scheduling method based on historical access popularity, comprising:
[0010] Obtain historical access information for memory page frames; the historical access information includes historical access records for each memory page frame over multiple processing cycles;
[0011] Based on the historical access information, a bitwise operation-based heat scoring model is used to determine the real-time heat score of the memory page frame; wherein, the heat scoring model simulates the decay of heat over time through bit shifting operations, and accumulates the heat weight of the current period's access events through bit setting operations, so as to quantify the access urgency of the memory page frame.
[0012] Based on the real-time popularity score of the memory page frames, the memory page frames to be processed are inserted into a priority queue for dynamic rearrangement; the priority queue is used to replace the first-in-first-out queue, so that memory page frames with high popularity scores are placed at the head of the queue for priority processing.
[0013] Once the background thread processes the memory page frame and removes its write protection, if the main computing thread accesses the memory page frame again, there is no need to trigger a write pause wait.
[0014] The present invention provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, can implement the steps of the asynchronous memory processing scheduling method based on historical access popularity.
[0015] The present invention provides an electronic device, comprising: a memory and a processor; the memory being used to store a computer program; the processor being used to implement the steps of the asynchronous memory processing scheduling method based on historical access popularity as described above when executing the computer program.
[0016] As can be seen from the above technical solution, this invention introduces a highly efficient popularity scoring model based on bit operations. It uses bit shift operations to simulate the natural decay of popularity over time and accumulates the popularity weight of the current access event through bit-setting operations, thereby quantifying the access urgency of memory page frames. Based on this real-time popularity scoring, the system constructs a priority-aware scheduling queue to replace the traditional first-in-first-out queue, dynamically adjusting the processing order of background tasks to ensure that high-popularity pages are processed first. This allows hot pages to have their write protection removed as quickly as possible, "preemptively" completing processing before the main thread accesses them again. Attached Figure Description
[0017] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0018] Figure 1 A flowchart of a page frame access prediction algorithm provided in an embodiment of this application. Detailed Implementation
[0019] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.
[0020] The core concept of this application is to provide an asynchronous memory processing scheduling mechanism based on historical access popularity. This mechanism is embedded in the task distribution stage of the asynchronous memory processing system. It aims to dynamically rearrange the background processing queue by quantifying the "access urgency" of memory pages, thereby transforming the passive blocking mode of "application waiting for I / O" into an active service mode of "I / O catching up with application", and minimizing the resource contention waiting time of the foreground computing threads.
[0021] To realize the above concept, this application introduces a popularity score field into the memory management metadata and constructs three core modules: popularity scorer, version / cycle manager, and priority scheduling queue.
[0022] The popularity scorer is responsible for maintaining the historical access records of each physical page frame and calculating the real-time popularity value based on the current access event;
[0023] The version / cycle manager maintains a global logical clock or processing cycle version number, which is used to calculate the time span from the last time the page was accessed to the present.
[0024] The priority scheduling queue replaces the traditional FIFO linked list, using a data structure that supports efficient insertion and sorting to organize memory pages to be processed.
[0025] The core of this application lies in employing a highly efficient heat scoring model based on bit operations to quantify the urgency of memory page frame accesses with extremely low computational overhead. This model abandons complex floating-point operations or machine learning regression models, using a 64-bit unsigned integer as the heat scoring field for each monitored physical page frame. This field is essentially a time-series bitmap, simulating heat decay over time through bit shifting operations and accumulating the heat weight of the current period's access events through bit-setting operations.
[0026] Specifically, the calculation formula for the popularity rating model is as follows:
[0027]
[0028] Snew represents the updated current popularity score, Sold represents the historical score of this page when it was last captured or processed (initially 0), and ΔV represents the version difference, which is the difference between the current global processing cycle version number Vcurr and the version number Vlast when this page was last accessed (ΔV = Vcurr - Vlast). This value represents the degree of time decay. This means setting the most significant bit of the 64-bit integer to 1, which represents the access event occurring "at the current moment" and has the highest weight. This represents a right shift operation, simulating the natural decay of popularity over time. The larger ΔV is, the more bits the historical score "Sold" is shifted to the right, and the smaller its value, the more its contribution weight to the current score decreases exponentially.
[0029] The physical meaning of this formula is as follows: each time a memory page is accessed, the system first marks the current access as the highest priority (the highest bit is 1), and then decays the historical popularity score by shifting it to the right according to the time interval. ΔV reflects the number of processing cycles since the last access. The more cycles that have passed, the greater the decay of historical popularity, reflecting the principle of "proximate cause"—the more recent the access, the greater its contribution to the current popularity, and the more distant the access, the smaller its contribution.
[0030] In addition, the model also includes logical threshold control: if This means that the page has not been visited in the past 64 processing cycles, its historical popularity has been completely exhausted and reset to zero, and the next visit will directly reset the rating to the base weight of the current cycle, i.e., execute... This threshold design ensures that popularity scores do not accumulate indefinitely, while also preventing invalid historical data from interfering with current decisions.
[0031] The following is combined with Figure 1 The specific execution flow of the physical page frame access prediction algorithm provided in this application is described in detail. This algorithm is invoked when a page fault exception is triggered in the main computing thread. It is used to update the popularity score of the accessed page frame in real time and insert it into the priority queue according to the new score, thereby achieving dynamic adjustment of the background processing order.
[0032] Step S1: Obtain context information. When the main computing thread attempts to write to a write-protected memory page, the hardware memory management unit triggers a page fault. After catching the exception, the system first resolves the corresponding physical page frame address (addr) from the page table based on the virtual address where the access occurred. Then, it retrieves the metadata structure corresponding to the physical page frame from the system-maintained metadata tree (unit_tree), which records information such as the page frame's historical popularity score (key) and the version number (last_version) at the time of the last access.
[0033] Step S2: Calculate the version difference. Read the currently maintained processing cycle version number (v) and obtain the version number (u.last_version) of the page when it was last accessed from the page frame metadata. Calculate the version difference Δv = v - u.last_version. This difference represents the number of processing cycles since the page was last accessed, and is used for subsequent popularity decay calculations.
[0034] Step S3: Calculate the popularity score. Based on the version difference Δv calculated in Step S2, update the popularity score of the page frame according to the following rules: If Δv == 0, it means that the page has been visited in the current period, and there is no need to update the popularity score again; return directly. If Δv ≥ 64, it means that the page has not been visited in the past 64 processing periods, and the historical popularity has been completely exhausted. At this time, the popularity score is reset to the basic weight of the current period, i.e., u.key = 1 << 63. If 0 < Δv < 64, then execute the popularity score calculation formula based on bit operations: u.key = (1 << 63) | (u.key >> Δv). This operation marks the current visit as the highest priority (the highest bit is 1), and shifts the historical popularity score to the right by Δv bits to achieve exponential decay of historical popularity.
[0035] Step S4: Dynamically generate the scheduling queue. After updating the popularity score, insert the page frame into the corresponding position in the priority queue according to the new popularity score. In this embodiment, a red-black tree is used as the underlying sorting container of the priority queue, with the popularity score u.key as the key and the pointer to the page frame descriptor as the value.
[0036] Furthermore, the specific logic of the insertion operation is as follows:
[0037] If the updated popularity score u.key already has a node with the same key value in the red-black tree, then append the linked list node of this page frame to the linked list node corresponding to that key value;
[0038] If u.key does not exist in the red-black tree, and there is a successor key value s.key that is larger than u.key, then the linked list node of the page frame is appended to the linked list node corresponding to the successor node;
[0039] If u.key does not exist and has no successor key value, then the linked list node of that page frame is inserted as the new head node into the sorted list.
[0040] Through the above insertion logic, the system maintains a linked list of unprocessed page frames in real time, strictly sorted by popularity from high to low, for background threads to process in sequence.
[0041] Step S5: Update metadata and page table. Write the calculated new popularity score u.key back to the page frame metadata, and update the last version number u.last_version in the metadata to the current version number v. At the same time, set the read-only page that triggered the page fault to a writable state, and then resume the access flow of the main calculation thread so that it can write to the memory page normally.
[0042] Through steps S1 to S5 above, this application achieves real-time tracking and dynamic sorting of the access frequency of each memory page frame. When a background thread processes a memory page, it will prioritize processing "hot" pages with high access scores according to the priority queue, enabling these pages to be unprotected as quickly as possible. When the main computing thread accesses these hot pages again, they have most likely already been processed, thus avoiding write pauses and realizing a proactive service model shift from "application waiting for I / O" to "I / O catching up with application".
[0043] Experimental results show that for write-intensive loads, the method described in this application can significantly reduce page fault blocking at lower checkpoint frequencies. For example, at a checkpoint frequency of 100Hz, the throughput of Redis setup operations is increased by 76.45%, and the throughput of fetch operations is increased by 57.61%. At higher checkpoint frequencies, due to the shorter persistent queue, the performance impact of algorithm computational overhead is minimal (e.g., performance fluctuation is approximately 4.83% at 1000Hz). This application effectively eliminates head-of-queue blocking by transforming the passive blocking mode of "application waiting for I / O" into an active service mode of "I / O catching up with application," significantly reducing long-tail latency in asynchronous memory processing, improving the overall throughput and stability of the system under high load, and achieving a better match between computing resources and I / O resources.
[0044] To more intuitively understand how the page frame access prediction algorithm provided in this application solves the "write pause" problem in a real system, a detailed explanation is given below using a specific memory data persistence scenario. In this scenario, the system periodically persists modified memory pages (dirty pages) to the backend storage device. A background thread is responsible for processing these dirty pages, and during processing, the relevant memory pages are set to write-protected state.
[0045] Scenario Setting: Assume the current system checkpoint cycle version number is v=100, and three dirty pages have accumulated in the background processing queue: page A, page B, and page C. Page A is a frequently updated metadata page, while pages B and C are ordinary data pages. According to historical access records, page A has a high popularity score of 0xF0000000000000000 (i.e., the high digit of the historical score is 1), while the popularity scores of pages B and C are 0x00000000C0000000 and 0x0000000040000000 respectively. Following traditional FIFO scheduling, assuming the enqueue order is page B → page C → page A, page A is placed at the end of the queue and must wait for pages B and C to be processed before it can be processed.
[0046] Step S1 Triggered: Before the start of the next processing cycle, the main computing thread attempts to update the data in page A, triggering a page fault. After the system catches the exception, it resolves the physical page frame address based on the virtual address of page A and retrieves the metadata structure of page A from the metadata tree, which records the historical popularity score S. old =0xF000000000000000, last accessed version number V last =98.
[0047] Step S2 calculation: Read the current global version number V curr =100, calculate the version difference ΔV = 100 - 98 = 2. This value indicates that page A has not been accessed in the past 2 processing cycles.
[0048] Step S3 Update: Since ΔV=2<64, execute the popularity score calculation formula: S new = (1<<63) | (S old >>2). The specific calculation process is as follows: First, right-shift the historical score Sold=0xF000000000000000 by 2 bits to obtain 0x3C00000000000000; then set the highest bit to 1, i.e., perform a bitwise OR operation with 0x80000000000000000 to finally obtain Snew=0xBC000000000000000. This operation achieves the decay of historical popularity (from 0xF... to 0x3C...), while assigning the highest weight to the current access (the highest bit is 1).
[0049] Step S4 Insertion: The system inserts page A into the priority queue with the new popularity score 0xBC00000000000000. Since this score is higher than page B's 0xC0000000 and page C's 0x40000000, page A is inserted before all existing keys in the red-black tree, becoming the new head of the priority queue.
[0050] Step S5 Recovery: The system updates page A's metadata with the new popularity rating and the version number of the last visit, V. last =100, and at the same time set the page table entry of page A to writable, restore the access flow of the main thread, and the main thread can continue to execute without waiting.
[0051] Background processing: When the background thread retrieves a task from the priority queue, page A is retrieved first. The background thread processes page A first, performs the data persistence operation, and then removes the write protection of page A after completion. At this time, pages B and C are still waiting for processing in the queue.
[0052] Performance Comparison: Suppose that shortly after page A is processed, the main computation thread attempts to update page A again. In a traditional FIFO scheme, page A might still be waiting at the end of the queue, forcing the main thread to block and wait for pages B and C to finish processing. However, in this application's scheme, since page A has already been processed first and write protection has been removed, the main thread can directly write to page A without any waiting. Even if the main thread's second access occurs during a very short period while page A is being processed, it only needs to wait for page A itself to finish processing, without having to wait for all the cold pages (pages B and C) at the front of the queue, significantly reducing waiting time.
[0053] The comparison of the above real-world scenarios demonstrates that this application, by introducing a bitwise operation-based popularity scoring model and a priority scheduling mechanism, transforms the application's access requests to "hot" pages into scheduling priorities for the background processing queue, thus achieving a proactive service mode of "hot page priority processing." When the main thread accesses these hot pages again, they are highly likely to have already been processed, effectively avoiding write pauses and significantly reducing long-tail latency in the system.
[0054] This application also provides an electronic device, including a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the steps of the asynchronous memory processing scheduling method based on historical access frequency described above.
[0055] Specifically, the electronic device can be any computing device that requires memory resource scheduling and management, such as a server, desktop computer, laptop computer, embedded device, or mobile terminal. The processor can be a central processing unit, digital signal processor, application-specific integrated circuit, field-programmable gate array, or other programmable logic device. The memory can include computer-readable storage media such as random access memory, read-only memory, flash memory, hard disk, or solid-state drive.
[0056] When the processor executes a computer program stored in memory, it can perform the following functions: obtain historical access information of memory page frames; determine the real-time heat score of memory page frames using a bitwise operation-based heat scoring model; insert the memory page frames to be processed into a priority queue for dynamic reordering based on the real-time heat score; and execute a page frame access prediction algorithm in response to page faults. Through the coordinated operation of the above functions, this electronic device can effectively avoid write pauses in asynchronous memory processing scenarios, reduce long-tail latency, and improve overall performance and stability.
[0057] This application also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, can implement the steps of the asynchronous memory processing scheduling method based on historical access popularity described above. The computer-readable storage medium may include, but is not limited to, various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory, random access memory, magnetic disks, or optical disks.
[0058] This application also provides a computer program product, including a computer program / instructions that, when executed by a processor, implement the steps of the asynchronous memory processing scheduling method based on historical access frequency described above. This computer program product can be distributed as a software product, existing independently of an electronic device, or pre-installed in an electronic device.
[0059] The above provides a detailed description of an asynchronous memory processing scheduling method and electronic device based on historical access popularity, as provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and its core ideas. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.
Claims
1. An asynchronous memory processing scheduling method based on historical access popularity, comprising obtaining historical access information of memory page frames, wherein the historical access information includes historical access records of each memory page frame in multiple processing cycles; Its features are, Also includes: Based on the historical access information, a bitwise operation-based heat scoring model is used to determine the real-time heat score of the memory page frame; wherein, the heat scoring model simulates the decay of heat over time through bit shifting operations, and accumulates the heat weight of the current period's access events through bit setting operations, so as to quantify the access urgency of the memory page frame. Based on the real-time popularity score of the memory page frames, the memory page frames to be processed are inserted into a priority queue for dynamic rearrangement; the priority queue is used to replace the first-in-first-out queue, so that memory page frames with high popularity scores are placed at the head of the queue for priority processing. Once the background thread processes the memory page frame and removes its write protection, if the main computing thread accesses the memory page frame again, there is no need to trigger a write pause wait.
2. The method according to claim 1, characterized in that: The historical access information includes the historical popularity score of the memory page frame and the version number at the time of the last access.
3. The method according to claim 1, characterized in that, The bitwise operation-based popularity scoring model uses a 64-bit unsigned integer as the popularity scoring field, which is a time-series bitmap.
4. The method according to claim 3, characterized in that, The popularity scoring model is as follows: Where Snew represents the updated current popularity score, Sold represents the historical score when the page was last captured or processed, and ΔV represents the version difference. This means setting the most significant bit of a 64-bit integer to 1. This indicates a right shift operation.
5. The method according to claim 1, characterized in that, The priority queue uses a red-black tree as the underlying sorting container, with the real-time popularity score as the key and the page frame descriptor pointer as the value.
6. The method according to claim 5, characterized in that, The step of inserting the memory page frame to be processed into the priority queue includes: If the real-time popularity score already exists, then the memory page frame is appended to the linked list node corresponding to the key value; If the real-time popularity score does not exist but a successor key value exists, then the memory page frame is appended to the linked list node corresponding to the successor key value. If neither the key value nor its successor exists, the memory page frame is inserted as the new head node into the sorted linked list.
7. The method according to claim 1, characterized in that, The method further includes: triggering a page fault when the main computing thread attempts to access a memory page frame that is being processed in the background and is write-protected; and obtaining the physical address and historical access information of the memory page frame based on the page fault.
8. The method according to claim 1, characterized in that, The background thread's processing of the memory page frame includes persisting dirty pages to the backend storage device, and the write protection is used to prevent write tearing during the persistence process.
9. A computer-readable storage medium, characterized in that, It stores a computer program that, when executed by a processor, can implement the steps of the asynchronous memory processing scheduling method based on historical access popularity as described in any one of claims 1-8.
10. An electronic device, characterized in that, include: Memory and processor; The memory is used to store computer programs; The processor, when executing the computer program, implements the steps of the asynchronous memory processing scheduling method based on historical access popularity as described in any one of claims 1-8.