A data writing method and a storage device

Abstract

This application relates to a data writing method and a storage device. The method includes: in response to a write command, acquiring data to be written; determining multiple physical blocks corresponding to the data to be written based on the target address corresponding to the write command; splitting the data to be written into multiple sub-data and then alternately writing them into the multiple physical blocks. Specifically, during the initial switch between the first and second physical blocks, the physical block written first is not fully written. Furthermore, in the two write operations before and after the switch, one write is to a first-type page on a physical block, and the other writes to a second-type page on a different physical block; the difference in programming time between the two types of pages is greater than a preset difference. This application can balance the writing based on the difference in programming time between different types of pages within a physical block, distributing pages with longer programming times as evenly as possible throughout the entire data writing process, thus solving the problem of write performance jitter.

Description

Technical Field

[0001] This application relates to the field of solid-state drive technology, and in particular to a data writing method and a storage device. Background Technology

[0002] Solid-state drives (SSDs) consist of flash memory chips and a controller chip. The storage medium used by the flash memory chips is generally NAND flash memory. The smallest unit for reading, writing, and erasing data on the storage medium differs. Data is typically stored and read in pages, such as 4KB, 8KB, or 16KB; while data is erased in blocks. A block contains multiple pages, usually ranging from dozens to hundreds, such as a block containing 64 pages or 128 pages.

[0003] In related technologies, there are significant differences in the completion time of data write operations on different pages in certain models of NAND flash memory. For example, the completion time of data write operations on the last page of the same block is significantly higher than that of other page areas. This causes the entire block to exhibit high write performance at the beginning, but then the performance suddenly drops in the last page of the block, resulting in periodic fluctuations in the overall write performance. Summary of the Invention

[0004] To address the aforementioned technical problems, this application provides a data writing method and a storage device.

[0005] Firstly, this application provides a data writing method, the method comprising: In response to a write command, retrieve the data to be written; According to the target address corresponding to the write command, the multiple sub-data segments divided from the data to be written are alternately written into at least two physical blocks containing a first physical block and a second physical block; Specifically, during the first switch between the first physical block and the second physical block, the physical block written first is not fully written; in the two writes before and after the switch of physical blocks, the difference in programming time for a single page write is greater than a preset difference.

[0006] In one alternative implementation, the number of pages of data written during the two write operations before and after switching physical blocks is related to the programming time of a single page write.

[0007] In one alternative implementation, Before alternatingly writing the multiple sub-data segments of the data to be written, divided into them, to at least two physical blocks containing a first physical block and a second physical block according to the target address corresponding to the write command, the method further includes: The target address corresponding to the write command is determined according to the address jump table; wherein the target address indicates at least two physical blocks, the at least two physical blocks include a first physical block and a second physical block, the address jump table is used to describe the alternating write order of the at least two physical blocks, the alternating write order includes the alternating write order between first type pages and second type pages on the at least two physical blocks, and the difference between the programming time of writing the first type page and writing the second type page is greater than a preset difference.

[0008] In one optional implementation, the step of alternately writing multiple sub-data segments, divided from the data to be written, into at least two physical blocks containing a first physical block and a second physical block, according to the target address corresponding to the write command, includes: Write the first sub-data, which is split from the data to be written, into the first number of pages of the first type in the first physical block; Switching from the first physical block to the second physical block, the second sub-data, which is split from the data to be written, is written into the second type of pages of the second physical block in the number of second pages; wherein, the programming time for writing the first type of pages is greater than the programming time for writing the second type of pages, and the ratio between the number of first pages and the number of second pages is determined based on the programming time of the first type of pages and the second type of pages.

[0009] In one optional implementation, the ratio between the number of the first page and the number of the second page is determined based on the ratio between the number of first type pages and the number of second type pages on the first physical block and the second physical block.

[0010] In one alternative implementation, the address skip table is determined based on the programming time of writing each page in the at least two physical blocks.

[0011] In one optional implementation, the method further includes: Real-time detection of the programming time of each page in the physical block corresponding to the address jump table; The address skip table is updated based on the programming time of each page.

[0012] In one optional implementation, updating the address skip table based on the programming time of each page includes: The number of consecutive pages of the second type of page in the address jump table is adjusted according to the programming time of each page.

[0013] In an optional implementation, before determining the target address corresponding to the write command based on the address jump table, the method further includes: Identify at least two physical blocks and detect the programming time for writing to each page on the at least two physical blocks; An address skip table is generated based on the programming time of each page.

[0014] Secondly, this application provides a storage device including a controller and a non-volatile memory chip, the controller being used to perform the data writing method described above.

[0015] The technical solution provided in this application has the following advantages compared with the prior art: In the data writing method provided in this application embodiment, in response to a write command, data to be written is obtained. Based on the target address corresponding to the write command, multiple physical blocks corresponding to the data to be written are determined. The data to be written is then split into multiple sub-data and alternately written to the multiple physical blocks. Specifically, during the initial alternation between the first and second physical blocks, the physical block written first is not fully written. Furthermore, in the two write operations before and after the alternation, one write is to a first-type page on a physical block, and the other writes to a second-type page on another physical block; the difference in programming time between the two types of pages is greater than a preset difference.

[0016] By adopting the above technical solution, the beneficial effect of this application is that when a write command is received to write data, the same data to be written can be written alternately across multiple physical blocks. Specifically, if the first physical block is not completely written, the application can switch to the second physical block to continue writing data, and there is a significant difference in the programming time of a single page before and after the switch. Therefore, this application can balance the writing based on the differences in programming time for different types of pages within a physical block, distributing pages with longer programming times as evenly as possible throughout the entire data writing process, thus solving the problem of write performance jitter. Attached Figure Description

[0017] The above and other features, advantages, and aspects of the embodiments of this application will become more apparent from the accompanying drawings and the following detailed description. Throughout the drawings, the same or similar reference numerals denote the same or similar elements. It should be understood that the drawings are schematic, and the originals and elements are not necessarily drawn to scale.

[0018] Figure 1 This is a programming time distribution diagram provided in related technologies; Figure 2 This is a schematic diagram of the write data bandwidth of NAND flash memory provided in related technologies; Figure 3 A flowchart illustrating a data writing method provided in an embodiment of this application; Figure 4 A schematic diagram of the structure of a physical block provided in an embodiment of this application; Figure 5 A flowchart illustrating another data writing method provided in an embodiment of this application; Figure 6 A schematic diagram of NAND flash memory write data bandwidth provided in an embodiment of this application; Figure 7 This is a schematic diagram of the structure of a data writing device provided in an embodiment of this application; Figure 8 This is a schematic diagram of the structure of a storage device provided in an embodiment of this application. Detailed Implementation

[0019] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0020] The following detailed embodiments are provided to aid the reader in gaining a comprehensive understanding of the methods, apparatus, and / or systems described herein. However, various changes, modifications, and equivalents of the methods, apparatus, and / or systems described herein will become apparent upon understanding this disclosure. For example, the order of operations described herein is merely illustrative and is not limited to those orders set forth herein, but may be changed as will become clear upon understanding this disclosure, except for operations that must occur in a specific order. Furthermore, for the sake of clarity and conciseness, descriptions of features known upon understanding this disclosure may be omitted.

[0021] The features described herein may be implemented in different forms and should not be construed as being limited to the examples described herein. Rather, the examples described herein are provided merely to illustrate some of the many feasible ways of implementing the methods, apparatus, and / or systems described herein that will be clear upon understanding the disclosure of this application.

[0022] Throughout this specification, when a component is described as "connected to" or "attached to" another component, the component may be directly "connected to" or "attached to" the other component, or there may be one or more other components in between. Conversely, when an element is described as "directly connected to" or "directly attached to" another element, there may be no other elements in between. Similarly, similar expressions (e.g., "between" and "immediately between," and "adjacent to" and "closely adjacent to") should be interpreted in the same manner. As used herein, the term "and / or" includes any one of the relevant listed items or any combination of any two or more of the relevant listed items.

[0023] Although terms such as “first,” “second,” and “third” may be used herein to describe various components, assemblies, regions, layers, or parts, these components, assemblies, regions, layers, or parts are not limited by these terms. Rather, these terms are used only to distinguish one component, assembly, region, layer, or part from another. Therefore, without departing from the teaching of the examples described herein, the first component, first assembly, first region, first layer, or first part referred to as the first component, first assembly, first region, first layer, or first part may also be referred to as the second component, second assembly, second region, second layer, or second part.

[0024] The terminology used herein is for the purpose of describing various examples only and is not intended to limit disclosure. Unless the context clearly indicates otherwise, the singular form is intended to include the plural form as well. The terms “comprising,” “including,” and “having” indicate the presence of the features, quantities, operations, components, elements, and / or combinations thereof stated therein, but do not preclude the presence or addition of one or more other features, quantities, operations, components, elements, and / or combinations thereof.

[0025] It should be noted that, unless there is a conflict, the various features in the embodiments of this application can be combined with each other, all of which are within the protection scope of this application. Furthermore, although functional modules are divided in the device schematic diagram and a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in a different order than the module division in the device or the order in the flowchart. Moreover, the terms "first," "second," and "third" used in this application do not limit the data or execution order, but only distinguish identical or similar items with essentially the same function and effect.

[0026] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as understood based on the disclosure of this application and as commonly understood by one of ordinary skill in the art to which this application pertains. Unless expressly defined herein, terms (such as those defined in a general dictionary) shall be interpreted as having the same meaning as they have in the context of the relevant art and in the disclosure of this application, and shall not be interpreted ideally or overly formally. The use of the term “may” herein with respect to examples or embodiments (e.g., regarding what an example or embodiment may include or implement) indicates the existence of at least one example or embodiment that includes or implements such a feature, while not all examples are limited thereto.

[0027] In related technologies, the data writing process of storage devices (such as solid-state drives) is usually as follows: the main control chip responds to the write command, receives the data to be written from the host, first checks whether there are free pages in the target storage block, if so, it allocates the target physical block and the pages in that physical block, and writes the data to the flash memory chip; if not, it first migrates the valid data in the physical block to other physical blocks, then erases the entire physical block, and only after releasing the free pages can new data be written.

[0028] For write commands, the smallest unit of writing is a page. The data to be written is written to the target block in the order of the page index. After the current block is full, the process switches to the next block to continue writing.

[0029] Figure 1 A programming time distribution diagram provided for related technologies, such as Figure 1 As shown, the horizontal axis corresponds to a page index within a block, and the vertical axis corresponds to programming time, measured in microseconds (µs). For certain NAND flash memory models, within the same block, the programming time (tProg) is short and the write performance is high when writing pages at the beginning of the block. However, when writing pages at the end of the block, the programming time (tProg) increases, leading to a significant decrease in write performance. This difference in write performance between different pages within a block causes the overall write bandwidth to fluctuate periodically, affecting write stability. The end of the block is roughly located at the last eighth of the total page area (the exact location may vary depending on the specific NAND model). The programming time also differs between different page areas, approximately 2 to 3 times longer.

[0030] To illustrate the above issues, the relevant embodiments in this document provide a schematic diagram of NAND flash memory write data bandwidth, such as... Figure 2 As shown, the horizontal axis represents time in seconds (s), reflecting the trend of data write performance over time; the vertical axis represents data bandwidth in MB / s, representing the data write speed at different times. Figure 2 The broken line represents the real-time write bandwidth, which exhibits periodic fluctuations. Figure 2 The straight line represents the relationship between speed and the amount of data written; as the amount of data written accumulates, the overall writing speed decreases.

[0031] To address the aforementioned problems, embodiments of this application provide a data writing method, apparatus, and storage device. The following describes... Figure 3 The data writing method provided in the embodiments of this application will be described in detail.

[0032] Figure 3 A flowchart illustrating a data writing method provided in an embodiment of this application is shown.

[0033] In this embodiment, the data writing method can be executed by the main control chip of the storage device. The storage device may include devices with flash memory storage media, such as solid-state drives (SSDs).

[0034] like Figure 3 As shown, the data writing method may include the following steps: S301: Responds to a write command and retrieves the data to be written.

[0035] In this embodiment, after receiving a write command from the host, the main control chip obtains the data to be written as indicated by the write command, which is then used as the data to be written. The data to be written is the data that needs to be written in this instance.

[0036] The write command instructs the main control chip to write data to the flash memory chip. The flash memory chip consists of physical blocks, and each physical block consists of pages. The write command writes data in the order of the page index, with the page as the smallest unit.

[0037] S302: Based on the target address corresponding to the write command, the multiple sub-data segments divided from the data to be written are alternately written into at least two physical blocks containing a first physical block and a second physical block.

[0038] Specifically, during the first switch between the first physical block and the second physical block, the physical block written first is not fully written; in the two writes before and after the switch of physical blocks, the difference in programming time for a single page write is greater than a preset difference.

[0039] In this embodiment, after determining the target address corresponding to the write command, the main control chip determines the physical block corresponding to the data to be written. In this embodiment, the target address of the data to be written corresponds to multiple physical blocks, meaning that writing the data to be written is completed by alternately switching between multiple physical blocks.

[0040] The first physical block and the second physical block can be any two of the multiple physical blocks indicated by the target address. During the writing process of the data to be written, there may be a situation where the writing is switched from one physical block to another. In this embodiment of the application, when switching between two physical blocks for the first time, the writing can be switched to another physical block to continue writing the data to be written before the first physical block has been completely written.

[0041] In addition, the difference in programming time for a single page write between the two writes before and after switching physical blocks is greater than a preset difference. Specifically, the difference between the programming time for a single page write in the previous write before switching physical blocks and the programming time for a single page write in the subsequent write of the same physical block is greater than the preset difference.

[0042] Suppose that, for a given physical block switch, the programming time for a single page write in the previous write operation is greater than a preset first threshold, indicating that the previous write was to a first-type page; and the programming time for a single page write in the subsequent write operation is less than a preset second threshold, indicating that the subsequent write was to a second-type page. The preset first threshold is significantly greater than the preset second threshold.

[0043] refer to Figure 4 This is a schematic diagram of a physical block structure provided in an embodiment of this application. The target address indicated by the write command includes block A and block B, where both block A and block B include pages with longer programming times and pages with shorter programming times. Writing is performed on the same block in page index order. After a block is full, the entire block is erased, and writing continues. Figure 4 The blockA' shown represents the state after blockA has been erased and writing continues. Similarly, blockB and blockB' can be understood in the same way.

[0044] In practical applications, assuming that after writing to page 5 in block A, you can switch to block B and continue writing to pages 6, 8, and 10 in block B, thereby achieving switching and writing between multiple physical blocks in sequence.

[0045] In one optional implementation, the target address corresponding to the write command includes block identifiers of multiple physical blocks. Based on the type of physical block corresponding to the block identifier, the timing of switching writes between different physical blocks can be determined. For example, if the previous physical block was written to a first-type page, such as a slow upper page, the subsequent physical block needs to be written to three consecutive second-type pages, such as fast lower pages.

[0046] In practical applications, after determining the target address corresponding to the write command, the data to be written is split into multiple sub-data, which are then written to multiple physical blocks indicated by the target address.

[0047] In one optional implementation, a first subset of the data to be written is written to a first physical block. While writing this first subset to the first physical block, the system switches to a second physical block and writes the second subset of the data to be written to the second physical block. It is worth noting that after writing the first subset of data to the first physical block, the first physical block does not need to be fully written. Each subset of data split from the data to be written can be written to a physical block using the above method.

[0048] In this embodiment, the data to be written is switched from the first physical block to the second physical block. The number of pages of data written in the two writing operations before and after the physical block switch is related to the programming time of a single page write.

[0049] Specifically, in the two write operations before and after the physical block switch, the first subset of data is written to M pages in the first physical block. After switching to the second physical block, the second subset of data is written to N pages in the second physical block. Here, M represents the number of pages written before the physical block switch, and N represents the number of pages written after the physical block switch. Specifically, the determination of M and N is related to the programming time of single-page writes in the first and second physical blocks during the two write operations before and after the physical block switch. Assuming that the programming time of single-page writes in the first physical block is greater than a preset first threshold, it indicates that the data is being written to first-type pages in the first physical block; and the programming time of single-page writes in the second physical block is less than a preset second threshold, it indicates that the data is being written to second-type pages in the second physical block. Therefore, M... <N。

[0050] Furthermore, the ratio between M and N can be determined based on the ratio of programming time for single-page writes in the first and second physical blocks during the two write operations before and after switching physical blocks. For example, if the ratio of programming time for single-page writes in the first and second physical blocks is 5:1, then M:N can be set to 1:5. That is, data is first written to one type 1 page in the first physical block, then switched to the second physical block, and finally data is written to five type 2 pages in the second physical block to balance the write time of pages with longer programming times.

[0051] In the data writing method provided in this application embodiment, when a write command is received to write data, the same data to be written can be written alternately across multiple physical blocks. Specifically, if the first physical block is not completely written, the system can switch to the second physical block to continue writing data, and there is a significant difference in the programming time of a single page before and after the switch. Therefore, this application embodiment can balance the writing process based on the differences in programming time for different types of pages within a physical block, distributing pages with longer programming times as evenly as possible throughout the entire data writing process, thus solving the problem of write performance jitter.

[0052] Based on the above embodiments, this application also provides a data writing method, referring to... Figure 5 The flowchart of another data writing method provided in the embodiments of this application specifically includes: S501: Responds to a write command and retrieves the data to be written.

[0053] In this embodiment, the main control chip receives a write command from the host. The write command indicates the data to be written in this instance.

[0054] S502: Determine the target address corresponding to the write command based on the address jump table.

[0055] The target address indicates at least two physical blocks, including a first physical block and a second physical block. The address skip table is used to describe the alternating write order of the at least two physical blocks. The alternating write order includes the order in which first type pages and second type pages are written alternately on the at least two physical blocks. The difference between the programming time for writing the first type page and the programming time for writing the second type page is greater than a preset difference.

[0056] In this embodiment, after receiving a write command, the main control chip allocates a target address for the write command according to a pre-configured address skip table. The target address uniquely identifies the physical address in the flash memory chip, i.e., the write location. Specifically, the target address can indicate the target block to which the data to be written is to be written. Further, the target address can also indicate the specific target page to be written on that target block. Specifically, the target address may include the page index of the target block and the target page.

[0057] The address skip table can be a pre-configured address alternation rule table used to describe the alternating write order when writing to at least two physical blocks simultaneously. Specifically, this alternating write order involves alternating between first-type and second-type pages in different physical blocks. In other words, during data writing, the process alternates between the first-type and second-type pages of different physical blocks. Specifically, it allows switching to another physical block to continue writing before the previous physical block has been fully written. By switching between different physical blocks, the page programming time of different physical blocks is balanced, further reducing the performance degradation caused by page writes that take longer to program on physical blocks.

[0058] Specifically, based on the duration of the write operation, pages within a physical block are divided into a first type of page and a second type of page. The programming time of the second type of page is less than a preset second threshold, while the programming time of the first type of page is greater than a preset first threshold. The preset first threshold is greater than the preset second threshold, and the preset first threshold and the preset second threshold are preset time values.

[0059] By setting a preset first threshold and a preset second threshold, the write performance difference between the first type of page and the second type of page can be distinguished, providing a basis for subsequent alternating writes and balancing write time.

[0060] In the alternating write sequence, adjacent first-type pages and second-type pages belong to different physical blocks. That is, the alternating write sequence pre-configured the adjacent write order between different types of pages, and adjacent writes of different types of pages are located in different physical blocks. Based on this alternating write sequence, during a data write operation to a first-type page of one physical block, the data write operation can be switched to a second-type page of another physical block without waiting for the write to complete. For example, the alternating write sequence can be preset as follows: first-type page 1 of block A — second-type pages 1, 2, 3 of block B — first-type page 2 of block A — second-type pages 4, 5, 6 of block B.

[0061] By alternating the writing order of first-type pages and second-type pages on different physical blocks, during the data writing process, when a data writing operation is performed on the first-type page of one physical block, a data writing operation is performed on the second-type page of another physical block. This balances the data writing time on pages with longer programming times, thereby achieving stable writing speed.

[0062] In one optional implementation, the address skip table can be generated in real time. Specifically, before the main control chip determines the target address corresponding to the write command based on the address skip table, at least two physical blocks are identified, and the programming time of each page on the at least two physical blocks is detected. Based on the detected programming time of each page, the page type (first type page or second type page) of each page in the at least two physical blocks is determined, and then the address skip table is generated. The address skip table is used to describe the alternating write order of the at least two physical blocks, and the alternating write order includes the alternating write order between the first type pages and the second type pages on the at least two physical blocks.

[0063] In this embodiment, by generating an address skip table in real time, the alternating write order in the address skip table can be precisely matched with the actual write performance of the current storage device, further improving the balance of data write speed and thus improving the stability of the overall data write speed.

[0064] S503: Write the first sub-data, which is split from the data to be written, into a first type of page, which is a first number of pages in the first physical block. Switch from the first physical block to the second physical block and write the second sub-data, which is split from the data to be written, into a second type of page, which is a second number of pages in the second physical block.

[0065] The programming time for writing to the first type of page is greater than the programming time for writing to the second type of page, and the ratio between the number of the first page and the number of the second page is determined based on the programming time of the first type of page and the second type of page.

[0066] In this embodiment of the application, after the main control chip determines the target address for the data to be written, it can divide the data to be written into multiple sub-data in sequence, including the first sub-data and the second sub-data.

[0067] Based on the target address, locate the corresponding physical block, and alternately write the sub-data, which is split from the data to be written, into different physical blocks to complete the data writing.

[0068] The data writing method provided in this application embodiment, after the main control chip receives a write command, determines the target address corresponding to the write command through an address jump table, and writes the data to be written indicated by the write command into multiple physical blocks corresponding to the target address. During data writing, by using the order of alternating writing of first-type pages and second-type pages on different physical blocks recorded in the address jump table, it is possible to switch to the second-type page of another physical block to continue the data writing operation without waiting for the first-type page of one physical block to complete the writing process. This balances the data writing time on pages with longer programming times, improves the stability of the data writing speed, and thus improves the overall data writing performance.

[0069] In one optional implementation, the ratio between the number of first pages and the number of second pages is determined based on the ratio between the number of first-type pages and second-type pages on the first physical block and the second physical block. Specifically, the address skip table configuration can be determined based on the ratio between the number of first-type pages and second-type pages on at least two physical blocks. Specifically, the ratio between the number of first-type pages and second-type pages on at least two physical blocks is first determined, and then, based on this ratio, the number of consecutive second-type pages in the address skip table that are adjacent to and follow the first-type pages is determined.

[0070] For example, suppose there are two physical blocks, block A and block B. The ratio of the number of second-type pages in block A to the number of first-type pages in block B is 10:1. Then, after writing a first-type page in block B, switch to block A to write 10 second-type pages continuously, and then switch back to block B, and so on.

[0071] By flexibly configuring the address skip table based on the ratio of the number of first-type pages to second-type pages, the data writing time of pages with longer programming times can be fully distributed among the write operations of more pages with shorter programming times, further balancing the overall write time, reducing write bandwidth fluctuations, and thus effectively improving the stability and continuous write performance of the data writing process.

[0072] Based on the above embodiments, in order to further improve the stability of data writing speed, the writing time of the first type page of at least one physical block in the address jump table can be made close to the writing time of the consecutive second type pages of the adjacent physical block. Specifically, a preset third threshold is set in advance, and the difference between the writing time of the first type page in the address jump table and the total writing time of the consecutive pages corresponding to the second type page is not greater than the preset third threshold.

[0073] By controlling the difference between the write time of the first type of page and the total write time of the corresponding consecutive pages of the second type of page within a preset third threshold, the write time of the page with a longer programming time can be masked by the write operation of the page with a shorter programming time in another physical block, avoiding significant bandwidth fluctuations, thereby ensuring a stable write speed and achieving smooth and stable write performance.

[0074] In one optional implementation, to further improve data write performance, the address skip table can be flexibly configured based on the analysis results of the write time of each page on the target physical block. Specifically, the write time of each page in at least two physical blocks is detected, and the address skip table is configured based on the detected write time analysis.

[0075] Optionally, the number of consecutive second-type pages adjacent to the first-type page in the address jump table can be determined based on the write time of the first-type page. This number of consecutive second-type pages is directly proportional to the write time of the first-type page; the longer the write time of the first-type page, the more consecutive second-type pages are adjacent to it.

[0076] By dynamically configuring the address skip table based on the actual write time of each page on the target physical block, the number of consecutive second-type pages can be flexibly adjusted, so that the data write time of the second-type pages is adapted to the data write time of the first-type pages. This can more accurately match the performance difference between the first-type pages and the second-type pages, fully offset the bandwidth jitter caused by the excessive write time of pages with long programming times, further ensure the smoothness of the data write process, and improve the overall write performance.

[0077] In practical applications, the write time of each page within a physical block can vary due to factors such as flash memory chip wear. Therefore, during data write operations, the write time of each page on the physical block corresponding to the address skip table can be monitored in real time, and the address skip table can be updated based on the real-time monitoring results.

[0078] Specifically, the write time of the first page on the first physical block is obtained. If this write time is different from the original detection time, the address skip table is updated based on the write time. Here, the first physical block can be any physical block in the address skip table, and the first page is any page (fast / slow page) on the first physical block.

[0079] In one optional implementation, if the first page is a first-type page, and during the data write operation, it is detected that the write time of the first page is greater than the original detected time, then based on the write time, the number of consecutive second-type pages adjacent to and following the first page in the address skip table is adjusted. The original detected time can be the write time detected when configuring the address skip table.

[0080] By monitoring the data writing time of each page in real time and dynamically updating the address jump table during the data writing process, the alternating writing order can be adjusted in a timely manner, ensuring that the data writing time between pages with different programming times is matched, maintaining stable writing bandwidth, and further improving overall writing performance.

[0081] To better understand the above content, this application provides an example of an address skip table. The alternating write order of the address skip table described below is as follows: ... A-page 5802 / 5803 / 5804, B-page 0 / 1 / 2, B-page 3 / 4 / 5, B-page 6 / 7 / 8, A-page 5805 / 5806 / 5807, B-page 9 / 10 / 11, B-page 12 / 13 / 14, B-page 15 / 16 / 17, B-page 18 / 19 / 20, B-page 21 / 22 / 23, A-page 5808 / 5809 / 5810, ... Among them, A-page 5802 / 5803 / 5804 correspond to three second-type pages in block B, and A-page 5805 / 5806 / 5807 correspond to four second-type pages in block B.

[0082] Because the write times of A-pages 5802 / 5803 / 5804 and A-pages 5805 / 5806 / 5807 are different, with A-pages 5805 / 5806 / 5807 taking longer, the number of pages of block B inserted between the two blocks of A is different. More pages of block B are inserted after A-pages 5805 / 5806 / 5807, which have longer write times, to balance the write latency fluctuations caused by the long-write-time pages in block A and ensure stable overall write bandwidth.

[0083] The address skip table described above uses TLC NAND flash as an example. Because it is a TLC type flash memory chip, three pages are written each time. If the NAND type changes, the number of pages written each time will also change accordingly. This also applies to the above embodiment and the address skip table switching method in this embodiment.

[0084] like Figure 6 The diagram illustrates the data writing bandwidth of a NAND flash memory according to an embodiment of this application. The main controller chip of the NAND flash memory uses the data writing method provided in this embodiment. The horizontal axis represents time in seconds (s), reflecting the changing trend of data writing performance over time; the vertical axis represents data bandwidth in MB / s, characterizing the data writing speed at different times.

[0085] As shown in the figure, the curve in the figure is the real-time write bandwidth curve, which shows a smooth trend overall; the straight line in the figure represents the relationship between speed and write volume, and the write speed is generally stable as the write volume accumulates.

[0086] A further implementation involves using two blocks alternately if this still cannot perfectly balance the distribution of time-consuming pages. More blocks can be used alternately to build a skip list of three or more blocks, enabling switching and writing between more blocks.

[0087] The above writing process can distribute the page areas with large programming times as much as possible throughout the entire writing process. In terms of second-level performance, it can reduce the impact of programming time fluctuations, resulting in stable overall performance and good performance consistency.

[0088] In one optional implementation, taking a three-block address skip table as an example, assuming the address skip table is for blocks A, B, and C, the physical block switching order can be set from block A, then block B, and finally block C. Block A has the longest programming time, followed by block B, and lastly block C. Therefore, when writing data, block A, which has the longest programming time, is written first. While data is being written to block A, the system switches to block B to continue writing data. If there is still data to be written, the system switches to block C to continue writing data. It is worth noting that the previous physical block may not have been completely written during each switch.

[0089] In this embodiment, the switching order can be from blockA, blockB to blockC, avoiding a direct switch from blockA to blockC, which would cause significant jitter due to large differences in programming time. In practical applications, it is necessary to switch to physical blocks with closer programming times, which can make the balancing smoother, the overall performance stable, and the performance consistency better.

[0090] Figure 7 This is a schematic diagram of a data writing device provided in an embodiment of this application. The device can be implemented by software and / or hardware, and can also be integrated into an electronic device. Figure 7 As shown, the data writing device includes: The acquisition module 701 is used to acquire the data to be written in response to a write command; The writing module 702 is used to alternately write multiple sub-data segments, which are divided into the data to be written, into at least two physical blocks containing a first physical block and a second physical block, according to the target address corresponding to the write command. Specifically, during the first switch between the first physical block and the second physical block, the physical block written first is not fully written; in the two writes before and after the switch of physical blocks, the difference in programming time for a single page write is greater than a preset difference.

[0091] In one alternative implementation, the number of pages of data written during the two write operations before and after switching physical blocks is related to the programming time of a single page write.

[0092] In one optional embodiment, the apparatus further includes: A determination module is used to determine the target address corresponding to the write command based on an address skip table; wherein the target address indicates at least two physical blocks, the at least two physical blocks include a first physical block and a second physical block, the address skip table is used to describe the alternating write order of the at least two physical blocks, the alternating write order includes the alternating write order between first type pages and second type pages on the at least two physical blocks, and the difference between the programming time for writing the first type page and writing the second type page is greater than a preset difference.

[0093] In one optional implementation, the writing module includes: The first writing submodule is used to write the first sub-data, which is split from the data to be written, into a first type of page of a first number of pages in the first physical block; The second write submodule is used to switch from the first physical block to the second physical block and write the second sub-data, which is split from the data to be written, into a second type of page with a second number of pages in the second physical block; wherein the programming time for writing the first type of page is greater than the programming time for writing the second type of page, and the ratio between the number of the first page and the number of the second page is determined based on the programming time of the first type of page and the second type of page.

[0094] In one optional implementation, the ratio between the number of the first page and the number of the second page is determined based on the ratio between the number of first type pages and the number of second type pages on the first physical block and the second physical block.

[0095] In one alternative implementation, the address skip table is determined based on the programming time of writing each page in the at least two physical blocks.

[0096] In one optional embodiment, the apparatus further includes: The first detection module is used to detect the programming time of each page in the physical block corresponding to the address jump table in real time. An update module is used to update the address skip table based on the programming time of each page.

[0097] In one optional implementation, the update module is specifically used for: The number of consecutive pages of the second type of page in the address jump table is adjusted according to the programming time of each page.

[0098] In one optional embodiment, the apparatus further includes: The second detection module is used to identify at least two physical blocks and detect the programming time of writing to each page on the at least two physical blocks; The generation module is used to generate an address skip table based on the programming time of each page.

[0099] The data writing apparatus provided in this application embodiment, in response to a write command, acquires the data to be written, determines multiple physical blocks corresponding to the data to be written based on the target address corresponding to the write command, and splits the data to be written into multiple sub-data, which are then alternately written into the multiple physical blocks. Specifically, during the initial alternation between the first and second physical blocks, the physical block written first is not completely written. Furthermore, in the two write operations before and after the alternation, one write is to a first type page on a physical block, and the other writes to a second type page on a different physical block; the difference in programming time between the two types of pages is greater than a preset difference.

[0100] By adopting the above technical solution, the beneficial effect of this application is that when a write command is received to write data, the same data to be written can be written alternately across multiple physical blocks. Specifically, if the first physical block is not completely written, the application can switch to the second physical block to continue writing data, and there is a significant difference in the programming time of a single page before and after the switch. Therefore, this application can balance the writing based on the differences in programming time for different types of pages within a physical block, distributing pages with longer programming times as evenly as possible throughout the entire data writing process, thus solving the problem of write performance jitter.

[0101] The data writing device provided in this application embodiment can execute the data writing method provided in any embodiment of this application, and has the corresponding functional modules and beneficial effects of the execution method.

[0102] Based on the same inventive concept, embodiments of this application also provide a storage device, such as... Figure 8 The diagram shown is a structural schematic of a storage device provided in an embodiment of this application. The storage device may include a controller 801 and a memory 802, wherein the memory 802 stores a computer program. When the computer program is executed by the controller 801, it can implement the method provided in any of the above embodiments. The execution method and beneficial effects are similar and will not be described again here.

[0103] Of course, for the sake of simplicity, Figure 8 Only some of the components of the storage device relevant to the present invention are shown, omitting components such as buses, input / output interfaces, input devices, and output devices. In addition, the storage device may include any other suitable components depending on the specific application.

[0104] This application also provides a non-volatile computer storage medium storing computer-executable instructions that are executed by one or more processors. For example, the one or more processors can execute the data writing method in any of the above method embodiments, such as executing the data writing method in any of the above method embodiments, or executing the steps described above.

[0105] The apparatus or device embodiments described above are merely illustrative. The unit modules described as separate components may or may not be physically separate, and the components shown as module units may or may not be physical units; that is, they may be located in one place or distributed across multiple network module units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0106] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented using software plus a general-purpose hardware platform, or of course, using hardware. Based on this understanding, the above technical solutions, in essence or the parts that contribute to the related technology, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods of various embodiments or some parts of embodiments.

[0107] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and not to limit them; under the concept of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of this application as described above. For the sake of brevity, they are not provided in detail; although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A data writing method, characterized in that, The method includes: In response to a write command, retrieve the data to be written; According to the target address corresponding to the write command, the multiple sub-data segments divided from the data to be written are alternately written into at least two physical blocks containing a first physical block and a second physical block; Specifically, during the first switch between the first physical block and the second physical block, the physical block written first is not fully written; in the two writes before and after the switch of physical blocks, the difference in programming time for a single page write is greater than a preset difference.

2. The method according to claim 1, characterized in that, The number of pages written before and after switching physical blocks is related to the programming time for a single page write.

3. The method according to claim 1 or 2, characterized in that, Before alternatingly writing the multiple sub-data segments of the data to be written, divided into them, to at least two physical blocks containing a first physical block and a second physical block according to the target address corresponding to the write command, the method further includes: The target address corresponding to the write command is determined according to the address jump table; wherein the target address indicates at least two physical blocks, the at least two physical blocks include a first physical block and a second physical block, the address jump table is used to describe the alternating write order of the at least two physical blocks, the alternating write order includes the alternating write order between first type pages and second type pages on the at least two physical blocks, and the difference between the programming time of writing the first type page and writing the second type page is greater than a preset difference.

4. The method according to claim 3, characterized in that, The step of alternately writing multiple sub-data segments, divided from the data to be written, into at least two physical blocks containing a first physical block and a second physical block, according to the target address corresponding to the write command, includes: Write the first sub-data, which is split from the data to be written, into the first number of pages of the first type in the first physical block; Switching from the first physical block to the second physical block, the second sub-data, which is split from the data to be written, is written into the second type of pages of the second physical block in the number of second pages; wherein, the programming time for writing the first type of pages is greater than the programming time for writing the second type of pages, and the ratio between the number of first pages and the number of second pages is determined based on the programming time of the first type of pages and the second type of pages.

5. The method according to claim 4, characterized in that, The ratio between the number of the first page and the number of the second page is determined based on the ratio between the number of first-type pages and second-type pages on the first physical block and the second physical block.

6. The method according to claim 3, characterized in that, The address skip table is determined based on the programming time of writing each page in the at least two physical blocks.

7. The method according to claim 3, characterized in that, The method further includes: Real-time detection of the programming time of each page in the physical block corresponding to the address jump table; The address skip table is updated based on the programming time of each page.

8. The method according to claim 7, characterized in that, The step of updating the address skip table based on the programming time of each page includes: The number of consecutive pages of the second type of page in the address jump table is adjusted according to the programming time of each page.

9. The method according to claim 3, characterized in that, Before determining the target address corresponding to the write command based on the address jump table, the method further includes: Identify at least two physical blocks and detect the programming time for writing to each page on the at least two physical blocks; An address skip table is generated based on the programming time of each page.

10. A storage device, characterized in that, It includes a controller and a non-volatile memory chip, the controller being used to perform the data writing method according to any one of claims 1-9.

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