Storage device and storage control method

Abstract

This disclosure relates to a storage device and a storage control method. The device includes a memory controller and multiple memory groups, each memory group including a first memory and a second memory. The memory controller includes one or more first controllers, one or more second controllers, and one or more request interfaces. The first controller controls memory access to one or more first memories, and if a replacement error is determined to have occurred in the first memory, it performs a replacement operation corresponding to the replacement error for the first memory with the replacement error. If the request interface determines that the mirroring conditions are not met, it sends a read request to the corresponding first controller; otherwise, it sends the read request to the corresponding second controller. By performing a replacement operation corresponding to the replacement error based on the occurrence of a replacement error in the first memory, fine-grained memory fault avoidance and replacement are achieved, thereby optimizing memory resource utilization, avoiding data loss risks, and improving fault tolerance while ensuring system stability and reliability.

Description

Technical Field

[0001] This disclosure relates to the field of memory management technology, and in particular to a storage device and a storage control method. Background Technology

[0002] In server systems, the integrity and reliability of in-memory data are paramount. As the core site of data exchange, memory is susceptible to errors during operation due to various reasons. With continuously increasing memory density and access speeds, the probability of memory errors also rises. Therefore, providing a more refined, flexible, and efficient fault-tolerance mechanism for errors occurring in memory, effectively preventing and mitigating potential data loss risks while minimizing the impact on server performance, and improving the overall stability and reliability of the server, is a pressing technical challenge. Summary of the Invention

[0003] In view of this, this disclosure proposes a storage device and a storage control method that can adopt a more refined, flexible and efficient fault-tolerant processing mechanism for errors occurring in memory, effectively prevent and avoid potential data loss risks while minimizing the impact on server performance, and improve the overall stability and reliability of the server.

[0004] According to one aspect of this disclosure, a storage device is provided, the device including a memory controller and a plurality of memory groups, each memory group including a first memory and a second memory, wherein the second memory is a mirror image of the first memory; the memory controller includes one or more first controllers, one or more second controllers, and one or more request interfaces;

[0005] Each of the first controllers is configured to control access to one or more first memories, and, if a replacement error is determined to have occurred in the first memory, to perform a replacement operation corresponding to the replacement error for the first memory where the replacement error occurred; the replacement error includes block replacement error and / or memory replacement error;

[0006] Each of the request interfaces is configured to, upon receiving a read request from the processor for a first memory group among the plurality of memory groups, if it is determined that the mirroring conditions are not met, send the read request to a first controller corresponding to the first memory in the first memory group; and if it is determined that the mirroring conditions are met, send the read request to a second controller corresponding to the second memory in the first memory group.

[0007] Through the above-mentioned device, the first controller performs the replacement operation corresponding to the replacement error when it is determined that a replacement error has occurred in the first memory. This realizes fine-grained memory fault avoidance and replacement for different replacement errors in each first memory. The request interface determines whether to send the read request for the first memory group to the more trusted one of the first memory and second memory in the first memory group based on whether the mirror condition is met. This ensures that the execution of the read request can always be based on the trusted memory in the memory group, thereby optimizing the memory resource utilization while ensuring the stability and reliability of the system, avoiding the risk of data loss, and improving the fault tolerance of the storage device.

[0008] In one possible implementation, the replacement operation includes a block replacement operation corresponding to a block replacement error and / or a memory replacement operation corresponding to a memory replacement error;

[0009] Among them, the block replacement operation refers to the operation of replacing the erroneous block in the first memory where the block replacement error occurred. The memory replacement operation refers to sending a memory replacement signal to the target memory group where the memory replacement error occurred to the corresponding request interface.

[0010] The conditions for meeting the image transmission criteria include: the target memory group targeted by the memory replacement signal includes the first memory group.

[0011] In one possible implementation, when there are multiple first controllers, each first controller corresponds one-to-one with one of the multiple memory groups; when there is only one first controller, the first controller is used to control all the first memory groups.

[0012] In one possible implementation, when there are multiple second controllers, each second controller corresponds one-to-one with one of the multiple memory groups; when there is only one second controller, the second controller is used to control all the second memory groups.

[0013] In one possible implementation, if there is only one request interface, the request interface is communicatively connected to all the first controllers and all the second controllers; if there are multiple request interfaces, each request interface corresponds to one of the multiple memory groups.

[0014] In one possible implementation, the request execution module in the first controller is configured to read first data from the corresponding first memory and send it to the request interface upon receiving the read request.

[0015] The second controller is configured to, upon receiving the read request, read second data from the corresponding second memory and send it to the request interface;

[0016] The request interface is also used to send trusted data that meets the trusted conditions in the received first data and / or the second data as read data to the processor;

[0017] The trusted condition includes at least one of the following: the first memory storing the first data did not experience a replacement error, or the first memory storing the first data experienced a replacement error and the corresponding untrusted moment occurred after the moment the first data was acquired.

[0018] In one possible implementation, the request interface is further configured to, upon receiving a memory replacement signal for a target memory group among the plurality of memory groups, retransmit each read request for the target memory group that meets the retransmission condition to the second controller corresponding to the target memory group.

[0019] The retransmission condition includes at least one of the following: the read request is directed to the target memory group and the request forwarding time is after the untrusted time indicated by the memory replacement signal; the first data corresponding to the read request is read from the first memory in the target memory group and the acquisition time of the first data is after the untrusted time.

[0020] In one possible implementation, the first controller includes:

[0021] The error monitoring module is used to monitor memory errors occurring in the controlled first memory, obtain monitoring results, and determine whether a replacement error has occurred in the first memory based on the monitoring results.

[0022] The memory error includes at least one of correctable errors and uncorrectable errors;

[0023] The monitoring results include at least one of the following: the number of correctable errors, the number of uncorrectable errors, the frequency of correctable errors, and the frequency of uncorrectable errors.

[0024] In one possible implementation, the occurrence of the block replacement error includes at least one of the following: the number of correctable errors is greater than or equal to a first threshold, and the frequency of correctable errors is greater than or equal to a first frequency.

[0025] In one possible implementation, the occurrence of the memory replacement error includes at least one of the following: the number of correctable errors is greater than or equal to a second threshold; the number of uncorrectable errors is greater than or equal to a third threshold; the frequency of correctable errors is greater than or equal to a second frequency; the frequency of uncorrectable errors is greater than or equal to a third frequency; the second threshold is greater than the first threshold; and the second frequency is greater than the first frequency.

[0026] In one possible implementation, the first controller further includes a data transfer module;

[0027] The error monitoring module is also used to send a data transfer instruction to the data transfer module when it is determined that a block replacement error has occurred based on the monitoring results.

[0028] The data transfer module is configured to, upon receiving the data transfer instruction, perform block replacement of the erroneous block in the main memory block of the first memory, based on the redundant block in the first memory where the block replacement error occurred.

[0029] The first memory includes the main memory block used as main memory and the redundant block.

[0030] In one possible implementation, based on the redundant blocks in the first memory where the block replacement error occurred, block replacement of the erroneous block in the main memory block of the first memory is performed, including:

[0031] The data in each sub-block to be moved from the erroneous block is sequentially moved to the corresponding replacement sub-block in the redundant block.

[0032] Wherein, the amount of data corresponding to each of the sub-blocks to be moved is less than or equal to the preset single-transfer amount, the sub-block to be moved is part or all of the erroneous block, and the replacement sub-block is part or all of the redundant block.

[0033] In one possible implementation, the data transport module is further configured to record the transport progress of replacing the erroneous block in response to the data transport instruction;

[0034] The request execution module in the first controller is used to determine the actual storage address of the first data to be read in the corresponding first memory in combination with the transport progress when the transport progress is obtained.

[0035] The actual storage address includes at least one of the following: a first address located in the main memory block of the corresponding first memory, and a second address located in the redundant block of the corresponding first memory.

[0036] In one possible implementation, the error monitoring module is further configured to send the memory replacement signal to the corresponding request interface when it is determined that a memory replacement error has occurred based on the monitoring results.

[0037] In one possible implementation, the request interface is configured to forward the write request to the first controller and the second controller corresponding to the second memory group upon receiving a write request from the processor for the second memory group.

[0038] The first controller is configured to write the data to be stored into the corresponding first memory in response to the write request;

[0039] The second controller is configured to write the data to be stored into the corresponding second memory in response to the write request.

[0040] According to another aspect of this disclosure, a storage control method is provided, applied to a memory controller in a storage device, the storage device further comprising a plurality of memory groups, each memory group including a first memory and a second memory, wherein the second memory is a mirror image of the first memory; the method includes:

[0041] Control access to one or more first memory locations, and if a replacement error is determined to have occurred in the first memory location, perform a replacement operation corresponding to the replacement error for the first memory location where the replacement error occurred; the replacement error includes block replacement error and / or memory replacement error;

[0042] Upon receiving a read request from the processor for the first memory group among the plurality of memory groups, if it is determined that the mirroring conditions are not met, the read request is executed based on the first memory in the first memory group; if it is determined that the mirroring conditions are met, the read request is executed based on the second memory in the first memory group.

[0043] In one possible implementation, the replacement operation includes a block replacement operation corresponding to a block replacement error and / or a memory replacement operation corresponding to a memory replacement error;

[0044] Among them, the block replacement operation refers to the operation of replacing the erroneous block in the first memory where the block replacement error occurred. The memory replacement operation refers to sending a memory replacement signal to the target memory group where the memory replacement error occurred to the corresponding request interface.

[0045] The conditions for meeting the image transmission criteria include: the target memory group targeted by the memory replacement signal includes the first memory group.

[0046] In one possible implementation, the method further includes:

[0047] After executing the read request to read the first data from the corresponding first memory under the condition that the mirror sending is not met, the trusted data in the first data that meets the trusted condition is sent to the processor as read data; after executing the read request to read the second data from the corresponding second memory under the condition that the mirror sending is met, the second data is sent to the processor as read data.

[0048] The trusted condition includes at least one of the following: the first memory storing the first data did not experience a replacement error, or the first memory storing the first data experienced a replacement error and the corresponding untrusted moment occurred after the moment the first data was acquired.

[0049] In one possible implementation, the method further includes:

[0050] In response to a memory replacement signal for a target memory group among the plurality of memory groups, for each read request for the target memory group that meets the retransmission condition, the read request is re-executed based on the second memory in the target memory group;

[0051] The retransmission condition includes at least one of the following: the read request is directed to the target memory group and the request forwarding time is after the untrusted time indicated by the memory replacement signal; the first data corresponding to the read request is read from the first memory in the target memory group and the acquisition time of the first data is after the untrusted time.

[0052] In one possible implementation, the method further includes:

[0053] For each memory error that occurs in the first memory, monitor the monitoring results, and determine whether a replacement error has occurred in the first memory based on the monitoring results;

[0054] The memory error includes at least one of correctable errors and uncorrectable errors;

[0055] The monitoring results include at least one of the following: the number of correctable errors, the number of uncorrectable errors, the frequency of correctable errors, and the frequency of uncorrectable errors.

[0056] In one possible implementation, the occurrence of the block replacement error includes at least one of the following: the number of correctable errors is greater than or equal to a first threshold, and the frequency of correctable errors is greater than or equal to a first frequency.

[0057] In one possible implementation, the occurrence of the memory replacement error includes at least one of the following: the number of correctable errors is greater than or equal to a second threshold; the number of uncorrectable errors is greater than or equal to a third threshold; the frequency of correctable errors is greater than or equal to a second frequency; the frequency of uncorrectable errors is greater than or equal to a third frequency; the second threshold is greater than the first threshold; and the second frequency is greater than the first frequency.

[0058] In one possible implementation, the method further includes:

[0059] If a block replacement error is determined to have occurred based on the monitoring results, the erroneous block in the main memory block of the first memory is replaced based on the redundant block in the first memory where the block replacement error occurred.

[0060] The first memory includes the main memory block used as main memory and the redundant block.

[0061] In one possible implementation, based on the redundant blocks in the first memory where the block replacement error occurred, block replacement of the erroneous block in the main memory block of the first memory is performed, including:

[0062] The data in each sub-block to be moved from the erroneous block is sequentially moved to the corresponding replacement sub-block in the redundant block.

[0063] Wherein, the amount of data corresponding to each of the sub-blocks to be moved is less than or equal to the preset single-transfer amount, the sub-block to be moved is part or all of the erroneous block, and the replacement sub-block is part or all of the redundant block.

[0064] In one possible implementation, the method further includes: recording the progress of replacing the erroneous block in response to the data transfer instruction.

[0065] In one possible implementation, the method further includes: upon obtaining the transport progress, determining the actual storage address of the first data to be read in the corresponding first memory in conjunction with the transport progress;

[0066] The actual storage address includes at least one of the following: a first address located in the main memory block of the corresponding first memory, and a second address located in the redundant block of the corresponding first memory.

[0067] In one possible implementation, the memory replacement signal is generated when it is determined that a memory replacement error has occurred based on the monitoring results.

[0068] In one possible implementation, upon receiving a write request from the processor for a second memory group among the plurality of memory groups, the data to be stored is written to the corresponding first memory and second memory in response to the write request.

[0069] By using the above method, when a replacement error is determined to have occurred in the first memory, a replacement operation corresponding to the replacement error is executed. This achieves refined memory fault avoidance and replacement for each different replacement error in the first memory. Furthermore, for read requests in the first memory group, the more reliable memory in the first memory group or the second memory group is determined based on the mirror condition to execute the read request. This ensures that the execution of read requests is always based on the reliable memory in the memory group, thereby optimizing memory resource utilization, avoiding the risk of data loss, and improving the fault tolerance of the storage device while ensuring system stability and reliability.

[0070] According to another aspect of this disclosure, a storage control device is provided, including a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the above-described method.

[0071] According to another aspect of this disclosure, a non-volatile computer-readable storage medium is provided, on which a computer program is stored, which, when executed by a processor, implements the steps of the above-described method.

[0072] According to another aspect of this disclosure, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps of the above-described method.

[0073] The storage device and storage control method provided in this disclosure execute a replacement operation corresponding to the replacement error when a replacement error occurs in the first memory. This achieves refined memory fault avoidance and replacement for different replacement errors, ensuring that the execution of read requests is always based on trusted memory in the memory group. This optimizes memory resource utilization, avoids data loss risks, and improves the fault tolerance of the storage device while ensuring system stability and reliability.

[0074] Other features and aspects of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0075] The accompanying drawings, which are included in and form part of this specification, illustrate exemplary embodiments, features, and aspects of this disclosure together with the specification and serve to explain the principles of this disclosure.

[0076] Figures 1-4 This diagram illustrates a structural block diagram of a storage device provided in an embodiment of the present disclosure.

[0077] Figure 5 This diagram illustrates a structural block diagram of a first controller and a first memory in a storage device provided in an embodiment of the present disclosure.

[0078] Figure 6 This diagram illustrates the process of processing a read request in a storage device according to an embodiment of the present disclosure.

[0079] Figure 7 This is a block diagram illustrating a storage control device 1900 according to an exemplary embodiment. Detailed Implementation

[0080] Various exemplary embodiments, features, and aspects of this disclosure will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0081] As used herein, the terms “comprising,” “including,” “having,” or variations thereof are open-ended and include one or more of the stated features, integrals, elements, steps, components, or functions, but do not exclude the presence or addition of one or more other features, integrals, elements, steps, components, functions, or groups thereof.

[0082] When an element is referred to as “connected,” “coupled,” “responding,” or a variation thereof relative to another element, it may be directly connected, coupled, or responding to another element, or there may be an intermediate element present.

[0083] Although the terms first, second, third, etc., may be used herein to describe various elements / operations, these elements / operations should not be limited by these terms. These terms are only used to distinguish one element / operation from another. Therefore, without departing from the teachings of the inventive concept, a first element / operation in some embodiments may be referred to as a second element / operation in other embodiments.

[0084] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0085] Furthermore, to better illustrate this disclosure, numerous specific details are set forth in the following detailed description. Those skilled in the art will understand that this disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art have not been described in detail in order to highlight the main points of this disclosure.

[0086] It should be noted that the information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, data stored, data displayed, etc.) and signals involved in this application are all authorized by the user or fully authorized by all parties, and the collection, use and processing of related data must comply with the relevant laws, regulations and standards of the relevant regions.

[0087] With the continuous development of critical business areas such as cloud computing, big data, financial transactions, and telecommunications core networks, the requirements for the stability and data reliability of server systems are increasing. Memory, as a core component for data storage and exchange in server systems, directly determines the system's processing performance and data security. However, memory errors can occur during operation due to hardware defects, electrical noise, electromagnetic interference, high-energy particle radiation (soft errors), and other reasons. Memory errors are divided into correctable and uncorrectable errors. Correctable errors, such as unit flips, can usually be repaired in real time using error checking and correction techniques without affecting system operation. Uncorrectable errors, such as multiple bit flips or severe physical damage, may lead to permanent data loss, potentially causing application crashes.

[0088] To improve memory fault tolerance, memory mirroring or memory backup technologies can be introduced. These technologies involve setting up a mirror backup of one portion of physical memory, and using hardware control logic to synchronously write data to both main memory and the mirror memory. When an unrecoverable error occurs in main memory, subsequent read / write operations can be switched to the mirror memory. However, this approach has at least the following problems: This mirroring mechanism typically performs coarse-grained switching based on the entire memory channel or memory module, with relatively simple triggering conditions, often only passively switching when an uncorrectable error occurs. This mechanism lacks proactive avoidance measures for the potential physical failure risk of memory regions indicated by frequent correctable errors. Once correctable errors accumulate and eventually evolve into uncorrectable errors, even switching to mirror memory may result in data loss due to untimely data migration or the sensitive timing of the error. Furthermore, coarse-grained memory replacement means that even if only a small range of memory blocks shows signs of failure, a large amount of valuable mirror memory resources need to be used for a complete replacement, resulting in wasted memory resources and reduced system configuration flexibility. Therefore, how to provide a storage device and storage control method that can combine different error levels to achieve fine-grained memory fault avoidance and replacement, thereby optimizing memory resource utilization while ensuring system stability and reliability, is a technical problem that urgently needs to be solved by those skilled in the art.

[0089] To address the aforementioned technical problems, this disclosure provides a storage device and a storage control method. The device includes a memory controller and multiple memory groups, each memory group including a first memory and a second memory, with the second memory being a mirror image of the first memory. The memory controller includes one or more first controllers, one or more second controllers, and one or more request interfaces. Each first controller controls memory access to one or more first memories and, upon determining that a replacement error has occurred in the first memory, performs a replacement operation corresponding to the replacement error for the first memory with the replacement error. Replacement errors include block replacement errors and / or memory replacement errors. Each request interface, upon receiving a read request from the processor for the first memory group among the multiple memory groups, if the mirror sending condition is not met, sends the read request to the first controller corresponding to the first memory in the first memory group; if the mirror sending condition is met, the read request is sent to the second controller corresponding to the second memory in the first memory group. In this way, by performing a replacement operation corresponding to the replacement error when a replacement error occurs in the first memory, fine-grained memory fault avoidance and replacement are achieved for different replacement errors. This ensures that the execution of read requests is always based on trusted memory in the memory group, thereby optimizing memory resource utilization while ensuring system stability and reliability, avoiding data loss risks, and improving the fault tolerance of the storage device.

[0090] like Figure 1 As shown, this disclosure provides a storage device 10, which includes a plurality of memory groups 11 (such as...). Figure 1 The diagram shows memory groups 0 to n and memory controller 12. Storage device 10 and processor 20 can reside in the same server. Processor 20 can be any processor in the server capable of accessing storage device 10, such as a CPU or GPU (Graphics Processing Unit), and this disclosure does not impose any limitations on this.

[0091] Among them, such as Figure 1 As shown, the memory controller 12 includes a first controller 121, a second controller 122, and a request interface 123. Each memory group 11 includes a first memory 111 and a second memory 112, and the second memory 112 is a partial or complete mirror of the first memory 111.

[0092] In this embodiment, the memory controller 12 has different implementations depending on the number of the first controller 121, the second controller 122, and the request interface 123 in the storage device 10. The following describes these implementations in conjunction with... Figures 2-4 The implementation of memory controller 12 will be explained. It is understandable that... Figures 2-4 The diagram only illustrates a portion of the implementation of memory controller 12 for ease of explanation. Figures 2-4Not all implementations of memory controller 12 are shown.

[0093] In some embodiments, the first controller 121 may be one or more. When there are multiple first controllers 121, such as... Figure 2 , Figure 3 As shown, multiple first controllers 121 correspond one-to-one with the multiple memory groups 11, and each first controller 121 is communicatively connected to a corresponding first memory 111. Each first controller 121 is used to control the first memory 111 it communicates with. When there is only one first controller 121, as... Figure 4 As shown, the first controller 121 is communicatively connected to each of the first memory 111 and is used to control all the first memory 111.

[0094] In some embodiments, the second controller 122 may be one or more. When there are multiple second controllers 122, such as... Figure 2 , Figure 3 As shown, multiple second controllers 122 correspond one-to-one with the multiple memory groups 11, and each second controller 122 is communicatively connected to a corresponding second memory 112. Each second controller 122 is used to control the second memory 112 it communicates with. When there is only one second controller 122, as... Figure 4 As shown, the second controller 122 is communicatively connected to each of the second memory 112 and is used to control all the second memory 112.

[0095] In some embodiments, the request interface 123 may be one or more. Where there is only one request interface 123, such as... Figure 2 , Figure 4 As shown, the request interface 123 is communicatively connected to each first controller 121 and each second controller 122. In the case of multiple request interfaces 123, such as... Figure 3 As shown, multiple request interfaces 123 correspond one-to-one with the multiple memory groups 11, and each request interface 123 is communicatively connected to a first controller 121 and a second controller 122 of the corresponding memory group 11.

[0096] In this embodiment, the first memory 111 in each memory group 11 serves as the main memory of that memory group 11. Under the default state, the main memory can be accessed normally (i.e., the mirroring conditions are not met), and read data is read from the main memory and write data is written to the main memory and the second memory; if the main memory is unreliable due to an error (i.e., the mirroring conditions are met), read data is read from the second memory and write data is written to the second memory at least.

[0097] In some embodiments, in each memory group 11, such as Figure 5 As shown, the first memory 111 may include a main memory block 301 serving as main memory and a redundant block 302. The main memory block 301 is used for normal memory access, and the redundant block 302 is used to replace faulty blocks in the main memory block 301. The storage capacity and ratio between the main memory block 301 and the redundant block 302 in the first memory 111 can be set according to actual storage needs and fault tolerance requirements; this disclosure does not impose limitations in this regard. For example, the storage capacity of the main memory block 301 can be set first according to actual storage needs; if the fault tolerance requirement for the main memory block 301 is high, the storage capacity of the redundant block 302 can be further determined based on the capacity ratio corresponding to a high fault tolerance rate and the storage capacity of the main memory block 301.

[0098] In some embodiments, the second memory 112 is used as a mirror of the main memory block 301 in the first memory 111. Then, the storage capacity of part or all of the storage space of the second memory 112 is the same as the storage capacity of the main memory block 301 and the model type is consistent, so that if the first memory 111 cannot continue to be used due to unreliability (i.e., a memory replacement error occurs), the first memory 111 can be replaced by the second memory 112.

[0099] In some embodiments, the second memory 112 may include a mirrored main memory block, which is a mirror of the main memory block 301 in the first memory 111. That is, the storage capacity of the mirrored main memory block in the second memory 112 is the same as the storage capacity of the main memory block 301 in the first memory 111 in the memory group 11, and they are of the same type. Ensuring that the mirrored main memory block has the same capacity and the same type as the main memory block guarantees that, in the event that the first memory 111 becomes unusable (i.e., a memory replacement error occurs), the mirrored main memory block in the second memory 112 can replace the main memory block 301 in the first memory 111. In some embodiments, the second memory 112 may also include a redundant block, which is used to replace the erroneous block in the case of a block replacement error in the mirrored main memory block, thereby improving the fault tolerance of the second memory.

[0100] For example, in a storage device 10 based on Double Data Rate 5 technology, a memory group 11 may include a sub-memory A accessed via sub-channel A and a sub-memory B accessed via sub-channel B, wherein all or part of the area of ​​sub-memory A is configured as first memory, and the corresponding area of ​​the same size in sub-memory B is configured as second memory.

[0101] In this embodiment, the first controller 121 is configured to control memory access to one or more first memory locations, and, upon determining that a replacement error has occurred in the first memory 111, to perform a replacement operation corresponding to the replacement error. The replacement error includes block replacement errors and / or memory replacement errors. A block replacement error may refer to a memory error occurring in the first memory 111 that can be resolved through block replacement. A memory replacement error may refer to a memory error occurring in the first memory 111 that cannot be resolved through block replacement, requiring the first memory to be discarded and a second memory 112 (to execute read requests) to replace the first memory 111. Therefore, the replacement operation may include a block replacement operation corresponding to a block replacement error and / or a memory replacement operation corresponding to a memory replacement error.

[0102] In one possible implementation, the block replacement operation can refer to the replacement of the erroneous block in the first memory segment where the block replacement error occurred. The memory replacement operation can also involve sending a memory replacement signal to the corresponding request interface for the target memory group where the memory replacement error occurred.

[0103] The memory replacement signal can be used to indicate the first memory 111 where the memory replacement error occurred and / or the target memory group where the first memory 111 is located, so that the request interface 123 can respond to the memory replacement signal and change the read request from the processor 20 for the target memory group from being sent to the first controller 121 corresponding to the target memory group by default to being sent to the second controller 122 corresponding to the target memory group.

[0104] In this embodiment, the request interface 123 is used to communicate with the processor 20 and receive at least one read request and / or at least one write request from the processor 20. When the request interface 123 receives a read request from the processor 20 for a first memory group among the plurality of memory groups 11, if the first memory group does not meet the mirroring conditions, the read request is sent to the first controller 121 corresponding to the first memory 111 in the first memory group; if the first memory group meets the mirroring conditions, the read request is sent to the second controller 122 corresponding to the second memory 112 in the first memory group. After a read request is sent to the first controller 121 or the second controller 122, if the read request is sent to the first controller 121, the request execution module 203 in the first controller 121 (e.g., ...) Figure 5(As shown) Upon receiving the read request, the system reads first data from the corresponding first memory 111 and sends it to the request interface 123 (i.e., sends it to the request interface 123 which is communicatively connected to the first controller 121). If the read request is sent to the second controller 122, the second controller 122, upon receiving the read request, reads second data from the corresponding second memory 112 and sends it to the request interface 123 (i.e., sends it to the request interface 123 which is communicatively connected to the second controller 122).

[0105] In one possible implementation, meeting the mirroring sending conditions may include: the target memory group targeted by the memory replacement signal includes the first memory group. Thus, in the event of a memory replacement error in the first memory group, the reliability of data reading can be guaranteed by setting the mirroring sending conditions.

[0106] In one possible implementation, such as Figure 5 As shown, each of the first controllers 121 may include an error monitoring module 201, a data transfer module 202, and a request execution module 203. It is understood that the inclusion of the error monitoring module 201, data transfer module 202, and request execution module 203 in the first controller 121 is an illustrative division method according to an embodiment of this application; other forms of module division can also be used for the first controller 121, and this disclosure does not limit this. It is understood that if there is only one first controller 121 in the storage device 10, then the first controller 121 can utilize... Figure 5 Each module shown performs memory error monitoring for each first memory 111, executes block replacement operations on the first memory 111 that has a block replacement error, and executes memory replacement operations on the first memory 111 that has a memory replacement error. If there are multiple first controllers 121 in the storage device 10 that correspond one-to-one with multiple memory groups 11, then each first controller 121 can utilize... Figure 5 Each module shown performs memory error monitoring on the unique first memory 111 it controls, executes block replacement operations when a block replacement error occurs, and executes memory replacement operations when a memory replacement error occurs. In this way, corresponding memory fault avoidance and replacement can be performed for different replacement errors of each first memory 111, achieving fine-grained control.

[0107] In one possible implementation, each first controller 121 includes an error monitoring module 201, which monitors memory errors in the controlled first memory 111, obtains monitoring results, and determines whether a replacement error has occurred in the first memory 111 based on the monitoring results.

[0108] The memory errors mentioned herein may include at least one of correctable errors (CE) and uncorrectable errors (UE). Correctable errors are read memory errors that can be corrected by ECC (Error Correcting Code). Uncorrectable errors include, for example, read memory errors that exceed the correction capabilities of ECC. The monitoring results include at least one of the following: the number of times the correctable errors occurred, the number of times the uncorrectable errors occurred, the frequency of the correctable errors, and the frequency of the uncorrectable errors. The aforementioned number of occurrences and frequencies may be within a fixed time range such as 1 hour, 1 day, or 1 month. The method and content of memory error statistics can be set according to actual needs, and this disclosure does not impose any limitations on this.

[0109] The error monitoring module 201 can be a hardware-implemented real-time monitoring unit that continuously verifies the read / write responses and data packets returned by the first memory 111. For example, it checks the error checking and correction results of read data, the cyclic redundancy check response after writing data, and the parity check results on the command address bus. Through these verifications, the error monitoring module 201 obtains a monitoring result. Correctable errors typically refer to single-bit errors, which can be repaired in real time by error checking and correction techniques, but their frequent occurrence is an early sign of degradation in the first memory 111. Uncorrectable errors typically refer to multi-bit errors or parity / cyclic redundancy check errors, which directly lead to unreliable data. By statistically analyzing the number and frequency of correctable and uncorrectable errors in the monitoring result, the severity and urgency of the fault can be more accurately determined.

[0110] In one possible implementation, for each first memory 111, the occurrence of the block replacement error may include at least one of the following: the number of correctable errors is greater than or equal to a first threshold, and the frequency of correctable errors is greater than or equal to a first frequency. The values ​​of the first threshold and the first frequency can be set according to actual needs to meet different memory control requirements, and this disclosure does not impose any limitations on this. For example, for scenarios with high precision requirements, high access frequency, and high system stability requirements, a relatively small first threshold (e.g., 10 times / day) and a relatively low first frequency (e.g., 5 times / day) can be set for errors in the first memory 111 to quickly and promptly resolve memory errors through block replacement; conversely, a relatively large first threshold (e.g., 20 times / day) and a relatively high first frequency (e.g., 10 times / day) can be set to balance the frequency of block replacement with actual needs.

[0111] In one possible implementation, for each first memory 111, the occurrence of the memory replacement error may include at least one of the following: the number of correctable errors is greater than or equal to a second threshold; the number of uncorrectable errors is greater than or equal to a third threshold; the frequency of correctable errors is greater than or equal to a second frequency; the frequency of uncorrectable errors is greater than or equal to a third frequency; the second threshold is greater than the first threshold, and the second frequency is greater than the first frequency. Similarly, the values ​​of the second threshold, the second frequency, and the third frequency can be set according to actual needs to meet different memory control requirements, and this disclosure does not impose any limitations in this regard.

[0112] Thus, by setting different replacement errors, a block replacement error indicates that a local memory region of the first memory 111 has shown signs of accelerated degradation, but has not yet affected the entire memory. In this case, initiating a lightweight block replacement can resolve the issue. A memory replacement error indicates that the reliability of the entire first memory 111 has severely degraded, and a complete memory switch is necessary to mitigate the risk. In some embodiments, the values ​​of block replacement errors and various thresholds (including the first threshold, first frequency, second threshold, second frequency, and third frequency) in memory replacement errors for different first memory 111s can be the same or different. This allows for more flexible and fine-grained hierarchical processing of errors in different first memory 111s.

[0113] In one possible implementation, the error monitoring module 201 is further configured to, after determining the monitoring result, send a data transfer instruction to the data transfer module 202 if a block replacement error is determined to have occurred based on the monitoring result. The data transfer module 202, upon receiving the data transfer instruction, performs block replacement of the erroneous block in the main memory block 301 of the first memory 111, based on the redundant block 302 in the first memory 111 where the block replacement error occurred. The block replacement operation includes sending the data transfer instruction to the data transfer module 202 and the block replacement performed by the data transfer module 202 in response to the data transfer instruction.

[0114] In some embodiments, during block replacement, the transport method for replacing the erroneous block can be dynamically selected based on the capacity of the erroneous block and a preset single transport volume.

[0115] If the capacity of the erroneous block is less than or equal to the set single-transfer volume, it indicates that the capacity of the erroneous block is small and block replacement can be achieved in one transfer. In this case, the entire erroneous block can be treated as a sub-block to be transferred, and then the data in the sub-block to be transferred is transferred to the corresponding replacement sub-block in the redundant block 302. In this process, the sub-block to be transferred is the entirety of the erroneous block, and the replacement sub-block is part or all of the redundant block 302.

[0116] If the capacity of the erroneous block exceeds the preset single-transfer limit, it indicates that the erroneous block is too large. A single transfer to replace the block might take too long, affecting the execution speed and efficiency of subsequent read and write requests. Therefore, the erroneous block can be divided into multiple sub-blocks to be transferred based on the preset single-transfer limit. Then, the data in each sub-block to be transferred is sequentially transferred to the corresponding replacement sub-block in the redundant block 302. During this process, the amount of data in each sub-block to be transferred is less than or equal to the preset single-transfer limit. Each sub-block to be transferred is a part of the erroneous block, and each replacement sub-block is a part of the redundant block 302. Furthermore, the storage space corresponding to multiple replacement sub-blocks is part or all of the redundant block 302.

[0117] In one possible implementation, the data transport module 202 is further configured to record the transport progress in response to the data transport instruction replacing the erroneous block, and synchronize the transport progress to the request execution module 203. The block replacement operation also includes recording the transport progress. The transport progress can record the sub-blocks currently being transported within the erroneous block, the sub-blocks that have been transported but have already been transported, and the sub-blocks waiting to be transported. In some embodiments, after determining that the replacement of the erroneous block has been completed, the data transport module 202 can also send a redirection instruction to the request execution module 203, so that the request execution module 203, based on the redirection instruction, permanently redirects all read / write requests targeting the address range of the original erroneous block to the address corresponding to the replacement sub-block in the new redundant block 302.

[0118] In one possible implementation, the request execution module 203 in the first controller 121 is used to execute the received read request. Upon obtaining the transport progress, it determines, based on the transport progress, the actual storage address of the first data to be read in the corresponding first memory 111. The actual storage address may include at least one of the following: a first address located within the main memory block 301 of the corresponding first memory 111, or a second address located within the redundant block 302 of the corresponding first memory 111.

[0119] If the first controller 121 does not receive a data transfer progress message, it indicates that the current data read operation in the first memory 111 is error-free and reliable. In this case, the original address in the read request is directly determined as the actual storage address. If the first controller 121 receives a data transfer progress message, it indicates that there is an ongoing block replacement in the first memory 111. In this case, the actual storage address of the first data to be read in the first memory 111 can be determined based on the data transfer progress and the original address, thus achieving address redirection. Through this address redirection mechanism based on data transfer progress, seamless data transfer to external interfaces (i.e., request interface 123 and processor 20) is achieved, ensuring the continuity of read request execution.

[0120] In one possible implementation, the error monitoring module 201 is further configured to send the memory replacement signal to the corresponding request interface 123 when it is determined that a memory replacement error has occurred based on the monitoring results.

[0121] In the case where there is one request interface 123 and one first controller 121 (and similarly, one second controller 122), the memory replacement signal can indicate "the first memory 111 where the memory replacement error occurred and / or the target memory group where the first memory 111 is located" by carrying a memory group identifier, a first memory identifier, etc.

[0122] When there are multiple first controllers 121 (and similarly multiple second controllers 122), regardless of whether there is one or multiple request interfaces 123, since there are multiple first controllers 121, the "first memory 111 where the memory replacement error occurred and / or the target memory group where the first memory 111 is located" can be directly determined based on the number, line, etc. of the first controller 121 that sent the memory replacement signal. That is, at this time, the way the memory replacement signal indicates "the first memory 111 where the memory replacement error occurred and / or the target memory group where the first memory 111 is located" does not need to be implemented by carrying memory group identifier, first memory identifier, etc., which can simplify the implementation of the memory replacement signal indicating "the first memory 111 where the memory replacement error occurred and / or the target memory group where the first memory 111 is located".

[0123] In one possible implementation, the memory replacement signal can also indicate an untrusted moment. The untrusted moment indicated by the memory replacement signal can include any of the following: a first moment determined based on the occurrence of the memory replacement error (e.g., the moment when the memory replacement error is satisfied, the moment when the memory replacement signal is generated, etc.); or a second moment when the request interface 123 receives the memory replacement signal.

[0124] In one possible implementation, when the request interface 123 receives a memory replacement signal for a target memory group among the plurality of memory groups 11, it can switch the channel of the first memory 111 and / or the target memory group where the memory replacement error occurred based on the memory replacement signal, so that subsequent read requests for the target memory group can be directly sent to the second controller corresponding to the target memory group. That is, the judgment process of "whether the mirror sending conditions are met" is skipped and the read request is sent directly, or the judgment result of "whether the mirror sending conditions are met" for the target memory group can be set to "meets" to simplify the judgment process.

[0125] In some embodiments, the request interface 123 is also used to record the request forwarding time of each sent read request, which may be the time when the read request is sent and / or the time when the read request is received by the first controller 121.

[0126] In one possible implementation, the request interface 123 is further configured to, upon receiving a memory replacement signal for a target memory group among the plurality of memory groups 11, retransmit each read request for the target memory group that meets the retransmission condition to the second controller 122 corresponding to the target memory group.

[0127] The retransmission condition can include at least one of the following: the read request is directed to the target memory group and the request forwarding time is after the untrusted time indicated by the memory replacement signal; the first data corresponding to the read request is read from the first memory 111 in the target memory group and the acquisition time of the first data (which can be the time when the first controller 121 reads the first data) is after the untrusted time. For example, such as Figure 6 In the read request sending example shown, request interface 123 receives a memory replacement signal at time T1, and this memory replacement signal indicates an unreliable time T. 不 Read requests a and b obviously do not meet the retransmission condition, while read requests d and c meet the retransmission condition. Therefore, read requests d and c need to be retransmitted to the second controller 122 corresponding to the target memory group. In this way, the request interface 123 can subsequently receive the second data read from the retransmitted read request returned by the second controller 122, ensuring that each read request meeting the retransmission condition can read the correct second data from the second memory 112 through this retransmission operation, thus ensuring the reliability of the data ultimately returned to the processor 20.

[0128] In one possible implementation, the request interface 123 is further configured to receive first data returned by the first controller 121 and / or second data returned by the second controller 122. If the request interface 123 receives the second data, it can directly determine that the second data is trustworthy and can send it as read data to the processor 20. If the request interface 123 receives the first data, it needs to first determine whether the first data meets the trustworthiness condition. If the first data meets the trustworthiness condition, it is determined to be trustworthy data and then sent as read data to the processor 20. If the first data does not meet the trustworthiness condition, it is discarded. Meeting the trustworthiness condition may include at least one of the following: the first memory 111 storing the first data has not experienced a memory replacement error; or the first memory 111 storing the first data experienced a memory replacement error, and the corresponding untrustworthy moment occurred after the moment the first data was acquired.

[0129] The reliability condition can be determined based on the statement that "no memory replacement error occurred in the first memory 111 storing the first data" because: if no memory replacement error occurred in the first memory 111 storing the first data, it naturally indicates that the read operation of the first memory 111 storing the first data is still normal and reliable, and therefore the first data can be determined as reliable data that can be sent to the processor 20 as read data. The request interface 123 can determine that no memory replacement error occurred in the first memory 111 storing the first data based on whether it receives a memory replacement signal sent by the same first controller 121 that sent the first data.

[0130] The determination of whether the trust condition is met can be based on the statement that "a memory replacement error occurred in the first memory 111 storing the first data and the corresponding untrusted moment is after the acquisition moment of the first data" because: although it has been determined at the request forwarding moment of the read request corresponding to the first data that no memory replacement error occurred in the first memory 111 storing the first data and the mirroring transmission condition is not met, there is an undetermined time period between the request forwarding moment and the acquisition moment of the first data. Therefore, it is necessary to further determine the relationship between the untrusted moment indicated by the memory replacement signal sent by the same first controller 121 before or simultaneously with the receipt of the first data and this time period. If a memory replacement error occurred in the first memory 111 storing the first data and the corresponding untrusted moment is after the acquisition moment of the first data, it means that the memory replacement error occurred after the first memory 111 and the first data was read first. The first data is trustworthy data, and naturally, the first data can be sent to the processor 20 as read data. If a memory replacement error occurs in the first memory 111 storing the first data and the corresponding untrusted time is before the time the first data is acquired, it means that the memory replacement error occurred in the first memory 111 first, and the first data was read later. The first data is untrusted and needs to be discarded. Since the read request corresponding to the first data meets the retransmission condition, the request interface 123 can also retransmit the read request to the corresponding second memory 112 (the second memory 112 and the first memory 111 storing the first data belong to the same memory group 11).

[0131] In one possible implementation, the request interface 123 is also used to determine whether the read request has been retransmitted if the retransmission condition is met. If not, it is retransmitted to the corresponding second controller 122 to avoid the read request that meets the retransmission condition being sent to the corresponding second controller 122 multiple times.

[0132] In one possible implementation, upon receiving a write request from the processor 20 for a second memory group among the plurality of memory groups 11, the request interface 123 sends the write request to a first controller 121 and a second controller 122 corresponding to the second memory group. The first controller 121, upon receiving the write request, writes the data to be stored into the corresponding first memory group 111 in response to the write request. The second controller 122, upon receiving the write request, writes the data to be stored into the corresponding second memory group 112 in response to the write request. This "dual-write" mechanism within the same memory group 11 ensures that the second memory group 112 always stores the same data as the first memory group 111, providing a solid guarantee for seamless memory replacement. Furthermore, even if the first memory 111 is determined to be at risk of failure or even unreliable (i.e., a memory replacement error has occurred), efforts will still be made to write the data to be stored into the first memory 111. This has at least the following advantages: First, the write operation itself does not affect the correctness of the currently read data; second, maintaining the write to the first memory 111 simplifies the control logic of the entire storage device 10; third, maintaining the write to the first memory 111 allows for attempts to repair or maintain its working state by rewriting correct data after the first memory 111 has malfunctioned due to some recoverable reasons (such as temporary interference), providing conditions for subsequent possible fault diagnosis. In some embodiments, the request execution module 203 in the first controller 121 is used to execute the received write request, that is, upon receiving the write request, write the data to be stored carried by the write request into the corresponding first memory 111.

[0133] This disclosure also provides a storage control method applied to a memory controller 12 in the aforementioned storage device. The storage device further includes multiple memory groups, each memory group including a first memory and a second memory, wherein the second memory is a mirror image of the first memory. The method includes:

[0134] Control access to one or more first memory locations, and if a replacement error is determined to have occurred in the first memory location, perform a replacement operation corresponding to the replacement error for the first memory location where the replacement error occurred; the replacement error includes block replacement error and / or memory replacement error;

[0135] Upon receiving a read request from the processor for the first memory group among the plurality of memory groups, if it is determined that the mirroring conditions are not met, the read request is executed based on the first memory in the first memory group; if it is determined that the mirroring conditions are met, the read request is executed based on the second memory in the first memory group.

[0136] In one possible implementation, the replacement operation includes a block replacement operation corresponding to a block replacement error and / or a memory replacement operation corresponding to a memory replacement error;

[0137] Among them, the block replacement operation refers to the operation of replacing the erroneous block in the first memory where the block replacement error occurred. The memory replacement operation refers to sending a memory replacement signal to the target memory group where the memory replacement error occurred to the corresponding request interface.

[0138] The conditions for meeting the image transmission criteria include: the target memory group targeted by the memory replacement signal includes the first memory group.

[0139] In one possible implementation, the method further includes:

[0140] After executing the read request to read the first data from the corresponding first memory under the condition that the mirror sending is not met, the trusted data in the first data that meets the trusted condition is sent to the processor as read data; after executing the read request to read the second data from the corresponding second memory under the condition that the mirror sending is met, the second data is sent to the processor as read data.

[0141] The trusted condition includes at least one of the following: the first memory storing the first data did not experience a replacement error, or the first memory storing the first data experienced a replacement error and the corresponding untrusted moment occurred after the moment the first data was acquired.

[0142] In one possible implementation, the method further includes:

[0143] In response to a memory replacement signal for a target memory group among the plurality of memory groups, for each read request for the target memory group that meets the retransmission condition, the read request is re-executed based on the second memory in the target memory group;

[0144] The retransmission condition includes at least one of the following: the read request is directed to the target memory group and the request forwarding time is after the untrusted time indicated by the memory replacement signal; the first data corresponding to the read request is read from the first memory in the target memory group and the acquisition time of the first data is after the untrusted time.

[0145] In one possible implementation, the method further includes:

[0146] For each memory error that occurs in the first memory, monitor the monitoring results, and determine whether a replacement error has occurred in the first memory based on the monitoring results;

[0147] The memory error includes at least one of correctable errors and uncorrectable errors;

[0148] The monitoring results include at least one of the following: the number of correctable errors, the number of uncorrectable errors, the frequency of correctable errors, and the frequency of uncorrectable errors.

[0149] In one possible implementation, the occurrence of the block replacement error includes at least one of the following: the number of correctable errors is greater than or equal to a first threshold, and the frequency of correctable errors is greater than or equal to a first frequency.

[0150] In one possible implementation, the occurrence of the memory replacement error includes at least one of the following: the number of correctable errors is greater than or equal to a second threshold; the number of uncorrectable errors is greater than or equal to a third threshold; the frequency of correctable errors is greater than or equal to a second frequency; the frequency of uncorrectable errors is greater than or equal to a third frequency; the second threshold is greater than the first threshold; and the second frequency is greater than the first frequency.

[0151] In one possible implementation, the method further includes:

[0152] If a block replacement error is determined to have occurred based on the monitoring results, the erroneous block in the main memory block of the first memory is replaced based on the redundant block in the first memory where the block replacement error occurred.

[0153] The first memory includes the main memory block used as main memory and the redundant block.

[0154] In one possible implementation, based on the redundant blocks in the first memory where the block replacement error occurred, block replacement of the erroneous block in the main memory block of the first memory is performed, including:

[0155] The data in each sub-block to be moved from the erroneous block is sequentially moved to the corresponding replacement sub-block in the redundant block.

[0156] Wherein, the amount of data corresponding to each of the sub-blocks to be moved is less than or equal to the preset single-transfer amount, the sub-block to be moved is part or all of the erroneous block, and the replacement sub-block is part or all of the redundant block.

[0157] In one possible implementation, the method further includes: recording the progress of replacing the erroneous block in response to the data transfer instruction.

[0158] In one possible implementation, the method further includes: upon obtaining the transport progress, determining the actual storage address of the first data to be read in the corresponding first memory in conjunction with the transport progress;

[0159] The actual storage address includes at least one of the following: a first address located in the main memory block of the corresponding first memory, and a second address located in the redundant block of the corresponding first memory.

[0160] In one possible implementation, the memory replacement signal is generated when it is determined that a memory replacement error has occurred based on the monitoring results.

[0161] In one possible implementation, upon receiving a write request from the processor for a second memory group among the plurality of memory groups, the data to be stored is written to the corresponding first memory and second memory in response to the write request.

[0162] By using the above method, when a replacement error is determined to have occurred in the first memory, a replacement operation corresponding to the replacement error is executed. This achieves refined memory fault avoidance and replacement for each different replacement error in the first memory. Furthermore, for read requests in the first memory group, the more reliable memory in the first memory group or the second memory group is determined based on the mirror condition to execute the read request. This ensures that the execution of read requests is always based on the reliable memory in the memory group, thereby optimizing memory resource utilization, avoiding the risk of data loss, and improving the fault tolerance of the storage device while ensuring system stability and reliability.

[0163] It should be noted that although the storage device has been described above as an example, those skilled in the art will understand that this disclosure is not limited thereto. In fact, users can flexibly configure each module according to their personal preferences and / or actual application scenarios, as long as it conforms to the technical solution of this disclosure.

[0164] In some embodiments, the functions or modules of the apparatus provided in this disclosure can be used to perform the methods described in the above method embodiments. The specific implementation can be referred to the description of the above method embodiments, and for the sake of brevity, it will not be repeated here.

[0165] This disclosure also provides a storage control device, including a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the above method.

[0166] This disclosure also provides a non-volatile computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the steps of the above-described method.

[0167] This disclosure also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the above-described method.

[0168] Figure 7 This is a block diagram illustrating a storage control apparatus 1900 according to an exemplary embodiment. For example, apparatus 1900 may be provided as a server. (Refer to...) Figure 7 The apparatus 1900 includes a processing component 1922, which further includes one or more processors, and memory resources represented by memory 1932 for storing instructions, such as application programs, that can be executed by the processing component 1922. The application programs stored in memory 1932 may include one or more modules, each corresponding to a set of instructions. Furthermore, the processing component 1922 is configured to execute instructions to perform corresponding methods. Memory 1932 includes the aforementioned one or more storage devices 10, each storage device 10 for executing the aforementioned storage control methods.

[0169] Device 1900 may also include a power supply component 1926 configured to perform power management of device 1900, a wired or wireless network interface 1950 configured to connect device 1900 to a network for communication, and an input / output interface 1958 (I / O interface). Device 1900 can operate on an operating system, such as Windows Server, stored in memory 1932. TM Mac OS X TM Unix TM Linux TM FreeBSD TM Or similar.

[0170] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0171] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or technical improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A storage device, characterized in that, The device includes a memory controller and multiple memory groups, each memory group including a first memory and a second memory, wherein the second memory is a mirror image of the first memory; The memory controller includes one or more first controllers, one or more second controllers, and one or more request interfaces; Each of the first controllers is configured to control access to one or more first memories, and, if a replacement error is determined to have occurred in the first memory, to perform a replacement operation corresponding to the replacement error for the first memory where the replacement error occurred; the replacement error includes block replacement error and / or memory replacement error; Each of the request interfaces is configured to, upon receiving a read request from the processor for a first memory group among the plurality of memory groups, if it is determined that the mirroring conditions are not met, send the read request to the first controller corresponding to the first memory in the first memory group. If the mirror sending conditions are met, the read request is sent to the second controller corresponding to the second memory in the first memory group.

2. The apparatus according to claim 1, characterized in that, The replacement operation includes a block replacement operation corresponding to a block replacement error and / or a memory replacement operation corresponding to a memory replacement error; Among them, the block replacement operation refers to the operation of replacing the erroneous block in the first memory where the block replacement error occurred. The memory replacement operation refers to sending a memory replacement signal to the target memory group where the memory replacement error occurred to the corresponding request interface. The conditions for meeting the image transmission criteria include: the target memory group targeted by the memory replacement signal includes the first memory group.

3. The apparatus according to claim 1 or 2, characterized in that, When there are multiple first controllers, each first controller corresponds one-to-one with one of the multiple memory groups; when there is only one first controller, the first controller is used to control all of the first memory groups. When there are multiple second controllers, each second controller corresponds to one of the multiple memory groups; When there is only one second controller, the second controller is used to control all of the second memory; When there is one request interface, the request interface is communicatively connected to all the first controllers and all the second controllers; when there are multiple request interfaces, each request interface corresponds to one of the multiple memory groups.

4. The apparatus according to claim 1 or 2, characterized in that, The request execution module in the first controller is used to read first data from the corresponding first memory and send it to the request interface when the read request is received; The second controller is configured to, upon receiving the read request, read second data from the corresponding second memory and send it to the request interface; The request interface is also used to send trusted data that meets the trusted conditions in the received first data and / or the second data as read data to the processor; The trusted condition includes at least one of the following: the first memory storing the first data did not experience a replacement error, or the first memory storing the first data experienced a replacement error and the corresponding untrusted moment occurred after the moment the first data was acquired.

5. The apparatus according to claim 1 or 2, characterized in that, The request interface is also used to, upon receiving a memory replacement signal for a target memory group among the plurality of memory groups, resend each read request for the target memory group that meets the retransmission conditions to the second controller corresponding to the target memory group; The retransmission condition includes at least one of the following: the read request is directed to the target memory group and the request forwarding time is after the untrusted time indicated by the memory replacement signal; the first data corresponding to the read request is read from the first memory in the target memory group and the acquisition time of the first data is after the untrusted time.

6. The apparatus according to claim 1 or 2, characterized in that, The first controller includes: The error monitoring module is used to monitor memory errors occurring in the controlled first memory, obtain monitoring results, and determine whether a replacement error has occurred in the first memory based on the monitoring results. The memory error includes at least one of correctable errors and uncorrectable errors; The monitoring results include at least one of the following: the number of correctable errors, the number of uncorrectable errors, the frequency of correctable errors, and the frequency of uncorrectable errors.

7. The apparatus according to claim 6, characterized in that, The occurrence of the block replacement error includes at least one of the following situations: the number of correctable errors is greater than or equal to a first threshold, and the frequency of correctable errors is greater than or equal to a first frequency; The occurrence of the memory replacement error includes at least one of the following situations: the number of correctable errors is greater than or equal to the second threshold; The number of uncorrectable errors is greater than or equal to the third threshold; The frequency of correctable errors is greater than or equal to the second frequency; The frequency of uncorrectable errors is greater than or equal to the third frequency; the second threshold is greater than the first threshold, and the second frequency is greater than the first frequency.

8. The apparatus according to claim 6, characterized in that, The first controller also includes a data transfer module; The error monitoring module is also used to send a data transfer instruction to the data transfer module when it is determined that a block replacement error has occurred based on the monitoring results. The data transfer module is configured to, upon receiving the data transfer instruction, perform block replacement of the erroneous block in the main memory block of the first memory, based on the redundant block in the first memory where the block replacement error occurred. The first memory includes the main memory block used as main memory and the redundant block.

9. The apparatus according to claim 8, characterized in that, Based on the redundant blocks in the first memory where the block replacement error occurred, perform block replacement of the erroneous blocks in the main memory blocks of the first memory, including: The data in each sub-block to be moved from the erroneous block is sequentially moved to the corresponding replacement sub-block in the redundant block. Wherein, the amount of data corresponding to each of the sub-blocks to be moved is less than or equal to the preset single-transfer amount, the sub-block to be moved is part or all of the erroneous block, and the replacement sub-block is part or all of the redundant block.

10. The apparatus according to claim 9, characterized in that, The data transfer module is also used to record the transfer progress in response to the data transfer instruction replacing the erroneous block; The request execution module in the first controller is used to determine the actual storage address of the first data to be read in the corresponding first memory in combination with the transport progress when the transport progress is obtained. The actual storage address includes at least one of the following: a first address located in the main memory block of the corresponding first memory, and a second address located in the redundant block of the corresponding first memory.

11. The apparatus according to claim 6, characterized in that, The error monitoring module is further configured to send the memory replacement signal to the corresponding request interface when it is determined that a memory replacement error has occurred based on the monitoring results.

12. The apparatus according to claim 1, characterized in that, The request interface is configured to, upon receiving a write request from the processor for a second memory group among the plurality of memory groups, forward the write request to the first controller and the second controller corresponding to the second memory group; The first controller is configured to write the data to be stored into the corresponding first memory in response to the write request; The second controller is configured to write the data to be stored into the corresponding second memory in response to the write request.

13. A storage control method, characterized in that, A memory controller applied in a storage device, the storage device further comprising multiple memory groups, each memory group including a first memory and a second memory, wherein the second memory is a mirror image of the first memory; the method includes: Control access to one or more first memory locations, and if a replacement error is determined to have occurred in the first memory location, perform a replacement operation corresponding to the replacement error for the first memory location where the replacement error occurred; the replacement error includes block replacement error and / or memory replacement error; Upon receiving a read request from the processor for the first memory group among the plurality of memory groups, if it is determined that the mirroring conditions are not met, the read request is executed based on the first memory in the first memory group; if it is determined that the mirroring conditions are met, the read request is executed based on the second memory in the first memory group.

14. A storage control device, comprising a memory, a processor, and a computer program stored in the memory, characterized in that, The processor executes the computer program to implement the steps of the method of claim 13.

15. A non-volatile computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method of claim 13.

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