Memory management methods and storage devices

Abstract

This invention provides a memory management method and a storage device. The method includes: predicting future link health information of the storage device based on multiple historical link health information; confirming or correcting the future link health information based on the environmental state information of the storage device; and performing dynamic pre-protection on the storage device based on the future link health information. This improves the efficiency of maintaining and coordinating the management of future link quality between the storage device and the host system.

Description

Technical Field

[0001] This invention relates to the field of storage technology, and more particularly to a memory management method and a storage device. Background Technology

[0002] As data transfer rates between storage devices and host systems increase, link stability becomes increasingly important for system performance and reliability. Current technologies mostly only report errors when they occur, failing to effectively integrate the impact of environmental factors on link quality. Furthermore, error reporting mechanisms themselves do not support error prediction mechanisms; systems often only perform relevant error handling after an error has occurred. Summary of the Invention

[0003] This invention provides a memory management method and a storage device that can improve the above-mentioned problems and thereby enhance the performance of maintaining and coordinating the quality of future links between the storage device and the host system.

[0004] This invention provides a memory management method for a storage device. The memory management method includes: predicting future link health information of the storage device based on multiple historical link health information; confirming or correcting the future link health information based on the environmental state information of the storage device; and performing dynamic pre-protection on the storage device based on the future link health information.

[0005] This invention also provides a storage device, which includes a connection interface, a memory module, and a memory controller. The connection interface is used to connect to a host system. The memory controller is connected to the connection interface and the memory module. The memory controller is used to execute a memory management method.

[0006] Based on the above, after predicting the future link health information of the storage device using multiple historical link health information, this future link health information can be confirmed or corrected based on the environmental status information of the storage device. Subsequently, the system can perform dynamic pre-protection on the storage device based on this future link health information.

[0007] Compared to traditional storage devices that can only handle current link errors, potentially leading to irreparable packet loss, the memory management method and storage device proposed in this invention can improve the efficiency of maintaining and coordinating the quality of future links between the storage device and the host system by predicting the future link health information of the storage device and adopting dynamic pre-protection strategies. Attached Figure Description

[0008] Figure 1 This is a schematic diagram of a data storage system according to an embodiment of the present invention;

[0009] Figure 2 This is a schematic diagram of a memory controller according to an embodiment of the present invention;

[0010] Figure 3 This is a schematic diagram of a memory management module according to an embodiment of the present invention;

[0011] Figure 4 This is a schematic diagram illustrating multiple time intervals according to an embodiment of the present invention;

[0012] Figure 5 This is a schematic diagram illustrating an operational scenario for information feedback under a first pre-protection strategy, as shown in an embodiment of the present invention.

[0013] Figure 6 This is a schematic diagram illustrating the operational scenario of information feedback under the second pre-protection strategy according to an embodiment of the present invention;

[0014] Figure 7 This is a flowchart illustrating a memory management method according to an embodiment of the present invention;

[0015] Figure 8 This is a flowchart illustrating a memory management method according to an embodiment of the present invention. Detailed Implementation

[0016] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0017] Figure 1 This is a schematic diagram of a data storage system according to an embodiment of the present invention. Please refer to... Figure 1 The data storage system 10 includes a host system 11 and a storage device 12. The storage device 12 can be connected to the host system 11 and can be used to store data from the host system 11. For example, the host system 11 can be a smartphone, tablet computer, laptop computer, desktop computer, industrial computer, game console, server, or computer system installed in a specific carrier (such as a vehicle, aircraft, or ship), and the type of host system 11 is not limited to these. In addition, the storage device 12 may include a solid-state drive, USB flash drive, memory card, or other types of non-volatile storage device.

[0018] The host system 11 may include a processor 111 and a buffer memory 112. The processor 111 is used to handle all or part of the operation of the host system 11. For example, the processor 111 may include a central processing unit (CPU), or other programmable general-purpose or special-purpose microprocessors, digital signal processors (DSPs), programmable controllers, application-specific integrated circuits (ASICs), programmable logic devices (PLDs), or other similar devices or combinations thereof.

[0019] Buffer memory 112 is connected to processor 111 and used to cache data. For example, buffer memory 112 may include static random access memory (SRAM), dynamic random access memory (DRAM), or other types of volatile memory. Buffer memory 112 can be used as the main memory of host system 11. In addition, host system 11 may also include various hardware circuit modules such as power management circuitry, mouse, keyboard, screen, and / or wired / wireless communication circuitry, which will not be described in detail here.

[0020] Storage device 12 includes a connection interface 121, a memory module 122, and a memory controller 123. The connection interface 121 is used to connect storage device 12 to host system 11. For example, connection interface 121 may support embedded multi-media card (eMMC), universal flash storage (UFS), peripheral component interconnect express (PCI Express), non-volatile memory express (NVM express), Serial Advanced Technology Attachment (SATA), universal serial bus (USB), or other types of connection interface standards. Therefore, storage device 12 can communicate with host system 11 (e.g., exchange signals, instructions, and / or data) via connection interface 121.

[0021] Memory module 122 is used to store data. For example, memory module 122 may include one or more rewritable non-volatile memory modules. Each rewritable non-volatile memory module may include one or more memory cell arrays. The memory cells in the memory cell array store data in the form of voltage (also known as threshold voltage). For example, memory module 122 may include a Single Level Cell (SLC) NAND flash memory module, a Multi Level Cell (MLC) NAND flash memory module, a Triple Level Cell (TLC) NAND flash memory module, a Quad Level Cell (QLC) NAND flash memory module, and / or other memory modules with the same or similar characteristics.

[0022] Memory controller 123 is connected to connection interface 121 and memory module 122. Memory controller 123 can be considered the control core of storage device 12 and is used to control storage device 12. For example, memory controller 123 can be used to control or manage the overall or partial operation of storage device 12. For example, memory controller 123 may include a CPU, or other programmable general-purpose or special-purpose microprocessor, DSP, programmable controller, ASIC, PLD, or other similar device or a combination of these devices. In one embodiment, memory controller 123 may include a flash memory controller.

[0023] The memory controller 123 can send instruction sequences to the memory module 122 to access the memory module 122. For example, the memory controller 123 can send a write instruction sequence to the memory module 122 to instruct the memory module 122 to store data in a specific memory cell. For example, the memory controller 123 can send a read instruction sequence to the memory module 122 to instruct the memory module 122 to read data from a specific memory cell. For example, the memory controller 123 can send an erase instruction sequence to the memory module 122 to instruct the memory module 122 to erase data stored in a specific memory cell. Furthermore, the memory controller 123 can also send other types of instruction sequences to the memory module 122 to instruct the memory module 122 to perform other types of operations; this invention is not limited thereto. The memory module 122 can receive instruction sequences from the memory controller 123 and access its internal memory cells according to these instruction sequences.

[0024] Figure 2 This is a schematic diagram of a memory controller according to an embodiment of the present invention. Please refer to... Figure 1 and Figure 2The memory controller 123 includes a host interface 21, a memory interface 22, and a memory control circuit 23. The host interface 21 is used to connect to the host system 11 via the connection interface 121 to communicate with the host system 11. The memory interface 22 is used to connect to the memory module 122 to access the memory module 122.

[0025] Memory control circuitry 23 is connected to host interface 21 and memory interface 22. Memory control circuitry 23 can be used to control or manage the overall or partial operation of memory controller 123. For example, memory control circuitry 23 can communicate with host system 11 via host interface 21 and access memory module 122 via memory interface 22. For example, memory control circuitry 23 may include control circuitry such as embedded controllers or microcontrollers. In the following embodiments, the description of memory control circuitry 23 is equivalent to the description of memory controller 123.

[0026] In one embodiment, the memory controller 123 may further include a buffer memory 24. The buffer memory 24 is connected to the memory control circuitry 23 and is used to cache data. For example, the buffer memory 24 may be used to cache instructions from the host system 11, data from the host system 11, and / or data from the memory module 122. The buffer memory 24 may include SRAM, DRAM, or other types of volatile memory.

[0027] In one embodiment, the memory controller 123 may further include a decoding circuit 25. The decoding circuit 25 is connected to the memory control circuit 23 and is used to encode and decode data to ensure data integrity. For example, the decoding circuit 25 may support various encoding / decoding algorithms such as Low Density Parity Check code (LDPC code), BCH code, Reed-solomon code (RS code), and Exclusive OR (XOR) code. In one embodiment, the memory controller 123 may also include other types of circuit modules (e.g., power management circuits), which are not limited by the present invention.

[0028] Figure 3 This is a schematic diagram of a memory management module according to an embodiment of the present invention. Please refer to... Figures 1 to 3 The memory module 122 includes multiple physical units 301(1) to 301(C). Each physical unit includes multiple storage units for non-volatile storage of data.

[0029] In one embodiment, an entity unit may include at least one entity programmable unit. For example, an entity programmable unit is the smallest unit of synchronously written data in memory module 122. For example, when performing a programming operation (also called a write operation) on an entity programmable unit to write data to that entity programmable unit, multiple memory cells in that entity programmable unit may be synchronously programmed to store the corresponding data. For example, when programming an entity programmable unit, a write voltage may be applied to that entity programmable unit to change the threshold voltage of at least some of the memory cells in that entity programmable unit. For example, the threshold voltage of a memory cell may reflect the bit data stored in that memory cell. In one embodiment, an entity programmable unit is also referred to as an entity page. For example, the storage capacity of an entity programmable unit may be 16 kilobytes, and the invention is not limited thereto.

[0030] In one embodiment, an entity programming unit includes multiple entity sectors. For example, the data capacity of an entity sector may be 512 bytes (B), and an entity programming unit may include 32 entity sectors. However, the data capacity of an entity sector and / or the total number of entity sectors included in an entity programming unit can be adjusted according to practical needs, and the present invention is not limited thereto.

[0031] In one embodiment, a physical erase unit may include multiple physical programmable units. For example, the multiple physical programmable units in a physical erase unit may be erased simultaneously. For example, when an erase operation is performed on a physical erase unit, an erase voltage may be applied to the multiple physical programmable units in this physical erase unit to change the threshold voltage of at least a portion of the memory cells in these physical programmable units. By performing an erase operation on a physical erase unit, the data stored in this physical erase unit can be erased. In one embodiment, a physical erase unit is also referred to as a physical block.

[0032] In one embodiment, an entity unit may include at least one entity erasure unit. In another embodiment, if an entity unit includes multiple entity erasure units, this entity unit is also referred to as a virtual block. Multiple entity erasure units contained in the same virtual block can operate synchronously.

[0033] In one embodiment, the memory control circuit 23 can logically associate entity units 301(1)-301(A) and 301(A+1)-301(B) with the data area 31 and the idle area 32, respectively. Entity units 301(1)-301(A) in the data area 31 all store data (also called user data) from the host system 11. For example, any entity unit in the data area 31 can store valid data and / or invalid data. In addition, entity units 301(A+1)-301(B) in the idle area 32 do not store any data (e.g., valid data).

[0034] In one embodiment, if a certain entity unit does not store valid data, this entity unit can be associated with the free area 32. Furthermore, entity units in the free area 32 can be erased to clear the data in that entity unit. In one embodiment, entity units in the free area 32 are also referred to as idle entity units. In one embodiment, the free area 32 is also referred to as the free pool.

[0035] In one embodiment, when data needs to be stored, the memory control circuit 23 can select one or more physical units from the idle area 32 and instruct the memory module 122 to store the data into the selected physical units. After the data is stored into this physical unit, this physical unit can be associated with the data area 31. In other words, one or more physical units can be used alternately between the data area 31 and the idle area 32.

[0036] In one embodiment, the memory control circuit 23 may be configured with multiple logic units 302(1)-302(C) to map physical units (i.e., physical units 301(1)-301(A)) in the data area 31. For example, a logic unit may correspond to a logical block address (LBA) or other logical management unit. A logic unit may be mapped to one or more physical units.

[0037] In one embodiment, if a physical unit is currently mapped by any logical unit, the memory control circuit 23 can determine that the data currently stored in this physical unit includes valid data. Conversely, if a physical unit is not currently mapped by any logical unit, the memory control circuit 23 can determine that this physical unit does not currently store any valid data.

[0038] In one embodiment, the memory control circuit 23 may record the mapping relationship between logic units and physical units in at least one management table (also known as a logic-to-physical mapping table). In one embodiment, the memory control circuit 23 may instruct the memory module 122 to perform operations such as data reading, writing, or erasing based on the information (also known as mapping information) in this management table (i.e., the logic-to-physical mapping table).

[0039] In one embodiment, the memory control circuit 23 can establish a connection (also referred to as a link) between the host system 11 and the storage device 12. For example, the memory control circuit 23 can perform a handshake operation between the storage device 12 and the host system 11 to establish a connection between the host system 11 and the storage device 12. For example, this handshake operation can be used to exchange parameter information such as voltage and / or clock frequency used by both parties between the host system 11 and the storage device 12 to facilitate subsequent signal transmission between the two parties.

[0040] In one embodiment, after establishing a connection between the host system 11 and the storage device 12, the memory control circuit 23 (or the storage device 12) can communicate with the host system 11 (e.g., exchange signals) through this connection. For example, the memory control circuit 23 (or the storage device 12) can obtain operation instructions (e.g., write instructions, read instructions, or other types of operation instructions) from the host system 11 through this connection. Furthermore, the memory control circuit 23 (or the storage device 12) can send data (e.g., data read from the memory module 122, etc.) back to the host system 11 through this connection.

[0041] In one embodiment, after establishing the connection between the host system 11 and the storage device 12, the memory control circuit 23 can obtain the link status information and environmental status information of the storage device 12. This link status information reflects the status of the connection (i.e., the link) between the host system 11 and the storage device 12 (also referred to as link status). This environmental status information reflects the environmental status of the storage device 12.

[0042] In one embodiment, the link status information includes at least one indicator (also known as a link anomaly indicator). In one embodiment, this link anomaly indicator can reflect whether an anomaly (also known as a link anomaly) has occurred in the connection between the host system 11 and the storage device 12. In one embodiment, this link anomaly indicator can reflect the stability of the connection between the host system 11 and the storage device 12.

[0043] In one embodiment, the memory control circuit 23 can monitor the status of the connection (i.e., link status) between the storage device 12 and the host system 11 within one or more detection windows (also referred to as the first detection window) to obtain monitoring results (also referred to as the first monitoring results). For example, the time length corresponding to the first detection window can be 100 milliseconds (ms). It should be noted that the time length corresponding to the first detection window can also be adjusted according to practical needs, and the present invention is not limited thereto. Based on the first monitoring results, the memory control circuit 23 can obtain link anomaly indicators.

[0044] In one embodiment, the link anomaly indicator includes a link initialization count indicator. This link initialization count indicator reflects the number of times the connection (i.e., the link) between storage device 12 and host system 11 is rebuilt (e.g., reinitialized) within the time length corresponding to the first detection window. For example, whenever the link fails due to signal instability, interference, or synchronization failure, the connection (i.e., the link) between storage device 12 and host system 11 can be rebuilt to maintain the communication quality between storage device 12 and host system 11.

[0045] In one embodiment, the link initialization count indicator may include a count value (also referred to as a first count value). The first count value may reflect (e.g., be equivalent to) the number of times the connection (i.e., link) between storage device 12 and host system 11 was rebuilt (e.g., reinitialized) within the time length corresponding to the first detection window. In one embodiment, this first count value may reflect (e.g., be negatively correlated with) the stability of the connection (i.e., link) between storage device 12 and host system 11. That is, the larger the first count value, the lower the stability of the connection (i.e., link) between storage device 12 and host system 11.

[0046] In one embodiment, the link anomaly indicator includes a check error count indicator. This check error count indicator reflects the number of times a cyclic redundancy check (CRC) error (i.e., CRC verification failure) occurs in packets transmitted between storage device 12 and host system 11 within the time length corresponding to the first detection window. For example, whenever the link experiences signal instability, interference, or synchronization failure, there is a high probability that packets transmitted between storage device 12 and host system 11 will result in CRC errors in subsequent verification of these packets due to lost or corrupted packet content.

[0047] In one embodiment, the CRC error count indicator may include a count value (also referred to as a second count value). The second count value may reflect (e.g., be equivalent to) the number of CRC errors occurring in packets transmitted between storage device 12 and host system 11 within the time length corresponding to the first detection window. In one embodiment, this second count value may reflect (e.g., be negatively correlated with) the stability of the connection (i.e., link) between storage device 12 and host system 11. That is, the larger the second count value, the lower the stability of the connection (i.e., link) between storage device 12 and host system 11.

[0048] In one embodiment, the link anomaly indicator includes a packet retransmission count indicator. This packet retransmission count indicator reflects the number of times packets transmitted between storage device 12 and host system 11 are required to be retransmitted due to special reasons (such as the aforementioned CRC error or sequence number error) within the time length corresponding to the first detection window. For example, whenever the link is unstable, interfered with, or fails to synchronize, packets transmitted between storage device 12 and host system 11 have a high probability of being required to be retransmitted due to the aforementioned special reasons.

[0049] In one embodiment, the packet retransmission count indicator may include a counter value (also referred to as a third counter value). The third counter value may reflect (e.g., be equivalent to) the number of times packets transmitted between storage device 12 and host system 11 are required to be retransmitted due to special reasons (e.g., the aforementioned CRC error or sequence number error) within the time length corresponding to the first detection window. In one embodiment, this third counter value may reflect (e.g., be negatively correlated with) the stability of the connection (i.e., link) between storage device 12 and host system 11. That is, the larger the third counter value, the lower the stability of the connection (i.e., link) between storage device 12 and host system 11.

[0050] In one embodiment, the link anomaly indicator may include at least one of the following: link initialization count indicator, check error count indicator, and packet retransmission count indicator. In another embodiment, the link anomaly indicator may include at least two of the following: link initialization count indicator, check error count indicator, and packet retransmission count indicator. In yet another embodiment, the link anomaly indicator may include the following: link initialization count indicator, check error count indicator, and packet retransmission count indicator. In one embodiment, the link anomaly indicator may also include one or more other indicators that can be used to measure or evaluate the stability of the connection (i.e., the link) between the storage device 12 and the host system 11, which will not be elaborated further here.

[0051] In one embodiment, the environmental state information includes at least one indicator (also known as an environmental stability indicator). In one embodiment, this environmental stability indicator may reflect the stability of the temperature state, voltage state, or other environmental states of the storage device 12.

[0052] In one embodiment, the memory control circuit 23 can monitor the temperature and voltage changes of the storage device 12 within one or more detection windows (also referred to as second detection windows) to obtain monitoring results (also referred to as second monitoring results). For example, the time length corresponding to the second detection window can be 100 ms. It should be noted that the time length corresponding to the second detection window can also be adjusted according to practical needs, and the present invention is not limited thereto. Based on the second monitoring results, the memory control circuit 23 can obtain environmental stability indicators.

[0053] In one embodiment, the memory control circuit 23 can obtain temperature change information and voltage change information of the storage device 12 based on the second monitoring result. This temperature change information reflects the temperature change of the storage device 12 within the time length corresponding to the second detection window (also referred to as the temperature change amount). This voltage change information reflects the voltage change of the storage device 12 within the time length corresponding to the second detection window (also referred to as the voltage change amount). Then, the memory control circuit 23 can obtain an environmental stability index based on this temperature change information and this voltage change information.

[0054] In one embodiment, the memory control circuit 23 may obtain an environmental stability index according to the following formula (1.1). The environmental stability index may reflect (e.g., negatively correlated with) the current environmental fluctuations of the storage device 12.

[0055]

[0056] In formula (1.1), ESI represents the environmental stability index, ΔT represents temperature change information, ΔV represents voltage change information, ΔTmax represents the critical temperature information (i.e., the maximum value of temperature change), and ΔVmax represents the critical voltage information (i.e., the maximum value of voltage change). For example, ESI is negatively correlated with ΔT and ΔV, and positively correlated with ΔTmax and ΔVmax. According to formula (1.1), if ΔT and / or ΔV are larger, and ΔTmax and / or ΔVmax are smaller, then the ESI is smaller, indicating that the current environmental fluctuation of the storage device 12 is greater. Alternatively, from another perspective, the larger the ESI, the more stable the current environment of the storage device 12 is. It should be noted that formula (1.1) can also be adjusted according to practical needs, and this invention does not impose any limitations.

[0057] In one embodiment, the memory control circuit 23 can obtain device status information corresponding to the storage device 12 based on link status information and environmental status information. This device status information can be used to comprehensively reflect the link status and environmental status.

[0058] In one embodiment, the device status information includes link health information. In another embodiment, this link health information can reflect the health (or stability) of the connection (i.e., the link) between the storage device 12 and the host system 11 through different link health levels. For example, this link health information can reflect the health (or stability) of the connection (i.e., the link) between the storage device 12 and the host system 11 through four levels (i.e., levels 0 to 3). Level 0 indicates the highest health (or stability) of the connection (i.e., no link abnormalities); Level 1 indicates a slight decrease in the health (or stability) of the connection (i.e., minor link abnormalities); Level 2 indicates a further decrease in the health (or stability) of the connection (i.e., moderate link abnormalities); and Level 3 indicates a severe decrease in the health (or stability) of the connection (i.e., severe link abnormalities).

[0059] In one embodiment, the memory control circuit 23 can predict the link health information (also referred to as future link health information) of the storage device 12 based on multiple historical link health information. In one embodiment, this future link health information can reflect the link health level (also referred to as future link health level) of the storage device 12 at a future point in time (also referred to as a future time point). For example, this future time point is later than the current time point. Furthermore, each piece of historical link health information corresponds to a past time interval (also referred to as a historical time interval).

[0060] Figure 4 This is a schematic diagram illustrating multiple time intervals according to an embodiment of the present invention. Please refer to... Figure 4 Multiple time intervals 41(1)-41(D) are arranged sequentially from past to present on the timeline. Each time interval lies between time point T(j-1) and T(j), where j is an integer between 1 and D. For example, D can be 10. It should be noted that D can also be any integer greater than 1, and this invention does not impose any restrictions.

[0061] In one embodiment, assuming the future time point is T(D+1), then time interval 41(p) is further away from the future time point (i.e., time point T(D+1)) than time interval 41(p+1), where p is an integer between 1 and D-1. In one embodiment, the future time point (e.g., T(D+1)) may belong to the next time interval following time interval 41(D+1).

[0062] In one embodiment, each time interval 41(1)-41(D) corresponds to a historical link health information. In one embodiment, the memory control circuit 23 can establish a buffer in the buffer memory 24. The memory control circuit 23 can store multiple historical link health information corresponding to the time intervals 41(1)-41(D) in this buffer.

[0063] In one embodiment, each historical link health information includes historical link anomaly count information. In one embodiment, taking time interval 41(i) (i is an integer between 1 and D) as an example, the memory control circuit 23 can obtain the historical link anomaly count information corresponding to time interval 41(i) based on the link anomaly indicators monitored within time interval 41(i).

[0064] In one embodiment, assuming the link anomaly indicators include at least two of the following: link initialization count, check error count, and packet retransmission count, the memory control circuit 23 can determine the historical link anomaly count information corresponding to time interval 41(i) based on the sum of at least two of the first, second, and third count values ​​measured within time interval 41(i). For example, the memory control circuit 23 can sum at least two of the first, second, and third count values ​​to obtain the historical link anomaly count information corresponding to time interval 41(i). In one embodiment, the historical link anomaly count information corresponding to time interval 41(i) may be the same as or positively correlated with the sum.

[0065] In one embodiment, the memory control circuit 23 can input multiple historical link anomaly counts corresponding to time intervals 41(1)-41(D) into a linear regression model to predict the link health level (i.e., future link health level) of the storage device 12 at a future time point (e.g., time point T(D+1)).

[0066] In one embodiment, the memory control circuit 23 can obtain link anomaly count information (also referred to as future link anomaly count information) corresponding to a future time point based on the output of a linear regression model. In one embodiment, the memory control circuit 23 can compare the future link anomaly count information with at least one critical information (also referred to as first critical information) to obtain a comparison result (also referred to as a first comparison result). Then, the memory control circuit 23 can determine the future link health level based on the first comparison result.

[0067] In one embodiment, at least part of the algorithmic logic employed by the linear regression model can be represented by the following formulas (2.1) to (2.3):

[0068]

[0069]

[0070] YP = a + b × (K + 1) (2.3)

[0071] In formulas (2.1) to (2.3), YP represents the future link anomaly count information, a represents the linear regression intercept, b represents the linear regression slope, yi represents the historical link anomaly count information corresponding to time interval 41(i), and K represents the total number of time intervals 41(1)-41(D) (for example, K can be equal to D). It should be noted that formulas (2.1) to (2.3) can also be adjusted according to practical needs, and this invention does not impose any restrictions.

[0072] In one embodiment, after obtaining the future link anomaly count information (i.e., YP in formula (2.3)), the memory control circuit 23 can compare the future link anomaly count information with the threshold values ​​TH1, TH2, and TH3 (i.e., the first threshold information) to obtain a first comparison result. The threshold value TH3 is greater than the threshold value TH2, and the threshold value TH2 is greater than the threshold value TH1. In one embodiment, the threshold value TH3 is twice the threshold value TH2 (i.e., THR3 = 2 × THR2).

[0073] In one embodiment, if (or in response to) the first comparison result indicating that the future link anomaly count is less than the threshold TH1, the memory control circuit 23 may determine the future link health level as level 0. In one embodiment, if (or in response to) the first comparison result indicating that the future link anomaly count is between the thresholds TH1 and TH2, the memory control circuit 23 may determine the future link health level as level 1. In one embodiment, if (or in response to) the first comparison result indicating that the future link anomaly count is between the thresholds TH2 and TH3, the memory control circuit 23 may determine the future link health level as level 2. In one embodiment, if (or in response to) the first comparison result indicating that the future link anomaly count is greater than the threshold TH3, the memory control circuit 23 may determine the future link health level as level 3.

[0074] In one embodiment, the memory control circuit 23 can also evaluate the changing trends of multiple historical link health information corresponding to time intervals 41(1)-41(D). Then, the memory control circuit 23 can determine the future link health level based on this changing trend.

[0075] In one embodiment, the memory control circuit 23 can analyze multiple historical link health information to obtain at least one evaluation value (also known as a trend evaluation value). Then, the memory control circuit 23 can obtain the trend of change of multiple historical link health information based on this trend evaluation value.

[0076] In one embodiment, the historical link health information for each time interval in time intervals 41(1)-41(D) may further include at least one of environmental stability indicators, temperature change information, and voltage change information. In one embodiment, the trend assessment value may include at least one of the following: anomaly frequency change rate, anomaly frequency acceleration, ESI change slope, anomaly frequency peak value, and environmental fluctuation amplitude.

[0077] In one embodiment, the memory control circuit 23 can take the difference between the link anomaly count information corresponding to any two adjacent time intervals (e.g., time intervals 41(D-1) and 41(D)) in the time interval 41(1)-41(D) to obtain the anomaly change rate. For example, assuming that y(D-1) represents the link anomaly count information corresponding to the time interval 41(D-1) and y(D) represents the link anomaly count information corresponding to the time interval 41(D), the memory control circuit 23 can subtract y(D-1) from y(D) to obtain the anomaly change rate Δy (i.e., Δy = y(D) - y(D-1)).

[0078] In one embodiment, the memory control circuit 23 can square the rate of change of the number of anomalies to obtain the acceleration of the number of anomalies.

[0079] In one embodiment, the memory control circuit 23 can perform linear fitting on the ESI corresponding to any three adjacent time intervals (e.g., time intervals 41(D-2), 41(D-1), and 41(D)) within the time intervals 41(1)-41(D) to obtain the fitting slope. The memory control circuit 23 can determine the ESI change slope based on this fitting slope. For example, this fitting slope can be positively correlated with the ESI change slope. The larger this ESI change slope (i.e., the larger the fitting slope), the more rapidly the link environment changes (e.g., gradually deteriorates).

[0080] In one embodiment, the memory control circuit 23 can obtain the maximum link anomaly count information and the minimum link anomaly count information from the link anomaly count information corresponding to the time intervals 41(1)-41(D) respectively. Then, the memory control circuit 23 can determine the peak value of the anomaly frequency based on the difference between the maximum link anomaly count information and the minimum link anomaly count information.

[0081] In one embodiment, the memory control circuit 23 can take the variance of the temperature change (and / or voltage change) corresponding to the time intervals 41(1)-41(D) respectively to determine the amplitude of environmental fluctuations.

[0082] In one embodiment, after determining the changing trends of multiple historical link health information, the memory control circuit 23 can determine the future link health level based on these trends. For example, the memory control circuit 23 can modify formula (2.3) to the following formula (2.4) to influence the predicted future link health level.

[0083] YP = a + b × (K + 1) + c (2.4)

[0084] In formula (2.4), c represents the trend control parameter. The memory control circuit 23 can adjust or set this trend control parameter based on the trend evaluation value (or the trend of multiple historical link health information) to influence the subsequently determined future link health level. For example, when the trend of multiple historical link health information reflects relatively severe environmental fluctuations or gradually increasing fluctuations over a period of time, the memory control circuit 23 can increase the value of c. Conversely, when environmental fluctuations are relatively mild or gradually decreasing over a period of time, the memory control circuit 23 can decrease the value of c. It should be noted that formula (2.4) can also be adjusted according to practical needs, and this invention does not impose any limitations on it.

[0085] In one embodiment, the environmental state information includes temperature change information and voltage change information. The memory control circuit 23 can obtain an environmental fluctuation factor based on this temperature change information and voltage change information. In one embodiment, the memory control circuit 23 can confirm or correct the predicted future link health level based on this environmental fluctuation factor.

[0086] In one embodiment, the memory control circuit 23 can obtain the environmental fluctuation factor according to the following formula (3.1).

[0087]

[0088] In formula (3.1), e represents the environmental fluctuation factor. It should be noted that formula (3.1) can also be adjusted according to practical needs, and the present invention does not limit it. For example, the environmental fluctuation factor (i.e., e) can reflect the sum of the normalized temperature change and voltage change of the storage device 12.

[0089] In one embodiment, the memory control circuit 23 can compare the environmental fluctuation factor with at least one critical information (also referred to as the second critical information) to obtain a comparison result (also referred to as the second comparison result). Then, the memory control circuit 23 can confirm or correct the future link health level based on the second comparison result.

[0090] In one embodiment, after obtaining the environmental volatility factor (i.e., e in formula (3.1)), the memory control circuit 23 can compare the environmental volatility factor with the critical values ​​TH4 and TH5 (i.e., the second critical information) to obtain a second comparison result. The critical value TH4 is greater than the critical value TH5.

[0091] In one embodiment, if (or in response to) a second comparison result where the environmental volatility factor is greater than the threshold value TH4 (also referred to as the first result), the memory control circuit 23 may upgrade the future link health level. For example, assuming the predicted future link health level is level 0, the memory control circuit 23 may upgrade this future link health level to level 1; or, assuming the predicted future link health level is level 1, the memory control circuit 23 may upgrade this future link health level to level 2; or, assuming the predicted future link health level is level 2, the memory control circuit 23 may upgrade this future link health level to level 3.

[0092] In one embodiment, if (or in response to) the second comparison result is that the environmental volatility factor is greater than the critical value TH4 (i.e. the first result), the memory control circuit 23 may adjust the predicted future link health level according to the following formula (4.1).

[0093] L = min ((LP + 1), 3) (4.1)

[0094] In formula (4.1), L represents the adjusted future link health level, min() is the minimum value function, and LP represents the original predicted future link health level. It should be noted that formula (4.1) can also be adjusted according to practical needs, and this invention does not impose any restrictions.

[0095] In one embodiment, if (or in response to) a second comparison result where the environmental volatility factor is between the critical values ​​TH4 and TH5 (also referred to as the second result), the memory control circuit 23 may maintain (i.e., not adjust) the predicted future link health level. For example, assuming the predicted future link health level is level 1 and the second comparison result is the second result, then after referencing the environmental volatility factor, the memory control circuit 23 may maintain the predicted future link health level at level 1.

[0096] In one embodiment, if (or in response to) a second comparison result where the environmental volatility factor is less than the critical value TH5 (also referred to as the third result), the memory control circuit 23 can set the predicted future link health level to be consistent with the link health level reflected by the historical link health information corresponding to the previous time interval. Figure 4 For example, suppose the historical link health information corresponding to time interval 41(D) reflects that the link health level corresponding to time interval 41(D) is level 0 and the currently predicted future link health level is level 1. In response to the second comparison result being the third result, the memory control circuit 23 can set the predicted future link health level to level 0 (i.e., consistent with the link health level reflected by the historical link health information corresponding to time interval 41(D) (i.e., level 0).

[0097] In one embodiment, the memory control circuit 23 may record at least one historical confidence level. This historical confidence level reflects the accuracy of the most recent M predicted link health levels. For example, after each time interval (also referred to as the target time interval), the memory control circuit 23 may compare the actual link health level corresponding to the target time interval with the previously predicted link health level (i.e., the future link health level) for the target time interval. If they are the same, the memory control circuit 23 may set the historical confidence level corresponding to the target time interval to a certain value (also referred to as the first value). However, if they are different, the memory control circuit 23 may set the historical confidence level corresponding to the target time interval to another value (also referred to as the second value). For example, the first value may be "0" and the second value may be "1". Alternatively, the first value may be "1" and the second value may be "0".

[0098] In one embodiment, after the target time interval has elapsed, the memory control circuit 23 can determine the actual link health level corresponding to the target time interval based on the parameters and / or indicators measured within this target time interval. For example, assuming that the predicted future link health level for the target time interval was level 1 and the actual link health level determined for the target time interval subsequently is also level 1 (i.e., they are the same), the memory control circuit 23 can set the historical confidence information corresponding to the target time interval to a first value. Alternatively, assuming that the predicted future link health level for the target time interval was level 1 and the actual link health level determined for the target time interval subsequently is also level 2 (i.e., they are different), the memory control circuit 23 can set the historical confidence information corresponding to the target time interval to a second value.

[0099] In one embodiment, the memory control circuit 23 can obtain future confidence information based on the recorded historical confidence information. The memory control circuit 23 can then use this future confidence information to assess the accuracy of the currently predicted future link health information.

[0100] In one embodiment, the future confidence information includes an assessment value (also known as a future confidence assessment value). This future confidence assessment value reflects the accuracy of the current prediction of future link health information.

[0101] In one embodiment, the memory control circuit 23 may obtain the future confidence assessment value according to the following formula (5.1).

[0102] CF = N / M (5.1)

[0103] In formula (5.1), CF represents the future confidence assessment value, and N represents the total number of first values ​​among the M recorded historical confidence information. In other words, N reflects the total number of correctly predicted link health levels among the M past predicted link health levels. Furthermore, the future confidence assessment value (i.e., CF) can reflect (e.g., positively correlated with) the correctness of the currently predicted future link health information. It should be noted that formula (5.1) can also be adjusted according to practical needs, and this invention does not impose any limitations.

[0104] In one embodiment, the memory control circuit 23 may further correct the future confidence assessment value according to the following formula (5.2).

[0105] CF' = α CF + (1 -α) × CF(0) (5.2)

[0106] In formula (5.2), CF(0) represents the previously obtained future confidence assessment value, CF represents the currently obtained future confidence assessment value, CF' represents the updated future confidence assessment value, and α represents the decay factor. Compared to CF, CF' further introduces the concept of a weighted moving average, making the numerical changes of multiple continuously determined future confidence assessment values ​​trend-like rather than abrupt. It should be noted that formula (5.2) can also be adjusted according to practical needs, and this invention does not impose any limitations on it.

[0107] In one embodiment, after determining the future link health information, the memory control circuit 23 can determine a pre-protection strategy (also known as a target pre-protection strategy) from multiple pre-protection strategies (also known as candidate pre-protection strategies) based on the future link health level. Then, the memory control circuit 23 can perform dynamic pre-protection on the storage device 12 according to this target pre-protection strategy.

[0108] In one embodiment, if (or in response to) a future link health level of a certain level (also referred to as a first level), the memory control circuit 23 can determine one of the multiple candidate pre-protection strategies (also referred to as a first pre-protection strategy) as the target pre-protection strategy. Furthermore, if (or in response to) a future link health level of another level (also referred to as a second level), the memory control circuit 23 can determine another of the multiple candidate pre-protection strategies (also referred to as a second pre-protection strategy) as the target pre-protection strategy.

[0109] In one embodiment, the first level includes levels 0 and 1, and the second level includes levels 2 and 3. However, in another embodiment, both the first and second levels can be adjusted according to practical needs.

[0110] In one embodiment, in response to the target pre-protection strategy being the first pre-protection strategy, the memory control circuit 23 can update the link anomaly attribute information to the Device Management Entity (DME) information of the storage device 12 for querying by the host system 11. For example, this link anomaly attribute information may include environmental parameter information, anomaly indicator details, and / or anomaly occurrence time information from the device status information. In one embodiment, the link anomaly attribute information may also include other types of device status information, which will not be described in detail here.

[0111] In one embodiment, the environmental parameter information may include at least one of temperature information, voltage information, and environmental stability indicators. The temperature information may reflect the current temperature of the storage device 12. The voltage information may reflect the current voltage of the storage device 12.

[0112] In one embodiment, the abnormal indicator details may include the peak value of at least one of the following indicators detected within the current detection window: the number of link initializations, the number of verification errors, and the number of packet retransmissions.

[0113] In one embodiment, the anomaly occurrence time information may include at least one timestamp. The anomaly occurrence time information reflects the time when the anomaly occurred.

[0114] In one embodiment, cross-index correlation information can reflect the relationship between environmental fluctuations and link anomalies. For example, within a certain period of time (e.g., within a first or second detection window), the second count value increases by 2 times for every 5-degree increase in the temperature of the storage device 12.

[0115] In one embodiment, under the first pre-protection strategy, the memory control circuit 23 may periodically (e.g., every 100 ms) update the link anomaly attribute information to the corresponding DME attribute field in the DME information of the storage device 12 based on the link status information and the environment status information.

[0116] In one embodiment, under the first pre-protection strategy, the memory control circuit 23 may receive a query command for DME information from the host system 11. This query command may request specific DME information from the storage device 12. In one embodiment, under the first pre-protection strategy, in response to this query command, the memory control circuit 23 may report link anomaly attribute information to the host system 11.

[0117] Figure 5 This is a schematic diagram illustrating an operational scenario for information feedback under a first pre-protection strategy, as shown in an embodiment of the present invention. Please refer to... Figure 5 Under the first pre-protection strategy, the memory control circuit 23 can update the link anomaly attribute information 53 to the DME information 54 of the storage device 12 based on the link status information 51 and the environment status information 52. Subsequently, in response to the host system 11's query command for the DME information, the memory control circuit 23 can report the link anomaly attribute information 53 back to the host system 11.

[0118] In other words, under the first pre-protection strategy, the memory control circuit 23 can passively feed back specific device status information (e.g., link anomaly attribute information 53) to the host system 11 only when the host system 11 actively requests it, in response to the host system 11's query command for DME information.

[0119] In one embodiment, in response to the target pre-protection strategy being the second pre-protection strategy (also known as the second feedback mode), the memory control circuit 23 can add abnormal reporting information to a packet (also known as a link packet) based on link status information and environmental status information. Then, the memory control circuit 23 can use this link packet to feed back this abnormal reporting information to the host system 11. It should be noted that, compared to the first pre-protection strategy, under the second pre-protection strategy, the link packet used to add this abnormal reporting information is used to respond to general operation commands (such as read commands, write commands, or delete commands) sent by the host system 11, rather than to respond to query commands from the host system 11 regarding DME information.

[0120] In one embodiment, under the second pre-protection strategy, the memory control circuit 23 can first determine the link packet to be sent to the host system 11. Then, the memory control circuit 23 can modify the payload area of ​​this link packet to add abnormal reporting information to this payload area. That is, under the second pre-protection strategy, the abnormal reporting information is added to the payload area of ​​the link packet, rather than to the header area of ​​the link packet.

[0121] Figure 6This is a schematic diagram illustrating the operational scenario of information feedback under the second pre-protection strategy according to an embodiment of the present invention. Please refer to... Figure 6 Under the second pre-protection strategy, the memory control circuit 23 can add anomaly report information 63 to the link packet 64 based on the link status information 61 and the environment status information 62. For example, the memory control circuit 23 can intercept at least one link packet to be sent to the host system 11 to obtain the link packet 64. After adding the anomaly report information 63 to the link packet 64, the memory control circuit 23 can transmit this link packet 64 along with the anomaly report information 63 to the host system 11.

[0122] In other words, under the second pre-protection strategy, without the host system 11 actively requesting it, the memory control circuit 23 can proactively feed back specific device status information (such as abnormal report information 63) to the host system 11 without receiving a query instruction from the host system 11 for DME information.

[0123] In one embodiment, the anomaly report information may include future link health level information and future confidence information. The future link health level information reflects the predicted future link health level. Furthermore, the future confidence information reflects the accuracy of the future link health information assessed by the storage device 12.

[0124] In one embodiment, the host system 11 can perform resource configuration or error protection measures in advance based on future link health level information and future confidence information. In one embodiment, the anomaly report information may further include at least one of environmental volatility information and anomaly occurrence frequency information. In one embodiment, environmental volatility information is also referred to as environmental attribution information.

[0125] In one embodiment, taking the UFS protocol as an example, the link packet may include a UFS Protocol Information Unit (UPIU) packet. Anomaly reporting information may be added to the device information field of the response UPIU packet or the query response UPIU packet. The response UPIU packet can be used to return the command execution status and / or task management request execution status to the host system 11. The query response UPIU packet can be used to return the query request execution status for the device manager to the host system 11. For example, in the device information field, the memory control circuit 23 can use 4 bits [7:4] to carry future link health information (e.g., using 0x0, 0x1, 0x2 and 0x3 to represent level 0, level 1, level 2 and level 3 respectively), use 4 bits [3:2] to carry environmental fluctuation information (i.e. environmental attribution information) (e.g., using 0x0, 0x1, 0x2 and 0x3 to represent no environmental fluctuation, slight environmental fluctuation, severe environmental fluctuation and extreme environmental fluctuation respectively), and use 2 bits [1:0] to carry anomaly occurrence frequency information (e.g., using 0x0, 0x1 and 0x2 to represent occasional, continuous and faulty respectively).

[0126] In one embodiment, the second pre-protection strategy may include multiple sub-modes (also referred to as sub-feedback modes). In one embodiment, under a certain sub-feedback mode (also referred to as the first sub-feedback mode) of the second pre-protection strategy, the anomaly report information includes link anomaly report information. For example, this link anomaly report information includes at least one of link health information, environmental fluctuation information, and anomaly occurrence frequency information.

[0127] In one embodiment, under another sub-feedback mode of the second pre-protection strategy (also referred to as the second sub-feedback mode), the anomaly report information includes link anomaly report information and fast recovery request information. In one embodiment, this fast recovery request information can be used to trigger or guide the host system 11 to prepare for and execute a hardware reset of the storage device 12. Thus, hardware-level reset, correction, and / or recovery are performed for more serious link errors and / or faults.

[0128] In one embodiment, in the second sub-feedback mode of the second pre-protection strategy, the memory control circuit 23 can transmit a link packet (also known as the first link packet) containing fast recovery requirement information (also known as the first fast recovery requirement information) to the host system 11, so that the host system 11 prepares to perform a hardware reset on the storage device 12.

[0129] In one embodiment, after transmitting the first link packet, the memory control circuit 23 can perform cache data backup on the storage device 12 during a period when the storage device 12 is not performing data defragmentation operations. For example, this cache data backup includes moving or copying data from the buffer memory 24 to the memory module 122 for backup. For example, this data defragmentation operation may include garbage collection operations, wear leveling operations, and / or data transfer between good and bad blocks, etc.

[0130] In one embodiment, after the cache data backup is completed, the memory control circuit 23 may transmit a link packet (also known as a second link packet) containing another fast recovery request information (also known as a second fast recovery request information) to the host system 11 to trigger the host system 11 to begin performing a hardware reset on the storage device 12.

[0131] In one embodiment, a first fast recovery request is used to notify the host system 11 to prepare for a hardware reset of the storage device 12. In another embodiment, upon receiving the first fast recovery request, the host system 11 may begin preparing for a hardware reset of the storage device 12 and wait for a second fast recovery request. Before receiving the second fast recovery request, the host system 11 may remain in a stage where it is prepared but has not yet instructed to begin a hardware reset of the storage device 12 (also referred to as the hardware reset preparation stage).

[0132] In one embodiment, the second fast recovery request information is used to trigger the host system 11 to begin performing a hardware reset on the storage device 12. In another embodiment, upon receiving the second fast recovery request information, the host system 11 can actually instruct the storage device 12 to perform a hardware reset. Thus, by utilizing both the first and second fast recovery request information, it is possible to avoid triggering a hardware reset on the storage device 12 without warning before the storage device 12 completes cached data backup, thereby preventing the loss of important data.

[0133] In one embodiment, after transmitting the first link packet, the memory control circuit 23 can determine whether the storage device 12 is performing at least one of a foreground data preparation operation and a background data preparation operation. If the storage device 12 is performing this foreground data preparation operation, the memory control circuit 23 can wait for this foreground data preparation operation to complete. In particular, before this foreground data preparation operation is completed, the memory control circuit 23 can temporarily refrain from performing cache data backup on the storage device 12. On the other hand, if the storage device 12 is performing a background data preparation operation, the memory control circuit 23 can forcibly stop this background data preparation operation. Subsequently, during the period when the storage device 12 is not performing any data preparation operation, the memory control circuit 23 can perform cache data backup on the storage device 12.

[0134] In one embodiment, under the second sub-feedback mode of the second pre-protection strategy, the memory control circuit 23 can update the anomaly cause field in the device health descriptor of the storage device 12 based on cross-index correlation information. For example, the memory control circuit 23 can record the cause of the anomaly in this anomaly cause field based on the cross-index correlation information (e.g., an increase in packet retransmissions due to an increase in the temperature of the storage device 12). Subsequently, the host system 11 can send a query command to instruct the reading of relevant information from the anomaly cause field in the device health descriptor.

[0135] In one embodiment, under the second pre-protection strategy (including the first sub-feedback mode and the second sub-feedback mode), the memory control circuit 23 can periodically update the log file to record system information at the time of the anomaly. This system information can be used for future debugging or firmware optimization of the storage device 12.

[0136] In one embodiment, a link anomaly (i.e., a link failure) refers to a situation where, within a predetermined detection window (e.g., a first detection window and / or a second detection window), the link status indicators deviate from the normal operating range or a similar condition. For example, when at least one of the following indicators—link initialization count, checksum error count, packet retransmission count, or other indicators reflecting link stability—exceeds its corresponding threshold, the memory control circuit 23 can determine that a link failure has occurred. The threshold can be preset based on protocol specifications, system design requirements, or actual test results, and can be adjusted according to different application scenarios.

[0137] In one embodiment, an environmental anomaly (i.e., an environmental anomaly) refers to a situation where, within a predetermined detection window (e.g., a first detection window and / or a second detection window), the temperature change and / or voltage change exceeds the corresponding allowable range of environmental variation, or a similar situation occurs. For example, when the environmental stability index is lower than a preset critical value, the memory control circuit 23 can determine that an abnormal fluctuation in the environment has occurred (i.e., an environmental anomaly). In one embodiment, the environmental stability index can be used to quantify the degree of impact of environmental changes on link stability and can be calculated based on the combined results of temperature and voltage changes.

[0138] In one embodiment, link anomalies and environmental anomalies can be further correlated to determine the possible source of the anomaly (i.e., perform anomaly attribution). When link status indicators are abnormal and environmental stability remains within a stable range, the memory control circuit 23 can presume that the anomaly is caused by channel interference or link transmission factors. Furthermore, when link status indicators are abnormal and environmental stability decreases simultaneously, the memory control circuit 23 can presume that the anomaly is at least partially related to environmental fluctuations. This improves the accuracy of the memory control circuit 23's judgment of link anomalies or its anomaly attribution capability, and serves as at least part of the basis for subsequent feedback mode selection.

[0139] In one embodiment, different pre-protection strategies can correspond to different anomaly feedback timing and methods, including: (1) a passive feedback mode where the host system 11 actively queries (i.e., the first pre-protection strategy); and (2) an active feedback mode where the memory control circuit 23 actively reports by modifying the link packet (i.e., the second pre-protection strategy). In one embodiment, dynamically selecting the pre-protection strategy based on the link status and environment status can reduce the communication burden while maximizing the timeliness of anomaly event reporting.

[0140] In one embodiment, different pre-protection strategies correspond to different communication overhead and response time characteristics. For example, the passive feedback mode (i.e., the first pre-protection strategy) updates via DME information and is suitable for situations where the link state is relatively stable or the degree of abnormality is relatively low, thus reducing the link transmission burden. Conversely, the active feedback mode (i.e., the second pre-protection strategy) provides real-time feedback of abnormal information via link packets, which is suitable for situations where the link state deteriorates rapidly or the degree of abnormality is relatively high, thereby improving the timeliness of abnormality reporting. Therefore, by dynamically selecting the pre-protection strategy under different link states, a balance can be achieved between communication resource utilization efficiency and abnormality response speed.

[0141] In one embodiment, by adding anomaly reporting information to the load area of ​​existing link packets, rather than establishing additional communication channels or adding dedicated packets, the transmission of anomaly information can be achieved without changing the existing communication protocol framework. This reduces additional communication overhead, avoids impacting compatibility with existing protocols, and improves the ease of system integration.

[0142] Figure 7 This is a flowchart illustrating a memory management method according to an embodiment of the present invention. Please refer to... Figure 7 In step S701, the future link health information of the storage device is predicted based on multiple historical link health information. In step S702, the future link health information is confirmed or corrected based on the environmental status information of the storage device. In step S703, dynamic pre-protection is performed on the storage device based on the future link health information. For example, dynamic pre-protection can pre-execute at least one link protection, anomaly notification, cache protection, or recovery preparation operation before the predicted link health decline.

[0143] Figure 8 This is a flowchart illustrating a memory management method according to an embodiment of the present invention. Please refer to... Figure 8In step S801, it is confirmed whether a first link packet intended to be sent to the host system has been detected. If a first link packet intended to be sent to the host system is detected, in step S802, the first link packet containing the first fast recovery request information is transmitted to the host system to notify the host system to prepare to perform a hardware reset on the storage device. If no first link packet intended to be sent to the host system is detected, the system continues to wait for a first link packet.

[0144] In step S803, it is confirmed whether the storage device is performing a foreground data preparation operation. If the storage device is performing a foreground data preparation operation, in step S804, the foreground data preparation operation is waited for to complete. If the storage device is not performing a foreground data preparation operation, in step S805, it is confirmed whether the storage device is performing a background data preparation operation. If the storage device is performing a background data preparation operation, in step S806, the background data preparation operation is forcibly stopped. If the storage device is not performing a background data preparation operation, in step S807, a cache data backup is performed on the storage device.

[0145] After the cached data backup is completed, in step S808, it is checked whether a second link packet intended to be sent to the host system has been detected. If a second link packet intended to be sent to the host system is detected, in step S809, the second link packet containing the second fast recovery request information is transmitted to the host system to trigger the host system to begin performing a hardware reset on the storage device. If no second link packet intended to be sent to the host system is detected, the system continues to wait for a second link packet.

[0146] However, Figure 7 and Figure 8 Each step has been explained in detail above and will not be repeated here. It is worth noting that... Figure 7 and Figure 8 Each step can be implemented as multiple program codes or circuits, and this invention is not limited thereto. Furthermore, Figure 7 and Figure 8 The method can be used in conjunction with the above examples and embodiments, or it can be used alone. This invention does not impose any limitations.

[0147] In summary, compared to traditional storage devices that can only handle current link errors, potentially leading to irreparable packet loss, the memory management method and storage device proposed in this invention can improve the performance of maintaining and coordinating the quality of future links between the storage device and the host system by predicting the future link health information of the storage device and adopting dynamic pre-protection strategies.

[0148] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory management method, characterized in that, For a storage device, the memory management method includes: Based on multiple historical link health information, predict the future link health information of the storage device; Based on the environmental status information of the storage device, confirm or correct the future link health information; and Based on the future link health information, dynamic pre-protection is performed on the storage device.

2. The memory management method according to claim 1, characterized in that, Each historical link health information includes historical link anomaly count information, and the future link health information reflects the future link health level of the storage device. The step of predicting the future link health information of the storage device based on the multiple historical link health information includes: The historical link anomaly count information is input into a linear regression model to predict the future link health level.

3. The memory management method according to claim 2, characterized in that, The steps of inputting the historical link anomaly count information into the linear regression model to predict the future link health level include: Based on the output of the linear regression model, future link anomaly count information is obtained; The future link anomaly count information is compared with at least one first critical information to obtain a first comparison result; and Based on the first comparison result, the future link health level is determined.

4. The memory management method according to claim 2, characterized in that, The steps of inputting the historical link anomaly count information into the linear regression model to predict the future link health level include: Assess the changing trends of the health information of the multiple historical links; and Based on the changing trend, the future link health level is determined.

5. The memory management method according to claim 4, characterized in that, The health information of each historical link also includes at least one of the following: environmental stability indicators, temperature change information, and voltage change information.

6. The memory management method according to claim 2, characterized in that, The environmental status information includes temperature change information and voltage change information, and the step of confirming or correcting the future link health information based on the environmental status information of the storage device includes: Based on the temperature change information and the voltage change information, the environmental fluctuation factor is obtained; and Based on the environmental volatility factor, confirm or revise the future link health level.

7. The memory management method according to claim 6, characterized in that, The steps for confirming or correcting the future link health level based on the environmental volatility factor include: The environmental volatility factor is compared with at least one second critical information to obtain a second comparison result; and Based on the second comparison result, the future link health level is confirmed or corrected.

8. The memory management method according to claim 7, characterized in that, Based on the second comparison result, the steps for confirming or correcting the future link health level include: In response to the second comparison result being the first result, the future link health level is increased; In response to the second comparison result being the second result, the future link health level is maintained; and In response to the second comparison result being the third result, the future link health level is set to be consistent with the link health level reflected in the previous historical link health information.

9. The memory management method according to claim 1, characterized in that, The memory management method further includes: Record at least one historical confidence level; Based on the at least one historical confidence level, obtain future confidence level information; and Based on the future confidence information, the correctness of the future link health information is evaluated.

10. The memory management method according to claim 1, characterized in that, The future link health information reflects the future link health level of the storage device, and the step of performing the dynamic pre-protection on the storage device based on the future link health information includes: Based on the future link health level, a target pre-protection strategy is determined from multiple candidate pre-protection strategies; and The dynamic pre-protection is performed on the storage device according to the target pre-protection strategy.

11. The memory management method according to claim 10, characterized in that, The steps of performing the dynamic pre-protection on the storage device according to the target pre-protection strategy include: In response to the target pre-protection policy being the first pre-protection policy, the link anomaly attribute information is updated in the device management entity information of the storage device for querying by the host system; and In response to the target pre-protection policy being the second pre-protection policy, abnormal reporting information is added to the link packet, and the abnormal reporting information is fed back to the host system through the link packet.

12. The memory management method according to claim 11, characterized in that, The abnormal report information includes future link health level information and future confidence information. The future link health level information reflects the future link health level, and the future confidence information reflects the correctness of the future link health information.

13. The memory management method according to claim 11, characterized in that, The link packet is used to respond to general operational instructions sent by the host system.

14. The memory management method according to claim 11, characterized in that, The steps of adding the abnormal report information to the link packet include: Determine the link packet to be sent to the host system; and Add the abnormal report information to the load area of ​​the link packet.

15. The memory management method according to claim 11, characterized in that, In the first sub-feedback mode of the second pre-protection strategy, the abnormal reporting information includes link abnormal reporting information.

16. The memory management method according to claim 15, characterized in that, In the second sub-feedback mode of the second pre-protection strategy, the abnormal report information includes the link abnormal report information and the fast recovery requirement information.

17. The memory management method according to claim 16, characterized in that, The step of feeding back the abnormal report information to the host system through the link packet further includes: In the second sub-feedback mode of the second pre-protection strategy, a first link packet with first fast recovery requirement information is transmitted to the host system, so that the host system prepares to perform a hardware reset on the storage device. After transmitting the first link packet, during the period when the storage device is not performing data defragmentation operations, a cache data backup is performed on the storage device; and After the cached data backup is completed, a second link packet containing the second fast recovery requirement information is transmitted to the host system, triggering the host system to perform the hardware reset on the storage device.

18. The memory management method according to claim 17, characterized in that, Also includes: After transmitting the first link packet, confirm whether the storage device is performing at least one of the foreground data processing operation and the background data processing operation; If the storage device is performing the foreground data preparation operation, wait for the foreground data preparation operation to be completed, and do not perform the cache data backup on the storage device before the foreground data preparation operation is completed; as well as If the storage device is performing the background data processing operation, the background data processing operation shall be forcibly stopped.

19. The memory management method according to claim 16, characterized in that, Also includes: In the second sub-feedback mode of the second pre-protection strategy, the anomaly reason field in the device health descriptor of the storage device is updated according to cross-index correlation information.

20. A storage device, characterized in that, include: A connection interface used to connect to the host system; Memory module; as well as The memory controller is connected to the connection interface and the memory module. The memory controller is used to execute the memory management method according to any one of claims 1-19.

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