A method, apparatus, electronic device, and storage medium for reducing Nand bit error rate.

Abstract

This invention discloses a method, apparatus, electronic device, and storage medium for reducing Nand bit error rate, relating to the field of flash memory storage control technology. The method includes: maintaining a dynamically added and deleted queue in SRAM or DRAM, recording the block numbers of data written within a set time period, and checking in real time whether the interval between the last write and the last write to each block in the queue exceeds the set time period; if it does, the block is removed from the queue. An offline lookup table is formed by pre-calculating the initial voltage offset under different erase / write counts as a gradient. When a read command is received, the most recently written queue is traversed to determine whether the target block of the read command is in the queue. If it is, the corresponding voltage compensation level is found in the offline lookup table based on the current erase / write count of the block, and the optimal voltage compensation level is applied to the target block before performing the read operation; otherwise, the default voltage is used for normal execution. This invention solves the problems of existing technologies, such as the inability to identify compensation in advance, frequent read retry, and severe degradation of read performance.

Description

Technical Field

[0001] This invention relates to the field of flash memory storage control technology, and in particular to a method, apparatus, electronic device, and storage medium for reducing Nand bit error rate. Background Technology

[0002] With the widespread application of solid-state drives (SSDs) in data centers, consumer electronics, and other fields, NAND flash memory, as the core storage medium, directly impacts overall system performance due to its read / write reliability. Writing data to NAND flash memory using a stepped programming voltage causes the write threshold voltage to shift to the right, resulting in an initial voltage offset (IVS) effect. This effect significantly increases the error rate (err bit) when reading immediately after writing, but it disappears automatically after a period of time. Current SSD read strategies generally use a default read threshold voltage for normal reading, only compensating for the IVS effect after an err bit occurs—a passive "error-first, recovery-later" approach.

[0003] However, in practical applications, it has been found that when NAND flash memory is read within a short period of time (e.g., within 10 minutes), a short-term composite drift problem is triggered, mainly characterized by initial voltage offset (IVS) supplemented by read interference. This problem is particularly severe in flash memory with high erase / write cycles (PE). Existing read retry mechanisms cannot identify and compensate for this short-term drift in advance, and can only repeatedly reread after a bit error occurs, resulting in a significant decrease in read performance.

[0004] Therefore, there is an urgent need for a method to reduce the bit error rate of Nand that can identify the IVS effect in advance and apply voltage compensation in advance, thereby eliminating short-term recombination drift after writing and ensuring random read and write performance. Summary of the Invention

[0005] The embodiments of this invention provide a method for reducing Nand bit error rate, addressing the problems of existing technologies that cannot identify short-term compound drift within a short period after writing and cannot prevent bit flips, leading to frequent read retry and severe performance degradation. The technical solution is as follows: According to one aspect of the present invention, a method for reducing the bit error rate of Nand signals is provided. The method includes: setting a dynamically added and deleted recently written queue in SRAM or DRAM, adding a block to the recently written queue whenever it is written within a set time period; checking in real time whether the interval between the last write and the last write of each block in the recently written queue exceeds the set time period, and removing the block from the recently written queue if it does; setting a corresponding voltage compensation level with a set number of erase / write cycles as a gradient, and statistically analyzing the initial voltage offset of Nand under different number of erase / write cycles to form an offline lookup table; the offline lookup table is used to map the optimal voltage compensation level corresponding to each erase / write cycle interval; upon receiving a read command, traversing the recently written queue, determining whether the target block of the read command is in the recently written queue, and if so, finding the corresponding voltage compensation level in the offline lookup table according to the current number of erase / write cycles of the target block, and applying the voltage of the specified level to the target block to perform a read operation.

[0006] In one embodiment, a dynamically added and deleted recent write queue is set up in SRAM or DRAM. Whenever a block is written within a set time period, it is added to the recent write queue. This is achieved through the following steps: maintaining a dynamically added and deleted recent write queue in SRAM or DRAM; the recent write queue is used to record the block number of data written within a certain period of time in real time; whenever a block is written, the block number of the block is added to the recent write queue to ensure that all blocks that complete the write operation within the set time period can be recorded in a timely manner.

[0007] In one embodiment, the real-time checking of whether the interval between the last write and the last write of each block in the most recently written queue exceeds the set time limit, and removing the block from the most recently written queue if the interval exceeds the set time limit, is achieved through the following steps: real-time checking of whether the interval between the last write and the last write of each block in the most recently written queue exceeds the set time limit, and removing the block from the most recently written queue; the removal is used to retain only blocks that have been written within the set time limit.

[0008] In one embodiment, a voltage compensation level is set based on a predetermined number of erase / write cycles. The initial voltage offset of the Nand at different erase / write cycles is statistically analyzed to form an offline comparison table. This is achieved through the following steps: a gradient is set based on the number of erase / write cycles of the Nand; multiple voltage compensation levels are divided based on the gradient; and the initial voltage offset corresponding to the number of erase / write cycles of the block is statistically analyzed offline to form an offline comparison table. The offline comparison table is used to select the optimal voltage compensation level based on the current number of erase / write cycles.

[0009] In one embodiment, upon receiving a read command, the most recently written queue is traversed to determine whether the target block of the read command is in the most recently written queue. If it is, the corresponding voltage compensation level is found in the offline lookup table based on the current erase / write count of the target block. This is achieved through the following steps: Upon receiving a read command, the most recently written queue is traversed to determine whether the target block to be read by the read command is in the most recently written queue; if the target block is in the most recently written queue, the current erase / write count of the target block is obtained, and the corresponding initial voltage offset level is found in the offline lookup table based on the current erase / write count to determine the optimal voltage compensation level to be applied.

[0010] In one embodiment, applying the voltage of the specified level to the object block to perform a read operation is achieved through the following steps: applying the optimal voltage compensation level to the object block to perform a read operation; the optimal voltage compensation level is used to eliminate the initial voltage offset effect and the accompanying read interference during the read operation, thereby avoiding excessively high err bit caused by the voltage offset effect.

[0011] In one embodiment, the method further includes the following step: if the object block of the read command is not in the recently written queue, then the read operation is performed using data with a normal default read threshold voltage.

[0012] According to one aspect of the present invention, an apparatus for reducing the bit error rate of Nand signals is provided. The apparatus includes: a recently written queue setting module, configured to set a dynamically added and deleted recently written queue in SRAM or DRAM, wherein each block is added to the recently written queue whenever it is written within a set time period; a recently written queue maintenance module, configured to check in real time whether the interval between each block in the recently written queue and the last write exceeds the set time period, and if it does, remove the block from the recently written queue; an offline lookup table construction module, configured to set corresponding voltage compensation levels with a set number of erase / write cycles as a gradient, and statistically analyze the initial voltage offset of Nand under different number of erase / write cycles to form an offline lookup table; the offline lookup table is used to map the optimal voltage compensation level corresponding to each erase / write cycle interval; and a voltage compensation and operation execution module, configured to traverse the recently written queue after receiving a read command, determine whether the target block of the read command is in the recently written queue, and if so, find the corresponding voltage compensation level in the offline lookup table according to the current number of erase / write cycles of the target block, and apply the voltage of the specified level to the target block to perform a read operation.

[0013] According to one aspect of the present invention, an electronic device includes at least one processor and at least one memory, wherein computer-readable instructions are stored on the memory; the computer-readable instructions are executed by one or more of the processors to cause the electronic device to implement the method for reducing the Nand bit error rate as described above.

[0014] According to one aspect of the invention, a storage medium stores computer-readable instructions thereon, which are executed by one or more processors to implement the method for reducing Nand bit error rate as described above.

[0015] The beneficial effects of the technical solution provided by this invention are: In the above technical solution, this invention first maintains a dynamically added and deleted recently written queue, RecentWriteQ, in SRAM or DRAM to record the block numbers of data written within a set time period in real time. The firmware then checks in real time whether the interval between each block and its last write exceeds the set time. If it does, the block is removed from the queue, thus accurately identifying target blocks within a short period after a write operation. Based on this, the initial voltage offset of Nand at different erase / write counts is statistically calculated using a set number of erase / write cycles as a gradient, forming an offline lookup table with three levels to map the optimal voltage compensation level corresponding to each erase / write count interval. Then, upon receiving a read command, the recently written queue is traversed to determine if the target block is in the queue. If it is, the corresponding voltage compensation level is found in the offline lookup table based on the current erase / write count of the block, and the optimal voltage compensation level is applied to the target block before performing the read operation. This eliminates the initial voltage offset IVS effect and the associated read interference, avoiding err caused by the voltage offset effect. If the error rate is too high and the target block is not in the queue, the default read threshold voltage is used to perform the read operation normally. This achieves proactive prevention and precise control of the Nand bit error rate, which not only significantly reduces the occurrence of err bits and the number of read retry, but also significantly reduces the performance degradation caused by frequent rereads. This enables the solid-state drive to complete data access tasks more efficiently and stably in random read and write scenarios, thus effectively solving the problems of existing technologies that cannot identify and compensate for short-term compound drift after writing, frequent read retry, and serious performance degradation. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention, and those skilled in the art can obtain other drawings based on these drawings without creative effort.

[0017] Figure 1 This is a flowchart illustrating a method for reducing Nand bit error rate according to an exemplary embodiment; Figure 2 This is a flowchart illustrating a method for reducing Nand bit error rate in an exemplary embodiment; Figure 3 This is a block diagram illustrating an apparatus for reducing Nand bit error rate according to an exemplary embodiment; Figure 4 This is a hardware structure diagram of an electronic device according to an exemplary embodiment; Figure 5 This is a block diagram illustrating an electronic device according to an exemplary embodiment. Detailed Implementation

[0018] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0019] Those skilled in the art will understand that, unless specifically stated otherwise, the singular forms “a,” “an,” “the,” and “the” used herein may also include the plural forms. It should be further understood that the term “comprising” as used in this disclosure means the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. It should be understood that when we say an element is “connected” or “coupled” to another element, it can be directly connected or coupled to the other element, or there may be intermediate elements. Furthermore, “connected” or “coupled” as used herein can include wireless connections or wireless coupling. The term “and / or” as used herein includes all or any units and all combinations of one or more associated listed items.

[0020] This invention provides a method for reducing the bit error rate (BER) of Nand signals. It employs an adaptive offline lookup table construction method for non-volatile storage media, dynamically tracking recently written blocks and combining this with an offline voltage compensation strategy based on erase / write cycles. During read operations, an optimal compensation voltage is adaptively applied to the target block, actively eliminating the initial voltage offset effect of the Nand signal. This effectively solves the problems of high BER, frequent read retry, and severe performance degradation in existing technologies. This method for reducing Nand BER is applicable to devices used to reduce Nand BER, such as electronic devices. The method for reducing Nand BER in this invention can be applied to various scenarios, such as reducing Nand BER.

[0021] Please see Figure 1 This invention provides a method for reducing the Nand bit error rate, which is applicable to electronic devices.

[0022] In the following method embodiments, for ease of description, the execution subject of each step of the method is an electronic device, but this does not constitute a specific limitation.

[0023] like Figure 1 As shown, the method may include the following steps: Step 110: Set up a dynamically added and deleted recent write queue in SRAM or DRAM. Whenever a block is written within a set time period, it is added to the recent write queue.

[0024] One possible implementation is to maintain a dynamically added and deleted recent write queue in SRAM or DRAM. Whenever a block is written to, the block number of the block is added to the recent write queue to ensure that all blocks that complete the write operation within the set time period are recorded in a timely manner.

[0025] The recently written queue is used to record the block number of data that has been written within a certain period of time.

[0026] Specifically, a memory region is allocated in the SRAM or DRAM of the solid-state drive to maintain a block queue called RecentWriteQ. The core function of this queue is to track and record in real time all block numbers that have been written to within a specific time period (e.g., 10 minutes). The specific operating mechanism is as follows: whenever the firmware detects that a block has completed a write operation, it immediately writes the block number of that block to the tail of the RecentWriteQ queue; at the same time, the firmware background periodically traverses each block in the queue, checking whether the time interval between the block and the last write operation has exceeded a preset time (e.g., 10 minutes). Once it is detected that the time interval of a block has exceeded the threshold, the block is immediately removed from the queue, ensuring that the queue always retains only blocks within the "short-term post-write window".

[0027] In Nand chips, within a short period after writing (e.g., within 10 minutes), the threshold voltage undergoes a significant rightward shift due to the Initial Voltage Slip (IVS) effect. This, coupled with read interference, creates a short-term compound drift phenomenon, particularly pronounced in high-write-cycle (PE) chips. Existing read retry mechanisms only respond passively after a read error occurs, failing to identify this short-term drift in advance. This step, however, uses a queuing mechanism to accurately mark all blocks within the active period of the IVS effect, laying the foundation for subsequent proactive compensation.

[0028] In the above process, the embodiments of the present invention construct a dynamically added and deleted RecentWriteQ queue in SRAM or DRAM and maintain its timeliness in real time, so that all blocks within the short-term post-write window can be captured and marked in a timely manner. This provides a lightweight and efficient short-term post-write read scenario identification mechanism, realizes the accurate positioning of blocks during the active period of IVS effect, and fundamentally solves the problem that the existing technology cannot identify short-term post-write composite drift in advance.

[0029] Step 120: Check in real time whether the interval between each block in the most recently written queue and the last write exceeds the set time. If it does, remove the block from the most recently written queue.

[0030] In one possible implementation, the system checks in real time whether the interval between the last write and the last write of each block in the most recently written queue has exceeded a set time. If the interval between the last write and the last write has exceeded the set time, the block is removed from the most recently written queue.

[0031] Among them, the "remove" option is used to retain only blocks that have been written within a set time period.

[0032] Specifically, offline experiments were conducted beforehand to determine the optimal IVS voltage compensation level for Nand particles at different erase / write cycles (PE), and the statistical results were compiled into a reference table. Specifically, the system was divided into three levels based on a set erase / write cycle A: level 1 for PE between 0 and A, level 2 for PE between A and 2A, and level 3 for PE greater than 2A. Each level corresponds to a specific voltage offset compensation value, which is the optimal voltage that maximizes the elimination of the IVS effect within that PE range, statistically derived from a large amount of experimental data.

[0033] The severity of the IVS effect is positively correlated with the number of write / erase cycles of the Nand chip—the higher the PE (Pressure Expiration) value, the more severe the threshold voltage drift, and the greater the required compensation voltage. While existing technologies use PE to determine the cause of bit flips after an error, they haven't established a systematic PE-voltage mapping relationship. Although existing technologies have empirical difference tables, these only apply to long-term hold scenarios and don't cover IVS scenarios where data is read immediately after a write. This step establishes a threshold table through offline statistics, clearly quantifying the relationship between PE and the optimal compensation voltage, providing a reliable basis for rapid table lookup during runtime.

[0034] In the above process, this embodiment of the invention establishes a three-level offline voltage compensation reference table with a set number of erase / write cycles as the gradient. This allows NAND flash memory chips with different aging levels to be matched with the optimal compensation voltage corresponding to their PE values, providing a systematic and quantifiable basis for voltage compensation decisions. It achieves precise graded compensation for the IVS effect under different erase / write cycles, effectively overcoming the deficiency of existing technologies lacking a mapping relationship between PE and voltage. Step 130: Set the corresponding voltage compensation level with a set number of erase / write cycles as the gradient, and statistically analyze the initial voltage offset of NAND flash memory under different erase / write cycles to form an offline reference table.

[0035] In one possible implementation, a gradient is set based on the number of erase / write cycles of the Nand, and multiple voltage compensation levels are divided according to the gradient. The initial voltage offset corresponding to the number of erase / write cycles of the block is calculated offline to form an offline comparison table.

[0036] The offline lookup table is used to map the optimal voltage compensation level corresponding to each erase / write cycle range.

[0037] Specifically, when the SSD receives a read command, the firmware first iterates through the RecentWriteQ queue to determine if the target block to be read exists in the queue. If the target block is in the queue, it means that the block is within the short post-write window, and the current read is highly likely to encounter bit errors caused by the IVS effect. At this time, the firmware immediately reads the current erase / write count (PE value) of the block and uses this PE value as an index to quickly look up the corresponding voltage compensation level in the offline lookup table established in step two, thereby determining the optimal compensation voltage to be applied.

[0038] Traditional read strategies use a default read threshold voltage, triggering ReadRetry for passive compensation only after a read error generates an err bit. However, within a short window after a write operation, the IVS effect combined with read interference causes the err bit to spike dramatically. Frequent retry not only severely degrades read performance but also negatively impacts the user experience in random read / write scenarios. This new step employs a dual judgment mechanism of "queue matching + PE table lookup" to accurately identify the scenarios requiring compensation before the read operation is executed and determine the optimal compensation level in one step, completely avoiding the passive mode of compensating after an error occurs.

[0039] In the above process, the embodiments of the present invention actively traverse the RecentWriteQ queue and locate the optimal compensation level by looking up the table in combination with the PE value when the read command arrives. This enables short-term read scenarios after write to be accurately identified and matched with the optimal compensation strategy before the read operation is executed. It provides an active read strategy of judgment first and compensation later, realizes early intervention in the IVS effect, and fundamentally avoids the decline in read performance caused by passive retry.

[0040] Step 140: After receiving the read command, traverse the most recently written queue and determine whether the target block of the read command is in the most recently written queue. If it is, find the corresponding voltage compensation level in the offline lookup table according to the current erase and write count of the target block, apply the voltage of the level to the target block and perform the read operation.

[0041] In one possible implementation, upon receiving a read command, the most recently written queue is traversed to determine if the object block to be read exists in the most recently written queue. If the object block is in the most recently written queue, the current erase / write count of the object block is obtained, and the corresponding initial voltage offset level is looked up in the offline lookup table based on the current erase / write count to determine the optimal voltage compensation level to be applied. The optimal voltage compensation level is then applied to the object block to perform the read operation.

[0042] In one possible implementation, if the object block of the read command is not in the recently written queue, the read operation is performed using data with a normal default read threshold voltage.

[0043] The optimal voltage compensation setting is used to eliminate the initial voltage offset effect and the associated read interference during read operations, thereby avoiding excessively high err bit due to the voltage offset effect.

[0044] Specifically, after determining the optimal voltage compensation level required for the target block, the firmware directly applies the corresponding voltage offset value to the block to perform read operations, instead of using the default read threshold. This compensation voltage counteracts the rightward bias of the threshold voltage caused by the IVS effect, while suppressing accompanying read interference risks, thereby keeping the errbit during read operations at an extremely low level and significantly reducing or even eliminating Read Retry triggers. For blocks not in the RecentWriteQ queue (i.e., blocks whose last write time exceeded 10 minutes), since their IVS effect has naturally decayed, the firmware directly uses the default read threshold voltage to perform read operations normally without additional compensation, ensuring that efficiency in normal read scenarios is not affected.

[0045] This design embodies the principle of on-demand compensation and precise policy implementation: compensation is only applied to blocks that are truly in the active period of the IVS effect, avoiding the unnecessary overhead of full compensation while ensuring read reliability in high-risk scenarios. Especially in applications with intensive random read and write operations, this strategy can significantly reduce performance fluctuations caused by frequent rereads, ensuring the stability of the user experience.

[0046] In the above process, the embodiments of the present invention apply the optimal voltage level to the Blocks in the queue and use the default read strategy for the Blocks outside the queue in a differentiated processing manner. This allows the IVS effect to be actively eliminated during the read operation and the potential for read interference to be suppressed simultaneously. This provides a dual-track read strategy that takes into account both read reliability and read efficiency, and achieves a significant reduction in err bit and ReadRetry count, especially ensuring the stability of read performance in random read and write scenarios.

[0047] Through the above process, this invention forms a closed-loop proactive defense mechanism of identification-table lookup-compensation by constructing a dynamic write queue to accurately capture short-term read scenarios after write, establishing an offline voltage compensation level table based on the erase / write count gradient, and actively matching the optimal compensation voltage and executing differentiated read strategies during read operations. Compared with existing technologies, it eliminates the need to wait for the err bit to be generated before passively rereading; instead, it completes the prediction and elimination of IVS effects before the read operation is executed, controlling the bit error rate at a low level from the source, significantly reducing the number of read retryes, and effectively solving the problems of existing technologies that cannot identify and compensate for short-term compound drift after write, frequent read retryes, and severely degraded random read / write performance.

[0048] In one exemplary embodiment, the method for reducing Nand bit error rate of the present invention is used to reduce the Nand bit error rate of a high-performance enterprise-grade solid-state drive (SSD). This SSD is mainly used for storage in a database server and has extremely high requirements for read / write latency and data reliability. The "recent write time" threshold is set to 10 minutes, and the voltage compensation level division standard for erase / write cycles (PE) is as follows: 0-M cycles correspond to level 1, M-2M cycles correspond to level 2, and >2M cycles correspond to level 3.

[0049] Figure 2 The flowchart illustrates the process of reducing Nand bit error rate, which may include the following steps: Step S1: Maintain a dynamically added and deleted recent write queue (RecentWriteQ).

[0050] Specifically, the SSD controller allocates a memory region in SRAM to maintain RecentWriteQ. Whenever the host issues a "write Block X" command and completes the write operation, the controller immediately adds the physical block number (LBA) of Block X to the tail of this queue.

[0051] Furthermore, the controller runs a periodic judgment task in the background (e.g., once per second) that iterates through all blocks in the queue and checks whether the "current time - last write time of the block" is greater than 10 minutes. If it is greater than 10 minutes, the block is determined to have exceeded the active window period of the IVS (Initial Voltage Shift) effect and is removed from the queue.

[0052] In the above process, the embodiments of the present invention construct a dynamically added and deleted recently written queue in SRAM and maintain its timeliness in real time, so that all blocks within the short-term window (10 minutes) after the write can be captured and marked in a timely manner, providing a lightweight and efficient short-term read after write scenario identification mechanism, and realizing accurate positioning of blocks during the active period of IVS effect.

[0053] Step S2: Construct an offline voltage compensation level table based on the number of erase / write cycles.

[0054] Specifically, during the aging test phase before the SSD leaves the factory, voltage scans are performed on Nand chips in different erase / write cycles (PE) ranges using offline statistical methods. The initial voltage offset is recorded, and the data is divided into three levels with the erase / write cycle count M as the gradient: Level 1 corresponds to PE cycles 0-M, Level 2 corresponds to M-2M, and Level 3 corresponds to >2M. Each level corresponds to a specific optimal voltage compensation value, and these mapping relationships are permanently stored in the firmware read-only storage area (ROM) of the SSD, forming an offline lookup table.

[0055] In the above process, the embodiments of the present invention establish a three-level offline voltage compensation comparison table with the number of erase / write cycles M as the gradient, so that Nand particles with different aging degrees can be matched with the optimal compensation voltage corresponding to their PE value. This provides a systematic and quantifiable basis for voltage compensation decision-making and realizes accurate graded compensation of IVS effect under different erase / write cycles.

[0056] Step S3: Read the queue matching and gear lookup table when the command arrives.

[0057] Specifically, when the host issues a "read Block Y" command, the SSD controller first checks if Block Y exists in the RecentWriteQ queue. If Block Y is in the queue (i.e., less than 10 minutes since the last write), the controller reads the current PE count of that block and looks up the corresponding voltage compensation level in the offline lookup table based on the PE value (e.g., level 2). If Block Y is not in the queue, it is determined that no special compensation is needed, and the default read process is directly entered.

[0058] In the above process, the embodiments of the present invention actively traverse the RecentWriteQ queue and locate the optimal compensation level by looking up the table in combination with the PE value when the read command arrives. This enables short-term read scenarios after write to be accurately identified and matched with the optimal compensation strategy before the read operation is executed. It provides an active read strategy of judgment before compensation and realizes early intervention in the IVS effect.

[0059] Step S4: Apply the optimal voltage setting to perform the read operation.

[0060] Specifically, if Block Y is in the queue, before sending a read command to the Nand Flash, the controller first applies the optimal voltage level obtained from the table lookup in step S3 (such as the voltage corresponding to level 2). After applying this compensation voltage, the standard read command operation is executed to read the data and perform ECC verification. If Block Y is not in the queue, no additional voltage is applied to the Nand, and the read operation is performed directly with the default read threshold voltage.

[0061] In the above process, the embodiments of the present invention apply the optimal voltage level to the Block within the queue and use the default read strategy for the Block outside the queue in a differentiated processing manner. This allows the IVS effect to be actively eliminated during the read operation and the potential for read interference to be suppressed simultaneously. This provides a dual-track read strategy that takes into account both read reliability and read efficiency, and achieves a significant reduction in err bit and ReadRetry count.

[0062] Through the above process, this embodiment of the invention demonstrates how, in enterprise-grade SSDs, a dynamic queuing mechanism can be used to accurately capture "high-risk" data blocks within 10 minutes of a write operation, and by combining this with an offline-calibrated PE-voltage mapping table, optimal compensation voltage can be proactively applied at the moment of reading. This process not only solves the bit error problem caused by short-term voltage drift after NAND Flash writes, but also avoids over-processing of inactive data through differentiated read strategies. Therefore, while ensuring high data reliability, it maximizes the read and write performance of the SSD, making it particularly suitable for latency-sensitive database applications.

[0063] The following are embodiments of the apparatus of the present invention, which can be used to execute the method for reducing Nand bit error rate involved in the present invention. For details not disclosed in the embodiments of the apparatus of the present invention, please refer to the method embodiments of the method for reducing Nand bit error rate involved in the present invention.

[0064] Please see Figure 3 This invention provides a device 800 for reducing Nand bit error rate.

[0065] The device 800 for reducing Nand bit error rate includes, but is not limited to: a recently written queue setting module 810, a recently written queue maintenance module 830, an offline lookup table construction module 850, and a voltage compensation and operation execution module 870.

[0066] The recently written queue setting module 810 is used to set a dynamically added and deleted recently written queue in SRAM or DRAM. Whenever a block is written within a set time period, it is added to the recently written queue.

[0067] The Recently Written Queue Maintenance Module 830 is used to check in real time whether the interval between each block in the Recently Written Queue and the last write exceeds the set time. If it does, the block is removed from the Recently Written Queue.

[0068] The offline lookup table construction module 850 is used to set the corresponding voltage compensation level with the set number of erase / write cycles as the gradient, and to count the initial voltage offset of Nand under different number of erase / write cycles to form an offline lookup table; the offline lookup table is used to map the optimal voltage compensation level corresponding to each erase / write cycle interval.

[0069] The voltage compensation and operation execution module 870 is used to traverse the most recently written queue after receiving a read command, determine whether the target block of the read command is in the most recently written queue, and if so, find the corresponding voltage compensation level in the offline lookup table according to the current erase and write count of the target block, apply the voltage of the level to the target block and perform the read operation.

[0070] It should be noted that the above embodiments for reducing Nand bit error rate are only illustrated by the division of the above functional modules. In actual applications, the above functions can be assigned to different functional modules as needed. That is, the internal structure of the device for reducing Nand bit error rate will be divided into different functional modules to complete all or part of the functions described above.

[0071] Furthermore, the embodiments of the apparatus for reducing Nand bit error rate and the method for reducing Nand bit error rate provided in the above embodiments belong to the same concept, and the specific way in which each module performs its operation has been described in detail in the method embodiments, and will not be repeated here.

[0072] Figure 4A schematic diagram of the structure of an electronic device according to an exemplary embodiment is shown.

[0073] It should be noted that this electronic device is merely an example adapted to the present invention and should not be construed as providing any limitation on the scope of use of the present invention. Furthermore, this electronic device should not be interpreted as requiring or depending on having... Figure 4 One or more components of the exemplary electronic device 2000 shown.

[0074] The hardware structure of electronic devices 2000 can vary significantly due to differences in configuration or performance, such as... Figure 4 As shown, the electronic device 2000 includes: a power supply 210, an interface 230, at least one memory 250, and at least one central processing unit (CPU) 270.

[0075] Specifically, power supply 210 is used to provide operating voltage for various hardware devices on electronic device 2000.

[0076] Interface 230 includes at least one wired or wireless network interface 231 for interacting with external devices. Of course, in other examples adapted to this invention, interface 230 may further include at least one serial-to-parallel conversion interface 233, at least one input / output interface 235, and at least one USB interface 237, etc. Figure 4 As shown, this does not constitute a specific limitation.

[0077] The memory 250 serves as a carrier for resource storage and can be a read-only memory, random access memory, disk, or optical disk, etc. The resources stored on it include the operating system 251, application programs 253, and data 255, etc., and the storage method can be temporary storage or permanent storage.

[0078] The operating system 251 is used to manage and control the various hardware devices and application programs 253 on the electronic device 2000, so as to enable the central processing unit 270 to perform calculations and processing on the massive data 255 in the memory 250. It can be Windows Server™, Mac OS X™, Unix™, Linux™, FreeBSD™, etc.

[0079] Application 253 is a computer-readable instruction based on operating system 251 that performs at least one specific task, and may include at least one module ( Figure 4 (Not shown), each module may contain computer-readable instructions for the electronic device 2000. For example, a device for reducing the Nand bit error rate can be considered as an application program 253 deployed on the electronic device 2000.

[0080] Data 255 may be signal information, etc., and is stored in memory 250.

[0081] The central processing unit 270 may include one or more processors and is configured to communicate with the memory 250 via at least one communication bus to read computer-readable instructions stored in the memory 250, thereby performing operations and processing on massive amounts of data 255 stored in the memory 250. For example, a method to reduce the Nand bit error rate can be implemented by having the central processing unit 270 read a series of computer-readable instructions stored in the memory 250.

[0082] Furthermore, the present invention can also be implemented through hardware circuits or a combination of hardware circuits and software. Therefore, the implementation of the present invention is not limited to any specific hardware circuit, software, or combination thereof.

[0083] Please see Figure 5 This invention provides an electronic device 4000, which may include: a desktop computer, a laptop computer, a server, etc., with sensor recognition capabilities.

[0084] exist Figure 5 In this context, the electronic device 4000 includes at least one processor 4001 and at least one memory 4003.

[0085] The data interaction between the processor 4001 and the memory 4003 can be achieved through at least one communication bus 4002. This communication bus 4002 may include a path for transmitting data between the processor 4001 and the memory 4003. The communication bus 4002 may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus, etc. The communication bus 4002 can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 5 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0086] Optionally, the electronic device 4000 may further include a transceiver 4004, which can be used for data interaction between the electronic device and other electronic devices, such as sending and / or receiving data. It should be noted that in practical applications, the transceiver 4004 is not limited to one type, and the structure of the electronic device 4000 does not constitute a limitation on the embodiments of the present invention.

[0087] Processor 4001 may be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. It can implement or execute the various exemplary logic blocks, modules, and circuits described in conjunction with the disclosure of this invention. Processor 4001 may also be a combination that implements computing functions, such as including one or more microprocessor combinations, a combination of a DSP and a microprocessor, etc.

[0088] The memory 4003 may be a ROM (Read Only Memory) or other type of static storage device capable of storing static information and instructions, RAM (Random Access Memory) or other type of dynamic storage device capable of storing information and instructions, or an EEPROM (Electrically Erasable Programmable Read Only Memory), CD-ROM (Compact Disc Read Only Memory) or other optical disc storage, optical disc storage (including compressed optical discs, laser discs, optical discs, digital universal optical discs, Blu-ray discs, etc.), magnetic disk storage media or other magnetic storage devices, or any other medium capable of carrying or storing desired program instructions or code in the form of instructions or data structures and accessible by the electronic device 4000, but not limited thereto.

[0089] The memory 4003 stores computer-readable instructions, and the processor 4001 can read the computer-readable instructions stored in the memory 4003 through the communication bus 4002.

[0090] The computer-readable instructions are executed by one or more processors 4001 to implement the methods for reducing the Nand bit error rate in the above embodiments.

[0091] Furthermore, this embodiment of the invention provides a storage medium storing computer-readable instructions that are executed by one or more processors to implement the method for reducing Nand bit error rate as described above.

[0092] This invention provides a computer program product including computer-readable instructions stored in a storage medium. One or more processors of an electronic device read the computer-readable instructions from the storage medium, load and execute the computer-readable instructions, thereby enabling the electronic device to implement the method for reducing Nand bit error rate as described above.

[0093] Compared with related technologies, the beneficial effects of the present invention are: 1. This invention can effectively eliminate the initial voltage shift (IVS) effect in the short term after writing to Nand chips, significantly reducing the number of err bits during read operations; by maintaining a dynamically added and deleted RecentWriteQ queue in SRAM or DRAM, the block number of data written within a certain period of time (e.g., 10 minutes) is recorded in real time, and the scenario of reading immediately after writing is accurately identified when the read command arrives, so as to apply the corresponding voltage level in advance for compensation, thereby avoiding bit flipping caused by the IVS effect from the source.

[0094] 2. This invention has a multi-level voltage adaptive compensation capability based on the erase / write cycle (PE) gradient, which can match the optimal compensation voltage for Nand particles with different aging levels. By pre-statistically compiling the optimal IVS voltage level table for Nand under different erase / write cycles, and forming an offline comparison table with the erase / write cycle as the gradient, the PE corresponds to different voltage levels in three intervals, thus realizing accurate graded compensation for particles with different aging levels.

[0095] 3. This invention can significantly reduce the number of Read Retry triggers, effectively avoiding severe performance degradation caused by frequent rereads; by determining the optimal compensation level based on queue matching and PE table lookup before the read operation is executed, and directly applying the voltage of that level to execute the read operation, the err bit is controlled at an extremely low level during the read operation, which is especially suitable for ensuring performance stability in random read and write scenarios.

[0096] 4. This invention features lightweight, low-overhead, on-demand compensation, which will not negatively impact the efficiency of conventional read scenarios. By applying the optimal voltage level only to blocks located in the RecentWriteQ queue, while using the default read threshold voltage to perform normal read operations on blocks outside the queue that have exceeded the set time, a differentiated dual-track read strategy is achieved. This ensures read reliability during the active period of the IVS effect and avoids the unnecessary overhead of full compensation.

[0097] 5. This invention can solve the fundamental defect of existing technologies that cannot identify short-term composite drift after writing in advance, especially in high-erasure-write-cycle chips; by changing the problem of short-term composite drift of IVS effect and read interference from "passive response" to "active prevention", it overcomes the shortcomings of existing technologies that do not consider the scenario of immediate read after writing and only target the scenario of long-term retention, so that the number of err bits appearing on the disk as a whole is significantly less than that of existing solutions.

[0098] It should be understood that although the steps in the flowcharts of the accompanying figures are shown sequentially as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the accompanying figures may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times, and their execution order is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the sub-steps or stages of other steps.

[0099] The above description is only a partial embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A method for reducing Nand bit error rate, characterized in that, The method includes: Set up a dynamically added and deleted recent write queue in SRAM or DRAM, and add the block to the recent write queue whenever it is written within a set time period; The system checks in real time whether the interval between each block in the most recently written queue and the last write exceeds the set time. If it does, the block is removed from the most recently written queue. The voltage compensation level is set according to the set number of erase / write cycles, and the initial voltage offset of Nand under different number of erase / write cycles is statistically analyzed to form an offline comparison table; the offline comparison table is used to map the optimal voltage compensation level corresponding to each erase / write cycle interval. Upon receiving a read command, the system iterates through the most recently written queue and determines whether the target block of the read command is in the most recently written queue. If it is, the system finds the corresponding voltage compensation level in the offline lookup table based on the current number of erases and writes of the target block, and applies the voltage of the specified level to the target block to perform the read operation.

2. The method for reducing Nand bit error rate as described in claim 1, characterized in that, The step of setting up a dynamically added and deleted recently written queue in SRAM or DRAM, whereby a block is added to the recently written queue whenever it has been written within a set time period, includes: Maintain a dynamically added and deleted recently written queue in SRAM or DRAM; the recently written queue is used to record the block number of data that has been written within a certain period of time in real time; Whenever a block is written to, the block number of that block is added to the most recently written queue to ensure that all blocks that complete the write operation within the set time period are recorded in a timely manner.

3. The method for reducing Nand bit error rate as described in claim 1, characterized in that, The real-time check of whether the interval between the last write and the last write of each block in the most recently written queue exceeds the set time, and if it does, removing the block from the most recently written queue, includes: The system checks in real time whether the interval between the last write and the last write of each block in the recently written queue has exceeded the set time. If the interval between the last write and the last write of a block has exceeded the set time, the block is removed from the recently written queue. The removal is used to retain only blocks that have been written within the set time.

4. The method for reducing Nand bit error rate as described in claim 1, characterized in that, The method involves setting corresponding voltage compensation levels based on a set number of erase / write cycles, statistically analyzing the initial voltage offset of the Nand at different erase / write cycles, and generating an offline comparison table, including: A gradient is set based on the upper limit of the number of erase / write cycles of the Nand, and multiple voltage compensation levels are divided according to the gradient. The initial voltage offset corresponding to the number of erase / write cycles of the block is calculated offline to form an offline lookup table. The offline lookup table is used to select the optimal voltage compensation level based on the current number of erase / write cycles.

5. The method for reducing Nand bit error rate as described in claim 1, characterized in that, Upon receiving a read command, the system iterates through the most recently written queue to determine if the target block for the read command is in the queue. If it is, it finds the corresponding voltage compensation level in the offline lookup table based on the current erase / write count of the target block, including: Upon receiving a read command, the most recently written queue is traversed to determine whether the object block to be read by the read command exists in the most recently written queue. If the object block is located in the most recently written queue, the current erase / write count of the object block is obtained, and the corresponding initial voltage offset level is found in the offline lookup table based on the current erase / write count to determine the optimal voltage compensation level to be applied.

6. The method for reducing Nand bit error rate as described in claim 1, characterized in that, The step of applying the voltage of the specified level to the object block to perform a read operation includes: The optimal voltage compensation level is applied to the object block to perform a read operation; the optimal voltage compensation level is used to eliminate the initial voltage offset effect and the accompanying read interference during the read operation, thereby avoiding excessively high err bit caused by the voltage offset effect.

7. The method for reducing Nand bit error rate as described in claim 1, characterized in that, The method further includes: If the target block of the read command is not in the most recently written queue, the read operation is performed using data with a normal default read threshold voltage.

8. An apparatus for reducing Nand bit error rate, characterized in that, The device includes: The recently written queue setting module is used to set a dynamically added and deleted recently written queue in SRAM or DRAM. Whenever a block is written within a set time period, it is added to the recently written queue. The recently written queue maintenance module is used to check in real time whether the interval between each block in the recently written queue and the last write exceeds the set time. If it exceeds the set time, the block is removed from the recently written queue. The offline lookup table construction module is used to set the corresponding voltage compensation level with a set number of erase / write cycles as a gradient, and to count the initial voltage offset of Nand under different number of erase / write cycles to form an offline lookup table; the offline lookup table is used to map the optimal voltage compensation level corresponding to each erase / write cycle interval. The voltage compensation and operation execution module is used to traverse the most recently written queue after receiving a read command, determine whether the target block of the read command is in the most recently written queue, and if so, find the corresponding voltage compensation level in the offline lookup table according to the current erase and write count of the target block, and apply the voltage of the specified level to the target block to perform the read operation.

9. An electronic device, characterized in that, include: At least one processor and at least one memory, wherein, The memory stores computer-readable instructions; The computer-readable instructions are executed by one or more of the processors, causing the electronic device to implement the method for reducing the Nand bit error rate as described in any one of claims 1 to 7.

10. A storage medium having computer-readable instructions stored thereon, characterized in that, The computer-readable instructions are executed by one or more processors to implement the method for reducing the Nand bit error rate as described in any one of claims 1 to 7.

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