Memory management methods, memory controllers, and computer program products

Abstract

This disclosure provides a memory management method, memory controller, and computer program product based on valid count tracking. In response to an update operation of the logical-to-physical address mapping table, the memory controller in the memory device decrements the valid count of old memory cells and increments the valid count of new memory cells. When the valid count of an old memory cell reaches zero, a release enable bit is set. In response to a synchronization operation and with the release enable bit active, multiple memory cells are traversed to search for a target memory cell with a valid count of zero and a statically marked "full" state. This target cell is then released to the free pool, and the release enable bit is cleared. Thus, the memory controller tracks valid count changes in real time within the existing mapping table update process and utilizes synchronization operations to batch release invalid memory cells that meet both conditions, thereby reducing the frequency of garbage collection and improving the overall performance of the memory device.

Description

Technical Field

[0001] This disclosure relates to the field of data storage technology, and in particular to a control technology for tracking changes in the effective count of memory cells and releasing invalid memory cells in batches based on the timing of mapping table updates in non-volatile memory devices, a memory management method, a memory controller, and a computer program product. Background Technology

[0002] In non-volatile storage devices, as data is continuously written, a large number of storage cells containing some valid data and some invalid data accumulate in the memory module. Existing technologies typically rely on garbage collection operations to reclaim this physical space.

[0003] However, when all valid data in a storage cell is updated to other locations due to subsequent writes, its valid count drops to zero, but the memory controller does not actively detect this state change. These storage cells with zero valid counts continue to occupy physical space until garbage collection identifies and reclaims them during the scanning phase. This reduces the actual usable capacity of the free pool and increases the frequency of garbage collection triggers.

[0004] Furthermore, attempting to proactively detect and release storage units with valid counts reaching zero can easily conflict with ongoing garbage collection operations. For example, during data migration during garbage collection, the valid count of a source storage unit may drop to zero due to a mapping table update. Releasing it at this time would duplicate the garbage collection's own release process, posing a risk to data consistency. Therefore, how to track changes in valid counts in real time with low overhead within the existing mapping table update process and safely release invalid storage units in batches at appropriate times is a pressing technical challenge in this field. Summary of the Invention

[0005] In view of this, this disclosure provides a memory management method, memory controller, and computer program product based on effective count tracking, so that the memory controller can track the effective count changes of memory cells in real time in response to the update operation of the logical-to-physical address mapping table, set a release enable bit as a trigger flag for batch processing when the effective count is detected to be zero, and traverse and search for target memory cells that simultaneously meet the dual conditions of an effective count of zero and a static flag indicating a full state during the synchronization operation phase, and release them in batches to the free pool, thereby timely reclaiming invalid memory cells without increasing additional scanning overhead, so as to solve the problem of untimely reclamation of invalid memory cells in the prior art and improve the write performance of the memory device.

[0006] According to one aspect of this disclosure, a memory management method based on effective count tracking is provided, applicable to a storage device configured with a memory controller and a memory module, wherein the memory module includes multiple storage cells, each storage cell having a corresponding effective count and a static flag. The method includes: in response to a mapping table update operation, performing a decrement operation on the effective count of the old storage cells involved in the update operation, and performing an increment operation on the effective count of the new storage cells; if the effective count of the old storage cells is decremented to zero, setting a release enable bit; in response to a synchronization operation and with the release enable bit in a valid state, traversing multiple storage cells, searching for one or more target storage cells, wherein the target storage cells have an effective count of zero and a static flag indicating a full state; releasing the target storage cells to a free pool and clearing the release enable bit.

[0007] According to another aspect of this disclosure, a memory controller is provided, suitable for a storage device configured with a memory module and a connection interface circuit. The memory module includes multiple storage cells, each storage cell having a corresponding valid count and a static flag. The connection interface circuit is electrically connected to a host system. The memory controller includes a buffer memory, a memory interface control circuit, and a processor. The memory interface control circuit is electrically connected to the memory module. The processor is electrically connected to the connection interface circuit, the memory interface control circuit, and the buffer memory, wherein the processor is configured to: in response to a mapping table update operation, perform a decrement operation on the valid count of the old storage cells involved in the update operation, and perform an increment operation on the valid count of the new storage cells; if the valid count of the old storage cells is decremented to zero, set a release enable bit; in response to a synchronization operation and with the release enable bit in a valid state, traverse multiple storage cells and search for one or more target storage cells, wherein the valid count of the target storage cells is zero and the static flag indicates that the storage cells are full; release the target storage cells to a free pool and clear the release enable bit.

[0008] According to another aspect of this disclosure, a computer program product is provided, comprising a computer program that, when loaded and executed by a memory controller of a storage device, causes the memory controller to perform the memory management method described above.

[0009] Based on the above, the memory management method, memory controller, and computer program product based on valid count tracking provided in this disclosure perform real-time decrementing and incrementing of the valid count during the update operation of the logic-to-physical address mapping table, thereby monitoring the status of memory cells with extremely low overhead in existing processes. When the valid count is detected to be zero, a release enable bit is set, accumulating scattered trigger events for unified processing during the synchronization operation phase. During the synchronization operation phase, the target memory cell is searched using the dual conditions of a zero valid count and a static flag indicating a full state, which not only excludes memory cells that are not yet full but also effectively avoids release conflicts with garbage collection operations. Thus, this disclosure can reclaim invalid memory cells in a timely and safe manner before garbage collection operations are triggered, increasing the available capacity of the free pool, thereby reducing the trigger frequency of garbage collection and improving the overall performance of the storage device. Attached Figure Description

[0010] Figure 1A This is a system architecture block diagram of the host system and storage device shown according to embodiments of the present disclosure;

[0011] Figure 1B This is a schematic diagram of an effective counter table and a release enable bit shown according to an embodiment of the present disclosure;

[0012] Figure 2 This is a main flowchart of a memory management method according to an embodiment of the present disclosure;

[0013] Figure 3 A flowchart illustrating waste recycling conflict avoidance according to embodiments of this disclosure;

[0014] Figure 4 A flowchart illustrating two effective count update paths for a trimming instruction according to embodiments of this disclosure;

[0015] Figure 5 This is a schematic diagram illustrating the dynamic adjustment of the search range according to embodiments of the present disclosure;

[0016] Figure 6 A flowchart illustrating a post-release erasure strategy according to embodiments of the present disclosure;

[0017] Figure 7 This is a flowchart illustrating the effective counting threshold prediction according to embodiments of the present disclosure;

[0018] Figure 8 A flowchart illustrating abnormal power failure protection according to an embodiment of this disclosure;

[0019] Figure 9 This is a schematic diagram illustrating batch threshold control and synchronization frequency adaptation according to embodiments of the present disclosure;

[0020] Figure 10 This is a timing diagram of component interactions from host write to synchronous release, as shown in an embodiment of the present disclosure. Detailed Implementation

[0021] Reference will now be made in detail to exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same component reference numerals are used in the drawings and description to denote the same or similar parts.

[0022] Figure 1A This is a block diagram illustrating a host system and storage device according to embodiments of the present disclosure. Please refer to... Figure 1A The host system 10 is, for example, a personal computer, a laptop computer, or a server. The host system 10 includes a processor 110 (also called a second processor), host memory 120 (also called host RAM), and a data transfer interface circuit 130. In this embodiment, the processor 110 is electrically connected (also called coupled) to the host memory 120 and the data transfer interface circuit 130. In another embodiment, the processor 110, host memory 120, and data transfer interface circuit 130 are electrically connected to each other via a system bus. In this embodiment, the processor 110, host memory 120, and data transfer interface circuit 130 may be mounted on the motherboard of the host system 10.

[0023] The storage device 20 includes a memory controller 210, a memory module 220 (also known as a rewritable non-volatile memory module), and a connection interface circuit 230. The memory controller 210 includes a processor 211 (also known as a first processor), a data management circuit 212, a memory interface control circuit 213, and a buffer memory 214.

[0024] In this embodiment, the host system 10 is electrically connected to the storage device 20 via a data transmission interface circuit 130 and a connection interface circuit 230 to perform data access operations. For example, the host system 10 can store data to or read data from the storage device 20 via the data transmission interface circuit 130.

[0025] In this embodiment, the number of data transmission interface circuits 130 can be one or more. Through the data transmission interface circuits 130, the motherboard can be electrically connected to the storage device 20 via wired or wireless means. The storage device 20 can be, for example, a USB flash drive, memory card, solid-state drive (SSD), or wireless storage device. The wireless storage device can be, for example, a Near Field Communication (NFC) storage device, a WiFi storage device, a Bluetooth storage device, or a Bluetooth Low Energy storage device (e.g., iBeacon), or other storage devices based on various wireless communication technologies. Furthermore, the motherboard can also be electrically connected via the system bus to various I / O devices such as a Global Positioning System (GPS) module, network interface card, wireless transmission device, keyboard, screen, and speaker.

[0026] In this embodiment, the data transmission interface circuit 130 and the connection interface circuit 230 are interface circuits compatible with the Peripheral Component Interconnect Express (PCI Express) standard. Furthermore, the data transmission interface circuit 130 and the connection interface circuit 230 transmit data using the Non-Volatile Memory Express (NVMe) communication protocol.

[0027] In this embodiment, the connection interface circuit 230 maintains a command queue to cache read commands, write commands, and trim commands sent by the host system 10 via the data transmission interface circuit 130. The processor 211 determines whether the host interface is idle by monitoring the status of the command queue of the connection interface circuit 230. When the command queue of the connection interface circuit 230 is empty, it indicates that the host system 10 currently has no commands to process, and the processor 211 can use this idle period to perform delayed valid count updates or background pre-erasure operations.

[0028] In this embodiment, the connection interface circuit 230 serves as the communication interface between the storage device 20 and the host system 10, and can also be referred to as the "host interface". The connection interface circuit 230 maintains a command queue to cache read commands, write commands, and trim commands sent by the host system 10 via the data transmission interface circuit 130. The processor 211 determines whether the host interface is idle by monitoring the status of the command queue of the connection interface circuit 230. When the command queue of the connection interface circuit 230 is empty, it indicates that the host system 10 currently has no commands to process, and the processor 211 can use this idle period to perform delayed valid count updates or background pre-erasure operations. In the following description of the embodiments, "the command queue of the host interface" refers to the command queue maintained by the connection interface circuit 230.

[0029] In another embodiment, the connection interface circuit 230 may be packaged in a chip with the memory controller 210, or the connection interface circuit 230 may be disposed outside a chip containing the memory controller 210.

[0030] In this embodiment, the host memory 120 is used to temporarily store instructions or data executed by the processor 110. In this embodiment, the host memory 120 may be Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), etc. However, it should be understood that this disclosure is not limited to this, and the host memory 120 may also be other suitable memories.

[0031] The memory controller 210 is used to execute multiple logic gates or control instructions implemented in hardware or firmware, and to perform operations such as writing, reading and erasing data in the memory module 220 according to the instructions of the host system 10, and to execute the memory management method provided in this disclosure.

[0032] More specifically, the processor 211 in the memory controller 210 is hardware with computing capabilities, used to control the overall operation of the memory controller 210. Specifically, the processor 211 is programmed by multiple control instructions / codes, and these control instructions / codes are executed when the storage device 20 is operating to perform operations such as writing, reading, and erasing data.

[0033] Furthermore, the processor 211 is configured to execute the memory management method provided in this disclosure. Specifically, in response to an update operation of the logical-to-physical address mapping table, the processor 211 performs a decrement operation on the valid count (VC) of the old memory cell 321 involved in the update operation and an increment operation on the valid count of the new memory cell 322, determines whether the valid count of the old memory cell 321 is zero, and if it is zero, sets a release enable bit 310 in the buffer memory 214; in response to a synchronization operation and the release enable bit 310 being valid, the processor 211 traverses multiple memory cells in the valid count table 300, searches for one or more target memory cells 330 whose valid count is zero and whose static flag indicates that they are full, releases the target memory cell 330 to the free pool 340, and clears the release enable bit 310.

[0034] It is worth mentioning that, in this embodiment, the processor 110 and the processor 211 are, for example, a central processing unit (CPU), a microprocessor, or other programmable processing units (microprocessor), digital signal processor (DSP), programmable controller, application specific integrated circuits (ASIC), programmable logic device (PLD), or other similar circuit components, and this disclosure is not limited thereto.

[0035] In this embodiment, as described above, the memory controller 210 further includes a data management circuit 212 and a memory interface control circuit 213. It should be noted that the operations performed by each component of the memory controller 210 can also be considered as operations performed by the memory controller 210 itself.

[0036] The data management circuit 212 is electrically connected to the processor 211, the memory interface control circuit 213, and the connection interface circuit 230. The data management circuit 212 receives instructions from the processor 211 to perform data transfer. For example, it reads data from the host system 10 (e.g., host memory 120) via the connection interface circuit 230 and writes the read data to the memory module 220 via the memory interface control circuit 213. Alternatively, it performs a read operation based on a read instruction from the host system 10, reading data from one or more physical units of the memory module 220 via the memory interface control circuit 213 and writing the read data to the host system 10 via the connection interface circuit 230. In one embodiment, when the processor 211 performs a mapping table update operation, the data management circuit 212 reads page table entries from the memory module 220 to the buffer memory 214 via the memory interface control circuit 213. The processor 211 then calculates the physical addresses of the old memory unit 321 and the new memory unit 322 and updates the corresponding valid counts in the valid count table 300.

[0037] In another embodiment, the data management circuit 212 may also be integrated into the processor 211. The memory interface control circuit 213 is used to receive instructions from the processor 211 and cooperate with the data management circuit 212 to perform write (also known as programming) operations, read operations, or erase operations on the memory module 220.

[0038] Furthermore, data to be written to memory module 220 is converted into a format acceptable to memory module 220 via memory interface control circuit 213. Specifically, if processor 211 needs to access memory module 220, processor 211 transmits a corresponding instruction sequence to memory interface control circuit 213 to instruct memory interface control circuit 213 to perform the corresponding operation. For example, these instruction sequences may include write instruction sequences indicating the writing of data, read instruction sequences indicating the reading of data, erase instruction sequences indicating the erasure of data, and corresponding instruction sequences for indicating various memory operations. These instruction sequences may include one or more signals, or data on the bus. These signals or data may include instruction codes or codes. For example, a read instruction sequence may include information such as the read identification code, memory address, and physical address.

[0039] Furthermore, the memory controller 210 establishes a logical-to-physical address mapping table and a physical-to-logic address mapping table to record the mapping relationship between the logical addresses of logical units (e.g., logical blocks, logical pages) and the physical addresses (physical addresses) of physical units (e.g., physical erase units / physical blocks, physical pages) configured for the memory module 220. In other words, the memory controller 210 can use the logical-to-physical address mapping table (also called the logical-to-physical mapping table) to find the physical unit mapped to a logical unit (e.g., find the physical page mapped to a logical page; find the logical address mapped to a logical address), and the memory controller 210 can use the physical-to-logic address mapping table (also called the physical-to-logical mapping table) to find the logical unit mapped to a physical unit (e.g., find the logical page mapped to a physical page; find the logical address mapped to a physical address).

[0040] Buffer memory 214 is electrically connected to processor 211 and is used to temporarily store data and instructions from host system 10, data from memory module 220, and various system data for managing storage device 20. In this embodiment, buffer memory 214 is also used to store valid count table 300 and release enable bit 310 required by this disclosure. Valid count table 300 records the valid counts and static flags of each of the multiple storage cells 320 in memory module 220, and its specific structure will be referred to... Figure 1B Please provide an explanation.

[0041] The memory module 220 is electrically connected to the memory controller 210 (specifically, electrically connected to the memory interface control circuit 213) and is used to store user data sent by the host system 10. In this disclosure, the memory module 220 serves as the management object of multiple storage units 320 carrying user data. Each storage unit 320 has a corresponding valid count and static flag. The memory controller 210 identifies and releases invalid storage units whose valid count has reached zero and are full by tracking changes in the valid count.

[0042] In one embodiment, the memory cell structure of the memory module 220 can be understood as a multi-layered physical organization architecture. Specifically, the memory module 220 includes multiple chips, each chip has multiple planes, and each plane contains multiple physical blocks, each physical block consisting of multiple physical pages. It should be noted that this disclosure is not limited to the specific size of each physical page and logical page.

[0043] Please refer to Figure 1BThe memory controller 210 maintains a valid count table 300 in its buffer memory 214. The valid count table 300 records the status information of each of the multiple storage units 320 in the memory module 220.

[0044] Specifically, each entry in the valid count table 300 corresponds to a storage unit and includes three basic fields: storage unit identifier, valid count, and static flag. For example... Figure 1B As shown in the dashed box, the effective count table 300 may also optionally include a candidate tag field, the specific use of which will be explained in subsequent embodiments.

[0045] The valid count indicates the number of currently valid data entries in the storage unit. When the host system 10 writes new data, causing an update to the logical-to-physical address mapping table, the valid count of the old storage unit 321 is decremented, and the valid count of the new storage unit 322 is incremented. A static flag indicates whether the storage unit is in a full state. When all pages of the storage unit have been written to, the static flag is set to full (i.e., 1); when the storage unit is not yet full or is being moved by a garbage collection operation, the static flag is set to not full (i.e., 0).

[0046] by Figure 1B Taking the effective count table 300 as an example, storage cell B has an effective count of 0 and a static flag of 1 (full). This means that storage cell 330 meets the dual conditions of an effective count of zero and a static flag indicating a full state, and can be released to the free pool 340 during the synchronization operation phase. In contrast, although storage cell C also has an effective count of 0, its static flag is 0 (not full), indicating that the storage cell may not yet be full or is being moved by garbage collection operations, and therefore does not meet the release conditions.

[0047] In one embodiment, the valid count table 300 further includes a candidate flag field. The candidate flag is used to make the candidate flag of the old memory cell 321 valid when the valid count of the old memory cell 321 drops to zero after a decrement operation, so that the subsequent traversal search phase only scans memory cells with valid candidate flags, thereby narrowing the search range and improving search efficiency.

[0048] In one embodiment, the valid count table 300 is entirely stored in the buffer memory 214. During each mapping table update operation, the processor 211 decrements or increments the valid count of the corresponding entry in the valid count table 300. The update of the valid count table 300 is synchronized with the update of the logical-to-physical address mapping table, ensuring that the valid count recorded in the valid count table 300 remains consistent with the actual valid data state of each storage unit in the memory module 220. During normal operation of the storage device 20, the valid count table 300 resides in the buffer memory 214 for fast read / write access by the processor 211, without requiring access to the memory module 220 via the memory interface control circuit 213.

[0049] The buffer memory 214 also stores a release enable bit 310. The release enable bit 310 is a global flag bit. When the processor 211 detects that the valid count of any old memory cell 321 has dropped to zero during a mapping table update, it sets the release enable bit 310 to an active state (e.g., ...). Figure 1B (As shown by the middle arrow A11). Releasing enable bit 310 serves as the trigger condition for whether to perform a traversal search during the synchronization operation phase, avoiding unnecessary traversal operations when there are no valid memory cell counts reaching zero.

[0050] Based on the above Figure 1A and Figure 1B The system architecture and valid count table structure shown are illustrated. The processor in the memory controller maintains a valid count table in the buffer memory to record the valid count and static mark of each memory cell. The release enable bit is used as the condition to trigger the traversal search in the synchronization operation phase, providing a data foundation and hardware support for the valid count tracking and batch release of invalid memory cells during subsequent mapping table updates.

[0051] Reference Figure 2 In one embodiment, the processor 211 of the memory controller 210 performs the following operations to manage the release of a plurality of memory cells 320 in the memory module 220.

[0052] In step S210, in response to the update operation of the logical-to-physical address mapping table, the processor 211 performs a decrement operation on the valid count of the old memory cell 321 involved in the update operation, and performs an increment operation on the valid count of the new memory cell 322 involved in the update operation.

[0053] Specifically, in one embodiment, when the host system 10 writes new data to the storage device 20, the memory controller 210 writes the new data to the new storage cell 322 and updates the logical-to-physical address mapping table to remap the corresponding logical address from the old storage cell 321 to the new storage cell 322. During this mapping table update process, the processor 211 reads the valid count of the old storage cell 321 from the valid count table 300 in the buffer memory 214 and decrements it by one, while simultaneously reading the valid count of the new storage cell 322 and incrementing it by one.

[0054] The following example illustrates the change in the valid count. Assume that storage unit B has a capacity of 4 data entries, and currently there are 3 valid data entries stored in storage unit B, i.e., the valid count is 3 and the static flag is full.

[0055] When the host system 10 sends three write commands sequentially, writing new data to other storage units to replace the three old data entries in storage unit B, each mapping table update causes the effective count of storage unit B to decrease by one. After the first write, the effective count of storage unit B decreases from 3 to 2; after the second write, it decreases from 2 to 1; and after the third write, it decreases from 1 to 0. After the third decrease is complete, the processor 211 detects that the effective count of storage unit B is zero, that is, it determines "yes" in step S220, and then sets the release enable bit 310 in step S230. At this time, although storage unit B still physically stores data, this data has been invalidated due to subsequent write operations, and storage unit B becomes a candidate object that can be released.

[0056] Furthermore, during the mapping table update process in step S210, the physical address corresponding to the old storage unit 321 or the new storage unit 322 may be invalid. An invalid physical address indicates that there is no valid data corresponding to that logical block address in the memory module 220, or that no valid data has been written to that logical block address. In this case, the processor 211 does not perform a decrement or increment operation on the valid count for the storage unit corresponding to the invalid physical address; that is, the decrement operation on the old storage unit 321 and the increment operation on the new storage unit 322 are independent of each other, depending on whether their corresponding physical addresses are valid. Specifically, if the physical address of the old storage unit 321 is invalid, it means that the logical block address was not mapped to any storage unit before this write operation. The processor 211 only increments the valid count of the new storage unit 322 and does not decrement it. If the physical address of the new storage unit 322 is invalid, it means that this operation only invalidates the old data and does not write new data (such as the mapping table update caused by the pruning operation). The processor 211 only decrements the valid count of the old storage unit 321 and does not increment it.

[0057] The following examples illustrate the two scenarios. In the first scenario, assume that host system 10 writes new data to a logical block address that has not been previously written to. Since this logical block address was not originally mapped to any memory unit in the mapping table (i.e., the physical address of the old memory unit 321 is invalid), processor 211 writes the new data to the new memory unit 322 and updates the mapping table so that the logical block address is mapped to the new memory unit 322. The processor only increments the valid count of the new memory unit 322 by one (e.g., from 2 to 3) and does not perform a decrement operation. In the second scenario, assuming a logical block address was originally mapped to old memory cell 321 and the effective count of old memory cell 321 is 3, when the host system 10 sends a pruning instruction to invalidate the data at that logical block address, since no new data is written in this operation (i.e., the physical address of the new memory cell 322 is invalid), the processor 211 updates the mapping table to mark the physical address corresponding to that logical block address as invalid, and only decrements the effective count of old memory cell 321 by one (e.g., from 3 to 2), without performing an increment operation; the specific process of updating the effective count involved in the pruning instruction will be discussed later. Figure 4 The embodiments are described in detail.

[0058] In step S220, the processor 211 determines whether the valid count of the old storage unit 321 is zero after the decrement operation. A valid count of zero indicates that there is no valid data in the old storage unit 321, that is, all the data originally stored in the old storage unit 321 has been updated to other storage units due to subsequent write operations.

[0059] In step S230, if the valid count of the old memory cell 321 is zero (step S220 determines "yes"), the processor 211 sets the release enable bit 310 in the buffer memory 214. The release enable bit 310 serves as a global flag, indicating that in subsequent synchronization operations, there is at least one memory cell with a valid count of zero awaiting search and release. If the valid count of the old memory cell 321 is not zero (step S220 determines "no"), the release enable bit 310 is not set, and the release operation is completed.

[0060] During the synchronization operation phase (such as) Figure 2 (As shown below the dashed dividing line), in response to the synchronization operation and the release enable bit 310 being in an active state, the processor 211 executes steps S240 and S250.

[0061] In step S240, the processor 211 traverses the multiple storage cells 320 recorded in the effective count table 300 in the buffer memory 214 and searches for one or more target storage cells 330 that simultaneously meet the following dual conditions: the effective count is zero and the static flag indicates that it is full.

[0062] A valid count of zero indicates that the storage unit contains no valid data; a static flag indicates a full state, meaning that all pages of the storage unit have been written and are not being moved by garbage collection. Based on these two conditions, the processor 211 excludes storage units that are not yet full and source storage units that are being moved by garbage collection, ensuring that only truly invalid and safe storage units are included in the release scope.

[0063] The following example illustrates the filtering process of the traversal search. Suppose that in a certain synchronization operation, the effective count table 300 records the following storage units: storage unit A has an effective count of 3 and is statically marked as full; storage unit B has an effective count of 0 and is statically marked as full; storage unit C has an effective count of 0 and is statically marked as not full; and storage unit D has an effective count of 7 and is statically marked as full.

[0064] Processor 211 evaluates each of the aforementioned storage units based on two conditions: Storage unit A is excluded because its effective count is not zero; Storage unit B has a zero effective count and its static flag indicates it is full, satisfying both conditions, and is therefore identified as target storage unit 330; Storage unit C, although having a zero effective count, is excluded because its static flag indicates it is not full (potentially a storage unit that is not yet full or a source storage unit being moved by garbage collection), not satisfying both conditions; Storage unit D is excluded because its effective count is not zero. Ultimately, processor 211 releases only storage unit B as target storage unit 330 to the free pool 340.

[0065] Furthermore, the multiple storage units 320 traversed by the processor 211 in step S240 are storage units (e.g., DataUnit) in the memory module 220 used to store user data. In addition to storage units for user data, the memory module 220 also includes storage units (e.g., TableUnit) for storing system management data such as logic-to-physical address mapping tables. When traversing and searching for the target storage unit 330, the processor 211 only performs the search within the range of storage units used to store user data, and does not perform effective count tracking and release operations on storage units storing system management data.

[0066] In step S250, the processor 211 releases one or more target memory cells 330 found to the free pool 340 and clears the release enable bit 310. As a result, the physical space occupied by the target memory cells 330 is returned to the free pool 340 for subsequent write operations, and the clearing of the release enable bit 310 avoids unnecessary repeated traversal in subsequent synchronization operations.

[0067] Based on the above Figure 2The process shown tracks changes in the effective count of memory cells in a timely manner with low overhead during the update operation of the logical-to-physical address mapping table. When the effective count is detected to be zero, the accumulated trigger flag is triggered by releasing the enable bit. Batch search and release are performed uniformly during the synchronization operation phase, thereby reclaiming invalid memory cells before the garbage collection operation is triggered, increasing the available capacity of the free pool, and reducing the trigger frequency of the garbage collection operation.

[0068] Reference Figure 3 In one embodiment, when Figure 2 The mapping table update operation shown originates from the data movement of the source storage unit during the garbage collection operation. The processor 211 of the memory controller 210 processes the data according to the following process to avoid conflicts between the release operation and the garbage collection operation.

[0069] In step S310, before the garbage collection operation begins moving valid data from the source storage unit, the processor 211 sets the static flag of the source storage unit in the valid count table 300 to an incomplete state. Therefore, even if the valid count of the source storage unit drops to zero during subsequent mapping table updates, Figure 2 In the traversal search of step S240, the source storage unit does not meet the dual conditions (the effective count is zero and the static mark indicates that it is full) because it is statically marked as not full. Therefore, it will not be mistakenly identified as the target storage unit 330 and will be released.

[0070] The necessity of this conflict avoidance mechanism is illustrated below with a specific example. Suppose that the garbage collection operation selects storage unit E as the source storage unit for data migration, and storage unit E currently has a valid count of 2 and is statically marked as full.

[0071] If step S310 is not executed, that is, if the static flag of storage unit E is not set to the unfilled state beforehand, then after the garbage collection operation moves the two valid data in storage unit E and completes the mapping table update, the valid count of storage unit E drops to zero. At this time, storage unit E simultaneously satisfies the dual conditions that the valid count is zero and the static flag indicates that it is in the full state.

[0072] If the traversal search during the synchronization operation phase identifies storage unit E as the target storage unit 330 and performs its release, and the garbage collection operation also performs its release on storage unit E, the same storage unit will be released repeatedly, resulting in duplicate entries in the free pool 340 and raising the risk of inconsistency in subsequent data writes. By pre-setting the static mark of storage unit E to an unfilled state in step S310, the traversal search phase automatically excludes storage unit E because it does not meet the static mark condition, and the garbage collection operation itself is responsible for releasing storage unit E, thus avoiding the aforementioned conflict.

[0073] In step S320, the processor 211 moves the remaining valid data in the source memory cell to other memory cells via the memory interface control circuit 213. During the moving process, for each piece of valid data moved, the processor 211 updates the logical-to-physical address mapping table to remap the corresponding logical address from the source memory cell to other memory cells.

[0074] In step S330, processor 211, in response to the mapping table update in step S320, performs a decrement operation on the valid count of the source storage cell. As the data transfer proceeds step by step, each valid data transfer triggers a mapping table update that causes the valid count of the source storage cell to decrease by one.

[0075] In step S340, processor 211 determines whether the valid count of the source storage unit has dropped to zero. The valid count of the source storage unit is zero once the garbage collection operation has moved all valid data from the source storage unit.

[0076] In step S350, even if the valid count of the source memory cell is zero after the decrement operation (step S340 determines "yes"), the processor 211 does not set the release enable bit 310. This is related to... Figure 2 The processing method of step S230 is compared: Figure 2 In the normal mapping table update process, the release enable bit 310 is triggered when the valid count reaches zero. However, when the mapping table update originates from a garbage collection operation, since the release of the source storage unit is handled by the garbage collection operation itself, the processor 211 does not set the release enable bit 310 to avoid performing repeated release operations on the source storage unit during subsequent synchronization operations. If the valid count of the source storage unit has not yet dropped to zero (step S340 determines "No"), it means that there is still valid data to be moved in the garbage collection operation. The process does not set the release enable bit 310, and the source storage unit is automatically released after the garbage collection operation completes all data movement.

[0077] If step S340 determines whether the result is "yes" or "no", the source storage units are released by the garbage collection operation's own process, rather than by... Figure 2 The synchronous operation phase shown is released.

[0078] Based on the above Figure 3 The process shown involves setting the static flag of the source storage unit to an unfilled state before moving valid data during garbage collection, so that the traversal search in the synchronization operation phase automatically excludes the source storage unit; at the same time, the mapping table update originating from garbage collection does not set the release enable bit even if it causes the valid count to return to zero, thus avoiding the conflict between the release operation and the garbage collection operation at both the flag level and the trigger level.

[0079] Reference Figure 4In one embodiment, except Figure 2 In addition to the mapping table update operation shown, when the processor 211 of the memory controller 210 receives the trim command sent by the host system 10, it also performs an update operation on the valid count of the memory cells involved in the trim command.

[0080] In step S410, the processor 211 receives a trimming command sent by the host system 10.

[0081] In step S420, the processor 211 determines whether the amount of data involved in the pruning instruction is less than the preset page table entry capacity. The preset page table entry capacity is the number of mapping relationships recorded in a single page table entry in the logical-to-physical address mapping table.

[0082] In one embodiment, a single page table entry records 1024 mappings between logical block addresses and physical addresses, thus the preset page table entry capacity is 1024. This determination is used to distinguish between small-scale pruning and large-scale pruning scenarios, and to select different effective count update strategies accordingly.

[0083] If the amount of data involved in the trimming instruction is less than the preset page table entry capacity (step S420 determines "yes"), in step S430, the processor 211 updates the effective count of the memory cells involved in the trimming instruction one by one.

[0084] Specifically, for each logical block address identified by the trim instruction, the processor 211 searches for the corresponding memory unit in the effective count table 300 and decrements its effective count by one. Since the amount of data is small, the overhead of updating each block is controllable, and the processor 211 performs the update immediately upon receiving the trim instruction.

[0085] If the amount of data involved in the trimming instruction is greater than or equal to the preset page table entry capacity (step S420 determines "No"), in step S440, the processor 211 does not immediately execute the valid count update operation. Instead, it only executes the valid count update of the memory cells involved in the trimming instruction when the command queue of the host interface (e.g., connection interface circuit 230) is empty. Since a large number of logical block addresses are involved in the large-scale trimming, if the updates are performed one by one immediately after receiving the trimming instruction, it will occupy the processor 211's computing resources for a long time and block the processing of subsequent instructions in the command queue. Therefore, the processor 211 waits for the command queue to be empty before performing the update in a concentrated manner, utilizing the idle time of the host interface to process the valid count update generated by the large-scale trimming, thus avoiding affecting the responsiveness of the storage device 20 to subsequent instructions from the host system 10.

[0086] After the valid count update is completed in step S430 or step S440, the process is merged into step S450.

[0087] In step S450, the processor 211 determines whether there are any memory cells whose valid count has dropped to zero after the update.

[0088] In step S460, if there is a memory cell with a valid count of zero (step S450 determines "yes"), processor 211 sets release enable bit 310, enabling subsequent synchronization operation phases to search for and release the memory cell. If there is no memory cell with a valid count of zero (step S450 determines "no"), release enable bit 310 is not set, and the trimming instruction processing is completed.

[0089] Based on the above Figure 4 The process shown includes the inclusion of logical block address invalidation caused by pruning instructions within the scope of effective counting and tracking, ensuring that invalid storage units generated by operations such as file deletion can be identified in a timely manner and released during subsequent synchronization operations. Furthermore, for pruning scenarios where the data volume is greater than or equal to the preset page table entry capacity, a strategy of delaying updates until the command queue is empty is adopted to avoid blocking the command queue from processing subsequent instructions.

[0090] Reference Figure 5 In one embodiment, in Figure 2 In step S240, when the processor 211 traverses multiple memory units 320 to search for the target memory unit 330, the traversal range is dynamically adjusted according to the number of free memory units in the free pool 340.

[0091] like Figure 5 As shown by the middle arrow A51, when the number of free storage units in the free pool 340 is lower than a preset space threshold, the processor 211 traverses the entire range of multiple storage units 320 in the memory module 220 (as shown in region B51).

[0092] Specifically, processor 211 scans the valid count table 300 for entries covering all chip enable groups (CE), that is, all chip enable groups from CE0 to CEn are included in the traversal range. When the free pool 340 is insufficient, a full range traversal can search for as many target memory units 330 as possible that meet the dual conditions to supplement the available capacity of the free pool 340.

[0093] like Figure 5 As shown by the middle arrow A52, when the number of free storage units in the free pool 340 is greater than or equal to a preset space threshold, the processor 211 only traverses the chip enable group or channel range where the old storage unit 321 is located (as shown in region B52).

[0094] Specifically, the processor 211 determines the chip enable group to which the old memory unit 321 belongs based on its physical address, and only scans the entries corresponding to that chip enable group in the valid count table 300. When the free pool 340 has sufficient margin, a local range traversal is used to narrow the search range and reduce the time overhead of the traversal operation.

[0095] In another embodiment, the processor 211 further narrows down the actual scan target by utilizing candidate tags within the dynamically adjusted traversal range described above. Specifically, the effective count table 300 in the buffer memory 214 records candidate tags in addition to recording the effective count and static tag for each memory cell.

[0096] exist Figure 2 In step S210, when the effective count of the old memory cell 321 drops to zero after the decrement operation, the processor 211 sets the candidate flag of the old memory cell 321 in the effective count table 300 to be valid.

[0097] exist Figure 2 In step S240, when traversing and searching the target memory unit 330, the processor 211 only scans the memory units in the valid count table 300 that are candidate-marked as valid, and skips the memory units that are candidate-marked as invalid. That is, within the dynamically adjusted traversal range (the entire range or a partial range), the candidate marks are used as a second layer of filtering conditions, so that the processor 211 does not need to check the valid count and static marks item by item, but directly locates the memory unit where the known valid count has been zero, further reducing the time overhead of traversal and search.

[0098] Based on the above Figure 5 The dynamic adjustment mechanism and candidate marking acceleration mechanism shown expand the search range to reclaim more invalid storage units when the free pool is insufficient, and narrow the search range to reduce traversal overhead when the free pool is sufficient. Within the defined traversal range, only storage units marked as valid by candidates are scanned to further shorten the search time.

[0099] Reference Figure 6 In one embodiment, Figure 2 In step S250, when the target storage unit 330 is released to the free pool 340, the processor 211 of the memory controller 210 adopts a delayed erase strategy and optionally cooperates with a background pre-erasure mechanism.

[0100] In step S610, the processor 211 marks one or more target memory cells 330 as free and adds them to the free pool 340 without performing an erase operation on the one or more target memory cells 330. That is, only a logical-level release (changing the state flag and registering with the free pool) is performed, instead of immediately performing an erase operation on the corresponding physical storage space in the memory module 220. Therefore, the execution time of step S610 is not affected by the time consumed by the erase operation, and the release operation can be completed quickly.

[0101] In step S640 of the left branch, in response to a subsequent write operation retrieving one or more target memory units 330 from the free pool 340, the processor 211 performs an erase operation on the retrieved memory unit via the memory interface control circuit 213 and then writes the data. That is, the erase operation is postponed until the moment when the memory unit is actually needed, avoiding a large number of erase operations being performed in a concentrated manner during the release phase.

[0102] In one embodiment, in the right branch, the processor 211 further executes a background pre-erasure mechanism to preemptively clear unerased memory cells in the free pool 340. In step S620, the processor 211 determines whether the number of free memory cells in the free pool 340 is lower than a first threshold.

[0103] In step S625, processor 211 determines whether the command queue of the host interface is empty. When the number of free storage units in the free pool 340 is lower than the first threshold and the command queue is empty (both steps S620 and S625 determine "yes"), processor 211 performs a background pre-erasure operation on the storage units in the free pool 340 that have not yet been erased in step S630.

[0104] In one embodiment, if the number of free storage units in the free pool 340 is not less than the first threshold or the command queue is not empty (step S620 or step S625 determines "no"), then the background pre-erasure operation is not performed and the pre-erasure process ends.

[0105] In step S635, the processor 211 continuously monitors the number of free storage units in the free pool 340 during the background pre-erasure operation.

[0106] In one embodiment, when the number of free storage units is higher than the second threshold (step S635 determines "yes"), the processor 211 pauses the background pre-erasure operation, and the pre-erasure process ends. When the number of free storage units is not higher than the second threshold (step S635 determines "no"), the processor 211 continues to perform the background pre-erasure operation until the number of free storage units is higher than the second threshold.

[0107] In one embodiment, the second threshold is greater than or equal to the first threshold. By setting the first threshold for initiating the background pre-erasure operation and the second threshold for pausing the background pre-erasure operation to different values, a hysteresis interval is formed between the first threshold and the second threshold. This allows the background pre-erasure operation to continue executing after initiation until the number of free storage units rises back above the second threshold, thus avoiding frequent start and stop of the background pre-erasure operation when the number of free storage units fluctuates around the first threshold.

[0108] In one embodiment, the first threshold is 20% of the total capacity of the free pool, and the second threshold is 50% of the total capacity of the free pool. When the number of free storage units drops from more than 20% to less than 20%, the background pre-erasure operation is started and paused until the number of free storage units rises back to more than 50%, ensuring that a sufficient number of storage units can be pre-erased after each start for subsequent write operations.

[0109] Based on the above Figure 6 The process shown in the diagram only performs logical release without erasing during the release phase, reducing the time consumption of the release operation itself; erasing is only performed when subsequent write operations retrieve the data, distributing the erasure overhead to the write time; background pre-erasure is actively performed when the free pool is insufficient and the host interface is idle to prepare available storage units in advance, and pre-erasure is paused after the free pool is restored to a level higher than the second threshold to release memory bus resources.

[0110] It should be noted that the command queue involved in the aforementioned background pre-erasure mechanism is the command queue maintained by the connection interface circuit 230. In response to the number of free memory cells in the free pool 340 being lower than a first threshold and the command queue of the connection interface circuit 230 being empty, the processor 211 performs a background pre-erasure operation on the memory cells in the free pool 340 that have not yet been erased. This configuration also applies to device embodiments primarily based on the memory controller 210.

[0111] Reference Figure 7 In one embodiment, the processor 211 of the memory controller 210, in addition to performing synchronous operations, Figure 2 In addition to the traversal search shown, active migration and release operations are also performed on memory cells whose effective count is close to zero but has not yet returned to zero.

[0112] In step S710, the processor 211 determines whether there is a near-empty storage cell 350 among the multiple storage cells 320 in the memory module 220 that simultaneously meets the following conditions: the effective count is less than or equal to a preset effective count threshold, and a static flag indicates that it is full. The preset effective count threshold is used to determine whether the amount of residual effective data in the storage cell is small enough that the overhead of active migration is lower than the critical value of the expected benefit of waiting for it to naturally return to zero. If there is no near-empty storage cell 350 that meets the conditions (step S710 determines "no"), then no subsequent operation is performed, and the near-empty storage cell is released.

[0113] In step S720, if a near-empty memory cell 350 exists that meets the conditions (step S710 determines "yes"), the processor 211 sets the static flag of the near-empty memory cell 350 to an incomplete state. This operation is similar to... Figure 3 The practice of pre-setting static markers in step S310 is consistent with the garbage collection operation, ensuring that the near-empty storage unit 350 will not be mistakenly identified as the target storage unit 330 in subsequent traversal searches because the static marker is still in a full state.

[0114] In step S730, during the synchronization operation, the processor 211 migrates the remaining valid data in the nearly empty storage unit 350 to other storage units. As each piece of valid data is migrated, the logical-to-physical address mapping table is updated accordingly, and the valid count of the nearly empty storage unit 350 gradually decreases.

[0115] In step S740, after all the remaining valid data in the near-empty storage unit 350 has been migrated, the valid count of the near-empty storage unit 350 drops to zero, and the processor 211 releases the near-empty storage unit 350 to the free pool 340, thus completing the release of the near-empty storage unit.

[0116] The following example illustrates the difference in overhead between the above-mentioned effective count threshold prediction mechanism and traditional garbage collection operations. Assume that storage unit F has a capacity of 256 data entries, the current effective count is 2, and it is statically marked as full, meaning that only 2 valid data entries remain in storage unit F, and the remaining 254 data entries are invalid. If traditional garbage collection operations were to process storage unit F, the garbage collection operation would need to select a source storage unit from memory module 220, move the valid data, erase the source storage unit, and update the mapping table. Its scheduling and execution involve the entire garbage collection process. However, using the above-mentioned effective count threshold prediction mechanism, processor 211 only needs to migrate the remaining 2 valid data entries in storage unit F to other storage units during synchronization operations. After the migration is completed, the effective count of storage unit F drops to zero, and it can be released to the free pool 340. The amount of data moved is only a small fraction of the total amount of valid data moved from the source storage unit in traditional garbage collection operations.

[0117] Based on the above Figure 7 The process shown proactively performs a small amount of data migration on storage units whose effective count is close to zero but has not yet naturally reached zero, so that they are released to the free pool in advance, further increasing the available capacity of the free pool and reducing the amount of data that needs to be moved in subsequent garbage collection operations.

[0118] Reference Figure 8 In one embodiment, the processor 211 of the memory controller 210 executes... Figure 2 During the release operation in step S250, a log recording and power-on replay mechanism is used to deal with abnormal power outage scenarios.

[0119] In step S810, before releasing one or more target storage units 330 to the free pool 340, the processor 211 writes the identifiers of the one or more target storage units 330 to be released into the system reserved area of ​​the memory module 220 as a release log 360. The release log 360 records a list of identifiers of the one or more target storage units 330 to be released in the current batch and stores it in the system reserved area to ensure that it can still be read after an abnormal power failure.

[0120] In step S820, the processor 211 performs a release operation, releasing one or more target storage units 330 to the free pool 340.

[0121] In step S830, it is determined whether an abnormal power outage occurred during the release operation. If no abnormal power outage occurred (step S830 determines "no"), the release operation is completed normally.

[0122] In step S840, if an abnormal power failure occurs during the execution of the release operation (step S830 determines "yes"), when the storage device 20 is powered on and restored, the processor 211 reads the release log 360 from the system reserved area of ​​the memory module 220 and replays the release operation according to the target storage unit identifier recorded in the release log 360.

[0123] Therefore, even if an abnormal power outage causes the release operation of some target storage units 330 to fail to complete, the processor 211 can still resume the execution of the release operation according to the release log 360 after power is restored, ensuring that one or more target storage units 330 are correctly released to the free pool 340 and the release operation is completed.

[0124] In another embodiment, the memory controller 210 uses a power-on rebuild method instead of a release log method to deal with abnormal power outages.

[0125] Specifically, in one embodiment, during the power-on initialization phase, the processor 211 scans the actual data status of all storage units 320 in the memory module 220, reconstructs the valid count table 300 in the buffer memory 214 based on the actual number of valid data entries in each storage unit, and reconstructs static markers based on whether each storage unit is full. After reconstruction, the valid count table 300 reflects the current true state of the memory module 220, and the processor 211 performs traversal search and release operations normally in subsequent synchronization operations without relying on the release log 360. This method eliminates the need to write logs before release, reducing the write overhead of the normal operation path, but the scan time during the power-on initialization phase increases with the capacity of the memory module 220.

[0126] Based on the above Figure 8 The two embodiments shown have different approaches. The release log method persists the release flag before release, enabling rapid replay recovery after an abnormal power outage. The power-on reconstruction method reconstructs the valid count table by fully scanning the memory module, so that the normal operation path does not need to be written to the log. Both are suitable for application scenarios that have high requirements for power-on recovery speed or are sensitive to the writing overhead of the normal operation path.

[0127] Reference Figure 9 In one embodiment, the processor 211 of the memory controller 210... Figure 2 The valid count zeroing events detected in step S220 are accumulated and monitored for frequency, so as to control the timing of setting the release enable bit 310 and the execution frequency of the synchronization operation.

[0128] like Figure 9 As shown on the left, a valid count reset counter 370 is maintained in buffer memory 214. Whenever the valid count of old memory cell 321 drops to zero after a decrement operation (as shown by arrow A90), processor 211 increments the value of valid count reset counter 370.

[0129] In one embodiment, when the value of the valid count zeroing counter 370 reaches a preset batch threshold, the processor 211 sets the release enable bit 310 and resets the valid count zeroing counter 370. This combines multiple scattered valid count zeroing events into a single batch trigger, avoiding frequent traversal searches during the synchronization operation phase caused by immediately setting the release enable bit 310 each time a valid count reaches zero.

[0130] like Figure 9 As shown on the right, the processor 211 simultaneously monitors the frequency of events where the effective count drops to zero per unit time, and dynamically adjusts the execution frequency of the synchronization operation accordingly.

[0131] As shown by arrow A91 and area B91, when the event frequency is higher than the first frequency threshold, it indicates that the effective data replacement of the storage cells in the memory module 220 is dense, and the storage cells with effective counts of zero accumulate rapidly. The processor 211 increases the execution frequency of the synchronization operation to shorten the interval between synchronization operations, so that the target storage cell 330 that meets the release conditions can be searched and released in a timely manner.

[0132] As shown by arrow A92 and area B92, when the event frequency is lower than the second frequency threshold, it indicates that the effective data replacement of the storage cells in the memory module 220 is sparse. The processor 211 reduces the execution frequency of the synchronization operation to lengthen the interval between synchronization operations and reduce unnecessary traversal operation overhead.

[0133] In one embodiment, the event frequency is the value obtained by the processor 211 counting events whose effective count drops to zero within a preset statistical time window, and the execution frequency of the synchronization operation is the number of times the synchronization operation is triggered per unit time. The processor 211 limits the execution frequency of the synchronization operation to a preset minimum execution frequency and a preset maximum execution frequency: when the event frequency is higher than a first frequency threshold, the processor 211 increases the execution frequency by a preset adjustment step, but does not exceed the maximum execution frequency; when the event frequency is lower than a second frequency threshold, the processor 211 decreases the execution frequency by an adjustment step, but does not fall below the minimum execution frequency. The first frequency threshold is greater than the second frequency threshold; when the event frequency is between the second frequency threshold and the first frequency threshold, the processor 211 maintains the execution frequency of the synchronization operation unchanged, thereby forming a hysteresis interval between the second frequency threshold and the first frequency threshold, avoiding frequent rises and falls of the execution frequency near the threshold. In another embodiment, the processor 211 can also adjust the increase or decrease of the execution frequency proportionally based on the difference between the event frequency and the first frequency threshold or the second frequency threshold.

[0134] Based on the above Figure 9 The mechanism shown combines batch threshold control into batch processing to reduce traversal frequency, while adaptive synchronization frequency dynamically adjusts the traversal timing based on the density of events. The two work together to match the execution rhythm of the release operation with the actual replacement rate of valid data in the memory module.

[0135] Reference Figure 10 In one embodiment, the host system 10, processor 211, buffer memory 214 and memory module 220 interact according to the following timing sequence to complete the entire process from map table update to batch release.

[0136] During the mapping table update phase (such as...) Figure 10 (As shown to the left of the dashed dividing line), the host system 10 sends a write command to the storage device 20 (step S1011).

[0137] After receiving the write command, the processor 211 writes the new data into the new storage unit 322 in the memory module 220 and sends a valid count update instruction to the buffer memory 214 to perform a decrement operation on the valid count of the old storage unit 321 and an increment operation on the valid count of the new storage unit 322 (step S1012).

[0138] The processor 211 then determines whether the effective count of the old memory cell 321 has dropped to zero after the decrement operation (step S1013).

[0139] If the valid count of the old memory cell 321 is zero, the processor 211 writes the release enable bit 310 to the buffer memory 214 and sets it to the valid state (step S1014).

[0140] During the synchronous release phase (e.g.) Figure 10 (As shown to the right of the dashed dividing line), when the synchronization operation is triggered, the processor 211 checks whether the release enable bit 310 in the buffer memory 214 is in a valid state (step S1021).

[0141] If the release enable bit 310 is valid, the processor 211 sends a traversal search instruction to the buffer memory 214 to scan the valid count table 300 to search for memory cells with a valid count of zero and a static marker indicating that they are full (step S1022).

[0142] The buffer memory 214 returns the identifier of the target memory cell 330 that meets the dual conditions to the processor 211. The processor 211 then sends a release command to the memory module 220 via the memory interface control circuit 213 to release one or more target memory cells 330 to the free pool 340 (step S1023).

[0143] After the release is completed, the processor 211 writes an instruction to the buffer memory 214 to clear the release enable bit 310 (step S1024), so that subsequent synchronization operations will no longer perform traversal search when there is no new valid count zeroing event.

[0144] Based on the above Figure 10 The timing interaction shown is as follows: during the mapping table update phase, the timely tracking of valid counts and the setting of the release enable bit are completed. During the synchronous release phase, the traversal search and batch release are completed under the triggering of the release enable bit. The two phases are decoupled in time and connected in logic through the release enable bit, so that the release operation does not block the normal execution of the mapping table update.

[0145] In another embodiment, when Figure 2In step S240, when the processor 211 finds multiple target memory cells 330 that simultaneously satisfy the condition that the effective count is zero and the static flag indicates that the state is full, the processor 211 further determines the release order based on the number of erases of each target memory cell 330.

[0146] Specifically, the memory controller 210 maintains a record of the erase counts for each memory cell 320. The processor 211 sorts the multiple target memory cells 330 found in the search according to their erase counts from low to high, and prioritizes releasing the target memory cells 330 with lower erase counts to the free pool 340. Since subsequent write operations use a first-in-first-out order when retrieving memory cells from the free pool 340, memory cells with lower erase counts will be prioritized and erased before being written. This allows memory cells with longer remaining erase lifetimes to undertake more subsequent write operations, while memory cells with higher erase counts are retrieved later. This makes the erase counts of each memory cell 320 in the memory module 220 tend to be balanced, extending the overall lifespan of the storage device 20.

[0147] It should be noted that although this disclosure has been presented above with reference to embodiments, it is not intended to limit this disclosure. Any person skilled in the art can make some modifications and refinements without departing from the spirit and scope of this disclosure. For example, the preset batch threshold, preset effective count threshold, preset space threshold, first frequency threshold, second frequency threshold, first threshold, and second threshold parameters in the above embodiments are only illustrative settings. Persons skilled in the art can adjust the above thresholds to other appropriate values ​​or adopt a dynamic adjustment strategy based on factors such as the capacity of the memory module, the number of memory units, the write load characteristics of the host system, and the triggering strategy of garbage collection operations.

[0148] Furthermore, the above embodiments use storage units as the management granularity for effective counting, tracking, and release. However, this disclosure is not limited to a specific management granularity. Storage units may correspond to physical blocks, superblocks, or other appropriate storage management units. Those skilled in the art can select a suitable management granularity based on the physical organization of the memory module.

[0149] The above embodiments use a solid-state drive based on NAND flash memory as an example for illustration, but this disclosure is not limited to a specific type of non-volatile storage device. This disclosure is also applicable to storage devices that use other non-volatile storage media and have similar mapping table update and garbage collection mechanisms.

[0150] Therefore, the scope of protection of this disclosure shall be determined by the scope defined in the appended claims.

[0151] In another embodiment, this disclosure also provides a computer program product comprising a computer program that, when loaded and executed by a memory controller of a storage device, causes the memory controller to perform the aforementioned memory management method, including: decrementing the effective count of old memory cells and incrementing the effective count of new memory cells in response to an update operation of a logical-to-physical address mapping table; determining whether the effective count of the old memory cells is zero; setting a release enable bit if it is zero; traversing a plurality of memory cells in response to a synchronization operation and with the release enable bit active, searching for one or more target memory cells with an effective count of zero and a statically marked state indicating that they are full; and releasing one or more target memory cells to a free pool and clearing the release enable bit. This computer program is stored, for example, in a read-only memory (ROM), flash memory, hard disk drive, compact disc, or similar storage medium, and this disclosure is not limited thereto.

[0152] In summary, the memory management method, memory controller, and computer program product based on effective count tracking provided in this disclosure enable the memory controller to monitor the effective data status of memory cells in real time with minimal overhead by synchronously executing the decrement and increment of the effective count during the update operation of the logic-to-physical address mapping table. By introducing a release enable bit mechanism, this disclosure accumulates scattered effective count zeroing events into the synchronization operation stage for batch processing, and combines static marking to exclude source memory cells being moved by garbage collection operations. This core mechanism not only avoids the system overhead of frequent traversals, but also fundamentally avoids the conflict between release operations and garbage collection operations, enabling the storage device to reclaim invalid physical space in a timely manner before garbage collection is triggered, significantly improving the available capacity of the free pool and overall write performance.

[0153] Furthermore, this disclosure provides multi-dimensional optimized implementations for different operating scenarios. In trimming instruction processing, a delayed update strategy based on data volume is adopted, effectively avoiding the blocking of the host command queue by a large number of trimming operations. At the release execution level, a strategy combining logical release and delayed erasure is adopted, supplemented by a background pre-erasure mechanism based on the free pool level, smoothly distributing the erasure overhead to system idle periods. Regarding search efficiency, by dynamically adjusting the traversal range (the entire range or a local chip enable group) based on the free pool remaining capacity and using candidate tags for precise filtering, the search time for target storage units is significantly shortened.

[0154] Furthermore, this disclosure also features a high degree of intelligence and reliability. By dynamically and adaptively adjusting the execution frequency of synchronization operations by monitoring the frequency of events where the effective count reaches zero, it ensures a perfect match between the management rhythm and the actual data replacement rate. For near-empty storage cells with extremely low effective counts but not yet zero, a threshold prediction and proactive migration mechanism (mini-GC) is introduced to release the entire physical space in advance with minimal relocation costs. Finally, by writing release logs to the system reserved area, it provides comprehensive protection against abnormal power outages for batch release operations, ensuring data consistency and system stability after power-on recovery. This disclosure comprehensively and systematically reconstructs the invalid space reclamation logic of non-volatile storage devices.

[0155] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory management method applicable to a storage device configured with a memory controller and a memory module, wherein the memory module includes multiple storage cells, each storage cell having a corresponding valid count and a static tag, characterized in that, The method includes: In response to a mapping table update operation, a decrement operation is performed on the valid count of the old storage cell involved in the update operation, and an increment operation is performed on the valid count of the new storage cell; If the effective count of the old memory cell decreases to zero, set the release enable bit; In response to a synchronization operation and with the release enable bit in an active state, the plurality of memory cells are traversed to search for one or more target memory cells, wherein the active count of the target memory cells is zero and the static flag indicates a memory cell that is full. Release the target storage unit to the free pool and clear the release enable bit.

2. The memory management method according to claim 1, characterized in that, The method, in response to a mapping table update operation, includes: When the update operation originates from a garbage collection operation that moves data from the source storage unit, and the old storage unit is the source storage unit, the static flag of the source storage unit is set to an unwritten state before the data is moved by the garbage collection operation; and Even if the valid count of the source memory cell is zero after the decrement operation, the release enable bit is not set.

3. The memory management method according to claim 1, characterized in that, The method further includes: In response to a pruning command, update the valid count of the memory cell involved in the pruning command; If the valid count of the updated storage cell is zero, set the release enable bit.

4. The memory management method according to claim 3, characterized in that, The method further includes: When the amount of data involved in the pruning instruction is greater than or equal to the preset page table entry capacity, in response to the host interface command queue being empty, the step of updating the effective count of the storage unit involved in the pruning instruction is executed.

5. The memory management method according to claim 1, characterized in that, The method of releasing the one or more target storage units to the free pool includes: Mark the one or more target storage units as free and add them to the free pool, without performing an erase operation on the one or more target storage units; and In response to a subsequent write operation, when one or more target storage units are retrieved from the free pool, an erase operation is performed and then data is written.

6. The memory management method according to claim 5, characterized in that, The method further includes: In response to the number of free storage units in the free pool falling below a first threshold and the command queue of the host interface being empty, a background pre-erasure operation is performed on the storage units in the free pool that have not yet been erased; and In response to the number of free storage units exceeding a second threshold, the background pre-erasure operation is suspended.

7. The memory management method according to claim 1, characterized in that, The method of traversing the plurality of storage units and searching for the one or more target storage units includes: When the number of free storage units in the free pool is lower than a preset space threshold, the entire range of the plurality of storage units is traversed. When the number of free storage units in the free pool is greater than or equal to the preset space threshold, only the chip enable group or channel range where the old storage unit is located is traversed.

8. The memory management method according to claim 7, characterized in that: The memory controller maintains a valid count table in its buffer memory, which records the valid count, static flag, and candidate flag for each of the plurality of memory cells. In response to the old memory cell's valid count becoming zero after the decrement operation, the candidate flag of the old memory cell in the valid count table is set to valid; as well as In the step of traversing the plurality of storage cells to search for the one or more target storage cells, only the storage cells marked as valid in the valid count table are scanned.

9. The memory management method according to claim 1, characterized in that, The step of setting the release enable bit if the effective count of the old memory cell is zero includes: In response to the valid count of the old memory cell being zero, increment the valid count reset counter; and In response to the value of the effective count zeroing counter reaching a preset batch threshold, the release enable bit is set and the effective count zeroing counter is reset.

10. The memory management method according to claim 9, characterized in that, The method further includes: The frequency of events in which the effective count drops to zero within a unit of time; In response to the event frequency exceeding a first frequency threshold, the execution frequency of the synchronization operation is increased; and In response to the event frequency falling below a second frequency threshold, the execution frequency of the synchronization operation is reduced.

11. The memory management method according to claim 1, characterized in that, The method further includes: Determine whether there exists a near-empty storage cell among the plurality of storage cells whose effective count is less than or equal to a preset effective count threshold and whose static flag indicates that it is full. Set the static flag of the near-empty memory cell to an incomplete state; and During the synchronization operation, the remaining valid data in the near-empty storage unit is migrated to other storage units, and after the valid count of the near-empty storage unit is reduced to zero, the near-empty storage unit is released to the free pool.

12. The memory management method according to claim 1, characterized in that, Before releasing the target storage unit to the free pool, the method further includes: Write the identifier of the target storage unit to be released into the system reserved area of ​​the memory module as a release log; and In response to power restoration after an abnormal power outage, the release log is read, and the release operation is replayed based on the release log.

13. A memory controller suitable for a storage device configured with a memory module and a connection interface circuit, the memory module comprising a plurality of storage cells, each storage cell having a corresponding valid count and a static tag, the connection interface circuit being used for electrical connection to a host system, characterized in that, The memory controller includes: Buffer memory; A memory interface control circuit, for electrically connecting to the memory module; and A processor electrically connected to the connection interface circuit, the memory interface control circuit, and the buffer memory, wherein the processor is configured to: In response to a mapping table update operation, a decrement operation is performed on the valid count of the old storage cell involved in the update operation, and an increment operation is performed on the valid count of the new storage cell; If the effective count of the old memory cell decreases to zero, set the release enable bit; In response to a synchronization operation and with the release enable bit in an active state, the plurality of memory cells are traversed to search for one or more target memory cells, wherein the active count of the target memory cells is zero and the static flag indicates a memory cell that is full. Release the target storage unit to the free pool and clear the release enable bit.

14. The memory controller according to claim 13, characterized in that: When the update operation originates from the data migration of the source storage unit by the garbage collection operation, and the old storage unit is the source storage unit, the static flag of the source storage unit is set to an unfilled state before the data migration by the garbage collection operation. as well as Even if the valid count of the source memory cell is zero after the decrement operation, the processor does not set the release enable bit.

15. The memory controller according to claim 13, characterized in that, The processor is also configured to: In response to the number of free storage units in the free pool being lower than a first threshold and the command queue of the connection interface circuit being empty, a background pre-erasure operation is performed on the storage units in the free pool that have not yet been erased.

16. A computer program product, comprising a computer program, characterized in that, When the computer program is loaded and executed by the memory controller of the storage device, the memory controller performs the following steps: In response to a mapping table update operation, a decrement operation is performed on the valid count of the old storage cell involved in the update operation, and an increment operation is performed on the valid count of the new storage cell, wherein the storage device is configured with the memory controller and the memory module, the memory module including a plurality of storage cells, each storage cell having a corresponding valid count and a static tag; If the effective count of the old memory cell decreases to zero, set the release enable bit; In response to a synchronization operation and with the release enable bit in an active state, the plurality of memory cells are traversed to search for one or more target memory cells, wherein the active count of the target memory cells is zero and the static flag indicates a memory cell that is full. Release the target storage unit to the free pool and clear the release enable bit.

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