Display control chip

Abstract

This application discloses a control chip for a display, belonging to the field of digital signal transmission. The aim is to effectively adjust various clock delays to appropriate parameters for subsequent data processing. The aforementioned display control chip is used to connect to a transistor-to-transistor logic circuit red-green-blue (TTL RGB) interface bus. Its key feature is that it includes a delay period calculation circuit for calculating the delay period of the aforementioned TTL RGB interface bus. The TTL RGB interface bus includes a clock signal circuit and multiple data signal circuits. The delay period calculation circuit detects signal flips in the multiple data signal circuits corresponding to multiple delay levels and selects the intermediate delay level among the multiple delay levels where no signal flips occur as the delay period of the clock signal circuit.

Description

Technical Field

[0001] This application belongs to the field of digital signal transmission and relates to a logic circuit that automatically adjusts the signal reception timing during transistor-transistor logic (TTL) transmission. Background Technology

[0002] Transistor-Transistor Logic (TTL) circuits are a common and widely used type of logic digital integrated circuit. TTL circuits are manufactured using bipolar technology and are characterized by high speed and a wide variety of types.

[0003] Thin-film transistor liquid crystal displays (TFT-LCDs) have many available interface options for driving and controlling them, one of which is called the TTL-RGB interface. The TTL interface transmits data in parallel, superimposing the changes in the red (R), green (G), and blue (B) color channels together for output. The RGB data signal output by the main control chip is directly transmitted to the input interface of the LCD panel. Therefore, it is also called the RGB interface. Display data is not written to DDRAM but directly to the screen. This interface is widely used in small and medium-sized displays. It is fast and often used for displaying video or animation.

[0004] Each RGB interface includes several types of signals: VS (Vertical Synchronization), a vertical synchronization signal for synchronizing pixel column data on the display; HS (Horizontal Synchronization), a horizontal synchronization signal for synchronizing pixel row data; CLK (Clock), a clock signal for synchronizing data; DE (Data Enable), a data enable signal for confirming the accuracy of data transmission; and multiple data signals for the red, green, and blue color channels.

[0005] Because there are so many data signal circuits, each with different line lengths, but only one clock signal to indicate the sampling timing of each data signal, not all data signals are in a stable period available for sampling when the clock signal is on its rising edge. If it's during a signal transition period, incorrect signals may be sampled. Especially when the receiver module needs to connect to many different types of modules, it must be customized to change the sampling timing of the signal after the frequency signal's delay. This results in customization for each new module, making the receiver module incompatible between different transmission modules and requiring significant manpower and time for modification. Therefore, a circuit that can automatically and autonomously adjust the clock signal's delay timing for sampling is needed. Such a circuit allows for the free connection of various TTL signals without being limited by the actual number of signals to be transmitted. Summary of the Invention

[0006] This application proposes an automatic correction method to address the shortcomings of existing technologies. The aim is to effectively adjust the parameters to appropriate levels for various clock delays in order to facilitate subsequent data processing.

[0007] To achieve the above objectives, this application adopts the following technical solution:

[0008] According to an embodiment of this application, a delay period calculation circuit is provided for calculating the delay period of a digital bus, wherein the digital bus includes a clock signal circuit and multiple data signal circuits. The delay period calculation circuit comprises: a signal flip period detection logic circuit, used to receive input from the multiple data signal circuits and output a flip signal indicating whether a signal flip occurs in a delay position; multiple memory circuits corresponding to the multiple delay positions, each memory circuit storing the value obtained by performing an OR operation between the flip signal and an internal memory signal at the corresponding delay position as the memory signal; and a calculation logic circuit, used to receive the memory signals from the multiple memory circuits as a digital array corresponding to the multiple delay positions, find the longest consecutive subarray in the digital array, wherein the multiple memory signals corresponding to the multiple delay positions of the subarray do not indicate a signal flip, and set the delay position corresponding to an element in the subarray as the delay period of the clock signal circuit.

[0009] Preferably, in order to provide the flip signal, the detection logic circuit for the signal flip period further comprises: a plurality of detection logic circuits, each of the detection logic circuits being used to receive an input signal from one of the plurality of data signal circuits, comprising: a delay circuit of a delay level for delaying the input signal into a delayed signal; and a mutual exclusion OR (XOR) logic gate for receiving the delayed signal and the input signal for outputting to a first OR gate circuit; and the first OR gate circuit for receiving the outputs of the plurality of detection logic circuits and outputting the flip signal.

[0010] Preferably, in order to provide a corresponding memory signal to the computational logic circuit, each of the above memory circuits further includes a D-type flip-flop and a second OR gate circuit. The data output terminal Q of the D-type flip-flop outputs the memory signal to the second OR gate circuit at the corresponding delay level. The value obtained by the OR operation of the flip-flop signal and the memory signal is input to the data input terminal D of the D-type flip-flop.

[0011] Preferably, in order to provide clock signals corresponding to multiple delay levels to each D-type flip-flop, the delay period calculation circuit further includes: a serial circuit for multiple delay circuits for delaying one delay level, the serial circuit being used to receive the input of the clock signal circuit and to connect the output signal of each delay circuit to the clock signal terminal of the corresponding D-type flip-flop.

[0012] Preferably, in order to select the delay period, the aforementioned computational logic circuit is further configured to: when the number of elements in the segment array is odd, use the delay position corresponding to the middle element of the segment array as the delay period of the clock signal circuit; and when the number of elements in the segment array is even, use the delay position corresponding to one of the two elements closest to the middle of the segment array as the delay period of the clock signal circuit.

[0013] Preferably, in order to apply the delay period calculation circuit to the control chip of the display, the digital bus is characterized in that the above-mentioned digital bus is a transistor-transistor logic circuit red-green-blue (TTL RGB) interface bus, and the multiple data signal circuits include an HS horizontal synchronization signal circuit, a VS vertical synchronization signal circuit, a DE data start signal circuit, multiple red data signal circuits, multiple blue data signal circuits, and multiple green data signal circuits.

[0014] Preferably, in order to detect the signal flipping of the TTL RGB bus, the aforementioned delay period calculation circuit is applicable to the control chip of the display, and the delay period calculation circuit is used to calculate the data signal of at least one frame after the control chip is powered on.

[0015] Preferably, one of the aforementioned delay levels is 1 nanosecond.

[0016] According to one embodiment of this application, a control chip for a display is provided for connecting to a transistor-to-transistor logic circuit red-green-blue (TTL RGB) interface bus, characterized in that it includes the aforementioned delay time calculation circuit for calculating the delay time of the transistor-to-transistor logic circuit red-green-blue interface bus.

[0017] The beneficial effects of this application due to the above solution are: even with various clock delays in dozens of modules, the clock can be adjusted to the appropriate position under the same set of settings to meet the differentiated needs of customers in use and reduce the complexity of mass production. Attached Figure Description

[0018] Figure 1 This is a block diagram according to an embodiment of the present application.

[0019] Figure 2 This is a schematic diagram of the signal lines of a TTL RGB interface according to an embodiment of this application.

[0020] Figure 3 This is a circuit diagram of a signal flip period detection logic circuit 300 according to an embodiment of this application.

[0021] Figure 4 This is a circuit diagram of a delay time calculation circuit 400 according to an embodiment of this application.

[0022] Figure 5 This is a block diagram of a delay time calculation circuit 400 according to an embodiment of this application. Detailed Implementation

[0023] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other implementation methods obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0024] The terms “first,” “second,” “third,” etc. (if present) in the specification, claims, and drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the objects described herein may be used interchangeably where appropriate. In the description of this application, “plural” means two or more, unless otherwise expressly and specifically defined. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover non-exclusive inclusion. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. Such functional entities may be implemented in software, in one or more hardware circuits or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0025] In the description of this application, it should be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", and "outer" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0026] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections, electrical connections, or connections that allow for communication; they can refer to direct connections or indirect connections via an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the aforementioned terms in this application according to the specific circumstances.

[0027] To make the objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the drawings and specific embodiments.

[0028] Please refer to Figure 1 As shown, it is a block diagram according to an embodiment of this application. Figure 1It includes a transmission module 110 and a receiving module 120. Between these two modules 110 and 120, there are multiple signals 199 and a clock signal 190. As mentioned earlier, the transmission module 110 and the receiving module 120 can be transistor-to-transistor logic circuits, particularly a TTL RGB interface. In the TTL RGB interface, the multiple signals 199 can include HS, VS, DE, R, G, and B data signals, while the clock signal 190 is the CLK clock signal.

[0029] Those skilled in the art will understand that although the TTL RGB interface is used as an example in this application, it can also be used for other different interfaces, such as other interfaces with different numbers of signal lines.

[0030] In one embodiment, the receiving module 120 described above can be connected to a liquid crystal display (LCD). The data signal received from the TTL RGB interface is used to directly update different pixels, enabling the LCD to update the content of an entire frame or even multiple frames.

[0031] Please refer to Figure 2 The diagram shown is a schematic representation of the signal lines of a TTL RGB interface according to an embodiment of this application. Figure 2 From top to bottom, the signal consists of clock signal 190, three data signals 199A, 199B, and 199C, and a delayed sample signal 200. Each of the three data signals has a transition period. During the transition period, the data signal may change from 0 to 1 or from 1 to 0.

[0032] exist Figure 2 In this embodiment, if the receiving module 120 samples the three data signals respectively based on the rising edge of the frequency signal 190, it can be seen that the signal of data signal 199A is in the signal transition period, while the signals of data signals 199B and 199C are the old signals from the previous clock cycle. Therefore, the receiving module 120 should delay the clock signal 190 for a period of time, for example, a delay period 210, before sampling based on this delayed frequency signal 200, so as to obtain the correct values ​​of the three data signals. Therefore, this application will now describe how to calculate the delay period 210.

[0033] Since different transmission modules 110 correspond to different delay periods 210, the delay period 210 can be divided into many increments. Then, the most suitable increment is selected from these increments as the delay period 210. The number of increments typically depends on the fineness of the delay period 210 adjustment and the period length of the interface's clock signal. For example, a clock signal cycle can be divided into 20 increments or 30 increments. Then, according to the interface specification, the length of a clock signal cycle determines the delay period length for each increment.

[0034] For example, if the frequency of the interface clock signal is 50 MHz, then one cycle is approximately 20 nanoseconds. If the number of speed settings is set to 20, then the delay time for one speed setting is one nanosecond. Since a one-nanosecond delay circuit can be found in the TTL standard circuit library, in one embodiment, the speed setting can be set to one nanosecond for ease of calculation. If the number of speed settings is changed to 10, then the delay time for one speed setting will be 2 nanoseconds. If the number of speed settings is changed to 40, then the delay time for one speed setting will be 0.5 nanoseconds. Those skilled in the art will understand that although the number of speed settings can be freely determined, it will generally not exceed the length of one cycle.

[0035] Please refer to Figure 3 The diagram shown is a circuit diagram of a signal switching period detection logic circuit 300 according to an embodiment of this application. In each detection logic circuit 300, each received data signal 199 passes through a delay circuit 310 to extend its duration by one level, and then enters the XOR logic gate 320 along with the signal 199 of the next level to output a signal 399.

[0036] According to the truth table of a mutual exclusion logic, if the signals for the two gears before and after are the same, then the value of signal 399 is 0. However, if the signals for the two gears before and after are different, then the value of signal 399 is 1. In other words, when the value of signal 399 is 1, it indicates that the data signal between the gears has changed, or has been flipped. That is to say, when the value of signal 399 is 1, it means that the signal is unstable at this time and cannot be sampled during this period.

[0037] However, the fact that the signals for the two gears are the same does not necessarily mean that the signals for the two gears have not undergone a periodic transition. This is because the signals for both gears may be identical, so a periodic transition cannot be determined solely from signal changes. Nevertheless, when the value of signal 399 is 1, it can be confirmed that the signals for both gears have flipped and changed.

[0038] To test whether all data signals in the interface have flipped, all data signals 199 can be connected to a signal flipping period detection logic circuit 300 simultaneously, and then the output signal 399 can be observed to flip. When one of the signal values ​​399 is 1, it indicates that the current gear's delay period is within the signal flipping period of a certain data signal, meaning that the delay signal of this gear is not used as the sampling point.

[0039] However, even if all signal values ​​399 are 0, it does not necessarily mean that the current gear is a good sampling point, because it is still possible that a certain data signal skips a cycle, even if the signal values ​​of the preceding and following cycles are exactly the same.

[0040] In the aforementioned TTL RGB interface, the data signals to be detected simultaneously include 27 lines such as DE, HS, VS, R, G, and B. Simply put, all simultaneously sampled data signal lines must pass through the detection logic circuit 300 to obtain 27 detection signals 399. As mentioned earlier, when the TTL RGB interface frequency is 50 MHz and there are 20 settings, the delay time for each setting is 1 nanosecond. Therefore, the delay time of the delay circuit 310 is also 1 nanosecond.

[0041] Please refer to Figure 4 The diagram shown is a circuit diagram of a delay time calculation circuit 400 according to an embodiment of this application. Figure 4 In this embodiment, the input terminal has a total of N data signal lines 199-1 to 199-N, where N is a positive integer greater than one. These N data signal lines pass through detection logic circuits 300-1 to 300-N with N signal transition periods, resulting in N signals 399. These N signals 399 are then connected to the input of a first OR gate circuit 410. Clearly, if any one of these N signals 399 has a value of 1, the output of the first OR gate circuit 410 will be 1. That is, at least one data signal before and after the current gear position has undergone a signal transition period.

[0042] exist Figure 4 Below is the input clock signal 190. This clock signal 190 passes through M series-connected delay circuits 310-1 to 310-M, where M is a positive integer greater than one. M+1 represents the number of gear positions. The clock signal 190 before the delay circuit 310 is connected to the clock signal terminal of the first D-type flip-flop 430. Each subsequent delay circuit 310 transfers its output signal to the clock signal terminal of a D-type flip-flop 430.

[0043] Corresponding to M delay circuits 310-1 to 310-M, there are a total of M+1 D-type flip-flops 430. The data output terminal Q of each D-type flip-flop 430 is connected to one of the M+1 second OR gate circuits 420. The other input of these second OR gate circuits 420 is the toggle signal value of the current gear, which is the output signal of the first OR gate circuit 410. Then, the output signal of the second OR gate circuit 420 is input to the data input terminal D of the D-type flip-flop 430 corresponding to the clock signal of the next gear.

[0044] Assuming there are 20 gear positions, there will be 20 D-type flip-flops 430 and 20 second OR gates 420. In one embodiment, these 20 D-type flip-flops 430 collect information on whether a signal toggle has occurred for each corresponding gear position within one frame time. If a gear position has experienced a signal toggle, the final output signal of the corresponding D-type flip-flop 430 will be 1. If a gear position has not experienced a signal toggle, the final output signal of the corresponding D-type flip-flop 430 will be 0. In the embodiment with 20 D-type flip-flops 430, 20 bits 499 will be output to the computational logic circuit 450. Each bit 499 corresponds to the information on whether a gear position has experienced a signal toggle. If there are several consecutive bits 499 with a value of 0, the logic circuit 450 can search for the intermediate gear position where the most consecutive 0s occur. That intermediate gear position is considered the gear position where a signal toggle has never occurred, that is, this gear position is the optimal position for sampling the signal. The computational logic circuit 450 can output a signal indicating the optimal gear position in order to adjust the aforementioned delay period 210.

[0045] For example, in one embodiment, after a period of time, output bits as shown in Table 1 below are obtained.

[0046]

[0047] Table 1: Output Bit Values

[0048] In the embodiments described in Table 1, there are five consecutive 0 bits from gear 0 to gear 4, and eight consecutive 0 bits from gear 9 to gear 16. Therefore, the time interval from gear 9 to gear 16 should be the optimal sampling signal range. Among these eight 0 bits, the 4th or 5th gear closest to the middle, i.e., gear 12 or gear 13, can be selected as the optimal sampling gear. If there is an odd number of consecutive 0 bits, the optimal sampling signal gear is naturally the middle gear.

[0049] In the above embodiments, the VS vertical sync signal of the frame can be selected as the start and end of a frame. That is, the data signal of a whole frame is between two VS vertical sync signals. The VS vertical sync signal can be used to reset the D-type flip-flop 440. The delay period calculation circuit 400 can perform the above sampling on the data signal of a whole frame in order to output a signal representing the optimal gear to adjust the aforementioned delay period 210.

[0050] However, those skilled in the art will understand that other signals can be chosen as the period for data signal flip-over detection, i.e., used to control signal 440. For example, the HS horizontal synchronization signal, i.e., the start and end of a pixel column, can be used to reset the D-type trigger 430. Of course, the longer the data signal is detected, the greater the chance of detecting signal flip-over at each level, and the greater the probability of selecting the optimal sampling level.

[0051] The delay period calculation circuit 400 can be used to detect the delay period of a digital bus with clock signals and multiple data signal circuits, so as to avoid erroneous reception due to different signal delays caused by the varying lengths of the multiple data signal circuits. The delay period calculation circuit 400 can be implemented using TTL to connect the transmission module 110 and a receiving module 120.

[0052] In one embodiment, the delay period calculation circuit 400 can be used to detect the delay period of the TTL RGB transmission interface. In this embodiment, the delay period calculation circuit 400 can be implemented by the control chip of the liquid crystal display. The control chip of the liquid crystal display can execute the delay period calculation circuit 400 after soft power-on or hard power-on, or after receiving a reset signal, in order to detect the delay period of the TTL RGB transmission interface. Data from the aforementioned multiple data signal circuits is received only after the detected delay period has elapsed following the receiving of the rising edge of the clock signal.

[0053] Please refer to Figure 5The diagram shows a block illustration of a delay period calculation circuit 400 according to an embodiment of this application. The delay period calculation circuit 400 includes: a signal flip period detection logic circuit 510, configured to receive input from the plurality of data signal circuits 199 and output a flip signal indicating whether a signal flip has occurred in a delay position; a memory circuit module 520, corresponding to a plurality of memory circuits in the plurality of delay positions, each memory circuit storing the value obtained by performing an OR operation between the flip signal and an internal memory signal at the corresponding delay position as the memory signal; and a calculation logic circuit 450, configured to receive the memory signals from the plurality of memory circuits as a digital array corresponding to the plurality of delay positions, find the longest consecutive subarray in the digital array, wherein the memory signals of the plurality of delay positions corresponding to the subarray do not indicate a signal flip, and set the delay position corresponding to an element in the subarray as the delay period of the clock signal circuit.

[0054] The detection logic circuit 510 for the signal flip period further includes: a plurality of detection logic circuits 300, each of which is used to receive an input signal from one of the plurality of data signal circuits, including: a delay circuit 310 for delaying the input signal into a delayed signal; a mutual exclusion OR (XOR) logic gate 320 for receiving the delayed signal and the input signal 199 so as to output signal 399 to a first OR gate circuit; and the first OR gate circuit 410 for receiving the outputs of the plurality of detection logic circuits and outputting the flip signal.

[0055] Each of the above memory circuits further includes a D-type flip-flop 430 and a second OR gate circuit 420. The data output terminal Q of the D-type flip-flop 430 outputs the memory signal to the second OR gate circuit 420 at the corresponding delay level. The value of the OR operation between the flip-flop signal and the memory signal is input to the data input terminal D of the D-type flip-flop 430.

[0056] The delay period calculation circuit 400 also includes: a serial circuit 530 for a plurality of delay circuits 310 for delaying a delay level, the serial circuit 530 being used to receive the input of the clock signal circuit 190 and to connect the output signal of each delay circuit to the clock signal terminal of the corresponding D-type flip-flop 430.

[0057] The aforementioned computational logic circuit 450 is further configured to: when the number of elements in the segment array is odd, use the delay position corresponding to the middle element of the segment array as the delay period of the clock signal circuit 190; and when the number of elements in the segment array is even, use the delay position corresponding to one of the two elements closest to the middle of the segment array as the delay period of the clock signal circuit 190.

[0058] According to an embodiment of this application, a delay period calculation circuit is provided for calculating the delay period of a digital bus, wherein the digital bus includes a clock signal circuit and multiple data signal circuits. The delay period calculation circuit comprises: a signal flip period detection logic circuit, used to receive input from the multiple data signal circuits and output a flip signal indicating whether a signal flip occurs in a delay position; multiple memory circuits corresponding to the multiple delay positions, each memory circuit storing the value obtained by performing an OR operation between the flip signal and an internal memory signal at the corresponding delay position as the memory signal; and a calculation logic circuit, used to receive the memory signals from the multiple memory circuits as a digital array corresponding to the multiple delay positions, find the longest consecutive subarray in the digital array, wherein the multiple memory signals corresponding to the multiple delay positions of the subarray do not indicate a signal flip, and set the delay position corresponding to an element in the subarray as the delay period of the clock signal circuit.

[0059] Preferably, in order to provide the flip signal, the detection logic circuit for the signal flip period further comprises: a plurality of detection logic circuits, each of the detection logic circuits being used to receive an input signal from one of the plurality of data signal circuits, comprising: a delay circuit of a delay level for delaying the input signal into a delayed signal; and a mutual exclusion OR (XOR) logic gate for receiving the delayed signal and the input signal for outputting to a first OR gate circuit; and the first OR gate circuit for receiving the outputs of the plurality of detection logic circuits and outputting the flip signal.

[0060] Preferably, in order to provide a corresponding memory signal to the computational logic circuit, each of the above memory circuits further includes a D-type flip-flop and a second OR gate circuit. The data output terminal Q of the D-type flip-flop outputs the memory signal to the second OR gate circuit at the corresponding delay level. The value obtained by the OR operation of the flip-flop signal and the memory signal is input to the data input terminal D of the D-type flip-flop.

[0061] Preferably, in order to provide clock signals corresponding to multiple delay levels to each D-type flip-flop, the delay period calculation circuit further includes: a serial circuit for multiple delay circuits for delaying one delay level, the serial circuit being used to receive the input of the clock signal circuit and to connect the output signal of each delay circuit to the clock signal terminal of the corresponding D-type flip-flop.

[0062] Preferably, in order to select the delay period, the aforementioned computational logic circuit is further configured to: when the number of elements in the segment array is odd, use the delay position corresponding to the middle element of the segment array as the delay period of the clock signal circuit; and when the number of elements in the segment array is even, use the delay position corresponding to one of the two elements closest to the middle of the segment array as the delay period of the clock signal circuit.

[0063] Preferably, in order to apply the delay period calculation circuit to the control chip of the display, the digital bus is characterized in that the above-mentioned digital bus is a transistor-transistor logic circuit red-green-blue (TTL RGB) interface bus, and the multiple data signal circuits include an HS horizontal synchronization signal circuit, a VS vertical synchronization signal circuit, a DE data start signal circuit, multiple red data signal circuits, multiple blue data signal circuits, and multiple green data signal circuits.

[0064] Preferably, in order to detect the signal flipping of the TTL RGB bus, the aforementioned delay period calculation circuit is applicable to the control chip of the display, and the delay period calculation circuit is used to calculate the data signal of at least one frame after the control chip is powered on.

[0065] Preferably, one of the aforementioned delay levels is 1 nanosecond.

[0066] According to one embodiment of this application, a control chip for a display is provided for connecting to a transistor-to-transistor logic circuit red-green-blue (TTL RGB) interface bus, characterized in that it includes the aforementioned delay time calculation circuit for calculating the delay time of the transistor-to-transistor logic circuit red-green-blue interface bus.

[0067] The delay time calculation circuit provided in this application is a circuit that can freely and automatically adjust the sampling timing of the clock signal after the delay. With this circuit, the sampling timing of the frequency signal after the delay can be changed without the need for a custom receiver module. This allows for free connection to various different TTL converters, without being limited by the actual number of signals to be transmitted, or by the type and type of bus.

[0068] The above description is merely a preferred embodiment of this application, but the scope of protection of this application is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in this application, based on the technical solution and application concept of this application, should be included within the scope of protection of this application.

Claims

1. A control chip for a display, used to connect to a transistor-to-transistor logic circuit red-green-blue (TTL RGB) interface bus, characterized in that, The circuit includes a delay period calculation circuit for calculating the delay period of the aforementioned transistor-to-transistor logic circuit red-green-blue interface bus, wherein the aforementioned transistor-to-transistor logic circuit red-green-blue interface bus includes a clock signal circuit and multiple data signal circuits. The delay period calculation circuit includes: The signal flip period detection logic circuit is used to receive the input of the multiple data signal circuits and output a flip signal indicating whether the multiple data signal circuits have flipped within a delay range. Multiple memory circuits, each corresponding to a plurality of delay levels, are used to store the value obtained by performing an OR operation between the flip signal and its internal memory signal at the corresponding delay level as the memory signal; and Computational logic circuits are used for: The memory signal received by the multiple memory circuits is a digital array corresponding to the multiple delay levels. Find the longest consecutive subarray within the numerical array, where multiple memory signals across multiple delay levels corresponding to this subarray do not indicate a signal flip. Let the delay level corresponding to one element in the subarray be used as the delay period of the clock signal circuit.

2. The control chip for the display as described in claim 1, characterized in that, The detection logic circuit for the signal flipping period also includes: Multiple detection logic circuits, each of which is used to receive an input signal from one of the multiple data signal circuits, including: The delay circuit of this delay level is used to delay the input signal into a delayed signal; and A mutually exclusive (XOR) logic gate is used to receive the delayed signal and the input signal so that the output can be sent to the first OR gate circuit; as well as The first OR gate is used to receive the outputs of the plurality of detection logic circuits and output the toggle signal.

3. The control chip for the display as described in claim 1, characterized in that, Each of the above memory circuits further includes a D-type flip-flop and a second OR gate circuit. The data output terminal Q of the D-type flip-flop outputs the memory signal to the second OR gate circuit at the corresponding delay level. The second OR gate circuit inputs the value of the OR operation between the flip-flop signal and the memory signal to the data input terminal D of the D-type flip-flop.

4. The control chip for the display as described in claim 3, characterized in that, The delay period calculation circuit also includes: a serial circuit for multiple delay circuits for delaying one delay level, the serial circuit being used to receive the input of the clock signal circuit and to connect the output signal of each delay circuit to the clock signal terminal of the corresponding D-type flip-flop.

5. The control chip for the display as described in claim 1, characterized in that, The aforementioned computational logic circuits are further used for: When the number of elements in the segment array is odd, the delay level corresponding to the middle element of the segment array is used as the delay period of the clock signal circuit; and When the number of elements in the segment array is even, the delay level corresponding to one of the two elements closest to the middle of the segment array is used as the delay period of the clock signal circuit.

6. The control chip for the display as described in claim 1, characterized in that, The multiple data signal circuits include the HS horizontal synchronization signal circuit, the VS vertical synchronization signal circuit, the DE data start signal circuit, multiple red data signal circuits, multiple blue data signal circuits, and multiple green data signal circuits.

7. The control chip for the display as described in claim 6, characterized in that, The aforementioned delay period calculation circuit is applicable to the control chip of the display. The delay period calculation circuit is used to calculate the data signal of at least one frame after the control chip is powered on.

8. The control chip for the display as described in claim 6, characterized in that, One of the aforementioned delay levels is 1 nanosecond.

9. The control chip for the display as described in claim 1, characterized in that, The delay period calculation circuit is executed after a soft or hard power-on, or after receiving a reset signal.

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