Adder tree device, multiply-accumulate circuit and its operation method

Abstract

Embodiments of this disclosure provide a full adder tree apparatus, circuit, and method of operation thereof. In one aspect, the adder tree apparatus may include a first adder circuit for receiving a first operand and a second operand as inputs and generating a negative sum value, wherein the negative sum value is the logical inversion of the sum of the first operand and the second operand. The adder tree apparatus may further include a second adder circuit for receiving the negative sum value and an additional operand as inputs and generating a positive sum value as output. The positive sum value may be equal to the sum of the first operand and the second operand plus the logical inversion of the additional operand.

Description

Technical Field

[0001] The embodiments of the present invention generally relate to the field of electronic circuits, and more specifically, to adder tree devices, multiply-accumulate circuits, and methods of operation thereof. Background Technology

[0002] The semiconductor industry has experienced rapid growth due to a series of improvements in the integration density of various electronic components, such as transistors, diodes, resistors, and capacitors. These improvements in integration density primarily stem from the continuous reduction in the size of the smallest feature, allowing more components to be integrated into a given area. Summary of the Invention

[0003] An embodiment of the present invention provides an adder tree apparatus, comprising: a first adder circuit configured to: receive a first operand and a second operand as inputs; and generate a negative sum value, wherein the negative sum value is the logical inversion of the sum of the first operand and the second operand; and a second adder circuit configured to: receive the negative sum value and an additional operand as inputs; and generate a positive sum value as output, wherein the positive sum value is equal to the sum of the first operand and the second operand plus the logical inversion of the additional operand.

[0004] One embodiment of the present invention provides a multiply-accumulate (MAC) circuit, comprising: a multiplier circuit configured to generate a plurality of partial products; and an adder tree circuit configured to: receive the plurality of partial products; generate an intermediate sum, the intermediate sum corresponding to a logical inversion of a first corresponding sum of at least two of the plurality of partial products; and generate an output sum based on the intermediate sum and a second operand, wherein the output sum corresponds to a logical inversion of a second corresponding sum of the intermediate sum and the second operand.

[0005] Another embodiment of the present invention provides a method for operating an adder circuit, comprising: receiving a first operand and a second operand as inputs through a first adder circuit of an adder tree circuit; generating a negative sum value through the first adder circuit, wherein the negative sum value is the logical inverse of the sum of the first operand and the second operand; receiving the negative sum value and a second value as inputs through a second adder circuit of the adder tree circuit; and generating a positive sum value as an output through the second adder circuit, wherein the positive sum value is equal to the sum of the first operand and the second operand plus the logical inverse of the second value. Attached Figure Description

[0006] The various aspects of the invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0007] Figure 1 A schematic diagram of an example circuit for implementing a full adder with an inverting output according to some embodiments is shown;

[0008] Figure 2 A schematic diagram of an example adder tree circuit including a full adder circuit with a negative sum output and a negative carry output, according to some embodiments, is shown.

[0009] Figure 3 A schematic diagram of an example adder tree circuit including a full adder circuit with a negative sum output and a positive carry output is shown according to some embodiments;

[0010] Figure 4 A schematic diagram of an example adder tree circuit including a full adder circuit with a positive sum output and a negative carry output is shown according to some embodiments;

[0011] Figure 5 Possible combinations according to some embodiments are shown. Figure 2 , Figure 3 and Figure 4 A schematic diagram of an example of a multiply-accumulate (MAC) circuit, describing one or more adder tree circuits;

[0012] Figure 6 It is shown that, according to some embodiments, it may be included in the combination Figure 5 A schematic diagram of a portion of the multiplier circuit in the described MAC circuit;

[0013] Figure 7 The illustration shows possible combinations according to some embodiments. Figure 5 A schematic diagram of one or more adder tree circuits in the described MAC circuit;

[0014] Figure 8 A schematic diagram of an example two-stage adder tree circuit including a full adder circuit with a negative sum output and a negative carry output, according to some embodiments, is shown; and

[0015] Figure 9 A flowchart illustrating an example method of operating one or more adder circuits described in this disclosure according to some embodiments is shown. Detailed Implementation

[0016] This invention provides numerous different embodiments or examples for implementing various features of this disclosure. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are formed in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the invention. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0017] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower," "above," and "upper" may be used to describe the relationship between one element or component and another (or other elements or components) as shown in the figure. In addition to the orientation shown in the figure, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0018] Digital compute-in-memory (DCIM) circuits reduce memory usage and improve the efficiency of various operations, such as matrix-matrix operations, by performing operations within or near memory elements. One example of an operation that can be performed in DCIM circuits is the multiply-accumulate (MAC) operation, which is helpful for applications such as neural network inference or scientific computing. In traditional DCIM implementations, MAC operations consume a significant amount of power, with multiplier circuits and adder trees accounting for over 75% of the total power consumption. Adder units (including half-adders and full-adder (FA) units) constitute the majority of the components in the multiplier and adder tree, and their contribution to dynamic power consumption is significant due to frequent state transitions and buffering operations within the logic path. Traditional adder circuits employ output buffers for summing and carrying to maintain signal integrity and polarity consistency between operational stages. However, these buffers introduce additional capacitors and switching activity, increasing power consumption without a corresponding performance improvement.

[0019] The techniques described in this disclosure introduce FA circuit topologies that modify the output polarity of the summing and carry paths to reduce power consumption in the DCIM adder tree. These techniques eliminate or reconfigure output buffers in FA cells based on predefined polarity configurations, thereby minimizing unwanted switching activity. The techniques described in this disclosure can be used to implement adder trees with various configurations, including: configurations containing only FA cells with summing and carry paths having negative outputs; configurations containing FA cells with negative summing outputs and positive carry outputs; and configurations containing FA cells with positive summing outputs and negative carry outputs. In some implementations, one or more of these configurations can be combined to implement various different adder trees, as described further in detail in this disclosure. Compared to circuits implementing conventional FA circuits, the techniques described in this disclosure significantly reduce power consumption in DCIM MAC operations.

[0020] Reference Figure 1 , Figure 1 An example full adder circuit 100 according to some embodiments is shown. Each component shown in the full adder circuit 100 may receive power from one or more voltage sources, such as the power supply voltage VDD. The full adder circuit 100 may include one or more logic gates and subcircuits, wherein each subcircuit may be composed of one or more logic gates. Logic gates are electronic devices used to perform logical operations on one or more input signals to produce a single output signal.

[0021] Various embodiments of the circuitry and logic gates implementing the full adder circuit 100 may include various transistors. The transistors described in this disclosure may have a specific type (n-type or p-type), but the embodiments are not limited thereto. The transistors may be any suitable type, including, but not limited to, metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, P-channel metal-oxide-semiconductor (PMOS), N-channel metal-oxide-semiconductor (NMOS), bipolar junction transistors (BJTs), high-voltage transistors, high-frequency transistors, P-channel and / or N-channel field-effect transistors (PFETs / NFETs), FinFETs, planar MOS transistors with convex source / drain terminals, nanosheet FETs, nanowire FETs, etc. It should be understood that... Figure 1The illustrated full adder circuit 100 may be part of a DCIM circuit, a MAC circuit, an adder tree circuit, or any other type of circuit that implements adder operations. In some implementations, the full adder circuit 100 may be included in one or more memory circuits. The full adder circuit 100 is shown as including transistors M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11, M12, M13, M14, M15, M16, M17, M18, M19, and M20. The full adder circuit 100 is also shown as including a first inverter 102 and a second inverter 104.

[0022] Although each transistor M1 to M20 in the full adder circuit 100 is shown as a single transistor, the embodiments are not limited thereto. For example, each transistor may comprise multiple transistors (“sub-transistors”) connected in parallel. For example, each sub-transistor of any transistor described in this disclosure may include a corresponding gate, drain, and source terminal, each of which may be connected in parallel. Each of transistors M1 to M20 includes a gate, a first source / drain terminal, and a second source / drain terminal. Transistors M1, M2, M5, M6, M9, M11, M12, M15, M16, and M17 are shown as p-type MOSFET transistors. Transistors M3, M4, M7, M8, M10, M13, M14, M18, M19, and M20 are shown as n-type MOSFET transistors. In some implementations, transistors M1 to M20 may comprise other types of transistors, such as bipolar junction transistors or high electron mobility transistors, but these remain within the scope of this disclosure.

[0023] The gates of transistors M2, M3, M6, M7, M12, M13, M17, and M18 are shown as coupled to the first input operand A. The gates of transistors M1, M4, M8, M5, M11, M14, M16, and M19 are shown as coupled to the second input operand B. The gates of transistors M9, M15, M10, and M20 are coupled to the carry input CI. The gates of transistors M1 through M20 are used to receive corresponding input signals to control the conduction state of the transistors.

[0024] The first source / drain terminals of transistors M1, M2, M5, M9, M11, M12, and M15 are connected to the power supply voltage VDD. The second source / drain terminals of transistors M3, M4, M8, M10, M13, M14, and M20 are coupled to ground. The second source / drain terminal of transistor M1 is coupled to the power supply terminal of the first inverter 102. The second source / drain terminal of transistor M2 is also coupled to the power supply terminal of the first inverter 102. The first source / drain terminals of transistors M3 and M4 are coupled to the ground terminal of the first inverter 102.

[0025] The second source / drain terminal of transistor M5 is coupled to the first source / drain terminal of transistor M6. The second source / drain terminal of transistor M6 is coupled to the output terminal of the first inverter 102, the first source / drain terminal of transistor M7, and the input terminal of the second inverter 104. The second source / drain terminal of transistor M7 is coupled to the first source / drain terminal of transistor M8. The second source / drain terminals of transistors M9, M11, and M12 are coupled to the power supply terminal of the second inverter 104. The first source / drain terminals of transistors M10, M13, and M14 are coupled to the ground terminal of the second inverter 104.

[0026] The second source / drain terminal of transistor M16 is coupled to the first source / drain terminal of transistor M17. The second source / drain terminal of transistor M17 is coupled to the output terminal of the second inverter 104. The first source / drain terminal of transistor M18 is coupled to the output terminal of the second inverter 104. The first source / drain terminal of transistor M19 is coupled to the second source / drain terminal of transistor M18. The first source / drain terminal of transistor M20 is coupled to the second source / drain terminal of transistor M19. The negative carry output CB of the full adder circuit 100 is provided at the output terminal of the first inverter 102, and the negative sum output SB of the full adder circuit 100 is provided at the output terminal of the second inverter 104.

[0027] During the operation of the full adder circuit 100, when the first input operand A is at logic low, the second input operand B is at logic low, and the carry input CI is at logic low, transistors M2, M6, M12, and M17 are turned on because their gates are coupled to the first input operand A, which is at logic low. Similarly, transistors M1, M5, M11, and M16 are turned on because their gates are coupled to the second input operand B, which is at logic low. Furthermore, n-type transistors M3, M7, M13, and M18 are turned off, while transistors M4, M8, M14, and M19 are turned on. Transistors M9 and M15 are turned on and conducting, while transistors M10 and M20 are turned off because their gates are coupled to the carry input CI.

[0028] In these states, the power supply terminal of the first inverter 102 is connected to the power supply voltage VDD via the on transistors M1 and M2. Due to the off transistors M3 and M4, the ground terminal of the first inverter 102 is disconnected from ground. According to the carry input CI, the input terminal of the first inverter 102 is grounded. This configuration causes the output terminal of the first inverter 102 to be in a logic high state, thereby providing a logic high negative carry output CB, which is the inverted (e.g., negative) of the actual carry value "0". Furthermore, because transistors M5 and M6 are on and transistors M7 and M8 are off, the node connected to the carry output CB and the input terminal of the second inverter 104 is pulled to a logic high state.

[0029] Furthermore, in these input states, the power supply terminal of the second inverter 104 is connected to the power supply voltage VDD due to the on transistors M9, M11, and M12. The ground terminal of the second inverter 104 is disconnected from ground via the off transistors M10, M13, and M14. The output node of the second inverter and the negative sum output SB of the circuit are pulled to a logic high state (e.g., the logic inversion of the actual sum value "0"). Since the second inverter 104 is disconnected from ground, the output terminal of the second inverter 104 will be a floating output (e.g., not pulled to ground). However, because transistors M15, M16, and M17 are on and conducting, while transistors M18, M19, and M20 are off, the negative sum output is pulled to a logic high state.

[0030] In another example, when the first input operand A is logic high, the second input operand B is logic high, and the carry input CI is logic high, transistors M3, M7, M13, and M18 are turned on because their gates are coupled to the first input operand A, which is logic high. Transistors M4, M8, M14, and M19 are also turned on because their gates are coupled to the second input operand B, which is logic high. Furthermore, transistors M10 and M20 are turned on, while transistors M9 and M15 are turned off because their gates are coupled to the carry input CI, which is logic high. Transistors M1, M2, M5, M6, M11, M12, M16, and M17 are turned off because their gates are coupled to the corresponding input operands A or B, which are logic high, while transistors M18 and M19 are turned on.

[0031] In these states, the power supply terminal of the first inverter 102 is disconnected from the power supply voltage VDD due to the off transistors M1 and M2. The ground terminal of the first inverter 102 is grounded via the on transistors M3 and M4. The output terminal of the first inverter 102 is pulled to a logic low state via a conductive path formed by the grounded on transistors M7 and M8. Furthermore, the first inverter 102 receives a carry input CI that is in a logic high state and pulls its output terminal to ground. This configuration causes the output of the first inverter 102 (e.g., a negative carry output CB) to be in a logic low state, which is the inversion of the actual carry value "1".

[0032] With transistors M9, M11, and M12 off, the power supply terminal of the second inverter 104 is disconnected from the power supply voltage VDD. The ground terminal of the second inverter 104 is grounded via the on-state transistors M10, M13, and M14. The output node of the second inverter and the negative sum output SB of the circuit are pulled to a logic low state (the inversion of the actual sum value "1"). Since the second inverter 104 is disconnected from the power supply voltage VDD, its output will be a floating output. However, with transistors M18, M19, and M20 on, the negative sum output SB is pulled to a logic low state (via ground connection), representing the inversion of the actual sum value "1".

[0033] In some implementations, when the first input operand A is in a logic high state, the second input operand B is in a logic low state, and the carry input CI is in a logic low state, transistors M3, M7, M13, and M18 (n-type, with their gates coupled to the first input operand A) are turned on. Transistors M2, M6, M12, and M17 (p-type, with their gates coupled to the first input operand A) are turned off. Transistors M1, M5, M11, and M16 (p-type, with their gates coupled to the second input operand B) are turned on. Transistors M4, M8, M14, and M19 (n-type, with their gates coupled to the second input operand B) are turned off. Transistors M9 and M15 (p-type, with their gates coupled to the carry input CI) are turned on, and transistors M10 and M20 (n-type, with their gates coupled to the carry input CI) are turned off.

[0034] The power supply terminal of the first inverter 102 is connected to the power supply voltage VDD via a switched-on transistor M1. The ground terminal of the first inverter 102 is grounded via a switched-on transistor M3. The input terminal of the first inverter 102 is pulled to a logic low state via a conductive path formed by a grounded switched-on transistor M7 (n-type). This configuration causes the output terminal of the first inverter 102 to be in a logic high state, thereby providing a logic high negative carry output CB (the inversion of the actual carry value "0").

[0035] The input of the second inverter 104 is pulled low via the on transistor M7 (n-type). Because transistors M2, M6, M12, and M17 are off, the power supply terminal of the second inverter 104 is disconnected from the power supply voltage VDD. The ground terminal of the second inverter 104 is grounded via the on transistor M13 (n-type). Therefore, the output of the second inverter 104 is pulled high (the inverted value of the actual sum of "1").

[0036] To further illustrate, if the input operands A and B are in a logic high state, while the carry input CI is in a logic low state, the power supply terminal of the second inverter 104 will be connected to the power supply voltage VDD, causing it to operate and pull the negative sum output SB to a logic high state (the inversion of the actual sum value "0"). Since the carry input CI is in a logic high state, the transistor M20 will be turned off, and therefore the negative sum output SB will not be pulled to ground as described above.

[0037] In some implementations, when one of the first input operand A and the second input operand B is at logic high and the other is at logic low, and the carry input CI is at logic high, the transistor coupled to the high operand (e.g., an n-type transistor used to make the first input operand A high or the second input operand B high) is turned on, thereby grounding the ground terminal of the first inverter 102. The transistor coupled to the low operand (e.g., a p-type transistor used to make the second input operand B low or the first input operand A low) is turned on, thereby connecting the power supply terminal of the first inverter 102 to the power supply voltage VDD. This configuration pulls the output terminal of the first inverter 102 to a logic low state, causing the negative carry output CB to be at a logic low state (the inversion of the actual carry value "1"). The ground terminal of the second inverter 104 is connected via a transistor (e.g., transistor M10 or M20) coupled to the carry input CI, while the power supply terminal of the second inverter 104 is connected via one of transistors M11 or M12, depending on which input operand is in a logic low state. This configuration will activate the second inverter 104, causing the negative sum output SB to be in a logic high state (the inversion of the actual sum value "0").

[0038] In some implementations, when one of the input operands A and B is in a logic high state and the other is in a logic low state, and the carry input CI is in a logic low state, the transistor coupled to the low operand (e.g., a p-type transistor used to bring the second input operand B low or the first input operand A low) is turned on, thereby connecting the power supply terminals of the first inverter 102 and the second inverter 104 to the power supply voltage VDD. The ground terminals of the first inverter 102 and the second inverter 104 are also grounded via one of transistors M3 and M4 or one of transistors M13 and M14, respectively. The first inverter 102 is activated and generates a negative carry output CB (the inverted version of the carry value "0") in a logic high state. The second inverter 104 is also activated and generates a negative sum output SB (the inverted version of the actual sum value "1") in a logic low state.

[0039] In another example, when the carry input CI is logic high and the first input operand A and the second input operand B are logic low, transistors M10 and M20 (n-type, with their gates coupled to the carry input CI) are turned on, while transistors M9 and M15 (p-type, with their gates coupled to the carry input CI) are turned off. Due to the off transistors M9, M11, and M12, the power supply terminal of the second inverter 104 is disconnected from the power supply voltage VDD. The ground terminal of the second inverter 104 is grounded via the turned-on transistor M10. The input terminal of the second inverter 104 is pulled to logic low via a conductive path formed by the turned-on transistor M10, causing the output (negative sum output SB) to be logic high (the inverted version of the actual sum value "1"). The negative carry output CB of the first inverter 102 is determined by the states of the input operands A and B.

[0040] The truth table of the negative full adder circuit 100 is as follows.

[0041] Input operand A Input operand B Carry Input CI Negative total output SB Negative carry output CB 0 0 0 1 1 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 0 0

[0042] The negative full adder circuit 100 can be implemented in any suitable circuit, including any adder tree circuit, MAC circuit, or multiplication circuit described in this disclosure. Although the full adder circuit 100 has been described as a “negative” adder circuit (e.g., logically inverting the sum and carry as described in this disclosure), the full adder circuit 100 may include inverters to produce one or more “positive” (e.g., uninverted) outputs. Without additional output inverters, the full adder circuit 100 may include 24 transistors (e.g., 20 transistors M1 to M20, with inverters 102 and 104 each having two transistors, etc.).

[0043] In one example, the negative sum output SB can be used as an input to an inverter to produce a positive sum output that reflects the actual sum value corresponding to the input operands A and B and the carry input CI. Furthermore, the negative carry output CB can be used as an input to an inverter to produce a positive carry output that reflects the actual sum value corresponding to the input operands A and B and the carry input CI. Different configurations of the negative full adder circuit 100 (including zero, one, or more additional inverters) can be implemented in various circuits described in this disclosure. For a single-output inverter, the full adder circuit 100 may include 26 transistors (e.g., 20 transistors M1 to M20 in total, where inverters 102 and 104 each contain two transistors, and the output inverter also contains two transistors, etc.).

[0044] Reference Figure 2 , Figure 2 A schematic diagram of an example adder tree circuit 200 according to some embodiments is shown. Adder tree circuit 200 includes a full adder circuit with a negative output. Each component shown in adder tree circuit 200 can receive power from one or more voltage sources, such as power supply voltage VDD (shown as "V" for simplicity, which can be interpreted as a logic high input in this disclosure). Adder tree circuit 200 may include one or more logic gates and subcircuits, wherein each subcircuit may be composed of one or more logic gates. Logic gates may be electronic devices used to perform logical operations on one or more input signals to produce a single output signal.

[0045] Various embodiments of the circuitry and logic gates implementing the adder tree circuit 200 may include various transistors. The transistors described in this disclosure may have a specific type (n-type or p-type), but the embodiments are not limited thereto. The transistors may be any suitable type, including, but not limited to, MOSFETs, CMOS transistors, PMOS, NMOS, BJTs, high-voltage transistors, high-frequency transistors, PFETs / NFETs, FinFETs, planar MOS transistors with convex source / drain terminals, nanosheet FETs, nanowire FETs, etc. It should be understood that... Figure 2 The adder tree circuit 200 shown can be included in any type of circuit, including but not limited to DCIM circuits, MAC circuits, multiplier circuits, or any other type of circuit that implements addition operations.

[0046] In this example, the adder tree circuit 200 is shown as comprising three stages, wherein the first stage adds 3-bit input values ​​A (represented by bits A1, A2, and A3) to 3-bit input values ​​B (represented by bits B1, B2, and B3). The first stage also includes the sum of 3-bit input values ​​C (represented by bits C1, C2, and C3) and 3-bit input values ​​D (represented by bits D1, D2, and D3).

[0047] Adder tree circuit 200 can be used Figure 1 The full adder circuit 100 is used to implement this. The adder tree circuit 200 is shown as comprising a set of first negative full adders 202A to 201I (sometimes collectively referred to as "first negative full adders 202") and a set of second negative full adders 204A to 204F (sometimes collectively referred to as "second negative full adders 204"). Each of the first negative full adders 202 and the second negative full adders 204 may contain... Figure 1 A full adder circuit 100 is constructed and implemented. Figure 1 The full adder circuit 100 can perform any function. In this way, the first negative full adder 202 and the second negative full adder 204 can produce a logically inverted sum output (e.g., the negative sum output SB described in this disclosure) and a logically inverted carry output (e.g., the negative carry output CB described in this disclosure).

[0048] exist Figure 2 In the adder tree circuit 200, due to its configuration of simultaneously generating a negative sum output and a negative carry output, and due to its connection with other negative adders within the adder tree circuit 200, the first negative full adder 202 receives a "positive" input (e.g., a logic-uninverted input) and generates a "negative" output (e.g., a logic-inverted output). For example, the first negative full adder 202A can receive positive inputs "1" and "0" and generate a negative output sum value "0" (e.g., the inverted version of the true sum value "1") and a negative output carry value "1" (e.g., the inverted version of the true carry value "0").

[0049] Furthermore, due to its configuration of simultaneously generating negative sum output and negative carry output, and its connection to other negative adders within the adder tree circuit 200, the second negative full adder 204 receives "negative" inputs (e.g., logically inverted inputs) and generates corresponding "positive" outputs (e.g., logically uninverted outputs). For example, the second negative full adder 204A can receive inverted inputs "0" and "1", an inverted carry input of "1", and generate a positive output sum value "1" (e.g., a true sum value "1", considering that the input carry itself represents the value "0") and a negative output carry value "0" (e.g., a true carry "0"). It should be noted that although the first full adder 202 and the second full adder 204 have the same structure, the second full adder 204 can generate an output that is logically uninverted relative to its represented value, while the first full adder 202 can generate an output that remains inverted. This difference arises because the second full adder 204 receives an inverted input, so its output returns to a non-inverted logic state, while the first full adder 202 processes a non-inverted input and maintains an inverted state in its output.

[0050] exist Figure 2In the example implementation method shown, the adder tree circuit 200 can sum four 3-bit values ​​A, B, C and D through a hierarchical configuration of the first negative full adder 202 and the second negative full adder 204. Figure 2 Each 3-bit value A, B, C, and D is shown, where digit identifiers are used to identify the index of the corresponding bit. For example, A0 corresponds to the least significant bit in value A, B2 corresponds to the most significant bit in value B, and so on. The first stage of the adder tree circuit 200 includes first full adders 202A to 202D and second full adders 204A and 204B. Based on inputs A and B, the first negative full adder 202A can receive positive inputs A0 and B0 and a grounded level carry input (G) representing a logic low state (e.g., a positive carry value of zero) of the carry input. The second negative full adder 204A can receive inverted inputs A1 and B1 (e.g., logic NOT versions of actual values ​​A1 and B1) and a negative carry output generated by the first negative full adder 202A. The inverted states of inputs A1 and B2 are... Figure 2 The horizontal line above the signal label is used for visual representation. The second negative full adder 204B can process the positive inputs A2 and B2 using the positive carry output from the second negative full adder 204A, as shown in the figure.

[0051] For inputs C and D, the first negative full adder 202C can similarly receive positive inputs C0, D0 and a level carry input (G). The second negative full adder 204B can receive inverted inputs C1 and D1 (logical inversions of the actual values ​​C1 and D1) and is coupled to the negative carry output from the first negative full adder 202C. The second negative full adder 204B can receive and process positive inputs C2 and D2 using the positive carry output from the previous second negative full adder 204B. The first stage is used to generate a sum representing inputs A+B and inputs C+D, and these sums are provided to the next stage of the adder tree circuit 200.

[0052] In the second stage of the adder tree circuit 200, the second negative full adder 204C sums the negative sum output of the first negative full adders 202A and 202C in the first stage and the logic high carry input (V), where the logic high carry input (V) is the inverted signal of the actual carry value "0". The second negative full adder 204C generates a positive sum output that is sent to the third stage adder in the adder tree circuit 200, and generates a positive carry output that is provided to the first negative full adder 202E. The first negative full adder 202E receives the positive sum output of the second negative full adders 204A and 204B in the first stage and the positive carry output of the second negative full adder 204C. The first negative full adder 202E generates a negative sum output that is provided to the third stage, and generates a negative carry output that is sent to the second negative full adder 204D.

[0053] The second negative full adder 204D adds the negative sum output of the first negative full adders 202B and 202D in the first stage to the negative carry output of the first negative full adder 202E, thereby generating a positive sum output for the third stage and a positive carry output provided to the first negative full adder 202F. The first negative full adder 202F can also process the negative sum output of the first negative full adders 202B and 202D and the positive carry output of the second negative full adder 204D to accommodate two's complement arithmetic. The alternating structure of inverted and non-inverted inputs and outputs on the first negative full adder 202 and the second negative full adder 204 enables the entire adder tree circuit 200 to transmit carry signals and intermediate sums, while maintaining operational accuracy through multiple adder stages.

[0054] The third stage of the adder tree circuit 200 serves as the final summing layer, and in this example includes first negative full adders 202G and 202H, and second negative full adders 204E and 204F. The first negative full adder 202G receives the negative sum output from the second negative full adder 204C in the second stage, a logic low value (G) as the second operand, and a logic low carry input (G). The logic low second operand is used as a logic zero operation to maintain the same sum of inputs. The first negative full adder 202G generates a negative sum output, which can be inverted using an inverter (as shown) to produce the final logically correct sum value. The negative carry output of the first negative full adder 202G can be provided to the second negative full adder 204E to transmit the carry signal via the third stage.

[0055] The second negative full adder 204E processes the negative sum output of the first negative full adder 202E in the second stage, and combines it with a logic high value (V) as the second operand (which is an inverted logic zero, essentially adding a logic zero) and a negative carry input from the first negative full adder 202G. The second negative full adder 204E can produce a positive sum output (which can be part of the final output) and a positive carry output provided to the first negative full adder 202H. The first negative full adder 202H can receive the negative sum output of the second negative full adder 204D in the second stage, and pair it with a logic low value (G) as the second identity operand and a positive carry input from the second negative full adder 204E. The first negative full adder 202H can produce a negative sum output, which is inverted to produce the correct (positive) final sum value, and can transmit the negative carry output to the second negative full adder 204F.

[0056] The second negative full adder 204F processes the negative sum output from the first negative full adder 202F in the second stage, the logic high value (V) as the second operand (e.g., the identity operator), and the negative carry input from the first negative full adder 202H. The second negative full adder 204F can produce a positive sum as part of the final output and generate a positive carry output provided to the first negative full adder 202I. The first negative full adder 202I also processes the negative sum output from the first negative full adder 202F in the second stage, combining it with the logic high value (V) and the positive carry input from the second negative full adder 204E. The inputs of the first negative full adder 202I are the same as those of the second negative full adder 204F to ensure compatibility with two's complement arithmetic. As shown, the first negative full adder 202I can produce a negative sum output, which is inverted to form the final logically accurate result.

[0057] Reference Figure 3 , Figure 3 A schematic diagram of an example adder tree circuit 300 according to some embodiments is shown. The adder tree circuit 300 includes a full adder circuit with a negative sum output and a positive carry output. Each component shown in the adder tree circuit 300 can receive power from one or more voltage sources, such as the power supply voltage VDD (shown as "V" for simplicity, and can be interpreted as a logic high input in this disclosure). The adder tree circuit 300 may include one or more logic gates and subcircuits, wherein each subcircuit may be composed of one or more logic gates. The logic gates may be electronic devices used to perform logical operations on one or more input signals to produce a single output signal.

[0058] Various embodiments of the circuitry and logic gates implementing the adder tree circuit 300 may include various transistors. The transistors described in this disclosure may have a specific type (n-type or p-type), but the embodiments are not limited thereto. The transistors may be any suitable type, including, but not limited to, MOSFETs, CMOS transistors, PMOS, NMOS, BJTs, high-voltage transistors, high-frequency transistors, PFETs / NFETs, FinFETs, planar MOS transistors with convex source / drain terminals, nanosheet FETs, nanowire FETs, etc. It should be understood that... Figure 3 The adder tree circuit 300 shown can be included in any type of circuit, including but not limited to DCIM circuits, MAC circuits, multiplier circuits, or any other type of circuit that implements addition operations.

[0059] and Figure 2Similar to the example shown, in this example, the adder tree circuit 300 is shown as comprising three stages, wherein the first stage adds 3-bit input values ​​A (represented by bits A1, A2, and A3) to 3-bit input values ​​B (represented by bits B1, B2, and B3). The first stage also includes the sum of 3-bit input values ​​C (represented by bits C1, C2, and C3) and 3-bit input values ​​D (represented by bits D1, D2, and D3).

[0060] and Figure 2 Similar to adder tree circuit 200, adder tree circuit 300 can be used. Figure 1 One or more full adder circuits 100 are used to implement this. The adder tree circuit 300 is shown as comprising a set of first negative full adders 302A to 302K (sometimes collectively referred to as "first negative full adders 302") and a set of second negative full adders 304A to 304D (sometimes collectively referred to as "second negative full adders 304"). Each of the first negative full adders 302 and the second negative full adders 304 may contain... Figure 1 A full adder circuit 100 is constructed and implemented. Figure 1 Any function of the full adder circuit 100.

[0061] In the illustrated example, the first negative full adder 302 and the second negative full adder 304 can produce a logically inverted sum output (e.g., the negative sum output SB described in this disclosure) and a logically inverted carry output (e.g., the negative carry output CB described in this disclosure). However, the logically inverted carry outputs of the first negative full adder 302 and the second negative full adder 304 are respectively used as inputs to the inverter 306, such that the carry output of the first negative full adder 302 is a positive carry output, and the carry output of the second negative full adder 304 is a negative carry output. It should be noted that, for clarity, Figure 3 The reference number of part of inverter 306 has been omitted.

[0062] In the first stage of the adder tree circuit 300, first negative full adders 302A to 302C can process individual bits of input values ​​A and B (e.g., positive inputs A0+B0, A1+B1, A2+B2), as shown. For example, first negative full adder 302A can receive positive inputs A0, B0 and a level carry input (G), and (via an inverter 306 applied to the carry output) produce a negative sum output (e.g., a logical inversion of the true sum) and a positive carry output. First negative full adder 302B can similarly receive positive inputs A1, B1 and a positive carry output from first negative full adder 302A via inverter 306 to produce a negative sum output and a positive carry output. The first negative full adder 302C can process the positive inputs A2 and B2 via inverter 306 and couple them with the positive carry output from the first negative full adder 302B to produce a negative sum output and a positive carry output.

[0063] The first stage of the adder tree circuit 300 is shown as comprising first negative full adders 302D to 302F for processing individual bits of the input values ​​C and D (e.g., positive inputs C0+D0, C1+D1, C2+D2). The first negative full adder 302D receives positive inputs C0 and D0 and a level carry input (G), producing a negative sum output and a positive carry output. The first negative full adder 302E processes positive inputs C1 and D1 and combines the positive carry output of the first negative full adder 302D to produce a negative sum output and a positive carry output (via inverter 306). Similarly, the first negative full adder 302F receives positive inputs C2 and D2 and the positive carry output of the first negative full adder 302E via inverter 306 to produce a negative sum output and a positive carry output via inverter 306.

[0064] In the second stage of the adder tree circuit 300, second negative full adders 304A to 304D sum the intermediate sum produced by the first negative full adder 302 in the first stage. Second negative full adder 304A receives the negative sum output from the first negative full adders 302A and 302D and a logic zero high carry input (V) representing inversion. Second negative full adder 304A can generate a positive sum output (e.g., a combination of the logic inverted and inverted carry inputs of the negative sum input) and a negative carry output (via an inverter 306 applied to the carry output). Second negative full adder 304B receives the negative sum output from the first negative full adders 302B and 302E and is coupled to the negative carry output from the second negative full adder 304A to generate a positive sum output and a negative carry output.

[0065] The second negative full adder 304C can process the negative sum output from the first negative full adders 302C and 302F and the negative carry output from the second negative full adder 304B to generate a positive sum output (provided to the third stage of the adder tree circuit 300) and a negative carry output via the corresponding inverter 306. The second negative full adder 304D can similarly receive the negative sum output from the first negative full adders 302B and 302D and combine it with the negative carry output from the second negative full adder 304C to generate a positive sum output (provided to the third stage of the adder tree circuit 300) and a negative carry output.

[0066] In the third stage, the first negative full adder 302G can receive the positive sum output of the second negative full adder 304A in the second stage, as well as the level value (G) and the level carry input (G) as the second operand (used as the identity operation input). The first negative full adder 302G can generate a negative sum output, which can be inverted by inverter 306 to produce the final logically correct least significant bit of the sum. The negative carry output of the first negative full adder 302G can be inverted by inverter 306 to generate a positive carry signal provided to the first negative full adder 302H.

[0067] The first negative full adder 302H can receive the positive sum output from the second negative full adder 304B of the second stage, pair it with the access level value (G) as the second operand, and receive the positive carry input from the first negative full adder 302G via inverter 306. The first negative full adder 302H can generate a negative sum output, which is inverted by inverter 306 to form the next valid bit of the final output. The negative carry output of the first negative full adder 302H is inverted by inverter 306 to generate a positive carry signal provided to the first negative full adder 302I.

[0068] The first negative full adder 302I processes the positive sum output from the second negative full adder 304C in the second stage, combined with the ground level value (G) as the second operand and the positive carry input from the inverter 306 coupled to the carry output of the first negative full adder 302H. The first negative full adder 302I generates a negative sum output, which is inverted by the inverter 306 to produce subsequent bits of the final output. The negative carry output of the first negative full adder 302I is inverted by the inverter 306 to generate a positive carry signal provided to the first negative full adder 302J.

[0069] The first negative full adder 302J can receive the positive sum output from the second negative full adder 304D in the second stage, the access level value (G) as the second operand, and the positive carry input from the inverter 306 coupled to the carry output of the first negative full adder 302I. The first negative full adder 302J can generate a negative sum output, which is inverted by the inverter 306 to form the most significant bit of the final output. The negative carry output of the first negative full adder 302J is inverted by the inverter 306 to pass the remaining carry signal to the higher-order bit.

[0070] The first negative full adder 302K can receive the positive sum output (identical to that of the first negative full adder 302J) from the second negative full adder 304D, paired with the access level value (G) as the second operand, and receive the positive carry output from the first negative full adder 302J via inverter 306. The first negative full adder 302K receives the output to maintain compatibility with two's complement arithmetic by preserving the state of the most significant bit for correct sign and overflow handling. The first negative full adder 302K can generate a negative sum output, which is inverted by inverter 306 to produce the final logically accurate result for the most significant bit. The negative carry output of the first negative full adder 302K can be ignored or retained as part of the overflow state signal.

[0071] Reference Figure 4 , Figure 4 A schematic diagram of an example adder tree circuit 400 according to some embodiments is shown. Adder tree circuit 400 includes a full adder circuit with a positive sum output and a negative carry output. Each component shown in adder tree circuit 400 can receive power from one or more voltage sources (such as power supply voltage VDD, shown as "V" for simplicity, which can be interpreted as a logic high input in this disclosure). Adder tree circuit 400 may include one or more logic gates and subcircuits, each subcircuit consisting of one or more logic gates. Logic gates can be electronic devices used to perform logical operations on one or more input signals to produce a single output signal.

[0072] Various embodiments of the circuitry and logic gates implementing the adder tree circuit 400 may include a variety of transistors. The transistors described in this disclosure may have a specific type (n-type or p-type), but the embodiments are not limited thereto. The transistors may be any suitable type, including, but not limited to, MOSFETs, CMOS transistors, PMOS, NMOS, BJTs, high-voltage transistors, high-frequency transistors, PFETs / NFETs, FinFETs, planar MOS transistors with convex source / drain terminals, nanosheet FETs, nanowire FETs, etc. It should be understood that... Figure 4 The adder tree circuit 400 shown can be included in any type of circuit, including but not limited to DCIM circuits, MAC circuits, multiplier circuits, or any other type of circuit that implements addition operations.

[0073] and Figure 2 The example shown is similar; in this example, the adder tree circuit 400 is shown as comprising three stages, where the first stage adds 3-bit input values ​​A (represented by bits A1, A2, and A3) to 3-bit input values ​​B (represented by bits B1, B2, and B3). The first stage also includes the sum of 3-bit input values ​​C (represented by bits C1, C2, and C3) and 3-bit input values ​​D (represented by bits D1, D2, and D3).

[0074] and Figure 2 Similar to adder tree circuit 200, adder tree circuit 400 can be used. Figure 1 One or more full adder circuits 100 are used to implement this. The adder tree circuit 400 is shown as comprising a set of first negative full adders 402A to 402I (sometimes collectively referred to as "first negative full adders 402") and a set of second negative full adders 404A to 404F (sometimes collectively referred to as "second negative full adders 404"). Each of the first negative full adders 402 and the second negative full adders 404 may contain... Figure 1 A full adder circuit 100 is constructed and implemented. Figure 1 Any function of the full adder circuit 100.

[0075] In the illustrated example, the first negative full adder 402 and the second negative full adder 404 can produce a logically inverted sum output (e.g., the negative sum output SB described in this disclosure) and a logically inverted carry output (e.g., the negative carry output CB described in this disclosure). However, the logically inverted carry outputs of the first negative full adder 402 and the second negative full adder 404 are respectively used as inputs to the inverter 406, such that the sum output of the first negative full adder 402 is a positive sum output, while the sum output of the second negative full adder 404 is a negative sum output. It should be noted that, for clarity, Figure 4 The reference number of part of inverter 406 has been omitted.

[0076] In the first level, with combination Figure 2 and Figure 3 The example arrangement is similar; the example adder tree circuit 400 can sum four 3-bit values ​​A, B, C, and D via a hierarchical configuration of a first negative full adder 402 and a second negative full adder 404. The first stage of the adder tree circuit 400 includes first negative full adders 402A, 402B, 402C, 402D and second negative full adders 404A and 404B. For inputs A and B, the first negative full adder 402A can receive positive inputs A0 and B0 and a level carry input (G), and generate a positive sum output via an inverter 406 coupled to the output. The second negative full adder 404A receives inverted inputs A1 and B1 (e.g., logically inverted versions of the actual values ​​A1 and B1, indicated by the horizontal lines above each value) and a negative carry output from the first negative full adder 402A, and generates a negative sum output via an inverter 406 coupled to the output. The first negative full adder 402B processes positive inputs A2 and B2 and a positive carry output from the second negative full adder 404A to generate a negative sum output, which is inverted by the inverter 406 to generate a positive sum output. As shown, the sum output generated by adders 402A, 404A, and 402B is provided as operands to the second stage.

[0077] In the first stage, for inputs C and D, the first negative full adder 402C similarly receives positive inputs C0 and D0 and a level carry input (G), producing a negative sum output, which is inverted by inverter 406 to produce a positive sum output. The second negative full adder 404B receives the logically inverted inputs C1 and D1 (indicated by the horizontal lines above each value) and the negative carry output from the first negative full adder 402C, producing a negative sum output via inverter 406 coupled to the output. The first negative full adder 402D processes positive inputs C2 and D2 and the positive carry output from the second negative full adder 404B to produce a negative sum, which is inverted by inverter 406 to produce a positive sum output. As shown, the sum outputs produced by adders 402C, 404B, and 402D are provided as operands to the second stage.

[0078] In the second stage, the adder tree circuit 400 includes first negative full adders 402E and 402F and second negative full adders 404C and 404D. The first negative full adder 402E receives the positive sum output from the first negative full adders 402A and 402C in the first stage and is connected to a level carry input (G). As shown, the first negative full adder 402E can generate a positive sum output provided to the third stage via inverter 406. The second negative full adder 404C can (via inverter 406) receive the negative sum output from the second negative full adders 404A and 404B in the first stage and the negative carry output from the first negative full adder 402E, and generate a negative sum output via a corresponding inverter. The first negative full adder 402F can (via inverter 406) process the negative sum output from the first negative full adders 402B and 402D in the first stage and the positive carry output from the second negative full adder 404C to generate a positive sum value via inverter 406. The second negative full adder 404D can receive the same negative sum output from the first negative full adders 402B and 402D and the negative carry output from the first negative full adder 402F to generate a negative sum output via inverter. The second negative full adder 404D receives the same input as the first negative full adder 402F to maintain two's complement compatibility.

[0079] The third stage (and the last stage in this example) of the adder tree circuit 400 is shown as comprising first negative full adders 402G to 402I and second negative full adders 404E and 404F. The first negative full adder 402G can (via inverter 406) receive the positive sum output from the first negative full adder 402E of the second stage, paired with the logic low value (G) and logic low carry input (G) as the second operand. The first negative full adder 402G can produce a negative sum output, which is inverted by inverter 406 to produce a final positive sum value for the least significant bit of the output. The negative carry output of the first negative full adder 402G can be provided to the second negative full adder 404E. The second negative full adder 404E can process the negative sum output from the second negative full adder 404C in the second stage, and combine it with the logic high value (V) as the inverted identity operand and the negative carry input from the first negative full adder 402G to produce a positive sum output, which is the next least significant bit of the resulting output.

[0080] The first negative full adder 402H can (via inverter 406) receive the negative sum output from the first negative full adder 402F of the second stage and the low logic value (G) as an identity operand, and receive the positive carry output from the second negative full adder 404E to produce a negative sum output, which is inverted via inverter 406 to become the positive output bit value of the third least significant bit of the output sum. The second negative full adder 404F can process the negative sum output from the second negative full adder 404D of the second stage, paired with the high logic value (V) as an inverted identity operand, and process the negative carry output from the first negative full adder 402H to produce a positive sum output as the second most significant bit of the output sum. The first negative full adder 402I can process the same input as the second negative full adder 404F, similar to other configurations described in this disclosure, to produce the most significant bit of the output sum while maintaining two's complement compatibility.

[0081] Although Figure 2 , Figure 3 and Figure 4 The adder tree circuits 200, 300, and 400 in the diagram are described as having three stages, but it should be understood that... Figure 4 , Figure 5 and Figure 6 Each stage of the adder tree circuits 200, 300, and 400 can contain any number of inputs, thus producing a ratio Figure 2 , Figure 3 and Figure 4 The three levels shown have more levels. For example, in some implementations, similar to... Figure 2 , Figure 3 and Figure 4The first two levels are supplemented with two additional levels to facilitate addition of the four additional values. For example, it can be done in... Figure 2 , Figure 3 and Figure 4 The third stage, as shown, combines the outputs of two second stages. For example, the output of the additional second stage can be provided as a second input operand to each adder in the third stage, instead of the identity input described in this disclosure. The output of the third stage can then be provided to a fourth stage, and so on, to combine any number of values. Furthermore, although combining... Figure 2 , Figure 3 and Figure 4 The described instance is described as adding 3 operands, but it should be noted that it can be used... Figure 1 A full adder circuit 100 (or a variant thereof) is used to accumulate operands with any bit width, for example by including additional adder circuitry in each adder stage to accommodate additional bits of each operand.

[0082] Reference Figure 5 , Figure 5 A schematic diagram of an example MAC circuit 500 according to some embodiments is shown. The MAC circuit 500 can implement a combination of Figure 2 , Figure 3 and Figure 4 The described one or more adder tree circuits. Each component shown in MAC circuit 500 can receive power from one or more voltage sources (such as power supply voltage VDD). MAC circuit 500 may include one or more logic gates and subcircuits, each subcircuit consisting of one or more logic gates. Logic gates can be electronic devices used to perform logical operations on one or more input signals to produce a single output signal.

[0083] The MAC circuit 500 is shown as including a MAC operand memory 502, an operand input register 504, a multiplier circuit 506, a first adder tree circuit 508, a set of partial sum registers 510, a second adder tree circuit 512, and a set of output registers 514. Various embodiments of the circuitry and logic gates implementing the MAC circuit 500 may include various transistors. The transistors described in this disclosure may have a specific type (n-type or p-type), but the embodiments are not limited thereto. The transistors may be any suitable type of transistor, including, but not limited to, MOSFETs, CMOS transistors, PMOS, NMOS, BJTs, high-voltage transistors, high-frequency transistors, PFETs / NFETs, FinFETs, planar MOS transistors with convex source / drain terminals, nanosheet FETs, nanowire FETs, etc. It should be understood that... Figure 5 The MAC circuit 500 shown can be included in any type of circuit, including but not limited to DCIM circuits, hardware accelerator circuits, memory circuits, or any other type of circuit that implements MAC operations.

[0084] The MAC operand memory 502 may include any type of memory circuitry, including but not limited to static random access memory (SRAM) arrays, dynamic random access memory (DRAM) circuitry, or other storage media capable of storing MAC operation operands. In some implementations, the MAC operand memory 502 may organize the stored data into columns and rows corresponding to the dimensions of the weight matrix or tensor, including but not limited to 8-bit weight values ​​used for machine learning operations. In some implementations, the MAC operand memory 502 may provide a read port to output selected 8-bit weight values ​​in parallel to the multiplier circuit 506, thereby enabling simultaneous access to multiple operands during operation.

[0085] The operand input register 504 may include a set of flip-flops for storing elements of the input vector. For example, the operand input register 504 may contain eight parallel 8-bit registers. In some implementations, the operand input register 504 may align the stored 8-bit values ​​with corresponding 8-bit weight values ​​from the MAC operand memory 502, such that each register pair forms a multiplicand-multiplier pair for the multiplier circuit 506. In some implementations, the operand input register 504 may include or be coupled to multiplexers that dynamically select input data from external memory interfaces and / or previous processing stages.

[0086] Multiplier circuit 506 can be any type of multiplier circuit, and can produce a product using a first operand stored in MAC operand memory 502 and a second operand stored in operand input register 504. In some implementations, multiplier circuit 506 may include an array of multiplier cells based on a lookup table (LUT). The multiplier cells can operate in parallel to improve overall multiplication performance. A portion of the product produced by multiplier circuit 506 can be provided as input to first adder tree circuit 508.

[0087] The first adder tree circuit 508 may contain a hierarchical structure of full adder levels, such as combining... Figure 2 , Figure 3 and Figure 4The adder tree circuits 200, 300, and 400 describe full adders. In one example, the first adder tree circuit 508 receives a set of 17-bit partial sums of inputs, which are then simplified to intermediate values ​​via the first stage of a 2:1 adder. Subsequent stages can further halve the number of partial sums while increasing the bit width of the multiple partial sums, so that after three stages, the output becomes a 19-bit value. In some implementations, pipelining registers may be included between the stages of the first adder tree circuit 508 to synchronize timing with the clock cycle of the MAC circuit 500. The partial sum register 510 may, for example, use an array of D-type flip-flops to store the 19-bit value.

[0088] The second adder tree circuit 512 may include a set of summing stages for combining 19-bit partial sums from the partial sum register 510. The second adder tree circuit 512 may include a hierarchical structure of full adder levels, such as combining... Figure 2 , Figure 3 and Figure 4 The adder tree circuits 200, 300, and 400 describe full adders. For example, the second adder tree circuit 512 can sum eight 19-bit values ​​into a single 22-bit result via two stages of processing, where the first stage reduces the input to 20-bit terms, the subsequent stage reduces the input to 21-bit terms, and the final output stage produces the final 22-bit output. The output register 514 can use, for example, one or more flip-flop circuits to obtain the output. In some implementations, the output register 514 may include error detection circuitry, such as parity check bits, to verify the integrity of the operation output value before transmission.

[0089] Figure 6 A schematic diagram of a portion of a multiplier circuit 600 according to some embodiments is shown, this portion may be included in a combination Figure 5 In the described MAC circuit 500, the multiplier circuit 600 may be or includes a combination of... Figure 5 The multiplier circuit 506 of the described MAC circuit 500 may have any structure and / or function. Each component shown in the multiplier circuit 600 may receive power from one or more voltage sources, such as the power supply voltage VDD. The multiplier circuit 600 may include one or more logic gates and subcircuits, each subcircuit consisting of one or more logic gates. The logic gates may be electronic devices used to perform logical operations on one or more input signals to produce a single output signal.

[0090] Multiplier circuit 600 is shown as including multiplexer array 602, a set of 11-bit adder circuits 604A to 604D, a set of 13-bit adder circuits 606A and 606B, and a 17-bit adder circuit 608. Any adder circuit in multiplier circuit 600 can be combined with... Figure 1 , Figure 2 , Figure 3 and Figure 4 The described arbitrary adder circuit is used for implementation. Various embodiments of the circuitry and logic gates implementing the multiplier circuit 600 may include various transistors. The transistors described in this disclosure may have a specific type (n-type or p-type), but the embodiments are not limited thereto. The transistors may be any suitable type, including but not limited to MOSFETs, CMOS transistors, PMOS, NMOS, BJTs, high-voltage transistors, high-frequency transistors, PFETs / NFETs, FinFETs, planar MOS transistors with convex source / drain terminals, nanosheet FETs, nanowire FETs, etc. It should be understood that... Figure 6 The multiplier circuit 600 shown can be included in any type of circuit, including but not limited to DCIM circuits, hardware accelerator circuits, memory circuits, or any other type of circuit that implements MAC operations.

[0091] In this example, multiplexer array 602 can provide outputs as part of multiplier circuit 600 to produce partial sums, which are accumulated using 11-bit adder circuits 604A to 604D, 13-bit adder circuits 606A and 606B, and 17-bit adder circuit 608. In one example, multiplexer array 602 (e.g., a MUX4 array) can provide eight 9-bit outputs. Each 11-bit adder circuit 604A to 604D can accumulate a corresponding pair of 9-bit outputs from multiplexer array 602. Each 11-bit adder circuit 604A to 604D can be used in combination with... Figure 2 , Figure 3 and Figure 4 One or more of the described adder circuit configurations can be used to implement this. For example, 11-bit adder circuits 604A to 604D may comprise a multi-stage adder tree that adds each output of the multiplexer array 602 to produce an 11-bit output. Each 11-bit output can be provided as input to a corresponding 13-bit adder circuit 606A, 606B, which in turn can be provided as input to a 17-bit adder circuit 608. The 17-bit adder circuit 608 can accumulate the outputs of the 13-bit adder circuits 606A, 606B to produce a 17-bit partially multiplied output.

[0092] Figure 6 A schematic diagram of a portion of a multiplier circuit 600 according to some embodiments is shown, which may be included in a combination Figure 5 In the described MAC circuit 500, the multiplier circuit 600 may be or includes a combination of... Figure 5The multiplier circuit 506 of the described MAC circuit 500 may have any structure and / or function. Each component shown in the MAC circuit 500 may receive power from one or more voltage sources, such as the power supply voltage VDD. The MAC circuit 500 may include one or more logic gates and subcircuits, each subcircuit consisting of one or more logic gates. The logic gates may be electronic devices used to perform logical operations on one or more input signals to produce a single output signal.

[0093] The multiplier circuit 600 is shown as including a multiplexer array 602, a set of 11-bit adder circuits 604A to 604D, a set of 13-bit adder circuits 606A and 606B, and a 17-bit adder circuit 608. Various embodiments of the circuitry and logic gates implementing the MAC circuit 500 may include various transistors. The transistors described in this disclosure may have a specific type (n-type or p-type), but the embodiments are not limited thereto. The transistors may be any suitable type of transistor, including, but not limited to, MOSFETs, CMOS transistors, PMOS, NMOS, BJTs, high-voltage transistors, high-frequency transistors, PFETs / NFETs, FinFETs, planar MOS transistors with convex source / drain terminals, nanosheet FETs, nanowire FETs, etc. It should be understood that... Figure 5 The MAC circuit 500 shown can be included in any type of circuit, including but not limited to DCIM circuits, hardware accelerator circuits, memory circuits, or any other type of circuit that implements MAC operation.

[0094] Reference Figure 7 , Figure 7 A schematic diagram of an example adder tree circuit 700 according to some embodiments is shown. The adder tree circuit 700 may include a combination of... Figure 5 The described MAC circuit 500 includes one or more adder tree circuits (e.g., a first adder tree circuit 508, a second adder tree circuit 512, etc.). Each component shown in the adder tree circuit 500 can receive power from one or more voltage sources (such as the power supply voltage VDD). The MAC circuit 500 may include one or more logic gates and sub-circuits, each sub-circuit consisting of one or more logic gates. The logic gates can be electronic devices used to perform logical operations on one or more input signals to produce a single output signal.

[0095] The adder tree circuit 700 is shown as comprising a set of 17-bit partial product circuits 702, a set of 17-bit adder circuits 704, a set of 18-bit adder circuits 706, a set of 19-bit adder circuits 708, a set of 20-bit adder circuits 710, a set of 21-bit adder circuits 712, and a set of 22-bit adder circuits 714. Any adder circuit in the adder tree circuit 700 can be used in combination. Figure 1 , Figure 2 , Figure 3 and Figure 4 The described arbitrary adder circuit is used for implementation. Various embodiments of the circuit and logic gates implementing the adder tree circuit 700 may include various transistors. The transistors described in this disclosure may have a specific type (n-type or p-type), but the embodiments are not limited thereto. The transistors may be any suitable type of transistor, including but not limited to MOSFETs, CMOS transistors, PMOS, NMOS, BJTs, high-voltage transistors, high-frequency transistors, PFETs / NFETs, FinFETs, planar MOS transistors with convex source / drain terminals, nanosheet FETs, nanowire FETs, etc. It should be understood that... Figure 7 The adder tree circuit 700 shown can be included in any type of circuit, including but not limited to DCIM circuits, hardware accelerator circuits, memory circuits, or any other type of circuit that implements MAC operations.

[0096] The 17-bit partial product 702 can be achieved through, for example... Figure 6 It is generated by one or more multiplier circuits 600, which can be used as Figure 5 This refers to a portion of the MAC circuit 500. To accumulate partial products, the adder tree circuit 700 can implement a hierarchical structure of multiple adder circuits. For example, a combination of... Figure 4 , Figure 5 and Figure 6 The described adder tree circuits 200, 300, or 400 implement any one of the following: 17-bit adder circuit group 704, 18-bit adder circuit group 706, 19-bit adder circuit group 708, 20-bit adder circuit group 710, 21-bit adder circuit group 712, and 22-bit adder circuit group 714. In some implementations, the output of adder tree circuit 700 can be a 23-bit output value, which can be stored as part of a 32-bit floating-point value in, for example, an output register (e.g., ...). Figure 5 In the output register 514).

[0097] Reference Figure 8 , Figure 8 A schematic diagram of an example two-stage adder tree circuit 800 according to some embodiments is shown. The two-stage adder tree circuit 800 includes a full adder circuit with a negative sum output and a negative carry output (e.g., Figure 1 The adder tree circuit 800 (as shown in the adder tree circuit 800) can receive power from one or more voltage sources (such as power supply voltage VDD, shown as "V" for simplicity, which can be interpreted as a logic high input in this disclosure). The adder tree circuit 800 may include one or more logic gates and sub-circuits, each of which may be composed of one or more logic gates. The logic gates may be electronic devices used to perform logical operations on one or more input signals to produce a single output signal.

[0098] Various embodiments of the circuitry and logic gates implementing the adder tree circuit 800 may include a variety of transistors. The transistors described in this disclosure may have a specific type (n-type or p-type), but the embodiments are not limited thereto. The transistors may be any suitable type, including, but not limited to, MOSFETs, CMOS transistors, PMOS, NMOS, BJTs, high-voltage transistors, high-frequency transistors, PFETs / NFETs, FinFETs, planar MOS transistors with convex source / drain terminals, nanosheet FETs, nanowire FETs, etc. It should be understood that... Figure 8 The adder tree circuit 800 shown can be included in any type of circuit, including but not limited to DCIM circuits, MAC circuits, multiplier circuits, or any other type of circuit that implements addition operations.

[0099] and Figure 2 The example shown is similar; in this example, the adder tree circuit 800 illustrates the first stage of summation. In the first stage of summation, the 3-bit input value A (represented by bits A1, A2, and A3) is added to the 3-bit input value B (represented by bits B1, B2, and B3). The adder tree circuit 800 is shown as comprising a set of first negative full adders 802A to 802D (sometimes collectively referred to as "first negative full adders 802") and a set of second negative full adders 804A to 804C (sometimes collectively referred to as "second negative full adders 804"). Each of the first negative full adders 802 and the second negative full adders 804 may contain... Figure 1 A full adder circuit 100 is constructed and implemented. Figure 1 Any function of the full adder circuit 100.

[0100] In the first level, the operation of the instance adder tree circuit 800 is similar to Figure 2 The adder tree circuit 200 includes a first adder 802A that calculates the negative sum of A0 and B0, a second adder 804A that calculates the positive output sum of negative A1 and negative B1, and a first adder 802B that calculates the negative sum of A2 and B2. Each sum carries the corresponding carry value (e.g., combined with...). Figure 2 (as described above), and provide the corresponding sum output to the second level.

[0101] and Figure 2Similarly, the example adder tree circuit 800 includes second negative adders 804B and 804C and first negative adders 802C and 802D. As shown, the first negative adder 804B receives the negative sum, the identity value (e.g., shown here as "V", or logic high, indicating that the actual sum is zero), and the logic high carry input (indicating that the actual carry input is zero) from the first adder 802A. The second negative adder 804B produces the least significant positive sum output and the positive carry passed to the first adder 802C.

[0102] The first negative adder 802C receives the positive sum from the second adder 804A, the positive carry output from the second adder 804B, and a logic low identity input (indicating that the actual sum input is zero). The first negative adder 802C generates the next least significant negative sum output and the negative carry passed to the second adder 804C. In some implementations, an inverter may be provided to invert the negative sum output of the first negative adder 802C to a positive output. In some implementations, an inverter may not be provided, allowing the negative sum output to be provided as an input to the next stage in the adder tree circuit.

[0103] The second negative adder 804C receives the negative sum from the first adder 802B, the negative carry output from the first adder 802C, and a high logic identity input (indicating that the actual sum input is zero). The second negative adder 804C generates the next least significant positive sum output and the positive carry passed to the first negative adder 802D. The first negative adder 802D receives the same negative sum from the first adder 802B, the positive carry output from the second negative adder 804C, and a high logic identity input. The first negative adder 802D generates the most significant positive sum output. The first negative adder 802D receives the same operand input as the second negative adder 804C to maintain two's complement compatibility, as described in this disclosure. In some implementations, an inverter may be provided to invert the negative sum output of the first negative adder 802C to a positive output. In some implementations, an inverter may not be provided, allowing the negative sum output to be used as input to the next stage in the adder tree circuit.

[0104] Figure 9 A flowchart illustrating an example method 900 for operating one or more adder circuits as described in this disclosure is shown. Method 900 or portions thereof may be derived from one or more components of an arithmetic system (e.g., Figure 5 The MAC circuit 500 in the present disclosure, and one or more adder tree circuits (e.g., the MAC circuit 500 in the present disclosure), and one or more adder tree circuits described in this disclosure. Figure 2 , Figure 3 , Figure 4 and Figure 8 Adder tree circuits 200, 300, 400, 800, etc.) and / or use adder circuits (e.g., Figure 1The adder circuit 100 in the middle is used to perform this. It should be noted that method 900 is merely an example and is not intended to limit this disclosure. Therefore, it can be understood that it can be applied to other methods. Figure 9 Additional operations are provided before, during, and after Method 900, and this disclosure may only briefly describe some of these other operations.

[0105] In summary, method 900 begins with operation 902, which includes the following steps: receiving a first operand and a second operand as input through a first adder circuit of the adder tree circuit. Method 900 continues with operation 904, which includes the following steps: generating a first negative sum value through the first adder circuit, wherein the first negative sum value is the logical inversion of the first operand and the second operand. Method 900 continues with operation 906, which includes the following steps: receiving the negative sum value and an additional operand as input through a second adder circuit of the adder tree circuit. Method 900 continues with operation 908, which includes the following steps: generating a positive sum value as output through the second adder circuit, wherein the positive sum value is equal to the sum of the first operand and the second operand plus the logical inversion of the additional operand.

[0106] Referring to operation 902, method 900 may include the following steps: via an adder tree circuit (e.g., Figure 2 , Figure 3 , Figure 4 and Figure 8 The first adder circuit (e.g., first adder 202A, etc.) of any of the adder tree circuits 200, 300, 400, 800, etc. in the example receives a first operand (e.g., A0, etc.) and a second operand (e.g., B0, etc.) as inputs. The first adder circuit can be a negative full adder (e.g., the first negative full adder 202A of adder tree circuit 200) to process inputs that are not logically inverted. For example, the first operand and the second operand can be single bits of the input values ​​provided to the first adder circuit (e.g., positive inputs A0 and B0 of input values ​​A and B, respectively). The first adder circuit can also receive carry inputs, such as level carry inputs (G). Operands can be transferred from upstream components (e.g., input registers or pre-stages of adder tree circuits) and can be coupled to the first adder circuit via conductive paths or signal lines.

[0107] Referring to operation 904, method 900 may include the following steps: generating a first negative sum value by means of a first adder circuit, wherein the first negative sum value is the logical inversion of a first operand and a second operand. The first negative sum value may be generated by the first adder circuit using its internal logic gates and transistors (e.g., such as...). Figure 1The first adder circuit can also generate a corresponding negative carry output, which can be transmitted to subsequent adder circuits in the adder tree, as described in this disclosure. Figure 2 , Figure 3 , Figure 4 and Figure 8 As described above. In some implementations, the first adder circuit may contain up to 24 transistors, such as in combination with... Figure 1 As stated above.

[0108] Referring to operation 906, method 900 may include the following steps: receiving a negative sum value and an additional operand as input via a second adder circuit of the adder tree circuit. The second adder circuit may be a negative full adder that processes inverted inputs (e.g., the second negative full adder 204A of adder tree circuit 200). For example, the negative sum value of the first adder circuit may be provided as input, along with the additional operand, to the second adder circuit, which may be another logic inverted input (e.g., another negative sum output of another adder circuit in the adder tree, etc.). In some implementations, the additional operand may include an identity operand (e.g., a logic high or low value) to preserve intermediate values ​​during hierarchical summation. The second adder circuit may receive the input via a conductive path or signal line coupled to the input, as described in this disclosure.

[0109] Referring to operation 908, method 900 may include the following steps: generating a positive sum value as output through a second adder circuit, wherein the positive sum value is equal to the sum of the first operand and the second operand plus the logical inversion of the additional operand. The second adder circuit can be a negative adder circuit, therefore, it can be based on... Figure 1 The circuitry processes negative values ​​(e.g., active low operands) to produce positive (active high) outputs. For example, a second negative full adder can add a negative sum from a first adder circuit to additional operands (e.g., another inverted sum from another carry circuit, a logic high identity signal, etc.) to produce a positive sum output. The negative adder effectively cancels out the initial inversion applied by the first adder circuit, resulting in the correct logical sum of the original operands. The positive sum can then be passed to downstream components, such as subsequent stages of the adder tree or output registers, for further processing.

[0110] One aspect of this disclosure provides an adder tree device. The adder tree device includes a first adder circuit and a second adder circuit. The first adder circuit receives a first operand and a second operand as inputs to the first adder circuit and generates a negative sum value, wherein the negative sum value is the logical inversion of the sum of the first operand and the second operand. The second adder circuit receives the first negative sum value and an additional operand as inputs to the second adder circuit and generates a positive sum value as outputs to the second adder circuit, wherein the positive sum value is equal to the sum of the first operand and the second operand plus the logical inversion of the additional operand.

[0111] In some embodiments of the adder tree device in this respect, one or more of the first adder circuit and the second adder circuit include up to 24 transistors.

[0112] In some embodiments of the adder tree device in this respect, both the first adder circuit and the second adder circuit contain up to 24 transistors.

[0113] In some embodiments of the adder tree device in this regard, the adder tree device further includes a third adder circuit. The third adder circuit is used to receive a third operand, a fourth operand, and a carry output from the first adder circuit.

[0114] In some embodiments of the adder tree device in this respect, the first adder circuit and the third adder circuit are part of the first stage, and the second adder circuit is part of the second stage.

[0115] In some embodiments of the adder tree device in this respect, the adder tree device further includes an inverter. The inverter is used to receive the negative sum output generated by the first adder circuit. The third adder circuit is used to receive the carry output via the output of the inverter.

[0116] In some embodiments of the adder tree device in this respect, the first operand and the second operand are logically inverted.

[0117] In some embodiments of the adder tree device in this respect, a first adder circuit is coupled to a multiplier circuit to receive a first operand and a second operand from the multiplier circuit.

[0118] In some embodiments of the adder tree device in this respect, the adder tree device further includes a third adder circuit. The third adder circuit is used as part of a third stage and is used to receive a positive sum value as input to the third adder circuit.

[0119] In some embodiments of the adder tree device in this respect, the third adder circuit is further configured to receive a logic low input as a second additional operand, and to use the second additional operand to generate a negative sum value as the output of the third adder circuit.

[0120] In another aspect of this disclosure, a multiply-accumulate (MAC) circuit is provided. The MAC circuit includes a multiplier circuit and an adder tree circuit. The multiplier circuit generates a plurality of partial products. The adder tree circuit receives the plurality of partial products, generates an intermediate sum corresponding to a first corresponding sum of at least two of the plurality of partial products that has been logically inverted, and generates an output sum based on the intermediate sum and a second operand. The output sum corresponds to a second corresponding sum of the intermediate sum and the second operand that has been logically inverted.

[0121] In some embodiments of this other side of the MAC circuit, the multiplier circuit includes at least one lookup table.

[0122] In some embodiments of this other side of the MAC circuit, the adder tree circuit comprises multiple adder circuits. Each of the adder circuits contains up to 24 transistors.

[0123] In some embodiments of this other side of the MAC circuit, the intermediate sum is generated by a first adder circuit among a plurality of adder circuits and provided as input to a second adder circuit among a plurality of adder circuits having a second operand, to produce an output sum.

[0124] In some embodiments of this other side of the MAC circuit, the multiply-accumulate circuit further includes a second adder tree circuit. The second adder tree circuit is used to receive the output sum of the adder tree circuit and to generate a second output sum based on the output sum.

[0125] In some embodiments of this other side of the MAC circuit, the second operand is a logic high operand. The adder tree circuit is further used to provide the intermediate sum as input to the adder circuit having a logic high operand, and to use the adder circuit to generate the output sum.

[0126] In some embodiments of this other side of the MAC circuit, the adder tree circuit is further used to generate at least one of the intermediate sum and the carry value via the inverters at the respective outputs of the adder circuit.

[0127] Another aspect of this disclosure provides an operating method. The operating method includes the following steps: receiving a first operand and a second operand as inputs to a first adder circuit of an adder tree circuit; generating a negative sum value through the first adder circuit, wherein the negative sum value is the logical inversion of the sum of the first operand and the second operand; receiving the negative sum value and a second value as inputs to a second adder circuit of the adder tree circuit; and generating a positive sum value as the output of the second adder circuit, wherein the positive sum value is equal to the sum of the first operand and the second operand plus the logical inversion of the second value.

[0128] In some embodiments of the operating method of this other aspect, the operating method further includes the step of generating a negative carry value through a first adder circuit, wherein the negative carry value is the logical inversion of the sum of the first operand and the second operand.

[0129] In some embodiments of this other aspect of the operating method, the operating method further includes the step of providing a negative carry value to a third adder circuit via a first adder circuit.

[0130] As used herein, the terms “about” and “approximately” generally refer to plus or minus 10% of the stated value. For example, about 0.5 would include 0.45 and 0.55, about 10 would include 9 to 11, and about 1000 would include 900 to 1100.

[0131] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that they can be modified, substituted, and altered in various ways without departing from the spirit and scope of this disclosure.

Claims

1. An adder tree device, comprising: The first adder circuit is configured to receive a first operand and a second operand as inputs; The negative sum is generated, wherein the negative sum is the logical inverse of the sum of the first operand and the second operand; The second adder circuit is configured to: receive the negative sum value and the additional operand as input; and generate a positive sum value as output, wherein the positive sum value is equal to the sum of the first operand and the second operand plus the logical inversion of the additional operand.

2. The adder tree apparatus according to claim 1, wherein, One or more of the first adder circuit and the second adder circuit include up to 24 transistors.

3. The adder tree apparatus according to claim 2, wherein, Both the first adder circuit and the second adder circuit include up to 24 transistors.

4. A multiply-accumulate (MAC) circuit, comprising: The multiplier circuit is configured to generate multiple partial products; as well as The adder tree circuit is configured as follows: Receive the plurality of partial products; Generate an intermediate sum, which corresponds to the logical inversion of the first corresponding sum of at least two of the plurality of partial products; and An output sum is generated based on the intermediate sum and the second operand, wherein the output sum corresponds to the logical inversion of the second correspondence sum of the intermediate sum and the second operand.

5. The multiplication and accumulation circuit according to claim 4, wherein, The multiplier circuit includes at least one lookup table.

6. The multiplication and accumulation circuit according to claim 4, wherein, The adder tree circuit includes multiple adder circuits, each of which includes up to 24 transistors.

7. The multiplication and accumulation circuit according to claim 6, wherein, The intermediate sum is generated by the first adder circuit in the plurality of adder circuits and, together with the second operand, is provided as input to the second adder circuit in the plurality of adder circuits to generate the output sum.

8. A method for operating an adder circuit, comprising: The first adder circuit of the adder tree circuit receives the first operand and the second operand as input; The first adder circuit generates a negative sum value, wherein the negative sum value is the logical inverse of the sum of the first operand and the second operand; The second adder circuit of the adder tree circuit receives the negative sum value and the second value as input; and The second adder circuit generates a positive sum as the output, wherein the positive sum is equal to the sum of the first operand and the second operand plus the logical inversion of the second value.

9. The method according to claim 8, further comprising: The first adder circuit generates a negative carry value, wherein the negative carry value is the logical inversion of the sum of the first operand and the second operand.

10. The method of claim 9, further comprising: The negative carry value is provided to the third adder circuit through the first adder circuit.

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