Program compilation methods, apparatus, electronic devices, storage media and computer program products

Abstract

This application discloses a program compilation method, apparatus, electronic device, storage medium, and computer program product. The method includes: compiling a first source code using a heterogeneous compiler to obtain a first executable file; compiling a second source code using the heterogeneous compiler to obtain a second executable file; and parsing the first executable file and the second executable file using a heterogeneous runtime, and sending the first executable file and the second executable file to a resource pool for execution.

Description

Technical Field

[0001] This application relates to the field of artificial intelligence technology, and in particular to a program compilation method, apparatus, electronic device, storage medium, and computer program product. Background Technology

[0002] In related technologies, the development of heterogeneous applications is highly complex and difficult in scenarios where multiple heterogeneous computing resources are integrated in cloud computing. Summary of the Invention

[0003] To address the related technical problems, embodiments of this application provide a program compilation method, apparatus, electronic device, storage medium, and computer program product.

[0004] The technical solution of this application embodiment is implemented as follows:

[0005] This application provides a program compilation method, including:

[0006] The first source code is compiled using a heterogeneous compiler to obtain the first executable file;

[0007] The second source code is compiled using the heterogeneous compiler to obtain a second executable file;

[0008] During heterogeneous runtime, the first executable file and the second executable file are parsed, and the first executable file and the second executable file are sent to the resource pool for execution.

[0009] In the above scheme, the first source code includes computation graph source code developed based on a machine learning framework and first information developed based on a unified programming model. The first information represents relevant information of the computation graph model file. The first executable file represents an executable file in computation graph format, which can be adapted to different hardware resources in the resource pool. The second source code represents general computing source code developed based on the unified programming model. The second executable file represents an executable file in general computing format, which can be adapted to different hardware resources in the resource pool.

[0010] In the above scheme, the computation graph source code includes a computation graph model file, and the computation graph model file contains the computation graph.

[0011] In the above scheme, the second source code includes host-side source code and device-side source code. The device-side source code contains the source code of operators used for parallel acceleration computing in general computing, and the host-side source code is used to control the execution logic of the operators on the device side.

[0012] In the above scheme, the step of compiling the first source code using a heterogeneous compiler to obtain the first executable file includes:

[0013] The first executable file is obtained by compiling the first information and the computational graph model file using the heterogeneous compiler.

[0014] In the above scheme, the step of compiling the first information and the computational graph model file using the heterogeneous compiler to obtain the first executable file includes:

[0015] The computation graph model file is compiled to obtain a first assembly file in computation graph format;

[0016] The first assembly file and the first information are linked to obtain the first executable file.

[0017] In the above scheme, compiling the computation graph model file to obtain a first assembly file in computation graph format includes:

[0018] Convert the computational graph model file into a first intermediate representation;

[0019] The first intermediate representation is graph optimized to obtain the first assembly file.

[0020] In the above scheme, the step of compiling the second source code using the heterogeneous compiler to obtain the second executable file includes:

[0021] The source code of the operator contained in the second source code is read through the heterogeneous compiler;

[0022] The source code of the operator and the source code of the host side are compiled to obtain the second executable file.

[0023] In the above scheme, compiling the source code of the operator and the host-side source code to obtain the second executable file includes:

[0024] The source code of the operator is compiled to obtain a second assembly file;

[0025] The host-side source code is compiled to obtain a third assembly file;

[0026] The second assembly file and the third assembly file are linked together to obtain the second executable file.

[0027] In the above scheme, compiling the source code of the operator to obtain a second assembly file includes:

[0028] Convert the source code of the operator into a second intermediate representation;

[0029] The second assembly file is generated based on the second intermediate representation.

[0030] In the above scheme, the heterogeneous runtime is used to manage the hardware resources in the resource pool, and to send the first executable file and the second executable file to the runtime of the hardware resources in the resource pool.

[0031] This application also provides a program compilation apparatus, including:

[0032] The first compilation unit is used to compile the first source code using a heterogeneous compiler to obtain the first executable file;

[0033] The second compilation unit is used to compile the second source code using the heterogeneous compiler to obtain the second executable file;

[0034] The parsing unit is used to parse the first executable file and the second executable file through heterogeneous runtime, and send the first executable file and the second executable file to the resource pool for execution.

[0035] This application also provides an electronic device, including: a processor and a communication interface; wherein,

[0036] The processor is configured to compile a first source code using a heterogeneous compiler to obtain a first executable file; and to compile a second source code using the heterogeneous compiler to obtain a second executable file;

[0037] The communication interface is used to parse the first executable file and the second executable file through heterogeneous runtime, and send the first executable file and the second executable file to the resource pool for execution.

[0038] This application also provides an electronic device, including a processor and a memory for storing a computer program capable of running on the processor.

[0039] When the processor runs the computer program, it executes the steps of any of the above methods.

[0040] This application also provides a storage medium storing a computer program thereon, which, when executed by a processor, implements the steps of any of the above methods.

[0041] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of any of the above methods.

[0042] In the program compilation methods, apparatuses, electronic devices, storage media, and computer program products provided in the various embodiments of this application, a first executable file is obtained by compiling a first source code using a heterogeneous compiler; a second executable file is obtained by compiling a second source code using the same heterogeneous compiler; and the first and second executable files are parsed and sent to a resource pool for execution using a heterogeneous runtime. In the above scheme, different types of source code can be compiled using the same heterogeneous compiler, and the compiled executable files can be sent to a resource pool for execution using a heterogeneous runtime. This simplifies the compilation difficulty and complexity of the source code, reduces the development complexity and difficulty of heterogeneous applications, and improves the flexibility and convenience of developing heterogeneous applications. Attached Figure Description

[0043] Figure 1 A schematic diagram of the existing computation graph compilation method;

[0044] Figure 2 This is a schematic flowchart of a program compilation method according to an embodiment of this application;

[0045] Figure 3 This is a schematic diagram of another program compilation method according to an embodiment of this application;

[0046] Figure 4 This is a schematic diagram of a program compilation device according to an embodiment of this application;

[0047] Figure 5 This is a schematic diagram of the electronic device structure according to an embodiment of this application. Detailed Implementation

[0048] Currently, technologies such as artificial intelligence and big data are developing rapidly, giving rise to various computing resources such as Graphics Processing Units (GPUs), Field Programmable Gate Arrays (FPGAs), and Data Streaming Accelerators (DAS). Cloud computing presents scenarios involving the integration of various heterogeneous computing resources. Currently, AI models are mostly expressed using computation graphs in artificial intelligence (AI) scenarios. A computation graph is a graphical model that expresses the relationships between computational operations, helping to optimize and schedule complex computational operations. Existing computation graph compilation methods include... Figure 1As shown, when writing the source code of a computation graph, it is necessary to bind it to a specific hardware platform. That is, the source code of the computation graph is bound to the hardware. When the computation graph needs to run on other hardware platforms, it is necessary to select new hardware to develop the source code of the computation graph. This makes development difficult and has poor portability.

[0049] Current cloud computing supports programming using a unified programming model, but only supports compilation using handwritten operators. It cannot support input in the form of computation graphs, nor can it support the compilation of computation graphs. In scenarios where various heterogeneous computing resources are integrated in cloud computing, computation graphs and handwritten operators cannot achieve cross-platform operation, resulting in high complexity and difficulty in developing heterogeneous applications.

[0050] Based on this, in various embodiments of this application, a first executable file is obtained by compiling the first source code using a heterogeneous compiler; a second executable file is obtained by compiling the second source code using the same heterogeneous compiler; and the first and second executable files are parsed by a heterogeneous runtime, and then sent to a resource pool for execution. The above scheme simplifies the compilation difficulty and complexity of the source code by using the same heterogeneous compiler to compile different types of source code, and sends the compiled executable files to a resource pool for execution via a heterogeneous runtime. This reduces the complexity and difficulty of developing heterogeneous applications and improves the flexibility and convenience of developing heterogeneous applications.

[0051] The present application will now be described in further detail with reference to the accompanying drawings and embodiments.

[0052] This application provides a program compilation method applied to electronic devices, including terminals and / or servers. Figure 2 As shown, the method includes:

[0053] Step 201: Compile the first source code using a heterogeneous compiler to obtain the first executable file.

[0054] Here, the electronic device obtains the first source code, inputs it into a heterogeneous compiler, compiles it to obtain the first executable file, and then sends the first executable file to the heterogeneous runtime. The runtime is a set of software libraries and tools provided by the electronic device, offering necessary services and support during program execution. Its main function is to simplify the development process, provide high-level abstractions, and allow developers to focus on program logic while shielding them from low-level hardware details. The heterogeneous runtime is a runtime built on top of multiple device runtimes, managing memory, task scheduling, and other operations across these runtimes. It provides a higher level of abstraction on top of the runtimes provided by each electronic device, helping developers shield themselves from the low-level hardware details of various electronic devices.

[0055] To enable computation graphs and handwritten operators to run across hardware platforms and improve the flexibility and convenience of developing heterogeneous applications, in one embodiment, the first source code includes computation graph source code developed based on a machine learning framework and first information developed based on a unified programming model. The first information represents relevant information of the computation graph model file; the first executable file represents an executable file in the computation graph format, which can be adapted to different hardware resources in the resource pool.

[0056] Here, users, developers, or AI developers develop computation graph source code based on machine learning frameworks and first information based on a unified programming model, resulting in the first source code. The computation graph source code primarily contains coarse-grained tensor computations, such as convolution operations in deep learning, like 2D convolution Convd2d. Developing first information based on the unified programming model can be understood as annotating the relevant source code for constructing the computation graph model file with macro comments. For example, AI developers develop source code based on the unified programming model's hardware and software stack, writing relevant information about the computation graph model file, and annotating the relevant source code for constructing the computation graph model file with macro comments to generate the first information. The first information can be used to locate and / or control the computation graph model file from the computation graph source code; the relevant information about the computation graph model file may include, but is not limited to, one or more of the following: the name, size, path, and control-related information of the computation graph model file.

[0057] It should be noted that machine learning frameworks include, but are not limited to, deep learning frameworks, AI learning frameworks, and one or more AI frameworks. The first source code can be described as the first source code or the first source program. The resource pool includes various different hardware resources, including but not limited to one or more of GPUs, FPGAs, and DSAs; hardware resources can be described as computing resources. The first executable file is adaptable to different hardware resources in the resource pool; that is, the first executable file can be executed or run on different hardware resources in the resource pool, meaning the first executable file can run across hardware platforms.

[0058] To optimize and schedule complex computational operations, the first source code includes source code related to the computation graph. Based on this, in one embodiment, the computation graph source code includes a computation graph model file, which contains the computation graph.

[0059] Here, the computation graph can contain coarse-grained tensor computations.

[0060] The electronic device obtains the first source code, inputs the first source code into the heterogeneous compiler, compiles the first source code by the heterogeneous compiler to generate an executable file in the form of a computation graph, thus obtaining the first executable file; the first executable file is then sent to the heterogeneous runtime by the heterogeneous compiler.

[0061] To compile the computation graph, in one embodiment, the compilation of the first source code using a heterogeneous compiler to obtain the first executable file includes:

[0062] The first executable file is obtained by compiling the first information and the computational graph model file using the heterogeneous compiler.

[0063] Here, the electronic device can parse the first source code through a heterogeneous compiler to obtain the first parsing result; based on the first information and the first parsing result, it can read, search or identify the computation graph model file from the computation graph source code, and compile the first information and the computation graph model file through the heterogeneous compiler to obtain the first executable file.

[0064] To compile the computation graph, in one embodiment, the first executable file is obtained by compiling the first information and the computation graph model file using the heterogeneous compiler, including:

[0065] The computation graph model file is compiled to obtain a first assembly file in computation graph format;

[0066] The first assembly file and the first information are linked to obtain the first executable file.

[0067] Here, the electronic device compiles the computation graph model file using a heterogeneous compiler to obtain a first assembly file in computation graph format; the first information and the first assembly file in computation graph format are linked using the heterogeneous compiler to obtain a first executable file. For example, the relevant information of the computation graph contained in the first assembly file is replaced based on the first information to obtain the first executable file.

[0068] To improve the compilation efficiency of the first source code and the accuracy of the computation graph, in one embodiment, compiling the computation graph model file to obtain a first assembly file in computation graph format includes:

[0069] Convert the computational graph model file into a first intermediate representation;

[0070] The first intermediate representation is graph optimized to obtain the first assembly file.

[0071] Here, the electronic device uses a heterogeneous compiler to convert the computation graph model file into a first intermediate representation (IR), and performs graph optimization on the first intermediate representation to obtain a first assembly file.

[0072] In practical applications, heterogeneous compilers can include general-purpose compilers and graph compilers. When a first parsing result is obtained by parsing the first source code using a heterogeneous compiler, the general-purpose compiler frontend can read the computation graph model file from the computation graph source code based on this result. The computation graph model file is then treated as device-side code and sent to the graph compiler frontend. The graph compiler frontend sends the computation graph model file to the graph compiler middleware for parsing. After processing by the graph compiler middleware, the computation graph model file is converted into a first intermediate representation of Open Neural Network Exchange (ONNX). The graph compiler then performs graph optimization on this first intermediate representation to obtain a first assembly file in computation graph format. Finally, the graph compiler links the first assembly file with the first information to obtain a first executable file.

[0073] Step 202: Compile the second source code using the heterogeneous compiler to obtain the second executable file.

[0074] Here, the electronic device obtains the second source code, inputs the second source code into the heterogeneous compiler, compiles the second source code by the heterogeneous compiler to obtain the second executable file; the heterogeneous compiler sends the second executable file to the heterogeneous runtime.

[0075] To enable computation graphs and handwritten operators to run across hardware platforms and to improve the flexibility and convenience of developing heterogeneous applications, in one embodiment, the second source code represents a general-purpose computation source code developed based on a unified programming model; the second executable file represents an executable file in a general-purpose computation format that can be adapted to different hardware resources in the resource pool.

[0076] Here, users, developers, or general-purpose computing developers develop general-purpose computing source code based on the unified programming model's hardware and software stack, resulting in a second source code. The unified programming model is used to develop general-purpose computing-related source code, i.e., source code that does not involve a computation graph. The second source code can be understood as general-purpose computing-related source code or unified programming source code; it can also be described as a second source code or a second source program.

[0077] The electronic device obtains the second source code, inputs the second source code into the heterogeneous compiler, compiles the second source code by the heterogeneous compiler to generate an executable file in a general computing format, thus obtaining the second executable file; the heterogeneous compiler sends the second executable file to the heterogeneous runtime.

[0078] To enable handwritten operators to run across hardware platforms, in one embodiment...

[0079] The second source code includes host-side source code and device-side source code. The device-side source code includes the source code of operators used for parallel acceleration in general computing, and the host-side source code is used to control the execution logic of the device-side operators.

[0080] Here, host-side source code can be described as host-side source code or host-side source program, and device-side source code can be described as device-side source code or device-side source program.

[0081] In practical applications, general-purpose computing developers write host-side source code and device-side source code based on the unified programming model's hardware and software stack to obtain the general-purpose computing source code, i.e., the second source code. The device-side source code contains the source code of the operators (kernels) used in general-purpose computing for parallel acceleration of computation and control. The device-side source code is used to run on the device for parallel acceleration of computation and control.

[0082] It should be noted that AI developers and general computing developers can be collectively referred to as users or developers. The second executable file is adaptable to different hardware resources in the resource pool, which can be understood as the second executable file being able to execute or run on different hardware resources within the resource pool; in other words, the second executable file can run across hardware platforms.

[0083] Based on the second source code, which includes the first information and the general computing source code, in one embodiment, the step of compiling the second source code using the heterogeneous compiler to obtain a second executable file includes:

[0084] The source code of the operator contained in the second source code is read through the heterogeneous compiler;

[0085] The source code of the operator and the source code of the host side are compiled to obtain the second executable file.

[0086] Here, the electronic device reads the source code of the operator contained in the device-side source code of the general computing source code from the second source code through a heterogeneous compiler; the heterogeneous compiler compiles the source code of the operator and the host-side source code to obtain the second executable file.

[0087] For example, the electronic device parses the second source code using a heterogeneous compiler to obtain a second parsing result; based on the second parsing result, it reads the device-side source code from the general computing source code and reads the source code of the operator used for parallel acceleration computing and control in the general computing from the device-side source code; and it compiles the source code of the operator and the host-side source code using a heterogeneous compiler to obtain a second executable file.

[0088] To improve the compilation efficiency of the second source code, in one embodiment, compiling the source code of the operator and the host-side source code to obtain the second executable file includes:

[0089] The source code of the operator is compiled to obtain a second assembly file;

[0090] The host-side source code is compiled to obtain a third assembly file;

[0091] The second assembly file and the third assembly file are linked together to obtain the second executable file.

[0092] Here, the electronic device compiles the operator's source code using a heterogeneous compiler to obtain a second assembly file, which can be understood as the device kernel assembly file; the host-side source code is also compiled using a heterogeneous compiler to obtain a third assembly file; the second and third assembly files are then linked to obtain a second executable file.

[0093] The second assembly file and / or the third assembly file can be assembly files in a general computing format.

[0094] To improve the compilation efficiency of the second source code, in one embodiment, compiling the source code of the operator to obtain a second assembly file includes:

[0095] Convert the source code of the operator into a second intermediate representation;

[0096] The second assembly file is generated based on the second intermediate representation.

[0097] Here, the electronic device uses a heterogeneous compiler to convert the source code of the operator into a second intermediate representation, and then uses the heterogeneous compiler to generate a second assembly file based on the second intermediate representation.

[0098] In practical applications, heterogeneous compilers can include general-purpose compilers and graph compilers. When a second parsing result is obtained by parsing the second source code using a heterogeneous compiler, the device-side source code can be identified from the second source code based on this result. The source code of all operators is then read from the device-side source code and sent to the general-purpose compiler frontend. The frontend then sends the source code of all operators to the general-purpose compiler backend for processing. After processing by each parser, the source code of all operators is converted into a second intermediate representation in LLVM (Low Level Virtual Machine) IR format. The general-purpose compiler backend generates a second assembly file based on this intermediate representation, for example, by optimizing the intermediate representation. The host-side source code is then compiled by the general-purpose compiler to obtain a third assembly file. Finally, the second and third assembly files are linked to obtain a second executable file.

[0099] Step 203: Through heterogeneous runtime, parse the first executable file and the second executable file, and send the first executable file and the second executable file to the resource pool for execution.

[0100] Here, the electronic device parses or analyzes the first executable file through heterogeneous runtime to obtain a third parsing result, and sends the first executable file to the resource pool for execution based on the third parsing result; it also parses or analyzes the second executable file through heterogeneous runtime to obtain a fourth parsing result, and sends the second executable file to the resource pool for execution based on the fourth parsing result.

[0101] It should be noted that the heterogeneous runtime defines a unified hardware resource interface, which manages the memory, execution, and other operations of each hardware resource in the resource pool. Through the hardware resource interface in the heterogeneous runtime, hardware resources that can be selected from the resource pool to execute or run a first executable file and a second executable file can be sent to the corresponding hardware resources in the resource pool for execution.

[0102] To enable the computation graph and handwritten operators to run across hardware platforms, in one embodiment, the heterogeneous runtime is used to manage hardware resources in the resource pool and to send the first executable file and the second executable file to the runtime of the hardware resources in the resource pool.

[0103] Here, electronic devices can select available hardware resources from the resource pool, or select hardware resources for running executable files, so that the corresponding hardware resources can obtain and run the first executable file and the second executable file through their respective runtime interfaces with heterogeneous runtimes, thereby deploying the first executable file and the second executable file on the corresponding hardware resources.

[0104] It should be noted that the resource pool can also select hardware resources that can execute the first executable file and / or the second executable file, and obtain the first executable file and the second executable file through heterogeneous runtime, and execute or run the first executable file and / or the second executable file through the selected hardware resources.

[0105] Figure 3 A general program compilation flow example diagram is provided for scenarios involving the integration of various heterogeneous computing resources in cloud computing. The program compilation flow of this application embodiment, based on existing program compilation flows, introduces a new heterogeneous compiler, a heterogeneous runtime, and a resource pool. The heterogeneous compiler can compile the first source code and the second source code into a first executable file and a second executable file, respectively, which are tightly integrated with the heterogeneous runtime and adapted to various hardware architectures. This allows the first executable file and the second executable file to run across hardware platforms, enabling computational graphs and handwritten operators to run across hardware platforms. This reduces the complexity and difficulty of developing heterogeneous applications and improves the flexibility and convenience of developing heterogeneous applications.

[0106] To implement the program compilation method of this application embodiment, this application embodiment also provides a program compilation device, which is installed on an electronic device, such as... Figure 4 As shown, the device includes:

[0107] The first compilation unit 401 is used to compile the first source code using a heterogeneous compiler to obtain the first executable file;

[0108] The second compilation unit 402 is used to compile the second source code using the heterogeneous compiler to obtain the second executable file;

[0109] The parsing unit 403 is used to parse the first executable file and the second executable file through heterogeneous runtime, and send the first executable file and the second executable file to the resource pool for execution.

[0110] In one embodiment, the first source code includes computation graph source code developed based on a machine learning framework and first information developed based on a unified programming model, wherein the first information represents relevant information of the computation graph model file; the first executable file represents an executable file in computation graph format, which can be adapted to different hardware resources in the resource pool; the second source code represents general-purpose computation source code developed based on the unified programming model; the second executable file represents an executable file in general-purpose computation format, which can be adapted to different hardware resources in the resource pool.

[0111] In one embodiment, the computation graph source code includes a computation graph model file, which contains the computation graph.

[0112] In one embodiment, the second source code includes host-side source code and device-side source code. The device-side source code contains source code for operators used in general computing for parallel acceleration of computing, and the host-side source code is used to control the execution logic of the device-side operators.

[0113] In one embodiment, the first compilation unit 401 is specifically used to compile the first information and the computation graph model file using the heterogeneous compiler to obtain the first executable file.

[0114] In one embodiment, the first compilation unit 401 is specifically used to compile the computation graph model file to obtain a first assembly file in computation graph format; and to link the first assembly file and the first information to obtain the first executable file.

[0115] In one embodiment, the first compilation unit 401 is specifically used to convert the computation graph model file into a first intermediate representation; and to perform graph optimization on the first intermediate representation to obtain the first assembly file.

[0116] In one embodiment, the second compilation unit 402 is specifically used to read the source code of the operator contained in the second source code through the heterogeneous compiler; and to compile the source code of the operator and the host-side source code to obtain the second executable file.

[0117] In one embodiment, the second compilation unit 402 is specifically used to compile the source code of the operator to obtain a second assembly file; compile the host-side source code to obtain a third assembly file; and link the second assembly file and the third assembly file to obtain the second executable file.

[0118] In one embodiment, the second compilation unit 402 is specifically used to convert the source code of the operator into a second intermediate representation; and to generate a second assembly file based on the second intermediate representation.

[0119] In one embodiment, the heterogeneous runtime is used to manage hardware resources in the resource pool and to send the first executable file and the second executable file to the runtime of the hardware resources in the resource pool.

[0120] In practical applications, the first compilation unit 401 and the second compilation unit 402 can be implemented by the processor in the program compilation device, and the parsing unit 403 can be implemented by the processor in the program compilation device in conjunction with the communication interface.

[0121] It should be noted that the program compilation device provided in the above embodiments is only illustrated by the division of the above program modules. In practical applications, the above processing can be assigned to different program modules as needed, that is, the internal structure of the device can be divided into different program modules to complete all or part of the processing described above. In addition, the program compilation device and the program compilation method embodiments provided in the above embodiments belong to the same concept, and the specific implementation process can be found in the method embodiments, which will not be repeated here.

[0122] Based on the hardware implementation of the above program modules, and in order to implement the program compilation method of the embodiments of this application, the embodiments of this application also provide an electronic device, such as... Figure 5 As shown, the electronic device 500 includes:

[0123] Communication interface 501 enables information exchange with other network nodes;

[0124] The processor 502 is connected to the communication interface 501 to enable information interaction with other network nodes and, when running a computer program, executes the methods provided by one or more technical solutions on the electronic device side. The computer program is stored in the memory 503.

[0125] Specifically, the processor 502 is configured to compile the first source code using a heterogeneous compiler to obtain a first executable file; compile the second source code using the heterogeneous compiler to obtain a second executable file; and parse the first executable file and the second executable file using a heterogeneous runtime environment.

[0126] The communication interface 501 is used to send the first executable file and the second executable file to the resource pool for execution via heterogeneous runtime.

[0127] In one embodiment, the first source code includes computation graph source code developed based on a machine learning framework and first information developed based on a unified programming model, wherein the first information represents relevant information of the computation graph model file; the first executable file represents an executable file in computation graph format, which can be adapted to different hardware resources in the resource pool; the second source code represents general-purpose computation source code developed based on the unified programming model; the second executable file represents an executable file in general-purpose computation format, which can be adapted to different hardware resources in the resource pool.

[0128] In one embodiment, the computation graph source code includes a computation graph model file, which contains the computation graph.

[0129] In one embodiment, the second source code includes host-side source code and device-side source code. The device-side source code contains source code for operators used in general computing for parallel acceleration of computing, and the host-side source code is used to control the execution logic of the device-side operators.

[0130] In one embodiment, the processor 502 is specifically used to compile the first information and the computational graph model file using the heterogeneous compiler to obtain the first executable file.

[0131] In one embodiment, the processor 502 is specifically configured to compile the computation graph model file to obtain a first assembly file in computation graph format; and to link the first assembly file and the first information to obtain the first executable file.

[0132] In one embodiment, the processor 502 is specifically configured to convert the computational graph model file into a first intermediate representation; and to perform graph optimization on the first intermediate representation to obtain the first assembly file.

[0133] In one embodiment, the processor 502 is specifically configured to read the source code of the operator contained in the second source code through the heterogeneous compiler; and to compile the source code of the operator and the host-side source code to obtain the second executable file.

[0134] In one embodiment, the processor 502 is specifically configured to compile the source code of the operator to obtain a second assembly file; compile the host-side source code to obtain a third assembly file; and link the second assembly file and the third assembly file to obtain a second executable file.

[0135] In one embodiment, the processor 502 is specifically configured to convert the source code of the operator into a second intermediate representation; and to generate a second assembly file based on the second intermediate representation.

[0136] In one embodiment, the heterogeneous runtime is used to manage hardware resources in the resource pool and to send the first executable file and the second executable file to the runtime of the hardware resources in the resource pool.

[0137] It should be noted that the specific processing procedures of processor 502 and communication interface 501 can be understood by referring to the above method.

[0138] Of course, in practical applications, the various components in electronic device 500 are coupled together through bus system 504. It can be understood that bus system 504 is used to realize the connection and communication between these components. In addition to a data bus, bus system 504 also includes a power bus, a control bus, and a status signal bus. However, for the sake of clarity, in... Figure 5 The general designated all buses as Bus System 504.

[0139] The memory 503 in this embodiment is used to store various types of data to support the operation of the electronic device 500. Examples of such data include any computer program used to operate on the electronic device 500.

[0140] The methods disclosed in the embodiments of this application can be applied to the processor 502, or implemented by the processor 502. The processor 502 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the integrated logic circuit of the hardware in the processor 502 or by instructions in the form of software. The processor 502 may be a general-purpose processor, a digital signal processor (DSP), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The processor 502 can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor may be a microprocessor or any conventional processor, etc. The steps of the methods disclosed in the embodiments of this application can be directly reflected as being executed by a hardware decoding processor, or being executed by a combination of hardware and software modules in the decoding processor. The software modules may be located in a storage medium, which is located in the memory 503. The processor 502 reads the information in the memory 503 and combines its hardware to complete the steps of the aforementioned method.

[0141] In an exemplary embodiment, the electronic device 500 may be implemented by one or more application-specific integrated circuits (ASICs), DSPs, programmable logic devices (PLDs), complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), general-purpose processors, controllers, microcontrollers (MCUs), microprocessors, or other electronic components to perform the aforementioned method.

[0142] It is understood that the memory (memory 503) in this embodiment of the application can be volatile memory or non-volatile memory, or both. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), ferromagnetic random access memory (FRAM), flash memory, magnetic surface memory, optical disc, or compact disc read-only memory (CD-ROM); the magnetic surface memory can be disk storage or magnetic tape storage. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as Static Random Access Memory (SRAM), Synchronous Static Random Access Memory (SSRAM), Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SDRAM), Double Data Rate Synchronous Dynamic Random Access Memory (DDRSDRAM), Enhanced Synchronous Dynamic Random Access Memory (ESDRAM), SyncLink Dynamic Random Access Memory (SLDRAM), and Direct Rambus Random Access Memory (DRRAM).The memories described in the embodiments of this application are intended to include, but are not limited to, these and any other suitable types of memories.

[0143] In an exemplary embodiment, this application also provides a storage medium, namely a computer storage medium, specifically a computer-readable storage medium, such as a memory 503 storing a computer program, which can be executed by the processor 502 of the electronic device 500 to complete the steps described in the aforementioned electronic device-side method. The computer-readable storage medium may be a memory such as FRAM, ROM, PROM, EPROM, EEPROM, Flash Memory, magnetic surface memory, optical disc, or CD-ROM.

[0144] For example, this application also provides a computer program product, including a computer program that can be executed by the processor 502 of an electronic device 500 to complete the steps described in the aforementioned electronic device-side method.

[0145] It should be noted that terms such as "first" and "second" are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. "Multiple" can refer to two or more items, and "multiple" can refer to two or more items. The term "and / or" in this document merely describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Furthermore, the term "one or more" in this document refers to any combination of at least two of the multiple elements. For example, including one or more of A, B, and C can represent including any one or at least two or more elements selected from the set consisting of A, B, and C.

[0146] Furthermore, the technical solutions described in the embodiments of this application can be combined arbitrarily without conflict.

[0147] The above description is merely a preferred embodiment of this application and is not intended to limit the scope of protection of this application.

Claims

1. A program compilation method, characterized in that, include: The first source code is compiled using a heterogeneous compiler to obtain the first executable file; The second source code is compiled using the heterogeneous compiler to obtain a second executable file; During heterogeneous runtime, the first executable file and the second executable file are parsed, and the first executable file and the second executable file are sent to the resource pool for execution.

2. The method according to claim 1, characterized in that, The first source code includes the source code of a computation graph developed based on a machine learning framework and first information developed based on a unified programming model, wherein the first information represents the relevant information of the computation graph model file; The first executable file represents a compute graph format executable file that can be adapted to different hardware resources in the resource pool; The second source code represents a general-purpose computing source code developed based on the unified programming model; The second executable file represents an executable file in a general computing format, which can be adapted to different hardware resources in the resource pool.

3. The method according to claim 2, characterized in that, The computation graph source code includes a computation graph model file, which contains the computation graph.

4. The method according to claim 2, characterized in that, The second source code includes host-side source code and device-side source code. The device-side source code contains the source code of operators used for parallel acceleration in general computing, and the host-side source code is used to control the execution logic of the operators on the device side.

5. The method according to claim 3, characterized in that, The process of compiling the first source code using a heterogeneous compiler to obtain the first executable file includes: The first executable file is obtained by compiling the first information and the computational graph model file using the heterogeneous compiler.

6. The method according to claim 5, characterized in that, The process of compiling the first information and the computational graph model file using the heterogeneous compiler to obtain the first executable file includes: The computation graph model file is compiled to obtain a first assembly file in computation graph format; The first assembly file and the first information are linked to obtain the first executable file.

7. The method according to claim 6, characterized in that, The process of compiling the computation graph model file to obtain a first assembly file in computation graph format includes: Convert the computational graph model file into a first intermediate representation; The first intermediate representation is optimized to obtain the first assembly file.

8. The method according to claim 4, characterized in that, The process of compiling the second source code using the heterogeneous compiler to obtain the second executable file includes: The source code of the operator contained in the second source code is read through the heterogeneous compiler; The source code of the operator and the source code of the host side are compiled to obtain the second executable file.

9. The method according to claim 8, characterized in that, The process of compiling the source code of the operator and the host-side source code to obtain the second executable file includes: The source code of the operator is compiled to obtain a second assembly file; The host-side source code is compiled to obtain a third assembly file; The second assembly file and the third assembly file are linked together to obtain the second executable file.

10. The method according to claim 9, characterized in that, The process of compiling the source code of the operator to obtain a second assembly file includes: Convert the source code of the operator into a second intermediate representation; The second assembly file is generated based on the second intermediate representation.

11. The method according to any one of claims 1 to 10, characterized in that, The heterogeneous runtime is used to manage hardware resources in the resource pool and to send the first executable file and the second executable file to the runtime of the hardware resources in the resource pool.

12. A program compilation apparatus, characterized in that, include: The first compilation unit is used to compile the first source code using a heterogeneous compiler to obtain the first executable file; The second compilation unit is used to compile the second source code using the heterogeneous compiler to obtain the second executable file; The parsing unit is used to parse the first executable file and the second executable file through heterogeneous runtime, and send the first executable file and the second executable file to the resource pool for execution.

13. An electronic device, characterized in that, include: Processor and communication interface; among which, The processor is configured to compile a first source code using a heterogeneous compiler to obtain a first executable file; and to compile a second source code using the heterogeneous compiler to obtain a second executable file; The communication interface is used to parse the first executable file and the second executable file through heterogeneous runtime, and send the first executable file and the second executable file to the resource pool for execution.

14. An electronic device, characterized in that, This includes a processor and memory for storing computer programs that can run on the processor. When the processor is used to run the computer program, it performs the steps of the method according to any one of claims 1 to 11.

15. A storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 11.

16. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 11.

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