Semiconductor testing apparatus, methods, devices and computer equipment

Abstract

This application relates to a semiconductor testing apparatus, method, device, and computer equipment. The apparatus includes: a processing module, a pre-calculation module, a shared instruction cache module, multiple channel processing units, and a resource allocation module. The processing module receives and parses test data from at least one chip under test (DUT) and generates corresponding intermediate representation codes. The pre-calculation module generates an address jump table. The shared instruction cache module stores the intermediate representation codes in a shared instruction cache and, through a prefetch controller, stores prefetched instructions into the local cache of the corresponding channel processing unit according to the address jump table. The multiple channel processing units execute tests on the corresponding DUT chips in parallel according to the prefetched instructions. The resource allocation module monitors the operating load status information of each channel processing unit and adaptively allocates resources among the channel processing units. This apparatus can reduce hardware costs while supporting high-speed, complex test pattern generation, reducing test power consumption, and increasing test speed.

Description

Technical Field

[0001] This application relates to the field of semiconductor testing technology, and in particular to a semiconductor testing apparatus, method, device, and computer device. Background Technology

[0002] With the iterative upgrades in semiconductor memory chip manufacturing technology, new types of memory chips such as high-capacity, high-speed dynamic random access memory (DRAM), flash memory, and static random access memory (SRAM) are gradually becoming more widespread, leading to a significant increase in the testing requirements for memory chips. Testing semiconductor memory chips requires generating a large number of complex test patterns, including address sequences, data patterns, and control timing sequences.

[0003] Traditional algorithmic graphics generators primarily employ two implementation methods. One is a centralized shared resource architecture, using a centralized arithmetic logic unit and instruction memory. Multiple input / output channels share a single set of computing resources. While this approach has lower hardware costs, it imposes strong channel synchronization constraints, and the operating frequency is limited by computational latency, failing to meet the testing requirements of high-speed memory chips. The other is a pin-independent algorithmic graphics generator, configuring an independent instruction memory and graphics generator for each input / output channel. Although this supports independent high-speed operation of each channel, hardware costs and complexity increase exponentially with the number of channels, resulting in a persistently high overall cost for the testing equipment. Furthermore, traditional algorithmic graphics generators often use a vector memory coupled with a cache system. Executing complex testing algorithms requires frequent access to the vector memory, leading to increased power consumption and reduced testing speed, making it difficult to adapt to the high-efficiency testing requirements of new memory chips. Summary of the Invention

[0004] Therefore, it is necessary to provide a semiconductor testing apparatus, method, device, and computer device that can reduce hardware costs while supporting high-speed, complex test pattern generation, reducing test power consumption, and improving test speed, in order to address the above-mentioned technical problems.

[0005] In a first aspect, this application provides a semiconductor testing apparatus, the apparatus comprising:

[0006] The system comprises a processing module, a pre-computation module, a shared instruction cache module, multiple channel processing units, and a resource allocation module. The processing module is connected to a communication bus. The pre-computation module is communicatively connected to both the processing module and the shared instruction cache module. Each channel processing unit is communicatively connected to the shared instruction cache module, the resource allocation module, and the processing module.

[0007] The processing module is used to receive and parse test data from at least one chip under test and generate corresponding intermediate representation codes.

[0008] The pre-calculation module is used to generate an address jump table based on the intermediate representation code;

[0009] The shared instruction cache module is used to store the intermediate representation code into the shared instruction cache, and to store the prefetched instructions into the local cache of the corresponding channel processing unit according to the address jump table by the prefetch controller;

[0010] Multiple channel processing units are used to perform tests on the corresponding chip under test in parallel according to the prefetch instructions;

[0011] The resource allocation module is used to monitor the operating load status information of each channel processing unit and adaptively allocate arithmetic logic unit resources among each channel processing unit according to the operating load status information.

[0012] In some embodiments of the device, the device may further include a loop buffer for storing loop body instructions, the loop buffer being configured to support zero-overhead loop execution.

[0013] In some embodiments of the device, the device further includes an algorithm matching module, which is communicatively connected to the processing module and the pre-computation module, respectively.

[0014] The algorithm matching module is used to receive the chip under test data and / or test requirement information and / or test result information sent by the processing module, and adaptively adjust the algorithm type and / or algorithm parameters of the pre-calculation module.

[0015] In some embodiments of the device, the channel processing unit includes at least one of a local instruction storage unit, an address generation unit, a data generation unit, a timing control unit, and a result comparison unit.

[0016] In some embodiments of the device, the local instruction storage unit is used to store prefetch instructions and / or test instructions executed by the current channel;

[0017] The address generation unit is used to calculate the test address sequence based on the current address pointer and the address step size;

[0018] The data generation unit is used to generate corresponding test graphic data according to the test algorithm type and the current test address sequence;

[0019] The timing control unit is used to output drive timing signals that match the test requirements according to preset timing parameters;

[0020] The result comparison unit is used to capture the output signal of the chip under test within the target sampling window and compare the output signal with the target data in real time.

[0021] In some embodiments of the device, the data generation unit includes a linear feedback shift register and a data synthesis unit, wherein the linear feedback shift register and the data synthesis unit are communicatively connected.

[0022] In some embodiments of the device, the linear feedback shift register includes at least one of a polynomial configuration register, a seed register, a parallel output register, and an overclock control unit;

[0023] The polynomial configuration register is configured to programmatically set the feedback polynomial of the linear feedback shift register;

[0024] The seed register is configured to load an initial seed from a prefetch instruction, or to obtain an optimized seed from the pre-computation module;

[0025] The parallel output register is used to output multi-bit pseudo-random data in parallel.

[0026] The overclock control unit is configured to operate at an integer multiple of the test cycle frequency to generate output data.

[0027] According to a second aspect of the present disclosure, a semiconductor testing method is provided, the method comprising:

[0028] The processing module receives and parses test data from at least one chip under test and generates the corresponding intermediate representation code.

[0029] The pre-calculation module generates an address jump table based on the intermediate representation code;

[0030] The intermediate representation code is stored in the shared instruction cache through the shared instruction cache module, and the prefetching instruction is stored in the local cache of the corresponding channel processing unit according to the address jump table through the prefetch controller.

[0031] The test of the corresponding chip under test is executed in parallel by multiple channel processing units according to the prefetch instructions;

[0032] The resource allocation module monitors the operating load status information of each channel processing unit and adaptively allocates arithmetic logic unit resources among the channel processing units based on the operating load status information.

[0033] In some embodiments of the method, the method further includes:

[0034] The algorithm matching module receives the chip under test data and / or test requirement information and / or test result information sent by the processing module, and adaptively adjusts the algorithm type and / or algorithm parameters of the pre-calculation module.

[0035] In some embodiments of the method, generating the address jump table based on the intermediate representation code via the pre-computation module includes:

[0036] The intermediate representation code is parsed to identify the start and end addresses of the loop structure;

[0037] Calculate the address range and iteration count of the loop body in the loop structure, generate jump table entries containing address information and iteration information, and construct a multi-level associated address jump table for nested loop structures;

[0038] Pre-calculate the test data that can be pre-computed for the current test, and store the pre-computed test data in the pre-computed cache.

[0039] In some embodiments of the method, the step of executing the test of the corresponding chip under test in parallel by multiple channel processing units according to the prefetch instruction includes:

[0040] The test address sequence is calculated by the address generation unit based on the current address pointer and the address step size;

[0041] The data generation unit generates corresponding test graphic data based on the test algorithm type and the current test address sequence.

[0042] The timing control unit outputs drive timing signals that match the test requirements according to preset timing parameters;

[0043] The result comparison unit captures the output signal of the chip under test within the target sampling window and compares the output signal with the target data in real time.

[0044] According to a third aspect of the present disclosure, a computer device is provided. The computer device includes a memory and a processor, the memory storing a computer program, and the processor executing the computer program to implement the semiconductor testing method described above.

[0045] According to a fourth aspect of the present disclosure, a computer-readable storage medium is provided. The computer-readable storage medium stores a computer program thereon, which, when executed by a processor, implements the semiconductor testing method described above.

[0046] According to a fifth aspect of the present disclosure, a computer program product is provided. The computer program product includes a computer program that, when executed by a processor, implements the semiconductor testing method described above.

[0047] According to a sixth aspect of the present disclosure, a semiconductor testing apparatus is provided. The semiconductor testing apparatus includes at least one of the above-described semiconductor testing devices and computer equipment.

[0048] The semiconductor testing solution provided in this application can achieve unified reuse of multi-channel instruction resources by using a shared instruction cache. Combined with a resource allocation module, it enables dynamic cross-channel allocation of arithmetic logic unit resources. Multiple channels share core hardware resources instead of being deployed independently, significantly reducing redundant hardware deployment while preserving the independent operating capabilities of each channel. This lowers the overall construction cost and complexity from a hardware architecture perspective. Through multi-level instruction execution, the testing process is broken down into algorithm-level, instruction-level, and micro-operation-level layered collaborative execution. This hierarchical decomposition and division of labor greatly simplifies the conversion link from test algorithms to hardware execution, reducing the overall scheduling and computational complexity. A layered cache prefetching mechanism transforms a large amount of real-time computation and frequent storage access into preprocessing, reducing the computational load and storage access frequency during the test execution phase. The resource allocation module accurately identifies and allocates idle resources, improving resource utilization efficiency and reducing idle power consumption.

[0049] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0050] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure, and are not intended to unduly limit this disclosure.

[0051] Figure 1 This is a structural block diagram of a semiconductor testing apparatus according to an exemplary embodiment;

[0052] Figure 2 This is a schematic diagram illustrating a multi-level instruction execution mechanism according to an exemplary embodiment;

[0053] Figure 3 This is a schematic diagram illustrating a hierarchical cache prefetching mechanism according to an exemplary embodiment;

[0054] Figure 4 This is a schematic diagram illustrating the structure of a reconfigurable linear feedback shift register according to an exemplary embodiment;

[0055] Figure 5 This is a schematic flowchart illustrating a semiconductor testing method according to an exemplary embodiment;

[0056] Figure 6 This is a diagram illustrating the internal structure of a computer device according to an exemplary embodiment. Detailed Implementation

[0057] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0058] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this disclosure described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure. The terms "comprising," "including," or any other variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, product, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, product, or apparatus. Without further limitations, the presence of other identical or equivalent elements in a process, method, product, or apparatus that includes said elements is not excluded. For example, the use of terms such as "first," "second," etc., to denote names does not indicate any specific order.

[0059] In some embodiments of this disclosure, a semiconductor testing apparatus is provided, such as... Figure 1 As shown, the device includes: a processing module, a pre-computation module, a shared instruction cache module, multiple channel processing units, and a resource allocation module. The processing module is connected to a communication bus. The pre-computation module is communicatively connected to both the processing module and the shared instruction cache module. Each channel processing unit is communicatively connected to the shared instruction cache module, the resource allocation module, and the processing module. The processing module receives and parses test data from at least one chip under test and generates a corresponding intermediate representation code. The pre-computation module generates an address jump table based on the intermediate representation code. The shared instruction cache module stores the intermediate representation code in a shared instruction cache and, through a prefetch controller, stores prefetched instructions in the local cache of the corresponding channel processing unit according to the address jump table. The multiple channel processing units execute tests on the corresponding chip under test in parallel according to the prefetched instructions. The resource allocation module monitors the operating load status information of each channel processing unit and adaptively allocates arithmetic logic unit resources among the channel processing units based on the operating load status information.

[0060] In some implementations, the processing module is connected to the system communication bus and can be configured as a main control processing unit, including a main control processor. The processing module can receive and parse test data from at least one chip under test (DUT), which can be a single DUT or an array of multiple DUTs. In some examples, the test data may include test programs. The processing module can receive and parse the test programs from the DUT array, and is responsible for loading, parsing, and scheduling the test programs, as well as allocating subsequent test tasks. The processing module can generate corresponding intermediate representation code, which typically refers to the specific code form of the intermediate representation (IR) during the compilation process. Intermediate representation code is an abstract, platform-independent intermediate form used by the compiler to convert high-level language source code into target machine code, supporting optimization, analysis, and cross-platform code generation.

[0061] The pre-computation module establishes communication connections with the processing module and the shared instruction cache module. The pre-computation module can generate an address jump table based on the intermediate representation code. In some implementations, the pre-computation module can also perform pre-computation on pre-computable test data, such as background data and address sequences, and store the pre-computation data in the pre-computation cache.

[0062] The shared instruction cache module can establish communication connections with each channel processing unit and the pre-computation module. The shared instruction cache module can store intermediate representation codes in the shared instruction cache. The shared instruction cache module may be equipped with a prefetch controller, which can store prefetched instructions into the local cache of the corresponding channel processing unit according to the address jump table. In some embodiments, the shared instruction cache module can also establish a communication connection with the processing module, and can receive intermediate representation codes and / or test instructions issued by the processing module.

[0063] The channel processing unit can execute tests on the corresponding chip under test in parallel according to the prefetch instructions. In some implementations, each channel processing unit can correspond to one chip under test and execute the corresponding test task.

[0064] The resource allocation module can monitor the operating load status of each channel processing unit and adaptively allocate resources of the Arithmetic and Logic Unit (ALU) among the channel processing units based on the operating load status information. An ALU is a combinational logic circuit capable of performing multiple sets of arithmetic and logical operations. Through dynamic resource sharing, while maintaining the independence of each channel, the hardware cost can be reduced by approximately 40% compared to a pin-independent test device.

[0065] In some implementations, such as Figure 2As shown, a semiconductor testing device can execute multi-level instructions through a processing module, a shared instruction cache module, a pre-computation module, and processing units in each channel. These instructions can include first-level, second-level, and third-level instructions. In some examples, first-level instructions can be configured for algorithm-level instruction execution, second-level instructions for prefetch-based instruction execution, and third-level instructions for micro-operation-level instruction execution. The processing module parses the test data, generates intermediate representation codes, and sends these codes to the shared instruction cache module. The shared instruction cache module stores the intermediate instruction codes in its shared instruction cache; this is first-level instruction execution, i.e., algorithm-level instruction execution. The pre-computation module generates prefetch instructions, which are sent to the local storage of each channel processing unit, achieving prefetch-based instruction execution; this is second-level instruction execution. Each channel processing unit reads the prefetch instructions from its local storage. These prefetch instructions include corresponding micro-operation instructions. Each channel processing unit executes the corresponding chip under test in parallel, achieving micro-operation-level instruction execution. The execution of multi-level instructions can break down the test process into layered collaborative execution at the algorithm level, instruction level, and micro-operation level. Through hierarchical decomposition and division of labor, the conversion link from test algorithm to hardware execution is greatly simplified, and the overall scheduling and computation complexity is reduced.

[0066] In some implementations, such as Figure 3 As shown, the semiconductor testing apparatus can also implement a hierarchical cache prefetching mechanism through a shared instruction cache module, each channel processing unit, and a prefetch controller. Hierarchical caches can be configured, including a Level 1 cache and a Level 2 cache. For example, the Level 1 cache is a shared instruction cache, which can be used to store all test data, i.e., the instruction codes of the entire test program; the Level 2 cache is a local cache for each channel processing unit, which can be used to store a subset of instructions currently being executed by the corresponding channel. In some examples, the capacity of the shared instruction cache can be 64KB to 256KB; the capacity of the local cache can be 2KB to 8KB. The prefetch controller can pre-store prefetched instruction blocks from the Level 1 cache to the Level 2 cache based on the address jump table generated by the pre-computation module.

[0067] In some embodiments of this disclosure, the semiconductor testing apparatus may further include a loop buffer, which can be used to store loop body instructions and can be configured to support zero-overhead loop execution.

[0068] In some implementations, a circular buffer can be used to eliminate the need to re-fetch instructions from the cache during loop iterations. Employing a tiered cache prefetch mechanism, complete test instructions can be stored in the first-level cache, while the second-level cache stores a subset of instructions currently being executed by the channel. The channel processing unit directly reads instructions from its local cache, significantly reducing instruction read latency and improving test efficiency. Tiered prefetching and local cache fetching reduce frequent access to large-capacity storage, lowering energy consumption in storage and transmission. Overall power consumption can be reduced by approximately 30% compared to a pin-independent test device, while simultaneously improving resource utilization efficiency. Through multi-level parallel execution and a zero-overhead loop mechanism, test execution speed can be increased by 30% to 50%, achieving a 38.8% improvement in DDR5 testing.

[0069] In some embodiments of this disclosure, a shared instruction cache can be used to achieve unified reuse of multi-channel instruction resources. This, combined with a resource allocation module, enables dynamic cross-channel allocation of arithmetic logic unit resources. Multiple channels share core hardware resources instead of being deployed independently, significantly reducing redundant hardware deployment while preserving the independent operating capabilities of each channel. This lowers the overall construction cost and complexity from a hardware architecture perspective. Multi-level instruction execution breaks down the test process into algorithm-level, instruction-level, and micro-operation-level layered collaborative execution. This hierarchical decomposition and division of labor greatly simplifies the conversion link from test algorithms to hardware execution, reducing the overall scheduling and computational complexity. A layered cache prefetching mechanism transforms a large amount of real-time computation and frequent storage access into preprocessing, reducing the computational load and storage access frequency during the test execution phase. Finally, the resource allocation module accurately identifies and allocates idle resources, improving resource utilization efficiency and reducing idle power consumption.

[0070] In some embodiments of this disclosure, the apparatus further includes an algorithm matching module, which is communicatively connected to the processing module and the pre-computation module, respectively. The algorithm matching module is used to receive the chip under test data and / or test requirement information and / or test result information sent by the processing module, and adaptively adjust the algorithm type and / or algorithm parameters of the pre-computation module.

[0071] In some implementations, the algorithm matching module may have an adaptive algorithm library, which may be stored in non-volatile memory. The algorithms may include various chip testing algorithms, such as memory chip testing algorithms, including March algorithms like March C, March C-, and March LR, as well as Checkerboard and Solid background algorithms, Galpat, Walking I / O algorithms, address line short / open circuit test algorithms, data retention time test algorithms, etc. The algorithm matching module can receive the chip under test data and / or test requirement information and / or test result information sent by the processing module, i.e., adaptively matching the algorithm type and / or adjusting the algorithm parameters based on one or more of the chip under test data, test requirement information, and test result information. In some examples, the chip under test data may include chip type information, such as Dynamic Random Access Memory (DRAM), Static Random-Access Memory (SRAM), Flash memory, etc. Test results can be aggregated by the channel processing unit after testing and sent to the processing module, which then distributes them to the algorithm matching module. The algorithm matching module can also proactively request one or more of the following from the processing module: chip data under test, test requirements, and test results. In other examples, the adaptive algorithm library can dynamically adjust based on test results, increasing vertical interference coverage from 65% to 96% in 3D NAND testing.

[0072] In some embodiments of this disclosure, the algorithm matching module can dynamically adjust the algorithm configuration of the pre-computation module according to chip data, test requirements and test results, so that the test process has adaptive optimization capabilities, can match the test requirements of different types of memory chips, and improve the flexibility and adaptability of the test scheme.

[0073] In some embodiments of this disclosure, the channel processing unit includes at least one of a local instruction storage unit, an address generation unit, a data generation unit, a timing control unit, and a result comparison unit.

[0074] In some embodiments of this disclosure, the local instruction storage unit is used to store the prefetch instructions and / or test instructions executed by the current channel; the address generation unit is used to calculate the test address sequence based on the current address pointer and address step size; the data generation unit is used to generate corresponding test graphic data based on the test algorithm type and the current test address sequence; the timing control unit is used to output drive timing signals that match the test requirements according to preset timing parameters; and the result comparison unit is used to capture the output signal of the chip under test within the target sampling window and compare the output signal with the target data in real time.

[0075] In some implementations, the channel processing unit is an independently operating hardware execution unit, which can be configured as a functional unit for local instruction storage, address generation, data generation, timing control, and result comparison. Each channel processing unit can correspond to one I / O (input / output) pin of the chip under test. The local instruction storage unit is used to store the pre-fetched instruction content, the address generation unit is used to calculate the address sequence required for the test step by step based on the instruction parameters, the data generation unit generates graphical data matching the test requirements based on reconfigurable logic circuits, the timing control unit can output stable drive timing according to the test requirements, and the result comparison unit is used to capture the chip output signal in real time and complete the data comparison, independently completing the single-channel test execution task throughout the entire process.

[0076] In some embodiments of this disclosure, each channel processing unit has a clear division of labor and executes in parallel, enabling it to independently complete the entire process of test operations, including address calculation, data generation, timing control, and result comparison, ensuring the integrity and stability of single-channel testing. Meanwhile, the independent operation of multiple channels can further improve the efficiency of parallel testing.

[0077] In some embodiments of this disclosure, such as Figure 4 As shown, the data generation unit includes a linear feedback shift register (LFSR) and a data synthesis unit, and the linear feedback shift register and the data synthesis unit are communicatively connected.

[0078] In some implementations, a linear feedback shift register typically refers to a shift register that, given the output of a previous state, uses a linear function of that output as its input.

[0079] In some embodiments of this disclosure, the linear feedback shift register includes at least one of a polynomial configuration register, a seed register, a parallel output register, and an overclock control unit; the polynomial configuration register is configured to programmatically set the feedback polynomial of the linear feedback shift register; the seed register is configured to load an initial seed from a prefetch instruction, or to obtain an optimized seed from the pre-computation module; the parallel output register is used to output multi-bit pseudo-random data in parallel; and the overclock control unit is configured to operate at an integer multiple of the test cycle frequency to generate output data.

[0080] In some examples, each channel processing unit may contain a configurable LFSR module. The LFSR module can support one or more of the following: polynomial configuration, seed loading, parallel output, and overclocking operation. The feedback polynomial of the LFSR can be programmed through the polynomial configuration register, supporting any primitive polynomial from order 2 to 32; an initial seed can be loaded from prefetch instructions through the seed register, or an optimized seed can be obtained from the pre-computation module; multiple bits of pseudo-random data can be output in parallel through the parallel output register, with a maximum configurable 32-bit parallel output; and high-speed output data can be generated by running at integer multiples of the test period frequency through the overclocking control unit, such as 2x or 4x.

[0081] In some embodiments of this disclosure, a reconfigurable linear feedback shift register array can be used to realize the real-time generation of test data. It can support one or more of polynomial configuration, seed loading, parallel output, and overclock operation, and can quickly generate multi-bit parallel test data to meet the data generation requirements of high-speed testing. At the same time, it is suitable for high-frequency testing scenarios, thereby expanding the application range of semiconductor testing devices.

[0082] The semiconductor testing apparatus disclosed herein can achieve unified reuse of multi-channel instruction resources through a shared instruction cache, and dynamically allocate arithmetic logic unit resources across channels in conjunction with a resource allocation module. Multiple channels share core hardware resources instead of being deployed independently, significantly reducing redundant hardware deployment while preserving the independent operating capabilities of each channel, thus lowering the overall construction cost and complexity from a hardware architecture perspective. Through multi-level instruction execution, the testing process is broken down into algorithm-level, instruction-level, and micro-operation-level layered collaborative execution. This hierarchical decomposition and division of labor greatly simplifies the conversion link from test algorithms to hardware execution, reducing the overall scheduling and computational complexity. A layered cache prefetching mechanism transforms a large amount of real-time computation and frequent storage access into preprocessing, reducing the computational load and storage access frequency during the test execution phase. The resource allocation module accurately identifies and allocates idle resources, improving resource utilization efficiency and reducing idle power consumption.

[0083] In some embodiments provided in this disclosure, the execution of the semiconductor testing method can be controlled by a unified controller or by multiple controllers. These controllers may include controllers on local terminals or controllers on remote servers. In some embodiments, the controllers on local terminals and the controllers on servers may work together to complete the semiconductor testing process. The local terminal mentioned in this disclosure may include, but is not limited to, various robotic devices, in-vehicle devices, personal computers, laptops, smartphones, tablets, wearable devices, medical devices, VR (Virtual Reality) devices, etc. The server may also be a server, server cluster, distributed subsystem, cloud processing platform, server containing blockchain nodes, or a combination thereof. The controllers described in this disclosure may include various control units capable of implementing logic processing functions, including but not limited to CPU (Central Processing Unit), PLC (Programmable Logic Controller), ECU (Electronic Control Unit), MCU (Microcontroller Unit), FPGA (Field Programmable Gate Array), and CPLD (Complex Programmable Logic Device), as well as controllers composed of one or more logic function units, chips, etc.

[0084] In some embodiments of this disclosure, a semiconductor testing method is provided, such as... Figure 5 As shown, it includes the following steps:

[0085] S20. The processing module receives and parses the test data of at least one chip under test and generates the corresponding intermediate representation code.

[0086] S22. The pre-calculation module generates an address jump table based on the intermediate representation code;

[0087] S24. The intermediate representation code is stored in the shared instruction cache through the shared instruction cache module, and the prefetching instruction is stored in the local cache of the corresponding channel processing unit according to the address jump table through the prefetch controller.

[0088] S26. The test of the corresponding chip under test is executed in parallel by multiple channel processing units according to the prefetch instruction;

[0089] S28. Monitor the operating load status information of each channel processing unit through the resource allocation module, and adaptively allocate arithmetic logic unit resources among each channel processing unit according to the operating load status information.

[0090] In some implementations, a processing module can receive test data transmitted via a communication bus. This test data may include a test program. The processing module parses the algorithm description, loop structure, and timing parameters within the test program, converting them into intermediate representation codes. A pre-computation module parses the intermediate representation codes and generates an address jump table based on them. A shared instruction cache module stores the intermediate representation codes in a shared instruction cache. This shared instruction cache module may include a prefetch controller, which stores prefetched instructions into the local cache of the corresponding channel processing unit based on the address jump table. This eliminates the need for repeated access to shared memory during channel instruction execution, improving instruction fetching speed. Each channel processing unit executes the corresponding chip under test in parallel based on the prefetched instructions. In some implementations, each channel processing unit may correspond to one chip under test, executing the corresponding test task. Multi-channel parallel execution without interference enables multi-chip parallel testing. A resource allocation module continuously monitors the operating load of each channel, identifies idle arithmetic logic unit resources, and dynamically allocates them to heavily loaded channels, ensuring the computational needs of high-load channels and avoiding resource waste.

[0091] In some embodiments of this disclosure, the test process can be broken down into algorithm-level, instruction-level, and micro-operation-level layered collaborative execution through multi-level instruction execution. This hierarchical decomposition and division of labor significantly simplifies the conversion link from test algorithm to hardware execution, reducing the overall scheduling and computational complexity. Through a layered cache prefetching mechanism, a large amount of real-time computation and frequent storage access are converted into preprocessing, reducing the computational load and storage access frequency during the test execution phase. Furthermore, the resource allocation module accurately identifies and allocates idle resources, improving resource utilization efficiency and reducing idle power consumption.

[0092] In some embodiments of this disclosure, the method further includes:

[0093] The algorithm matching module receives the chip under test data and / or test requirement information and / or test result information sent by the processing module, and adaptively adjusts the algorithm type and / or algorithm parameters of the pre-calculation module.

[0094] In some implementations, the algorithm matching module may have an adaptive algorithm library, which can be stored in non-volatile memory. The algorithm matching module can receive the chip under test (DUT) data and / or test requirement information and / or test result information sent by the processing module. Specifically, it can adaptively match the algorithm type and / or adjust the algorithm parameters based on one or more of the DUT data, test requirement information, and test result information. This ensures the test algorithm always maintains optimal execution, improving test accuracy and adaptability.

[0095] In some embodiments of this disclosure, the algorithm configuration of the pre-computation module can be dynamically adjusted by the algorithm matching module according to chip data, test requirements and test results, so that the test process has adaptive optimization capabilities, thereby matching the test requirements of different types of memory chips and improving the flexibility and adaptability of the test scheme.

[0096] In some embodiments of this disclosure, S22 includes:

[0097] The intermediate representation code is parsed to identify the start and end addresses of the loop structure;

[0098] Calculate the address range and iteration count of the loop body in the loop structure, generate jump table entries containing address information and iteration information, and construct a multi-level associated address jump table for nested loop structures;

[0099] Pre-calculate the test data that can be pre-computed for the current test, and store the pre-computed test data in the pre-computed cache.

[0100] In some implementations, a pre-computation module can parse the intermediate representation code, identify the loop structure, and determine the start and end addresses of the loop. It can then calculate the address range and iteration count of the loop body, generating jump table entries containing address and iteration information. In cases of multi-level nested loops, multi-level jump tables can be generated and inter-level relationships established, forming a multi-level associated address jump table. Furthermore, pre-computable test data required for the current test can be pre-computed, and the pre-computed test data can be stored in a pre-computation cache, reducing the real-time computational pressure during the test execution phase.

[0101] In some embodiments of this disclosure, loop structures can be accurately identified and corresponding address jump tables can be constructed. For nested loop structures, multi-level associated address jump tables can also be constructed to achieve efficient execution of loops. Test data pre-calculation can be completed, reducing the real-time calculation pressure during the test execution phase and significantly improving the execution efficiency of complex test algorithms.

[0102] In some embodiments of this disclosure, S26 includes:

[0103] The test address sequence is calculated by the address generation unit based on the current address pointer and the address step size;

[0104] The data generation unit generates corresponding test graphic data based on the test algorithm type and the current test address sequence.

[0105] The timing control unit outputs drive timing signals that match the test requirements according to preset timing parameters;

[0106] The result comparison unit captures the output signal of the chip under test within the target sampling window and compares the output signal with the target data in real time.

[0107] In some implementations, the channel processing unit can be configured into different functional units, including local instruction storage, address generation, data generation, timing control, and result comparison. The address generation unit calculates the test address sequence based on the current address pointer and address step size; the data generation unit generates corresponding test graphic data or pseudo-random data based on the test algorithm type and the current test address sequence; the timing control unit outputs the edges of the drive timing signals that match the test requirements according to preset timing parameters; and the result comparison unit captures the output signal of the chip under test within the target sampling window and compares the output signal with the target data (e.g., the expected value) in real time.

[0108] In some embodiments of this disclosure, each channel processing unit can independently complete the entire testing process, including address calculation, data generation, timing control, and result comparison, ensuring the integrity and stability of single-channel testing. At the same time, independent operation of multiple channels can further improve the efficiency of parallel testing.

[0109] Some semiconductor testing methods disclosed herein can break down the testing process into algorithm-level, instruction-level, and micro-operation-level layered collaborative execution through multi-level instruction execution. This hierarchical decomposition and division of labor significantly simplifies the conversion link from test algorithms to hardware execution, reducing the overall scheduling and computational complexity. Through a layered cache prefetching mechanism, a large amount of real-time computation and frequent memory access are converted into preprocessing, reducing the computational load and memory access frequency during the test execution phase. Furthermore, the resource allocation module accurately identifies and allocates idle resources, improving resource utilization efficiency and reducing idle power consumption.

[0110] It is understood that the various embodiments of the methods described in this specification are presented in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. Related details can be found in the descriptions of other method embodiments.

[0111] It should be understood that although the steps in the flowcharts shown in the accompanying drawings are displayed sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some of the steps in the accompanying drawings may include multiple steps or stages, which are not necessarily completed at the same time, but may be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but may be performed alternately or in turn with other steps or at least a portion of the steps or stages of other steps.

[0112] In one embodiment, a computer device is provided, which may be a terminal, and its internal structure diagram may be as follows: Figure 6 As shown, the computer device includes a processor, memory, communication interface, display screen, and input device connected via a system bus. The processor provides computing and control capabilities. The memory includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage medium. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, mobile cellular networks, NFC (Near Field Communication), or other technologies. When executed by the processor, the computer program implements a semiconductor testing method.

[0113] Those skilled in the art will understand that Figure 6 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0114] Based on the foregoing description of the relevant methods and apparatus embodiments, this disclosure also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and when the computer program is executed by the processor, it implements the semiconductor testing method described in any embodiment of this specification.

[0115] Based on the foregoing description of the relevant methods and apparatus embodiments, this disclosure also provides a computer-readable storage medium that, when the instructions in the computer-readable storage medium are executed by the processor of a computer device, enables the computer device to implement the semiconductor testing method as described in any embodiment of this disclosure.

[0116] Based on the foregoing description of the relevant methods and apparatus embodiments, this disclosure also provides a computer program product, including a computer program that, when executed by a processor, implements the semiconductor testing method described in any embodiment of this specification.

[0117] Based on the foregoing description of the relevant methods and apparatus embodiments, this disclosure also provides a semiconductor testing device, including at least one of the above-described semiconductor testing apparatus and computer equipment.

[0118] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on its differences from other embodiments. In particular, hardware + program embodiments are relatively simple in description because they are fundamentally similar to method embodiments; relevant parts can be referred to the descriptions in the method embodiments.

[0119] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties.

[0120] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments described above. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.

[0121] It should be noted that the apparatus, computer equipment, storage medium, and computer program products described above may also include other implementation methods according to the description of the method embodiments. Specific implementation methods can be found in the description of the relevant method embodiments. Furthermore, new embodiments formed by combinations of features from various methods, apparatuses, devices, and server embodiments still fall within the scope of this disclosure and will not be elaborated upon here.

[0122] For ease of description, the above devices are described in terms of function, divided into various modules. Of course, when implementing one or more of these specifications, the functions of each module can be implemented in the same or different software and / or hardware, or a module that performs the same function can be implemented by a combination of multiple sub-modules or sub-units. The device embodiments described above are merely illustrative. For example, the division of modules or units is only a logical functional division; in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling and communication connections between the devices or units shown or described can be implemented through direct and / or indirect coupling / connection, through standard or custom interfaces or protocols, and can be implemented electrically, mechanically, or in other forms.

[0123] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the following claims.

[0124] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope.

Claims

1. A semiconductor testing apparatus, characterized in that, The device includes: The system comprises a processing module, a pre-computation module, a shared instruction cache module, multiple channel processing units, and a resource allocation module. The processing module is connected to a communication bus. The pre-computation module is communicatively connected to both the processing module and the shared instruction cache module. Each channel processing unit is communicatively connected to the shared instruction cache module, the resource allocation module, and the processing module. The processing module is used to receive and parse test data from at least one chip under test and generate corresponding intermediate representation codes. The pre-calculation module is used to generate an address jump table based on the intermediate representation code; The shared instruction cache module is used to store the intermediate representation code into the shared instruction cache, and to store the prefetched instructions into the local cache of the corresponding channel processing unit according to the address jump table by the prefetch controller; Multiple channel processing units are used to perform tests on the corresponding chip under test in parallel according to the prefetch instructions; The resource allocation module is used to monitor the operating load status information of each channel processing unit and adaptively allocate arithmetic logic unit resources among each channel processing unit according to the operating load status information.

2. The semiconductor testing apparatus according to claim 1, characterized in that, The device may further include a loop buffer for storing loop body instructions, the loop buffer being configured to support zero-overhead loop execution.

3. The semiconductor testing apparatus according to claim 1, characterized in that, The device further includes an algorithm matching module, which is communicatively connected to the processing module and the pre-computation module, respectively. The algorithm matching module is used to receive the chip under test data and / or test requirement information and / or test result information sent by the processing module, and adaptively adjust the algorithm type and / or algorithm parameters of the pre-calculation module.

4. The semiconductor testing apparatus according to claim 1, characterized in that, The channel processing unit includes at least one of a local instruction storage unit, an address generation unit, a data generation unit, a timing control unit, and a result comparison unit.

5. The semiconductor testing apparatus according to claim 4, characterized in that, The local instruction storage unit is used to store the prefetch instructions and / or test instructions executed by the current channel; The address generation unit is used to calculate the test address sequence based on the current address pointer and the address step size; The data generation unit is used to generate corresponding test graphic data according to the test algorithm type and the current test address sequence; The timing control unit is used to output drive timing signals that match the test requirements according to preset timing parameters; The result comparison unit is used to capture the output signal of the chip under test within the target sampling window and compare the output signal with the target data in real time.

6. The semiconductor testing apparatus according to claim 4, characterized in that, The data generation unit includes a linear feedback shift register and a data synthesis unit, and the linear feedback shift register and the data synthesis unit are communicatively connected.

7. The semiconductor testing apparatus according to claim 6, characterized in that, The linear feedback shift register includes at least one of a polynomial configuration register, a seed register, a parallel output register, and an overclock control unit; The polynomial configuration register is configured to programmatically set the feedback polynomial of the linear feedback shift register; The seed register is configured to load an initial seed from a prefetch instruction, or to obtain an optimized seed from the pre-computation module; The parallel output register is used to output multi-bit pseudo-random data in parallel. The overclock control unit is configured to operate at an integer multiple of the test cycle frequency to generate output data.

8. A semiconductor testing method, characterized in that, The method includes: The processing module receives and parses test data from at least one chip under test and generates the corresponding intermediate representation code. The pre-calculation module generates an address jump table based on the intermediate representation code; The intermediate representation code is stored in the shared instruction cache through the shared instruction cache module, and the prefetching instruction is stored in the local cache of the corresponding channel processing unit according to the address jump table through the prefetch controller. The test of the corresponding chip under test is executed in parallel by multiple channel processing units according to the prefetch instructions; The resource allocation module monitors the operating load status information of each channel processing unit and adaptively allocates arithmetic logic unit resources among the channel processing units based on the operating load status information.

9. A computer device, characterized in that, It includes a memory and a processor, the memory storing a computer program, and the processor executing the computer program to implement the steps of the method of claim 8.

10. A semiconductor testing device, characterized in that, It includes at least one of the semiconductor testing apparatus as described in any one of claims 1 to 7 and the computer device as described in claim 9.

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