Instruction-parallel computing methods, devices, electronic devices, storage media, and programs

Abstract

This invention discloses an instruction-parallel computing method, apparatus, electronic device, storage medium, and program. The method includes: acquiring sequential instruction arrangement information and the total number of target instruction slots for sequential computation of a currently executing instruction group in a single target instruction slot; uniformly distributing each instruction of the currently executing instruction group to each of the target instruction slots according to the sequential instruction arrangement information and the total number of target instruction slots; and performing parallel computation processing on the current input data according to the distribution result of the currently executing instruction group. The technical solution of this invention can compress the overall computation cycle of a vector processor, improving the instruction-level parallelism, computational efficiency, and computing power utilization of the vector processor.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to an instruction-parallel computing method, apparatus, electronic device, storage medium and program. Background Technology

[0002] In computational implementation scenarios using VLIW (Very Long Instruction Word), specifically those employing a SIMD (Single Instruction Multiple Data) + VLIW architecture to achieve high-speed parallel processing of large amounts of data, SIMD can compute k double-precision floating-point numbers simultaneously with a single instruction, while VLIW can execute J groups of SIMD instructions at the same time. For example, in the example architecture, each FMA instruction can compute 8 multiplications. Assuming there are 4 such FMAs [0-3], this means the maximum computing power can support 8 multiplications per cycle (clock cycle). 4. Due to the different calculation formulas for different operators, there may be dependencies between instructions during computation, and the instructions themselves may have different computation cycles. Therefore, gaps inevitably exist between different instructions when implementing a certain function. Thus, how to make better use of instructions, i.e., reduce cavitation, is the key to improving the overall performance of vector processors.

[0003] Currently, vector processors in VLIW architecture typically employ sequential computation and computational logic merging methods for parallel computation. Sequential computation allocates computation instructions to instruction slots sequentially according to the algorithm. This method is simple to develop, requiring no instruction slot allocation and offering high development efficiency, but its execution efficiency is low because its loop body is the width from the first instruction to the last. Computational logic merging allocates computational logic consecutively to the same instruction slots, utilizes as many instruction slots as possible for task distribution, and finally uses synchronous pipelines to align instructions, shortening the actual loop body. This method is also relatively easy to implement, but its efficiency is not optimal. In summary, the parallel computation processes performed by vector processors in the current VLIW architecture cannot fully utilize remaining idle computing power, cannot achieve extreme customization, and the utilization rate of computing power always has an upper limit bottleneck. Summary of the Invention

[0004] This invention provides an instruction-parallel computing method, apparatus, electronic device, storage medium, and program that can compress the overall computing cycle of a vector processor and improve the instruction-level parallelism, computing efficiency, and computing power utilization of the vector processor.

[0005] According to one aspect of the present invention, an instruction-parallel computing method is provided, comprising: Obtain the sequential instruction arrangement information and the total number of target instruction slots for the current execution instruction group to be calculated sequentially in a single target instruction slot; Based on the sequential instruction arrangement information of the current instruction group and the total number of target instruction slots, each instruction of the current instruction group is evenly distributed to each of the target instruction slots; The current input data is processed in parallel based on the allocation result of the current instruction group.

[0006] According to another aspect of the present invention, an instruction-parallel computing device is provided, comprising: The instruction arrangement and instruction slot information acquisition module is used to acquire the sequential instruction arrangement information and the total number of target instruction slots for the current execution instruction group to perform sequential calculations in a single target instruction slot. The instruction uniform distribution module is used to evenly distribute each instruction of the current execution instruction group to each of the target instruction slots according to the sequential instruction arrangement information of the current execution instruction group and the total number of target instruction slots; The data parallel computing processing module is used to perform parallel computing processing on the current input data according to the allocation result of the current execution instruction group.

[0007] According to another aspect of the present invention, an electronic device is provided, the electronic device comprising: At least one processor; and a memory communicatively connected to said at least one processor; wherein, The memory stores a computer program that can be executed by the at least one processor, which enables the at least one processor to execute the instruction-parallel computing method described in any embodiment of the present invention.

[0008] According to another aspect of the present invention, a computer-readable storage medium is provided, the computer-readable storage medium storing computer instructions for causing a processor to execute and implement the instruction-parallel computing method described in any embodiment of the present invention.

[0009] According to another aspect of the present invention, a computer program product is also provided, comprising a computer program that, when executed by a processor, implements the instruction-parallel computing method described in any embodiment of the present invention.

[0010] This invention, through obtaining the sequential instruction arrangement information of the currently executing instruction group in a single target instruction slot and the total number of target instruction slots, evenly distributes each instruction of the currently executing instruction group to each target instruction slot based on the sequential instruction arrangement information and the total number of target instruction slots. Then, it performs parallel computation processing on the current input data based on the allocation result of the currently executing instruction group. This technical solution can utilize the processor's idle instruction slots for real-time compensation operations without increasing hardware costs or compromising computational accuracy and correctness. It solves the problem of low computational efficiency in existing processors when performing parallel instruction processing, compresses the overall computation cycle of the vector processor, and improves the instruction-level parallelism, computational efficiency, and computing power utilization of the vector processor.

[0011] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 This is a schematic diagram illustrating the computational intensity of the loop body corresponding to the parallel instruction that executes a set of data using the sequential computation method in the existing VLIW architecture. Figure 2 This is a schematic diagram illustrating the computational intensity of the loop body corresponding to the parallel instructions that execute n sets of data using the sequential computation method in the existing VLIW architecture. Figure 3 This is a schematic diagram illustrating the computational intensity of the loop body corresponding to the parallel instruction that executes a set of data using the computational logic merge method in the existing VLIW architecture. Figure 4 This is a schematic diagram illustrating the computational intensity of the loop body corresponding to the parallel instructions that execute n sets of data using the computational logic merge method in the existing VLIW architecture. Figure 5 This is a flowchart of an instruction-parallel computing method provided in Embodiment 1 of the present invention; Figure 6 This is a flowchart of an instruction-parallel computing method provided in Embodiment 2 of the present invention; Figure 7 This is a schematic diagram illustrating the effect of arranging some instructions in an instruction group according to Embodiment 2 of the present invention; Figure 8 This is a schematic diagram illustrating the effect of allocating core loop body placeholders to each instruction within a set of instructions, as provided in Embodiment 2 of the present invention. Figure 9 This is a schematic diagram illustrating the effect of uniformly distributing each instruction within a set of instructions to the target instruction slot, as provided in Embodiment 2 of the present invention. Figure 10 This is a schematic diagram illustrating the effect of adjusting the position of a command, provided in Embodiment 2 of the present invention. Figure 11 This is a schematic diagram illustrating the effect of multi-round cyclic execution of an instruction group provided in Embodiment 2 of the present invention; Figure 12 This is a schematic diagram illustrating the effect of another instruction group multi-round cyclic execution provided in Embodiment 2 of the present invention; Figure 13 This is a schematic diagram of an instruction-parallel computing device provided in Embodiment 3 of the present invention; Figure 14 This is a schematic diagram of the structure of an electronic device provided in Embodiment 4 of the present invention. Detailed Implementation

[0014] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0015] It should be noted that the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to such process, method, product or device.

[0016] A vector processor (CPU) is a central processing unit (CPU) architecture capable of directly manipulating one-dimensional arrays (vectors). Its core characteristic is Single Instruction Multiple Data (SIMD) execution, meaning that a single instruction performs the same operation on multiple data elements simultaneously, a stark contrast to scalar processors that process only a single data element at a time. The FMA (Fused Multiply-Add) unit and the interleaving unit are both hardware functional modules within a vector processor. The FMA unit is composed of dedicated logic circuits made of transistors, including multipliers, adders, shifters, and rounding logic, responsible for performing fused multiplication and addition operations and rounding only once within a single clock cycle. In the VLIW architecture, the compiler packages multiple independent instructions, and the instruction pointing to the FMA slot directly triggers the execution of that hardware unit. The FMA unit itself does not handle dynamic scheduling; it only executes the instructions. The interleaving unit is used for data interleaving and logical processing based on the instructions. The interleaving unit is the control and data processing unit within the vector processor. It is responsible for interleaving data, supporting logical and some fixed-point / floating-point calculations, as well as numerous customized instructions, including table lookup, lateral computation, sparse matrix computation, precision conversion, and FIFO (First Input First Output) functions. It executes instructions such as data broadcasting, decimation, and internal interleaving. Each interleaving unit has a set of private vector registers; therefore, there is a one-to-one correspondence between the private vector registers of each interleaving unit and the interleaving unit itself. For a vector processor, the loop body refers to a software loop unrolling code block designed to maximize instruction slot throughput. Its core is to mask instruction latency and fully utilize the issue port by filling a single loop iteration with multiple data-independent instructions.

[0017] Currently, VLIW architectures typically employ two parallel computation methods for loop bodies: sequential computation and computational logic merging. Sequential computation allocates instructions to the corresponding instruction slots in the algorithm's native order, with the loop body covering the entire instruction width. While this method is easy and efficient to develop, its extremely large loop body instruction span results in very low instruction slot parallel utilization and a significant waste of hardware computing power. Figure 1 This is a schematic diagram illustrating the computational intensity of the loop body corresponding to a parallel instruction that executes a set of data using a sequential computation method in the existing VLIW architecture. Figure 2 This is a schematic diagram illustrating the computational intensity of the loop body corresponding to parallel instructions executing n sets of data using a sequential computation method in the existing VLIW architecture. In a specific example, such as... Figure 1 and Figure 2As shown, taking the FMA instruction slot as an example, each clock cycle between LOOP_START and LOOP_END in the FMA instruction slot constitutes a loop body. LOOP_START represents the start of the loop body, and LOOP_END represents the end of the loop body. Each rectangular cell represents a logical cycle. Within LOOP_START-LOOP_END, cnt1-cntn represent n instructions, where cnt1 is the first instruction in the loop body, occupying 2 clock cycles. cntn is the nth instruction in the loop body, occupying 1 clock cycle. Assuming n is 14, the computational cost is equivalent to 14 cycles in LOOP_START-LOOP_END. Therefore, if you want to compute n sets of data, the computation time is ceil(N / k). 14, meaning the calculation pattern for each k inputs is as follows: Figure 2 As shown. At this point, there are a total of 7 valid computation instructions, and 7 empty bubbles in the FMA0 instruction slot. If there are a total of 4 FMAs, then FMA[1-3] are unused, and the empty bubble count is 14. 3. The total cavitation is: (7+14) 3)n.

[0018] The principle of computational logic merging is to consolidate consecutive associative computations into the same instruction slot, filling as many slots as possible. This is achieved by synchronizing the pipeline through pipeline alignment instructions, specifically the WAIT instruction, thus shortening the loop. The WAIT instruction sets all instructions in the corresponding slot to execute with a predefined delay, synchronizing all slots and achieving pipeline alignment. While computational logic merging offers improved efficiency compared to sequential computation, its uneven task load distribution leads to underutilization of instruction slot resources, resulting in a lower theoretical performance ceiling and an inability to fully exploit computational limits. Figure 3 This is a schematic diagram illustrating the computational intensity of the loop body corresponding to the parallel instructions that execute one set of data using the computational logic merge method in the existing VLIW architecture. Figure 4 This is a schematic diagram illustrating the computational intensity of the loop body corresponding to the parallel instructions executing n sets of data using the computational logic merge method in the existing VLIW architecture. In a specific example, such as... Figure 3 and Figure 4 As shown, taking the FMA instruction slot as an example, if the computational logic merging method is used to execute the above n instructions, the computational logic merging method can compress the loop body to 4 cycles, that is, the next set of data calculations will be executed in multiples of 4. Figure 4 As shown, if the different instruction slots are aligned using the synchronous pipeline alignment instruction, i.e., the WAIT instruction, the effect is the same as the effect of the right-hand loop, i.e., the core loop is 4 cycles, and the calculation time is ceil(N / k). 4 + 10, where 10 is the total time spent on each round of non-WAIT instructions minus the time spent on the loop body after the WAIT instruction. Here, the total time is still 14, and the loop body time is 4. The resulting cavitation is 1 of FMA0 slot + 2 of FMA1 slot + 2 of FMA2 slot + 4 of FMA3 slot, which is 9. n. Figure 4 A position within the loop with no instruction is considered an empty bubble. FMA4 is in an idle state, therefore... Figure 4 Not shown in the image.

[0019] Example 1 Figure 5 This is a flowchart of an instruction-parallel computing method provided in Embodiment 1 of the present invention. This embodiment is applicable to situations where each instruction in an instruction group is evenly distributed to its corresponding instruction slot. This method can be executed by an instruction-parallel computing device, which can be implemented in software and / or hardware, and is generally integrated into an electronic device. This electronic device can be a terminal device or a server device, as long as it can execute the instruction-parallel computing method. The present invention does not limit the specific type of electronic device. Correspondingly, as... Figure 5 As shown, the method includes the following operations: S510. Obtain the sequential instruction arrangement information and the total number of target instruction slots for the current execution instruction group to be calculated sequentially in a single target instruction slot.

[0020] The currently executing instruction group can be a set of instructions within a vector processor that requires parallel computation through a loop. The target instruction slot can be an instruction slot capable of processing each instruction within the currently executing instruction group, and can be any type of data transfer instruction slot. For example, the target instruction slot can be one or more of an FMA instruction slot, an interleaving unit instruction slot, or an instruction slot for processing memory move instructions; this embodiment of the invention does not limit the type of the target instruction slot. A single target instruction slot can be of one type. For example, when an FMA instruction slot is needed to process the currently executing instruction group, the single target instruction slot can be one of the FMA instruction slots. The sequential instruction arrangement information can be the information showing how each instruction in the currently executing instruction group is arranged sequentially within a loop within a single target instruction slot according to the instruction processing flow. The total number of target instruction slots is also the total number of target instruction slots used to process the currently executing instruction group.

[0021] It is understandable that each algorithm implemented by a vector processor consists of a set of instructions. When parallel computation optimization is needed for the instruction set corresponding to an algorithm, it can be used as the current execution instruction set. For example, the algorithm type corresponding to the current execution instruction set can include, but is not limited to, trigonometric functions, power functions, and various multi-branch high-precision calculation algorithms from nonlinear mathematics libraries. Simultaneously, each vector processor is configured with multiple types of target instruction slots, and each type of target instruction slot can include multiple types of instruction slots. For example, a vector processor typically includes multiple types of target instruction slots, such as FMA instruction slots, interleaving unit instruction slots, and instruction slots for handling memory move instructions. Taking FMA instruction slots as an example, FMA instruction slots can also include four types of FMA instruction slots: FMA0, FMA1, FMA2, and FMA3. Some vector processors may also include eight types of FMA instruction slots: FMA0-FMA7.

[0022] When a vector processor receives the currently executing instruction set, it can first determine the type of target instruction slot appropriate for processing that instruction set. For example, if the instructions in the currently executing instruction set are various calculation instructions related to floating-point numbers or long integers, the FMA instruction slot can be determined as the target instruction slot. If the instructions in the currently executing instruction set are various calculation instructions related to integers, the instruction slot of the interleaving unit can be determined as the target instruction slot. If the instructions in the currently executing instruction set are memory movement instructions, the instruction slot used to process memory movement instructions can be determined as the target instruction slot.

[0023] Furthermore, the vector processor can parse each instruction in the currently executing instruction group to determine its function and execution requirements. Based on the instruction parsing results, it can then determine the instruction order and arrangement information when each instruction in the current execution instruction group is sequentially computed in a single target instruction slot. Simultaneously, the vector processor can obtain the total number of target instruction slots used to execute the current execution instruction group, providing a reference for the even distribution of instructions within the current execution instruction group.

[0024] S520. Based on the sequential instruction arrangement information of the currently executed instruction group and the total number of target instruction slots, evenly distribute each instruction of the currently executed instruction group to each of the target instruction slots.

[0025] Accordingly, when optimizing parallel computation for the currently executing instruction set, the instructions of the current execution instruction set can be evenly distributed among the target instruction slots based on the total number of target instruction slots included in the vector processor for processing the current execution instruction set and the sequential instruction arrangement information of the current execution instruction set. Even distribution of instructions means uniformly allocating each instruction of the current execution instruction set to each target instruction slot, ensuring that each occupied instruction slot receives the same or approximately the same number of instructions, guaranteeing a highly balanced instruction load for each occupied instruction slot with minimal bias. The instructions evenly distributed to each target instruction slot need to be sorted within each target instruction slot. The purpose of sorting is to ensure that each occupied instruction slot can achieve pipeline alignment of the instructions within the instruction slot according to the execution order of the instructions in the current execution instruction set. If multiple sets of the current execution instruction set need to be executed in parallel, the multiple sets of concurrently executed current execution instruction sets can be staggered in timing during sorting to avoid memory access and read / write conflicts for instructions of the same type.

[0026] For example, taking FMA instruction slots as the target instruction slots, if the number of target instruction slots is 2, that is, including two types of FMA instruction slots, FMA0 and FMA1, then all instructions in the currently executing instruction group can be evenly distributed between FMA0 and FMA1. If the currently executing instruction group includes a total of 8 instructions, then each instruction slot in FMA0 and FMA1 can be allocated 4 instructions, and the execution order of the instructions allocated in each instruction slot in FMA0 and FMA1 can be sorted and aligned.

[0027] S530. Perform parallel computation processing on the current input data according to the allocation result of the current execution instruction group.

[0028] Accordingly, after instruction allocation is completed, each instruction in the current execution instruction group can be executed sequentially according to its sorting and allocation in the corresponding target instruction slot, thereby realizing the parallel computation processing of the current input data. A single current execution instruction group can complete the parallel computation processing of the current input data, but executing multiple current execution instruction groups simultaneously can further improve the instruction-level parallelism under the VLIW architecture.

[0029] Therefore, the above technical solution can perform real-time computation by dynamically scheduling idle instruction slots. Through dedicated instruction scheduling design, it achieves computational power supplementation of vector processors without increasing hardware costs or compromising computational accuracy and correctness. It can revitalize the idle computing power of idle instruction slots, effectively compressing the overall instruction computation cycle and significantly improving the instruction-level parallelism under the VLIW architecture. In scenarios such as mathematical library computation, it can achieve computational performance improvements that exceed theoretical limits. The above technical solution is not limited to specific mathematical functions or branch logic and has strong versatility. Regardless of algorithm complexity, computational power supplementation can be achieved through the above dynamic scheduling optimization method.

[0030] This invention, through obtaining the sequential instruction arrangement information of the currently executing instruction group in a single target instruction slot and the total number of target instruction slots, evenly distributes each instruction of the currently executing instruction group to each target instruction slot based on the sequential instruction arrangement information and the total number of target instruction slots. Then, it performs parallel computation processing on the current input data based on the allocation result of the currently executing instruction group. This technical solution can utilize the processor's idle instruction slots for real-time compensation operations without increasing hardware costs or compromising computational accuracy and correctness. It solves the problem of low computational efficiency in existing processors when performing parallel instruction processing, compresses the overall computation cycle of the vector processor, and improves the instruction-level parallelism, computational efficiency, and computing power utilization of the vector processor.

[0031] Example 2 Figure 6 This is a flowchart of an instruction parallel computing method provided in Embodiment 2 of the present invention. This embodiment is based on the above embodiment and is further specified. In this embodiment, various specific optional implementation methods are given for obtaining the sequential instruction arrangement information of the currently executed instruction group for sequential computation in a single target instruction slot and for evenly distributing each instruction of the currently executed instruction group to each target instruction slot. Accordingly, as Figure 6 As shown, the method in this embodiment may include: S610. Determine the dependencies between individual instructions in the currently executed instruction group and the instruction execution cycle of each individual instruction.

[0032] The instruction execution cycle is the clock cycle required to execute one instruction.

[0033] It is understandable that different instructions within an instruction set may have dependencies or may execute independently. For example, if the output of cnt1 serves as part of the input to cnt2 in the computation process, then cnt1 and cnt2 have a dependency relationship; if the output of cnt1 and the input of cnt2 have no relationship, meaning cnt1 and cnt2 can execute independently, then cnt1 and cnt2 do not have a dependency relationship. While determining the dependencies between individual instructions in the currently executing instruction set, the vector processor can determine the instruction execution cycle of each individual instruction in the currently executing instruction set based on the parsing results of each instruction. The instruction execution cycle of a single instruction must include at least one clock cycle. Each clock cycle can only process one instruction from a single target instruction slot.

[0034] S620. Based on the dependencies between the individual instructions and the instruction execution cycle of each individual instruction, determine the sequential arrangement information of each individual instruction in a single target instruction slot.

[0035] Specifically, the vector processor can first determine the instruction execution order of each individual instruction in the current instruction group, and then determine the sequential arrangement order of each individual instruction in a single target instruction slot based on the instruction execution order of each individual instruction in the current instruction group. Further, based on the dependencies between individual instructions and the instruction execution cycle of each individual instruction, it determines the clock cycles required for the staggered arrangement of each individual instruction in the single target instruction slot. Then, it inserts corresponding clock cycles between the sequential arrangement order of each individual instruction in the single target instruction slot to meet the arrangement requirements of the instruction execution cycles between dependent individual instructions, ultimately obtaining the sequential arrangement information of each individual instruction in the single target instruction slot.

[0036] In a specific example, such as Figure 1 As shown, assume the current instruction set includes n instructions, cnt1-cntn. The vector processor can first determine the execution order of cnt1-cntn, i.e., executing cnt1 sequentially to cntn. Based on the execution order of individual instructions in the current instruction set, it can determine the sequential arrangement of each individual instruction in a single target instruction slot. For example, starting from cnt1, the n instructions (cnt1-cntn) might be arranged sequentially over n clock cycles. Furthermore, the dependencies between individual instructions and their execution cycles are determined. Based on these dependencies and execution cycles, the required number of clock cycles for each individual instruction to be arranged in a staggered manner within a single target instruction slot can be determined. Figure 1As shown, if there is a dependency between cnt1 and cnt2, the output of cnt1 is used as the input data for cnt2. If the instruction execution cycle of cnt1 is two clock cycles, an idle clock cycle needs to be inserted between cnt1 and cnt2, meaning that cnt2 will be executed only after cnt1 has completed its two-clock-cycle execution. If there is no dependency between cnt2 and cnt3, i.e., cnt3 can execute independently without waiting for the execution result of cnt2, no idle clock cycle needs to be inserted between cnt2 and cnt3. Regardless of how many clock cycles cnt2's instruction execution cycle includes, cnt3 can be executed immediately in the next clock cycle after cnt2's instruction has been issued from the instruction slot. Similarly, the instruction adjustments for cnt4-cntn can be made in the same way to obtain the following results. Figure 1 The final sequential arrangement information of the cnt1-cntn instructions is shown.

[0037] S630. Obtain the total number of target instruction slots. Based on the total number of instructions in the currently executed instruction group and the total number of target instruction slots, determine the number of instructions included in the core loop body of the currently executed instruction group that each target instruction slot will process.

[0038] The core loop body can be the basic loop body distributed in each target instruction slot when the currently executing instruction group performs multiple rounds of loop processing.

[0039] After determining the total number of target instruction slots, the vector processor can determine the number of instructions from the current instruction set to be evenly distributed among the target instruction slots, based on the total number of instructions in the current instruction set and the total number of target instruction slots. The instructions evenly distributed among the target instruction slots can constitute the core loop body for each target instruction slot to process the corresponding instruction set. Each target instruction slot then performs multiple rounds of iterative computation on a portion of the instructions in the current instruction set, based on its own core loop body.

[0040] In an optional embodiment of the present invention, determining the number of instructions included in the core loop of the current instruction group processed by each target instruction slot based on the total number of instructions in the current instruction group and the total number of target instruction slots may include: dividing the total number of instructions in the current instruction group by the total number of target instruction slots; if the division result does not include a remainder, directly using the value of the division result as the number of instructions included in the core loop; if the division result includes a remainder, using the value of the quotient rounded up as the number of instructions included in the core loop.

[0041] Specifically, vector processors can directly divide the total number of instructions in the current instruction set by the total number of target instruction slots. If the total number of instructions in the current instruction set is divisible, the division result does not include a remainder, indicating that the total number of instructions in the current instruction set can be evenly distributed among the target instruction slots. In this case, the division result can be directly used as the number of instructions included in the kernel loop. Furthermore, after the instructions in the current instruction set are evenly distributed among the target instruction slots, there will be no idle instruction slots, maximizing the utilization of idle computing power in idle instruction slots and achieving maximum performance gains. If the total number of instructions in the current instruction set is not divisible, the division result includes a remainder, indicating that the total number of instructions in the current instruction set cannot be evenly distributed among the target instruction slots. In this case, the quotient in the division result can be rounded up as the number of instructions included in the kernel loop. In cases where the instruction cannot be evenly divided, there will be idle instruction slots after the instructions of the current instruction group are evenly distributed to the target instruction slot. However, compared with the sequential calculation method and the calculation logic merging method, the idle instruction slot resources can be greatly reduced, so a significant improvement in hardware utilization can still be achieved.

[0042] S640. Distribute each instruction of the currently executed instruction group evenly to each of the target instruction slots according to the number of instructions included in the core loop.

[0043] Once the number of instructions in the core loop of the currently executing instruction group is determined for each target instruction slot, the instructions in the currently executing instruction group can be evenly distributed to each target instruction slot based on the number of instructions in the core loop.

[0044] In a specific example, taking the FMA instruction slot as the target instruction slot, assuming the current instruction set includes 8 instructions and the vector processor includes 4 types of FMA instruction slots, then 2 instructions can be evenly allocated to each FMA instruction slot. If the current instruction set includes 11 instructions and the vector processor includes 4 types of FMA instruction slots, then 3 instructions can be allocated to each FMA instruction slot. Since the current instruction set includes a total of 11 instructions, after evenly distributing these 11 instructions to the 4 types of FMA instruction slots, the core loop of one FMA instruction slot will contain 3 instructions and one idle instruction slot.

[0045] In an optional embodiment of the present invention, the step of evenly distributing each instruction of the currently executing instruction group to each of the target instruction slots according to the number of instructions included in the core loop body may include: determining the initial instruction position of each instruction of the currently executing instruction group within the initial loop body; assigning a core loop body placeholder identifier to each instruction of the currently executing instruction group according to the initial instruction position of each instruction of the currently executing instruction group within the initial loop body; determining a local instruction group evenly distributed to each of the target instruction slots according to the core loop body placeholder identifiers assigned to each instruction of the currently executing instruction group and the number of instructions included in the core loop body; adjusting the initial instruction position of each instruction in the local instruction group to obtain the target instruction position of each instruction in the local instruction group, and updating the core loop body placeholder identifier at the target instruction position, wherein the core loop body placeholder identifiers at the target instruction positions of each instruction in the local instruction group are different; configuring a synchronous pipeline alignment instruction for each of the target instruction slots according to the dependency relationship between the local instruction groups allocated to each of the target instruction slots.

[0046] The initial loop body can be the loop body formed by the sequential arrangement of all instructions in the currently executing instruction group within a single target instruction slot. The initial instruction position can be the instruction slot position allocated to each instruction in the currently executing instruction group within the initial loop body. The kernel loop body placeholder can be the absolute position marker of the instruction within the kernel loop body. The local instruction group is the instruction group consisting of the portion of the currently executing instruction group allocated to the target instruction slot.

[0047] When evenly distributing the instructions of the currently executing instruction group to the target instruction slots based on the number of instructions in the kernel loop, two constraints need to be considered: algorithmic constraints and hardware constraints. Algorithmic constraints stipulate that the instructions allocated to each FMA are related, therefore the order of instructions cannot be adjusted. Hardware constraints, due to computational rules, prevent reducing the number of idle clock cycles between instructions. One clock cycle represents one period of time, and an idle clock cycle represents the clock cycle of the idle state, which can also be understood as an idle instruction slot. Figure 7 This is a schematic diagram illustrating the effect of arranging some instructions in an instruction group according to Embodiment 2 of the present invention. In a specific example, such as Figure 7 As shown, assuming the instructions cnt3 and cnt4 are dependent, requiring a two-clock interval between them, the result of cnt3 can only be calculated after three clock cycles. Therefore, moving the cnt4 instruction to the clock cycles corresponding to positions 5 or 6 will result in a calculation error. During instruction allocation, the position of the cnt4 instruction can only be greater than or equal to position 7.

[0048] Accordingly, the vector processor can first determine the initial instruction position of each instruction in the current instruction group within the initial loop body of a single target instruction slot. Then, based on the initial instruction position of each instruction in the current instruction group within the initial loop body, and combined with the number of instructions included in the core loop body, it calculates and generates core loop body placeholders allocated to each instruction in the current instruction group. After determining the core loop body placeholders allocated to each instruction, it can determine the evenly distributed local instruction groups for each target instruction slot based on the allocated core loop body placeholders and the number of instructions included in the core loop body. To further improve the utilization of instruction slots, it can be ensured that the core loop body placeholders of the local instruction groups allocated to one type of target instruction slot do not conflict as much as possible.

[0049] Figure 8 This is a schematic diagram illustrating the effect of allocating core loop body placeholders to each instruction within a set of instructions, as provided in Embodiment 2 of the present invention. Figure 9 This is a schematic diagram illustrating the effect of uniformly distributing instructions within a set of instructions to a target instruction slot, as provided in Embodiment 2 of the present invention. In a specific example, the FMA instruction slot is used as the target instruction slot for illustration. Figure 8 and Figure 9 As shown, assume the currently executing instruction group includes 10 instructions, cnt1-cnt10. (Reference) Figure 8 When the 10 instructions in the current instruction set are sequentially arranged in FMA0, cnt1-cnt10 occupy a total of 17 clock cycles, meaning the initial loop length is 17. Assuming there are two types of FMA instruction slots, FMA0 and FMA1, and since the total number of instructions in the current instruction set is 10, the kernel loop contains 5 instructions, meaning the kernel loop length is 5. Allocating 5 instructions to each type of FMA instruction slot is the optimal allocation method.

[0050] First, such as Figure 8 As shown, the vector processor can determine the initial instruction position of each instruction in the current execution instruction group within the initial loop body, resulting in (1)1, (2)3, (3)4, (4)7, (5)8, (6)10, (7)11, (8)14, (9)16, and (10)17. Here, (1)1 indicates that the initial instruction position of cnt1 is 1, and (4)7 indicates that the initial instruction position of cnt4 is 7. That is, the number in parentheses indicates the instruction number, while the number outside the parentheses indicates the initial instruction position. Further, based on the initial instruction position of each instruction in the current execution instruction group within the initial loop body and the number of instructions included in the kernel loop body, a kernel loop body placeholder is assigned to each instruction in the current execution instruction group. For example, the formula for calculating the kernel loop body placeholder can be: Y = Xa floor(X / m) m or Y = X + a floor(X / m) m, etc. Here, Y represents the kernel loop body placeholder identifier, X represents the initial instruction position, m represents the number of instructions included in the kernel loop body, floor() function represents rounding down, and a represents an integer, optional; a value of 1 results in the highest instruction slot utilization. In the example above, m=5. That is, in the above example, the formula for calculating the kernel loop body placeholder identifier can be: Y=X-floor(X / 5) 5. Accordingly, based on the formula Y=X-floor(X / 5) 5. The initial instruction position of each instruction can be used to calculate the core loop body placeholder of each instruction: (1)1, (2)3, (3)4, (4)2, (5)3, (6)5, (7)1, (8)4, (9)1, (10)2. Similarly, the number in the parentheses indicates which instruction, and the number outside the parentheses can indicate the core loop body placeholder of the instruction.

[0051] To ensure that multi-round loop instruction slots do not conflict, when determining the local instruction groups to be evenly distributed among target instruction slots based on the allocation of core loop body placeholders and the number of instructions included in the core loop body for each instruction in the currently executed instruction group, the instructions with the first complete set of core loop body placeholders can be prioritized and allocated to one target instruction slot as the local instruction group allocated to that target instruction slot. For example, as... Figure 8 and Figure 9 As shown, the instructions can be allocated as follows: the first occurrences (1)1, (2)3, (3)4, (4)2, (6)5, i.e., cnt1, cnt2, cnt3, cnt4, and cnt6, are grouped into a local instruction set and assigned to slot FMA0. The remaining instructions are then assigned to slot FMA1, i.e., (5)3, (7)1, (8)4, (9)1, and (10)2, resulting in the following: Figure 9 The diagram shows the effect of instruction allocation.

[0052] Each target instruction slot is evenly allocated to corresponding local instruction groups. Conflict checks can be performed on the core loop body placeholders of each instruction within the local instruction group for each target instruction slot to ensure that each core loop body placeholder is unique. Once a conflict is determined between the core loop body placeholders of instructions within a local instruction group, to avoid calculation errors, the initial instruction positions of each instruction in the local instruction group need to be adjusted promptly to obtain the target instruction positions of each instruction, and the core loop body placeholders at the target instruction positions are updated. The core principle of this adjustment is that the core loop body placeholders at the target instruction positions of each instruction in the local instruction group must be distinct.

[0053] In an optional embodiment of the present invention, adjusting the initial instruction position of each instruction in the local instruction group may include: determining conflicting instructions that conflict with the core loop body placeholder identifier in the local instruction group; filtering the conflicting instructions into a baseline conflicting instruction and a target adjustment conflicting instruction; keeping the initial instruction position of the baseline conflicting instruction unchanged, and shifting the instruction position of the target adjustment conflicting instruction downwards.

[0054] Among them, the baseline conflict instruction can be an instruction that does not require adjustment of the initial instruction position. The target adjustment conflict instruction can be an instruction that requires adjustment of the initial instruction position.

[0055] Specifically, when adjusting the initial instruction positions of each instruction in a local instruction group, instructions that conflict with the core loop body placeholder markers can be first filtered out, and these filtered conflicting instructions can be further divided into baseline conflicting instructions and target adjustment conflicting instructions. Furthermore, the initial instruction position of the baseline conflicting instructions remains unchanged; optionally, there can be only one baseline conflicting instruction. Simultaneously, to ensure sufficient execution cycles for the instructions, the instruction position of the target adjustment conflicting instructions can be shifted downwards. Optionally, there can be one or more target adjustment conflicting instructions. It should be noted that new conflicting instructions may be generated during the downward adjustment of the target adjustment conflicting instructions. When new conflicting instructions are generated during the adjustment of the target adjustment conflicting instructions, the updated instruction positions of each conflicting instruction can be adjusted using the same instruction position adjustment method described above.

[0056] Figure 10 This is a schematic diagram illustrating the effect of adjusting the position of a command according to Embodiment 2 of the present invention. In a specific example, such as... Figure 9 As shown, since the core loop body placeholder identifier of each instruction in the local instruction group of FMA0 appears only once, that is, the FMA0 slot completes the instruction allocation according to the constraint conditions, and each instruction has a unique placeholder in the core loop body of length 5. However, among the instructions allocated in the FMA1 slot, (7)1 and (9)1 conflict, that is, the core loop body placeholder identifiers of cnt7 and cnt9 are the same, and a conflict occurs. At this time, cnt7 can be used as the base conflict instruction, keeping its instruction position unchanged, and cnt9 can be used as the target adjustment conflict instruction, shifting down to adjust the instruction position of cnt9. In order to minimize the idle instruction slot resources as much as possible, such as Figure 10As shown, shifting cnt9 down by one clock cycle updates its core loop body placeholder flag to 2, thus avoiding conflict with (7)1. Simultaneously, to comply with hardware constraints, cnt10 also shifts down by one clock cycle, updating its core loop body placeholder flag to (10)3. At this point, the updated core loop body placeholder flag 3 of cnt10 conflicts with the core loop body placeholder flag 3 of cnt5. Therefore, as... Figure 10 As shown, the core loop body placeholders that have been used are 1, 2, 3 and 4. Only the core loop body placeholder of 5 is not used. Therefore, cnt10 can be shifted down by two clock cycles. The core loop body placeholder of cnt10 is updated to (10)5 again, which finally satisfies the instruction allocation requirements that the core loop body placeholders at the target instruction positions of each instruction are different.

[0057] To better demonstrate the execution effect of the core loop body in multi-round loops, it is necessary to perform multiple rounds of expansion in the multi-round loop execution scenario of the instruction group in order to find the final core loop body. Figure 11 This is a schematic diagram illustrating the effect of multi-round cyclic execution of an instruction group according to Embodiment 2 of the present invention. Figure 12 This is a schematic diagram illustrating the effect of another instruction group multi-round loop execution provided in Embodiment 2 of the present invention. In a specific example, such as Figure 11 and Figure 12 As shown, the kernel loop can appear during the fourth iteration of the instruction group execution. The kernel loop is the interval within each target instruction slot containing all instructions of the currently executing instruction group. For example... Figure 12 As shown, this means that for each additional round of computation of the currently executing instruction group, the overall overhead of instruction execution only increases by 5. Total overhead = pre-calculation overhead + loop overhead. N+ post-overhead overhead. Therefore, it can be seen that while the above-mentioned instruction parallel computing method, which distributes instructions evenly, may introduce pre- or post-overhead overhead, it can greatly reduce the time consumed by the core loop body overhead. Since the performance of the operator is mainly determined by the loop body overhead, this instruction parallel computing method can maximize the utilization of all instruction slots and maximize performance improvement.

[0058] After evenly distributing the instructions of the current instruction group to the target instruction slots, it is necessary to configure synchronous pipeline alignment instructions (WAIT instructions) for each target instruction slot based on the dependencies between the local instruction groups allocated to each target instruction slot. This completes synchronous wait compression and full pipeline timing alignment, ultimately compressing the overall core loop depth limit to the minimum number of clock cycles. The WAIT instruction sets all instructions in the corresponding target instruction slot to execute with a set delay period value to align all target instruction slots, thereby achieving pipeline synchronous alignment of instructions. The delay period of each WAIT instruction can be determined based on the dependencies between the local instruction groups allocated to the target instruction slot. Optionally, the specific delay period of the WAIT instruction for each target instruction slot can be determined based on the actual clock cycle interval between the first instructions of each target instruction slot.

[0059] For example, such as Figure 12 As shown, since the first instruction group of FMA0 has no misalignment or offset arrangement adjustment, the extension period value of the WAIT instruction in the first instruction group is 0, meaning that the first instruction group does not need to be delayed in execution. Since the first instruction cnt5 in the second instruction group is extended by 7 clock cycles compared to the first instruction cnt1 in the first instruction group, the extension period value of the WAIT instruction in the second instruction group is 7, meaning that the second instruction group needs to be executed after extending by 7 clock cycles based on the first instruction of the first instruction group.

[0060] S650. Perform parallel computation processing on the current input data according to the allocation result of the current execution instruction group.

[0061] The above technical solution addresses the instruction slot idleness problem caused by iterative dependencies in existing instruction-parallel computing methods. This means that each iteration must wait for the results of the preceding iteration before initiating subsequent computations, resulting in idle hardware units during the waiting period. An innovative instruction slot scheduling mechanism with interleaved slots is proposed to maximize the release of hardware computing power. Specifically, in each step of the sequential computation method's iteration, when a set of data enters a brief idle period while waiting for the results of the preceding iteration, other pending input data is immediately allocated to idle instruction slots. This waiting period is used to complete the initialization calculation of new data or intermediate step calculations. This strategy works in conjunction with the multiple parallel computing units of the vector processor. By dynamically tracking the busy status of each instruction slot unit, the originally scattered idle periods are transformed into effective computing time, increasing hardware utilization from around 60% in traditional parallel schemes to over 90%. While maintaining the high precision of the iterative method, it completely solves the industry pain point of inefficiency in parallel processing, compressing the overall computation cycle of the vector processor and improving its instruction-level parallelism, computational efficiency, and computing power utilization.

[0062] It should be noted that all information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for display, data used for analysis, etc.) involved in this disclosure are information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of the relevant data comply with the relevant laws, regulations and standards of the relevant regions, and do not violate public order and good morals.

[0063] It should be noted that any arrangement or combination of the technical features in the above embodiments also falls within the protection scope of this invention.

[0064] Example 3 Figure 13 This is a schematic diagram of an instruction-parallel computing device provided in Embodiment 3 of the present invention, as shown below. Figure 13 As shown, the device includes: an instruction arrangement and instruction slot information acquisition module 1310, an instruction uniform distribution module 1320, and a data parallel computing processing module 1330, wherein: The instruction arrangement and instruction slot information acquisition module 1310 is used to acquire the sequential instruction arrangement information and the total number of target instruction slots for the current execution instruction group to perform sequential calculations in a single target instruction slot. The instruction uniform distribution module 1320 is used to evenly distribute each instruction of the current execution instruction group to each of the target instruction slots according to the sequential instruction arrangement information of the current execution instruction group and the total number of target instruction slots; The data parallel computing processing module 1330 is used to perform parallel computing processing on the current input data according to the allocation result of the current execution instruction group.

[0065] This invention, through obtaining the sequential instruction arrangement information of the currently executing instruction group in a single target instruction slot and the total number of target instruction slots, evenly distributes each instruction of the currently executing instruction group to each target instruction slot based on the sequential instruction arrangement information and the total number of target instruction slots. Then, it performs parallel computation processing on the current input data based on the allocation result of the currently executing instruction group. This technical solution can utilize the processor's idle instruction slots for real-time compensation operations without increasing hardware costs or compromising computational accuracy and correctness. It solves the problem of low computational efficiency in existing processors when performing parallel instruction processing, compresses the overall computation cycle of the vector processor, and improves the instruction-level parallelism, computational efficiency, and computing power utilization of the vector processor.

[0066] Optionally, the instruction arrangement and instruction slot information acquisition module 1310 is further configured to: determine the dependency relationship between each individual instruction in the currently executed instruction group and the instruction execution cycle of each individual instruction; and determine the sequential arrangement information of each individual instruction in a single target instruction slot based on the dependency relationship between each individual instruction and the instruction execution cycle of each individual instruction.

[0067] Optionally, the instruction uniform distribution module 1320 is further configured to: determine the number of instructions included in the core loop of the current execution instruction group to be processed by each target instruction slot based on the total number of instructions in the current execution instruction group and the total number of target instruction slots; and uniformly distribute each instruction of the current execution instruction group to each target instruction slot according to the number of instructions included in the core loop.

[0068] Optionally, the instruction uniform distribution module 1320 is further configured to: divide the total number of instructions in the currently executed instruction group by the total number of target instruction slots; if the division result does not include a remainder, directly use the value of the division result as the number of instructions included in the core loop body; if the division result includes a remainder, use the value of the quotient in the division result rounded up as the number of instructions included in the core loop body.

[0069] Optionally, the instruction uniform allocation module 1320 is further configured to: determine the initial instruction position of each instruction in the current execution instruction group within the initial loop body; allocate core loop body placeholders to each instruction in the current execution instruction group according to the initial instruction position of each instruction in the current execution instruction group within the initial loop body; determine the local instruction groups uniformly allocated to each of the target instruction slots according to the allocated core loop body placeholders and the number of instructions included in the core loop body; adjust the initial instruction position of each instruction in the local instruction group to obtain the target instruction position of each instruction in the local instruction group, and update the core loop body placeholders at the target instruction positions, wherein the core loop body placeholders at the target instruction positions of each instruction in the local instruction group are different; and configure synchronous pipeline alignment instructions for each of the target instruction slots according to the dependency relationship between the local instruction groups allocated to each of the target instruction slots.

[0070] Optionally, the instruction uniform distribution module 1320 is further configured to: determine conflicting instructions with conflicting core loop body placeholders in the local instruction group; filter the conflicting instructions into a baseline conflicting instruction and a target adjustment conflicting instruction; keep the initial instruction position of the baseline conflicting instruction unchanged, and shift the instruction position of the target adjustment conflicting instruction downwards.

[0071] The above-described instruction-parallel computing device can execute the instruction-parallel computing method provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the execution method. Technical details not described in detail in this embodiment can be found in the instruction-parallel computing method provided in any embodiment of the present invention.

[0072] Since the instruction-parallel computing device described above is capable of executing the instruction-parallel computing method in the embodiments of the present invention, those skilled in the art can understand the specific implementation methods and various variations of the instruction-parallel computing device in this embodiment based on the instruction-parallel computing method described in the embodiments of the present invention. Therefore, how the instruction-parallel computing device implements the instruction-parallel computing method in the embodiments of the present invention will not be described in detail here. Any device used by those skilled in the art to implement the instruction-parallel computing method in the embodiments of the present invention falls within the scope of protection of this application.

[0073] Example 4 Figure 14 A schematic diagram of an electronic device 10 that can be used to implement embodiments of the present invention is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices (such as helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein.

[0074] like Figure 14 As shown, the electronic device 10 includes at least one processor 11 and a memory, such as a read-only memory (ROM) 12 and a random access memory (RAM) 13, communicatively connected to the at least one processor 11. The memory stores computer programs executable by the at least one processor. The processor 11 can perform various appropriate actions and processes based on the computer program stored in the ROM 12 or loaded into the RAM 13 from storage unit 18. The RAM 13 can also store various programs and data required for the operation of the electronic device 10. The processor 11, ROM 12, and RAM 13 are interconnected via a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0075] Multiple components in electronic device 10 are connected to I / O interface 15, including: input unit 16, such as keyboard, mouse, etc.; output unit 17, such as various types of displays, speakers, etc.; storage unit 18, such as disk, optical disk, etc.; and communication unit 19, such as network card, modem, wireless transceiver, etc. Communication unit 19 allows electronic device 10 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0076] Processor 11 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, digital signal processors (DSPs), and any suitable processor, controller, microcontroller, etc. Processor 11 performs the various methods and processes described above, such as instruction-parallel computing methods.

[0077] Optionally, the instruction parallel computing method may include: obtaining the sequential instruction arrangement information of the currently executed instruction group in a single target instruction slot and the total number of target instruction slots; uniformly distributing each instruction of the currently executed instruction group to each of the target instruction slots according to the sequential instruction arrangement information of the currently executed instruction group and the total number of target instruction slots; and performing parallel computing processing on the current input data according to the distribution result of the currently executed instruction group.

[0078] In some embodiments, the instruction-parallel computing method may be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or mounted on electronic device 10 via ROM 12 and / or communication unit 19. When the computer program is loaded into RAM 13 and executed by processor 11, one or more steps of the instruction-parallel computing method described above may be performed. Alternatively, in other embodiments, processor 11 may be configured to execute the instruction-parallel computing method by any other suitable means (e.g., by means of firmware).

[0079] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0080] Computer programs used to implement the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the processor, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be performed. The computer programs may be executed entirely on a machine, partially on a machine, or as a standalone software package, partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0081] In the context of this invention, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination thereof. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0082] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device for displaying information to the user (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor); and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0083] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or middleware components (e.g., application servers), or frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

[0084] A computing system can include clients and servers. Clients and servers are generally located far apart and typically interact through communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a hosting product within the cloud computing service system to address the shortcomings of traditional physical hosts and VPS services, such as high management difficulty and weak business scalability.

[0085] This invention also discloses a computer program product, which includes a computer program that, when executed by a processor, implements the instruction-parallel computing method provided in any embodiment of this invention. This program product shares the same inventive concept as the instruction-parallel computing methods disclosed in the embodiments of this invention, and therefore will not be described further here.

[0086] It should be understood that the various forms of processes shown above can be used to reorder, add, or delete steps. For example, the steps described in the embodiments of the present invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in the embodiments of the present invention can be achieved, and this is not limited herein.

[0087] The specific embodiments described above do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A method for parallel instruction computing, characterized in that, include: Obtain the sequential instruction arrangement information and the total number of target instruction slots for the current execution instruction group to be calculated sequentially in a single target instruction slot; Based on the sequential instruction arrangement information of the current instruction group and the total number of target instruction slots, each instruction of the current instruction group is evenly distributed to each of the target instruction slots; The current input data is processed in parallel based on the allocation result of the current instruction group.

2. The method according to claim 1, characterized in that, The step of obtaining the sequential instruction arrangement information of the currently executed instruction group for sequential computation in a single target instruction slot includes: Determine the dependencies between individual instructions in the currently executing instruction group and the instruction execution cycle of each individual instruction; Based on the dependencies between the individual instructions and the instruction execution cycle of each individual instruction, the sequential arrangement information of each individual instruction in a single target instruction slot is determined.

3. The method according to claim 1, characterized in that, The step of evenly distributing each instruction of the current instruction group to each of the target instruction slots according to the sequential instruction arrangement information of the current instruction group and the total number of target instruction slots includes: Based on the total number of instructions in the current instruction group and the total number of target instruction slots, determine the number of instructions included in the core loop of the current instruction group that each target instruction slot will process; The instructions of the currently executing instruction group are evenly distributed to the target instruction slots according to the number of instructions included in the core loop.

4. The method according to claim 3, characterized in that, The step of determining the number of instructions in the core loop of the current instruction group to be processed by each target instruction slot based on the total number of instructions in the current instruction group and the total number of target instruction slots includes: Divide the total number of instructions in the currently executing instruction group by the total number of target instruction slots; If it is determined that the division result does not include the remainder, the value of the division result is directly used as the number of instructions included in the core loop body; If it is determined that the division result includes a remainder, the quotient in the division result is rounded up to the nearest integer and used as the number of instructions included in the core loop body.

5. The method according to claim 4, characterized in that, The step of evenly distributing the instructions of the currently executing instruction group to the target instruction slots according to the number of instructions included in the core loop includes: Determine the initial instruction position of each instruction in the currently executed instruction group within the initial loop body; Based on the initial instruction position of each instruction in the current instruction group within the initial loop body, assign a core loop body placeholder to each instruction in the current instruction group. Based on the core loop body placeholder identifier of each instruction in the currently executed instruction group and the number of instructions included in the core loop body, a local instruction group evenly distributed among each target instruction slot is determined. If a conflict is found between the core loop body placeholders of each instruction in the local instruction group, the initial instruction positions of each instruction in the local instruction group are adjusted to obtain the target instruction positions of each instruction in the local instruction group, and the core loop body placeholders at the target instruction positions are updated; wherein, the core loop body placeholders at the target instruction positions of each instruction in the local instruction group are different. Based on the dependencies between the local instruction groups allocated to each target instruction slot, a synchronous pipeline alignment instruction is configured for each target instruction slot.

6. The method according to claim 5, characterized in that, Adjusting the initial instruction position of each instruction in the local instruction group includes: Identify conflicting instructions in the local instruction group that conflict with the core loop body placeholder identifier; The conflict instructions are filtered to select baseline conflict instructions and target adjustment conflict instructions; Keeping the initial command position of the reference conflict command unchanged, the command position of the target adjustment conflict command is shifted downwards.

7. An instruction-parallel computing device, characterized in that, include: The instruction arrangement and instruction slot information acquisition module is used to acquire the sequential instruction arrangement information and the total number of target instruction slots for the current execution instruction group to perform sequential calculations in a single target instruction slot. The instruction uniform distribution module is used to evenly distribute each instruction of the current execution instruction group to each of the target instruction slots according to the sequential instruction arrangement information of the current execution instruction group and the total number of target instruction slots; The data parallel computing processing module is used to perform parallel computing processing on the current input data according to the allocation result of the current execution instruction group.

8. An electronic device, characterized in that, The electronic device includes: At least one processor; and a memory communicatively connected to said at least one processor; wherein, The memory stores a computer program that is executed by the at least one processor, such that the at least one processor is able to perform the instruction-parallel computing method according to any one of claims 1-6.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that are used to cause a processor to execute the instruction-parallel computing method according to any one of claims 1-6.

10. A computer program product, characterized in that, It includes a computer program / instruction, wherein the computer program / instruction, when executed by a processor, implements the instruction-parallel computing method according to any one of claims 1-6.

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