Data processing methods, devices, communication methods, media, products, and chip systems

Abstract

This disclosure provides a data processing method, apparatus, communication method, medium, product, and chip system, including: in response to a matrix processing request, performing multiple loading processes on a first matrix and a second matrix; the matrix processing request is used to request multiplication operations to be performed on the first matrix and the second matrix; the first matrix includes multiple first sub-matrices; the second matrix includes multiple second sub-matrices; each loading process is used to load a row of unloaded first sub-matrices from the first matrix and a column of unloaded second sub-matrices from the second matrix; after loading a row of first sub-matrices and a column of second sub-matrices, performing multiplication operations on the currently loaded row of first sub-matrices and column of second sub-matrices to obtain the sub-operation result corresponding to the current loading process; based on the sub-operation result corresponding to each loading process, obtaining the multiplication operation result for the first matrix and the second matrix, thereby reducing memory usage during data processing.

Description

Technical Field

[0001] This disclosure relates to the field of data processing technology, and in particular to a data processing method, apparatus, communication method, medium, product, and chip system. Background Technology

[0002] When performing multiplication of matrices A and B on a terminal device, it is usually necessary to first load both matrices A and B completely into the terminal's memory before performing the multiplication operation. However, for terminal devices with limited memory space, such as mobile devices, if the dimensions of matrices A and B are large, the terminal device may be unable to load both matrices A and B completely into memory, thus preventing the multiplication operation from being performed. Summary of the Invention

[0003] To overcome the problems existing in related technologies, this disclosure provides a data processing method, apparatus, communication method, medium, product, and chip system.

[0004] According to a first aspect of the present disclosure, a data processing method is provided, comprising: in response to a matrix processing request, performing multiple loading processes on a first matrix and a second matrix; the matrix processing request is used to request a multiplication operation to be performed on the first matrix and the second matrix; the number of columns of the first matrix is ​​equal to the number of rows of the second matrix; the first matrix includes a plurality of first sub-matrices; the second matrix includes a plurality of second sub-matrices; each loading process is used to load a row of a first sub-matrice that has not been loaded and a column of a second sub-matrice that has not been loaded in the first matrix; for each row of a first sub-matrice and column of a second sub-matrice loaded, performing a multiplication operation on the currently loaded row of a first sub-matrice and column of a second sub-matrice to obtain a sub-operation result corresponding to the currently loaded loading process; and obtaining a multiplication operation result for the first matrix and the second matrix based on the sub-operation result corresponding to each loading process.

[0005] As can be seen, this disclosure enables terminal devices to avoid loading the entire first matrix and the second matrix into memory at once, thereby reducing memory usage during data processing and enabling memory-constrained mobile terminals to handle large-scale matrix multiplications. Furthermore, since each loading process only involves one row and one column of submatrices, it can reduce the computational complexity of the terminal device when performing matrix multiplication operations and improve the overall computational efficiency.

[0006] According to a first aspect of this disclosure, in some embodiments, the number of row indices of the first submatrix loaded in the first matrix and the number of column indices of the second submatrix loaded in the second matrix are the same in each load process.

[0007] As can be seen, by limiting the row index of the first submatrix loaded in each loading process to be the same as the column index of the second submatrix, this disclosure can ensure that each row of the first submatrix and each column of the second submatrix loaded are in corresponding positions in the block structure. This ensures that the sub-operation result obtained from each multiplication operation can correctly correspond to the specific sub-block position of the result matrix, avoiding erroneous results caused by misaligned accumulation. Furthermore, due to the index correspondence, the terminal device can predetermine the number of loading operations to be performed, thereby simplifying the control logic of the loading process and further reducing the overall computational complexity.

[0008] According to a first aspect of this disclosure, in some embodiments, in response to a matrix processing request, performing multiple loading processes on a first matrix and a second matrix includes: in response to a matrix processing request, dividing the first matrix into a plurality of first sub-matrices, and dividing the second matrix into a plurality of second sub-matrices; the number of first sub-matrices in each column is the same as the number of second sub-matrices in each row; and performing multiple loading processes on the first matrix and the second matrix based on the plurality of first sub-matrices and the plurality of second sub-matrices.

[0009] As can be seen, this disclosure divides the first matrix into multiple first sub-matrices and the second matrix into multiple second sub-matrices in response to a matrix processing request, ensuring that the number of first sub-matrices in each column is the same as the number of second sub-matrices in each row. This allows the terminal device to flexibly choose the granularity of the division based on the available memory capacity. Thus, while ensuring that multiple loading processes can be performed in a row-to-column correspondence after the blocks are divided, it adapts to terminal devices with different hardware configurations. Furthermore, this flexible division design allows this method to ensure basic usability on mobile devices with small memory spaces, and also to reduce the number of loading operations on devices with large memory spaces, thereby improving the overall computing speed.

[0010] According to a first aspect of this disclosure, in some embodiments, the multiple loading process includes N loading processes; N is greater than 1; for each loading of a row of first submatrix and a column of second submatrix, a multiplication operation is performed on the row of first submatrix and the column of second submatrix loaded in the current loading process to obtain the sub-operation result corresponding to the current loading process, including: multiplying the row of first submatrix and the column of second submatrix loaded in the i-th loading process in parallel according to the corresponding positions of the row and column to obtain the sub-operation result corresponding to the i-th loading process; 1≤i≤N.

[0011] As can be seen, this disclosure enables the terminal device to calculate the product of multiple pairs of submatrices at the same time by performing parallel multiplication of a row of the first submatrix and a column of the second submatrix loaded in the i-th loading process according to the corresponding row and column positions, thereby significantly shortening the computation time of a single loading process; and since each loading process only involves a row of the first submatrix and a column of the second submatrix, the memory usage remains at a low level, and there is no additional memory pressure due to the increase in parallelism, thus achieving high computational efficiency with low memory overhead.

[0012] According to a first aspect of this disclosure, in some embodiments, the first submatrix in a row and the second submatrix in a column loaded in the i-th loading process are multiplied in parallel according to the corresponding positions of the row and column to obtain the sub-operation result corresponding to the i-th loading process, including: multiplying the first submatrix in the k-th column loaded in the i-th loading process with the second submatrix in the k-th row to obtain the k-th intermediate result corresponding to the i-th loading process; 1≤k≤M; M is the number of first submatrixes loaded in the i-th loading process; and summing the intermediate results corresponding to the i-th loading process to obtain the sub-operation result corresponding to the i-th loading process.

[0013] As can be seen, this disclosure obtains multiple intermediate results by first multiplying the first submatrix in column k and the second submatrix in row k loaded in the i-th loading process, and then summing the intermediate results to obtain the sub-operation result. This makes the multiplication of each pair of submatrices independent of each other and can be executed in parallel. The computation time of a single loading process is only limited by the time required for the multiplication and summation of a pair of submatrices, rather than being proportional to the number of submatrices M. This method of first multiplying in parallel and then summing can significantly improve computational efficiency, and the memory usage of the terminal device will not increase additionally due to the increase of M. It is especially suitable for devices with limited memory resources, such as mobile terminals.

[0014] According to a first aspect of this disclosure, in some embodiments, the multiplication result for the first matrix and the second matrix is ​​obtained based on the sub-operation result corresponding to each loading process, including: updating the position of the sub-block in the result matrix corresponding to the i-th loading process based on the sub-operation result corresponding to the i-th loading process; and determining the updated result matrix obtained based on the sub-operation results of N loading processes as the multiplication result for the first matrix and the second matrix.

[0015] As can be seen, this disclosure updates the position of the sub-block in the result matrix corresponding to the i-th loading process based on the sub-operation result of the i-th loading process, and determines the result matrix after N updates as the final multiplication result. This allows the terminal device to update the result matrix immediately after obtaining each sub-operation result, without waiting for all loading processes to be completed before writing it uniformly, thereby reducing the overhead of data copying and temporary storage. Furthermore, since the different sub-block positions in the result matrix corresponding to each update operation do not interfere with each other, no additional synchronization mechanism is required, further improving the overall computational efficiency.

[0016] According to a first aspect of this disclosure, in some embodiments, the data processing method provided by this disclosure further includes: initializing a result matrix and updating the initialized result matrix based on the sub-operation results of N loading processes; the number of rows in the result matrix is ​​the same as the number of rows in the first matrix, and the number of columns in the result matrix is ​​the same as the number of columns in the second matrix.

[0017] As can be seen, by initializing the result matrix, this disclosure enables the sub-operation result to be directly written when the sub-operation result is obtained and the corresponding sub-block position is updated in each subsequent loading process, thereby avoiding data residue errors caused by uninitialization and ensuring the correctness of the multiplication operation result.

[0018] According to a second aspect of this disclosure, a communication method is provided, comprising: in response to a signal transmission request, acquiring a first matrix; the first matrix being a data matrix to be transmitted; generating a matrix processing request to perform data processing on the first matrix and a second matrix based on the data processing method described in the first aspect and any one thereof, to obtain a processing result; the second matrix being a precoding matrix or a channel coding matrix; generating a communication signal based on the processing result; and transmitting the communication signal to a receiving device.

[0019] According to a third aspect of the present disclosure, a communication method is provided, comprising: in response to receiving a communication signal, extracting a first matrix from the communication signal; the first matrix being a data matrix corresponding to the communication signal; generating a matrix processing request to perform data processing on the first matrix and a second matrix based on the data processing method described in the first aspect and any one thereof, and obtaining a processing result; the matrix processing request being used to request the execution of a multiplication operation on the first matrix and the second matrix; the second matrix being a channel estimation matrix or a reference signal matrix.

[0020] According to a fourth aspect of the present disclosure, an apparatus is provided, comprising: a processor; and a memory for storing processor-executable instructions; wherein the processor is configured to: execute the executable instructions to implement the data processing method described in the first aspect and any one thereof, or execute the executable instructions to implement the communication method described in the second or third aspect.

[0021] According to a fifth aspect of the present disclosure, a non-transitory computer-readable storage medium is provided, wherein when instructions in the storage medium are executed by a processor, the processor is enabled to perform the data processing method described in the first aspect and any one thereof, or to perform the communication method described in the second or third aspect.

[0022] According to a sixth aspect of the present disclosure, a computer program product is provided, including a computer program that, when executed by a processor, implements the data processing method described in the first aspect and any one thereof, or implements the communication method described in the second or third aspect.

[0023] According to a seventh aspect of the present disclosure, a chip system is provided. The chip system includes a processing unit and an interface circuit. The processing unit obtains program instructions through the interface circuit. The program instructions are executed by the processing unit. The processing unit is used to execute the data processing method described in the first aspect and any one thereof, or the processing unit is used to execute the communication method described in the second or third aspect.

[0024] It should be understood that the beneficial effects achieved by the communication method described in the second aspect, the communication method described in the third aspect, the apparatus described in the fourth aspect, the non-transitory computer-readable storage medium described in the fifth aspect, the computer program product described in the sixth aspect, and the chip system described in the seventh aspect can be referred to the beneficial effects of the first aspect and any of its embodiments, which will not be repeated here.

[0025] Furthermore, the above general description and the following detailed description are exemplary and explanatory only, and do not limit this disclosure. Attached Figure Description

[0026] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0027] Figure 1 This is a schematic flowchart illustrating a data processing method according to some embodiments of the present disclosure;

[0028] Figure 2 This is a schematic diagram illustrating a method for dividing a first matrix according to some embodiments of the present disclosure; Figure 3 This is a schematic diagram illustrating a method for dividing a second matrix according to some embodiments of the present disclosure; Figure 4 This is a schematic diagram illustrating another method for dividing a first matrix according to some embodiments of the present disclosure; Figure 5This is a schematic diagram illustrating another method for dividing a second matrix according to some embodiments of the present disclosure; Figure 6 This is a schematic flowchart illustrating a process for determining the result of a sub-operation according to some embodiments of the present disclosure; Figure 7 This is a schematic diagram illustrating the structure of a data processing apparatus 700 according to some embodiments of the present disclosure; Figure 8 This is a flowchart illustrating a communication method according to some embodiments of the present disclosure; Figure 9 This is a flowchart illustrating another communication method according to some embodiments of the present disclosure; Figure 10 This is a block diagram illustrating an apparatus 1000 for data processing according to some embodiments of the present disclosure; Figure 11 This is a block diagram illustrating a chip system according to some embodiments of the present disclosure. Detailed Implementation

[0029] Some embodiments of this disclosure will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. Various changes, modifications, and equivalents of the methods and apparatus described herein will become apparent upon understanding this disclosure. For example, the order of operations described herein is merely illustrative and is not limited to those orders set forth herein, but can be changed as will become apparent upon understanding this disclosure, except for operations that must be performed in a particular order. Furthermore, for clarity and brevity, descriptions of features known in the art may be omitted.

[0030] The embodiments described in the following examples of this disclosure are not representative of all embodiments consistent with this disclosure. Rather, they are merely examples of methods and apparatus consistent with some aspects of this disclosure as detailed in the appended claims.

[0031] In applications such as neural network inference, image processing, or wireless communication signal transmission, terminal devices often need to perform matrix operations, for example, multiplying matrix A and matrix B.

[0032] In related technologies, when performing matrix multiplication, terminal devices need to first load matrices A and B completely into the terminal memory before performing the multiplication operation. However, this method consumes a large amount of terminal memory. Specifically, the memory usage may increase quadratically with the dimensions of matrices A and B, and the computational complexity may increase cubically with the dimensions of matrices A and B. For example, a 1024×1024 int32 matrix requires 4MB of memory, and multiplying two such matrices requires more than 1 billion multiplication operations. Furthermore, for terminals with limited memory space, such as mobile devices, if the dimensions of matrices A and B are large, the terminal device may be unable to load matrices A and B completely into the terminal memory, thus preventing the multiplication operation from being performed.

[0033] It is evident that loading matrices A and B into the terminal memory first, and then performing multiplication operations on matrices A and B, has limited applicability. It can usually only support operations on matrices with small dimensions and is difficult to handle operations on large or very large matrices.

[0034] Figure 1 This is a flowchart illustrating a data processing method according to some embodiments of the present disclosure. The data processing methods illustrated in some embodiments of the present disclosure can be applied to terminal devices with data processing capabilities. Examples include portable computers (such as mobile phones), tablets, laptops, personal computers (PCs), wearable electronic devices (such as smartwatches), augmented reality (AR) / virtual reality (VR) devices, smart cockpits, in-vehicle computers (vehicle systems), and smart vehicles (or smart cars), etc. The embodiments of the present disclosure do not impose any special limitations on the specific form of such terminal devices. The data processing methods illustrated in some embodiments of the present disclosure will be described in detail below, using the terminal device as the execution subject.

[0035] like Figure 1 As shown, the data processing method provided in this embodiment may include the following steps S101-S102: S101: In response to a matrix processing request, perform multiple loading processes on the first matrix and the second matrix; the matrix processing request is used to request multiplication operations on the first matrix and the second matrix. The number of columns in the first matrix is ​​equal to the number of rows in the second matrix; the first matrix includes multiple first submatrices; the second matrix includes multiple second submatrices; each loading process is used to load one unloaded row of the first submatrices and one unloaded column of the second submatrices in the second matrix; after loading one row of the first submatrices and one column of the second submatrices, perform a multiplication operation on the currently loaded row of the first submatrices and one column of the second submatrices to obtain the sub-operation result corresponding to the current loading process.

[0036] Specifically, the matrix processing request can be received by the terminal device from an external source. For example, a server or other terminal device may send a matrix multiplication task request to the terminal device, which carries the storage addresses of the first and second matrices or directly includes the matrix data. Alternatively, the matrix processing request can be automatically generated by the terminal device while running a local application. For instance, when the terminal device receives a communication signal from a base station, it needs to extract a data matrix from the communication signal as the first matrix, and simultaneously obtain a reference signal matrix or channel estimation matrix pre-stored locally or stored in an external device as the second matrix. It then performs a multiplication operation on the first and second matrices to complete channel estimation or signal detection. In this case, the terminal device's application can automatically detect the multiplication operation requirement and generate the matrix processing request. Since the matrix processing request is used to request the multiplication operation on the first and second matrices, the terminal device, in response to the matrix processing request, can perform multiple (at least two) loading processes on the first and second matrices to complete the multiplication operation.

[0037] For example, the first matrix can be of dimension n. A matrix of size m, that is, the first matrix can have n rows and m columns, can be represented as: ; The second matrix can be of dimension m. A matrix of size n, that is, the second matrix, can have m rows and n columns, and can be represented as: ; The number of columns in the first matrix is ​​equal to the number of rows in the second matrix. Elements a11-anm in the first matrix can all be called elements of the first matrix; elements b11-bmn in the second matrix can all be called elements of the second matrix.

[0038] In some embodiments, the terminal device may, in response to a matrix processing request, divide a first matrix into multiple first sub-matrices, and divide a second matrix into multiple second sub-matrices. The number of first sub-matrices in each column is the same as the number of second sub-matrices in each row. Multiple loading processes are performed on the first and second matrices based on the multiple first and second sub-matrices.

[0039] In other words, the terminal device can respond to a matrix processing request and divide the first matrix into j Divide the second matrix into k first submatrices. There are j second submatrices. The dimensions of each first submatrix are the same, and the dimensions of each second submatrix are also the same.

[0040] For example, the terminal device can use the first matrix in the aforementioned example as... Figure 2 The division is as shown, where, Figure 2 The four elements at each dashed box can be merged into a new matrix, which is the first submatrix. In this case, the terminal device can use the second matrix from the previous example... Figure 3 The division is as shown, where, Figure 3 The four elements at each dashed box can be merged into a new matrix, which is a second submatrix.

[0041] For example, the terminal device can use the first matrix from the aforementioned example... Figure 4 The division is as shown, where, Figure 4 The two elements at each dashed box can be merged into a new matrix, which is the first submatrix. In this case, the terminal device can use the second matrix from the previous example... Figure 5 The division is as shown, where, Figure 5 The two elements at each dashed box can be merged into a new matrix, which is a second submatrix.

[0042] It should be noted that this disclosure does not impose any restrictions on the specific partitioning method of the first and second matrices. The terminal device can flexibly choose the partitioning granularity based on the available memory capacity, the processor's parallel computing capability, and preset size requirements for the first and second sub-matrices. For example, when the terminal device has limited memory, it can choose to partition the matrix into smaller sub-matrices, further reducing the memory required for each loading process; when memory is relatively abundant or it is desirable to reduce the number of loading operations, a larger sub-matrix size can be selected. Regardless of the partitioning method, as long as the number of columns of the first sub-matrix is ​​the same as the number of rows of the second sub-matrix, the terminal device can complete the multiplication operation row by row and column by column according to the aforementioned loading process. This flexible partitioning design allows this method to adapt to terminal devices with different hardware configurations. It can ensure basic usability on mobile devices with small memory spaces through fine-grained partitioning, and it can reduce the number of loading operations and improve the overall computing speed on terminal devices with large memory spaces through coarse-grained partitioning.

[0043] In some embodiments, the number of row indices of the first submatrix loaded in the first matrix is ​​the same as the number of column indices of the second submatrix loaded in the second matrix during each load process.

[0044] Here, the row index number refers to the position number of the first submatrix within the first matrix, specifically in which row of the submatrix block it is located. For example, Figure 2 The row index of the first submatrix composed of a11, a12, a21, and a22 is 1; the row index of the first submatrix composed of a33, a34, a43, and a44 is 2; and the row index of the first submatrix composed of a(a-1)(m-1), an(m-1), a(n-1)m, and anm is n / 2, etc.

[0045] The column index number refers to the position number of the second submatrix within the second matrix, specifically in which column of the submatrix block it resides. For example, Figure 3 The column index of the second submatrix composed of b11, b12, b21, and b22 is 1; the column index of the second submatrix composed of b33, b34, b43, and b44 is 2; and the column index of the second submatrix composed of b(m-1)(n-1), bm(n-1), b(m-1)n, and bmn is n / 2, etc.

[0046] By ensuring that the row index of the first submatrix and the column index of the second submatrix are the same in each loading process, the terminal device can ensure that each loaded row of the first submatrix and one column of the second submatrix are in corresponding positions in the block structure. For example, when the row index is 1, the first row of the first submatrix block is loaded (i.e., Figure 2 The first submatrix with all rows indexed by 1) and the first column submatrix block of the second matrix (i.e. Figure 3 (The second submatrix with all column indices of 1); when the row index is 2, the second row submatrix block of the first matrix and the second column submatrix block of the second matrix are loaded, and so on.

[0047] This correspondence between row and column indices allows the terminal device to retrieve submatrix blocks row-by-row and column-by-column in a fixed order during multiple loading processes. Each loading process only needs to focus on which row's first submatrix and column's second submatrix correspond to the current row and column indices, without needing to search or match submatrix positions throughout the entire matrix. Because the indices are identical, the number of first submatrixes in a row and the number of second submatrixes in a column are naturally equal each time. This ensures that the two loaded submatrix blocks can perform a complete multiplication operation without any mismatch in quantity that could prevent execution. Furthermore, because the indices are identical, the terminal device can pre-determine the number of loading operations required based on the total number of row blocks in the first matrix or the total number of column blocks in the second matrix, thus allocating memory and computational resources efficiently. For example, if the first matrix is ​​divided into N rows of submatrix blocks, only N loading processes are needed to traverse all submatrix blocks that need to participate in the operation, avoiding unnecessary duplicate loading or missed loading. This index design not only simplifies the control logic of the loading process, but also makes the number of loading processes linearly related to the number of rows (or columns) of the submatrix block, further reducing the overall computational complexity.

[0048] In some embodiments, the multiple loading process includes N loading processes; N is greater than 1; each time a row of the first submatrix and a column of the second submatrix are loaded, a multiplication operation is performed on the row of the first submatrix and the column of the second submatrix loaded in the current loading process to obtain the sub-operation result corresponding to the current loading process, which may include: multiplying the row of the first submatrix and the column of the second submatrix loaded in the i-th loading process in parallel according to the corresponding positions of the row and column to obtain the sub-operation result corresponding to the i-th loading process; 1≤i≤N.

[0049] Taking i=1 as an example, the first submatrix of the row loaded in the i-th loading process is as follows: ; Among them, A11 can be as follows: Figure 4 The first submatrix shown consists of a11 and a12, where A12 can be as follows: Figure 4 The first submatrix shown, consisting of a13 and a14, can be represented as follows: Figure 4 The first submatrix shown is composed of a1(m-1) and a1m.

[0050] The second sub-matrix loaded in the i-th loading process is shown below: ; Among them, B11 can be as follows: Figure 5 The second submatrix shown consists of b11 and b21, where B21 can be as follows: Figure 5 The second submatrix shown, consisting of b31 and b41, can be BM1 as follows: Figure 5 The second submatrix shown is composed of b(m-1)1 and bm1.

[0051] Multiplying the first submatrix (one row) and the second submatrix (one column) loaded in the i-th loading process in parallel according to their corresponding row and column positions allows the terminal device to quickly calculate the sub-operation result corresponding to this loading process, thereby improving computational efficiency. Furthermore, since each loading process only involves one row of the first submatrix and one column of the second submatrix, the memory usage remains constant at the sum of the storage space for M first submatrixes and M second submatrixes, saving memory space on the terminal device.

[0052] In some embodiments, such as Figure 6 As shown, the above-mentioned parallel multiplication of the first submatrix in a row and the second submatrix in a column loaded in the i-th loading process according to the corresponding row and column positions, to obtain the sub-operation result corresponding to the i-th loading process, may include the following steps S601-S602: S601: Multiply the first submatrix in the kth column loaded in the i-th loading process with the second submatrix in the kth row to obtain the k-th intermediate result corresponding to the i-th loading process; 1≤k≤M; M is the number of first submatrices loaded in the i-th loading process.

[0053] Still using i=1 and the first submatrix as described above The second submatrix is ​​as described above. For example, multiplying the first submatrix in the kth column and the second submatrix in the kth row during the i-th loading process is equivalent to parallel computation of A11×B11, A12×B21, ..., A1M×BM1, resulting in the product of M pairs of submatrices.

[0054] S602: Accumulate the intermediate results corresponding to the i-th loading process to obtain the sub-operation result corresponding to the i-th loading process.

[0055] Taking the intermediate results A11×B11, A12×B21, ..., A1M×BM1 calculated by the terminal device when i=1 as an example, the terminal device can determine the sum of A11×B11, A12×B21, ..., A1M×BM1 as the sub-operation result corresponding to the first loading process.

[0056] As can be seen, by first performing parallel multiplication of the first submatrix in each column and the corresponding second submatrix in the i-th loading process to obtain multiple intermediate results, and then accumulating these multiple intermediate results into a single sub-operation result, the terminal device can complete the core computational task of a single loading process with a small memory footprint. Since the multiplication of each pair of submatrices is independent, multi-core processors or single instruction multiple data stream instructions can be fully utilized to achieve true parallel computing. This ensures that the computation time of a single loading process is limited only to the time required for the multiplication and accumulation operations of a pair of submatrices, rather than being proportional to the number of submatrix pairs M. When M is large, such as M equals 16 or 32, this method of parallel multiplication followed by accumulation can significantly improve computational efficiency, and the memory footprint is always only the storage space of one row of the first submatrix and one column of the second submatrix. It will not increase memory pressure due to the increase of M, thus improving the operation speed of large-scale matrix multiplication with low memory overhead. This is especially suitable for scenarios requiring real-time processing of large-scale matrix data in memory-constrained devices such as mobile terminals.

[0057] S102: Based on the sub-operation results corresponding to each loading process, obtain the multiplication results for the first matrix and the second matrix.

[0058] After completing multiple loading processes, the terminal device can obtain the sub-operation results corresponding to each loading process. Since each loading process corresponds to a row of the first submatrix in the first matrix and a column of the second submatrix in the second matrix, these sub-operation results have a specific positional correspondence. The terminal device can integrate all sub-operation results according to the execution order of each loading process or the positional relationship of the submatrix blocks to obtain the complete multiplication result of the first matrix and the second matrix.

[0059] In some embodiments, the multiplication result for the first matrix and the second matrix is ​​obtained based on the sub-operation result corresponding to each loading process, including: updating the position of the sub-block in the result matrix corresponding to the i-th loading process based on the sub-operation result corresponding to the i-th loading process; and determining the updated result matrix obtained based on the sub-operation results of N loading processes as the multiplication result for the first matrix and the second matrix.

[0060] Specifically, different loading processes correspond to different sub-block positions in the result matrix. For example, the first loading process corresponds to the first sub-block in the first row and first column of the result matrix, the second loading process corresponds to the second sub-block in the second row and second column of the result matrix, and so on. Each time the terminal device completes a loading process, it updates the sub-block position in the result matrix corresponding to that loading process with the corresponding sub-operation result. The update operations do not interfere with each other and do not require additional synchronization.

[0061] In some examples, the terminal device can update the corresponding sub-block in the result matrix after receiving the result of each sub-operation, without waiting for all loading processes to complete before writing it all at once. After all N loading processes are completed, each sub-block in the result matrix is ​​correctly filled, and the result matrix is ​​then the result of the multiplication of the first and second matrices. The terminal device can directly use this result matrix for subsequent application logic, such as as an intermediate feature map for neural network inference, a transformation result in image processing, or demodulation data in wireless communication signal detection. This successive cumulative update method not only reduces the terminal device's memory footprint but also highly integrates the result matrix construction process with the computation process, reducing the overhead of data copying and temporary storage, thereby further improving overall computational efficiency.

[0062] In other examples, the terminal device can update the result matrix uniformly after obtaining all sub-operation results. Specifically, the terminal device can pre-allocate a temporary buffer to store the results of N sub-operations. After each load processing is completed, the obtained sub-operation results are stored in this buffer instead of being immediately written to the result matrix. When all N load processing operations are completed, the terminal device can write the sub-blocks corresponding to each sub-operation result, either individually or in parallel, to the corresponding areas of the result matrix. Although this uniform update method requires additional temporary storage space to store the N sub-operation results, when the result matrix itself is located in external memory or shared memory, a one-time batch write can reduce the bus overhead caused by multiple small data block writes. In addition, the uniform update method can also allow the terminal device to verify or post-process all sub-operation results before writing, for example, checking for overlaps or omissions between sub-blocks, thereby improving the reliability of the calculation.

[0063] In some embodiments, the data processing method provided in this disclosure further includes: initializing the result matrix and updating the initialized result matrix based on the sub-operation results of N loading processes; the number of rows in the result matrix is ​​the same as the number of rows in the first matrix, and the number of columns in the result matrix is ​​the same as the number of columns in the second matrix.

[0064] Specifically, initializing the result matrix can include allocating storage space for the result matrix in memory and setting all elements in the result matrix to zero. By initializing the result matrix, each sub-block position of the result matrix can have a clear starting value (zero). This allows the sub-operation result to be directly written (for the first update) or accumulated with zero during subsequent loading and processing to obtain the sub-operation result and update the corresponding sub-block position, thereby avoiding data residue errors caused by uninitialization.

[0065] Figure 7 This is a schematic diagram illustrating the structure of a data processing apparatus 700 according to some embodiments of the present disclosure. Figure 7 As shown, the data processing apparatus 700 provided in this embodiment may include: Loading module 701 is used to perform multiple loading processes on a first matrix and a second matrix in response to a matrix processing request; the matrix processing request is used to request the multiplication operation to be performed on the first matrix and the second matrix; the number of columns of the first matrix is ​​equal to the number of rows of the second matrix; the first matrix includes multiple first sub-matrices; the second matrix includes multiple second sub-matrices; each loading process is used to load a row of the first sub-matrices that has not been loaded and a column of the second sub-matrices that has not been loaded in the second matrix. The first operation module 702 is used to perform multiplication operations on the first submatrix and the second submatrix loaded in each row and column, and obtain the sub-operation result corresponding to the current loading process. The second operation module 703 obtains the multiplication results of the first matrix and the second matrix based on the sub-operation results of each loading and processing.

[0066] In some embodiments, the loading module 701 loads the first submatrix each time, and the number of row indices in the first matrix is ​​the same as the number of column indices in the second matrix for the second submatrix.

[0067] In some embodiments, the loading module 701 is specifically configured to: in response to a matrix processing request, divide a first matrix into a plurality of first sub-matrices, and divide a second matrix into a plurality of second sub-matrices; the number of first sub-matrices in each column is the same as the number of second sub-matrices in each row; and perform multiple loading processes on the first matrix and the second matrix based on the plurality of first sub-matrices and the plurality of second sub-matrices.

[0068] In some embodiments, the multiple loading process includes N loading processes; N is greater than 1; the first operation module 702 is specifically used to: multiply the first submatrix in a row and the second submatrix in a column loaded in the i-th loading process in parallel according to the corresponding positions of the row and column, to obtain the sub-operation result corresponding to the i-th loading process; 1≤i≤N.

[0069] In some embodiments, the first operation module 702 is specifically used to: multiply the first submatrix in the kth column loaded in the i-th loading process with the second submatrix in the kth row to obtain the k-th intermediate result corresponding to the i-th loading process; 1≤k≤M; M is the number of first submatrixes loaded in the i-th loading process; and sum up the intermediate results corresponding to the i-th loading process to obtain the sub-operation result corresponding to the i-th loading process.

[0070] In some embodiments, the second operation module 703 is specifically used to: update the position of the sub-block in the result matrix corresponding to the i-th loading process based on the sub-operation result corresponding to the i-th loading process; and determine the updated result matrix obtained based on the sub-operation results of N loading processes as the result of the multiplication operation for the first matrix and the second matrix.

[0071] In some embodiments, the second operation module 703 is further configured to: initialize the result matrix and update the initialized result matrix based on the sub-operation results of N loading processes; the number of rows in the result matrix is ​​the same as the number of rows in the first matrix, and the number of columns in the result matrix is ​​the same as the number of columns in the second matrix.

[0072] Regarding the apparatus in the above embodiments, the specific manner in which each module performs its operation has been described in detail in the embodiments related to the method, and will not be elaborated upon here.

[0073] Figure 8 This is a flowchart illustrating a communication method according to some embodiments of the present disclosure. Figure 8 As shown, the communication method provided in this embodiment may include the following steps: S801: In response to a signal transmission request, obtain the first matrix; the first matrix is ​​the data matrix to be transmitted.

[0074] Specifically, when a terminal device needs to send data to a receiving device, it can generate a signal transmission request. This signal transmission request can be used to trigger the terminal device to begin preparing the data to be transmitted. In response to the signal transmission request, the terminal device can obtain a first matrix, which is the data matrix to be transmitted. The data matrix can be a matrix composed of raw information bits that need to be encoded, modulated, or pre-coded before transmission. For example, in a wireless communication system, the terminal device can map the binary bit stream to be transmitted into complex symbols according to a specific modulation method (such as quadrature amplitude modulation), and arrange these symbols into a matrix by rows or columns to obtain the first matrix.

[0075] In some embodiments, the first matrix can be obtained by receiving it from the upper-layer protocol stack, reading it from a specified buffer in memory, or generating it in real time by the terminal device based on the sent content. This disclosure does not limit the method.

[0076] S802: Generate a matrix processing request to perform data processing on the first matrix and the second matrix based on the data processing method provided in the embodiments of this disclosure, and obtain a processing result; the second matrix is ​​a precoding matrix or a channel coding matrix.

[0077] Specifically, after acquiring the first matrix, the terminal device can generate a matrix processing request. This matrix processing request can be used to invoke the data processing method provided in the embodiments of this disclosure to perform data processing on the first and second matrices, thereby obtaining a processing result. A description of the data processing method can be found in the foregoing embodiments, and will not be repeated here.

[0078] The second matrix can be either a precoding matrix or a channel coding matrix. A precoding matrix is ​​used in multi-antenna systems for spatial domain preprocessing of transmitted signals. For example, in multiple-input multiple-output (MIMO) communication, the terminal device can select a precoding matrix from a codebook based on channel state information to map the data stream onto different transmit antennas, thereby improving signal transmission quality or suppressing inter-user interference. A channel coding matrix, on the other hand, is used for error control coding of data bits, such as the generator matrix of low-density parity-check codes or the coding matrix of polar codes. By multiplying the data matrix by the channel coding matrix, redundant information can be introduced into the original data, thereby enhancing the receiver's ability to correct transmission errors.

[0079] After the terminal device generates a matrix processing request, it can call the aforementioned data processing method to perform multiplication operations on the first and second matrices to obtain the processing result.

[0080] S803: Generates communication signals based on the processing results.

[0081] Specifically, the processing result can be a matrix obtained by multiplying the first matrix and the second matrix. For example, when the second matrix is ​​a precoding matrix, the processing result is a precoded data matrix, where each column corresponds to a transmitted symbol of an antenna port; when the second matrix is ​​a channel coding matrix, the processing result is a coded data matrix, which contains redundant information for error correction. The terminal device can map the elements in the processing result to time-frequency resources according to the order specified by the communication protocol, for example, mapping them to each subcarrier of an orthogonal frequency division multiplexing symbol, and then perform operations such as inverse fast Fourier transform, adding a cyclic prefix, digital-to-analog conversion, and radio frequency up-conversion to obtain a communication signal that can be transmitted in a wireless channel.

[0082] S804: Sends communication signals to the receiving device.

[0083] As can be seen, the communication method provided in this disclosure can obtain the data matrix to be sent as the first matrix in response to a signal transmission request, generate a matrix processing request to call the data processing method of this disclosure to perform multiplication operations on the first matrix and the precoding matrix or channel coding matrix, and then generate and send a communication signal based on the processing result. This allows the terminal device to complete the large-scale matrix multiplication operations involved in precoding or channel coding with low memory usage during data transmission. Because the data processing method of this disclosure adopts a strategy of block loading, parallel multiplication, and accumulation, even if the dimension of the first matrix is ​​large or the size of the second matrix is ​​large, the terminal device does not need to load the entire matrix into memory at once, thereby avoiding the situation where matrix multiplication cannot be performed due to insufficient memory. Furthermore, the terminal device can significantly improve computational efficiency through parallel multiplication and accumulation operations, thereby meeting the real-time requirements of communication transmission.

[0084] In some embodiments, generating a communication signal based on the processing result may include: weighting the processing result and generating a communication signal based on the weighted processing result.

[0085] Weighted processing refers to multiplying each element in the processing result by a weighting coefficient. This weighting coefficient can be a scalar value or a weighting matrix that matches the dimension of the processing result. For example, in a wireless communication system, a terminal device can multiply the precoded data matrix by a power allocation factor according to transmit power control requirements, ensuring that the transmit power on different antenna ports or different resource blocks meets preset power spectral density limits. As another example, in beamforming scenarios, a terminal device can multiply the encoded data matrix by a beamforming weight vector or matrix to focus signal energy onto a specific spatial direction, thereby improving the signal reception quality at the receiver.

[0086] Weighted processing can be performed after the processing result is generated but before the communication signal is generated. The terminal device can map the elements in the weighted processing result to time-frequency resources, and then perform subsequent operations such as inverse fast Fourier transform and adding cyclic prefixes to finally generate the communication signal.

[0087] By weighting the processing results before generating communication signals, terminal devices can flexibly adjust the power allocation and spatial pointing of transmitted signals, thereby meeting the requirements of communication systems such as transmit power constraints, interference suppression, or beamforming. Furthermore, the weighting operation can be performed in-place on the existing processing result matrix without requiring the allocation of large blocks of memory.

[0088] Figure 9 This is a flowchart illustrating another communication method according to some embodiments of the present disclosure. Figure 9As shown, the communication method provided in this embodiment may include the following steps: S901: In response to receiving a communication signal, extract a first matrix from the communication signal; the first matrix is ​​the data matrix corresponding to the communication signal.

[0089] Specifically, when a terminal device receives a communication signal from a transmitting device, it can analyze and process the signal. The communication signal is typically a radio frequency (RF) signal propagating in a wireless channel. After processing by the receiver's RF front-end, analog-to-digital conversion, synchronization, cyclic prefix removal, and fast Fourier transform, received symbols in the frequency domain are obtained. The terminal device can extract a first matrix from these received symbols; this first matrix is ​​the data matrix corresponding to the communication signal. For example, in a multiple-input multiple-output (MIMO) orthogonal frequency division multiplexing (OFDM) system, the receiver arranges the received symbols of each subcarrier on each antenna port into a matrix according to the antenna index and subcarrier index. The number of rows in this matrix can correspond to the number of subcarriers or time symbols, and the number of columns can correspond to the number of antenna ports, thus obtaining the first matrix. This first matrix carries the original data information transmitted by the transmitter, but it may be affected by channel fading and noise interference. By extracting the first matrix from the communication signal, the terminal device can obtain the input data needed for subsequent channel estimation, equalization, or signal detection, preparing for the recovery of the original information transmitted by the transmitter.

[0090] S902: Generate a matrix processing request to perform data processing on the first matrix and the second matrix based on the data processing method provided in the embodiments of this disclosure, and obtain a processing result; the matrix processing request is used to request the multiplication operation to be performed on the first matrix and the second matrix; the second matrix is ​​a channel estimation matrix or a reference signal matrix.

[0091] The channel estimation matrix can be a matrix describing the transmission characteristics of a wireless channel. For example, in a multiple-input multiple-output (MIMO) system, the receiver can estimate the channel frequency response between each transmit and receive antenna by analyzing the received reference signal (pilot). Arranging these channel responses into a matrix according to the antenna indices yields the channel estimation matrix. The reference signal matrix, on the other hand, refers to a matrix composed of known signals pre-agreed upon by the transmitter and receiver. For instance, in LTE or New Radio systems, the receiver locally stores the same reference signal sequence as the transmitter. Arranging these sequences into a matrix according to time-frequency resource locations forms the reference signal matrix.

[0092] After generating a matrix processing request, the terminal device can invoke the data processing method provided in this embodiment to perform multiplication operations on the first matrix (i.e., the data matrix extracted from the communication signal) and the second matrix (i.e., the channel estimation matrix or the reference signal matrix). For example, when the second matrix is ​​the channel estimation matrix, multiplying the first matrix by the channel estimation matrix yields equalized data, which is used for subsequent demodulation and decoding; when the second matrix is ​​the reference signal matrix, performing correlation operations between the first matrix and the reference signal matrix yields a channel estimate or is used for time and frequency synchronization.

[0093] Because the data processing method of this embodiment employs a strategy of block loading and parallel multiplication, the terminal device can process large-scale first and second matrices even with limited memory, without having to load both complete matrices into memory simultaneously. Furthermore, the terminal device achieves significantly improved computational efficiency through parallel multiplication and accumulation operations, thereby meeting the real-time and low-latency requirements of wireless communication reception processing.

[0094] Figure 10 This is a block diagram illustrating an apparatus 1000 for data processing according to some embodiments of the present disclosure. For example, apparatus 1000 may be a mobile phone, computer, digital broadcasting terminal, messaging device, game console, tablet device, medical device, fitness equipment, personal digital assistant, etc.

[0095] Reference Figure 10 The device 1000 may include one or more of the following components: a processing component 1002, a memory 1004, a power component 1006, a multimedia component 1008, an audio component 1100, an input / output (I / O) interface 1012, a sensor component 1014, and a communication component 1016.

[0096] Processing component 1002 typically controls the overall operation of device 1000, such as operations associated with display, telephone calls, data communication, camera operation, and recording operations. Processing component 1002 may include one or more processors 1020 to execute instructions to perform all or part of the steps of the methods described above. Furthermore, processing component 1002 may include one or more modules to facilitate interaction between processing component 1002 and other components. For example, processing component 1002 may include a multimedia module to facilitate interaction between multimedia component 1008 and processing component 1002.

[0097] Memory 1004 is configured to store various types of data to support the operation of device 1000. Examples of such data include instructions for any application or method operating on device 1000, contact data, phonebook data, messages, pictures, videos, etc. Memory 1004 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0098] The power supply component 1006 provides power to the various components of the device 1000. The power supply component 1006 may include a power management system, one or more power sources, and other components associated with generating, managing, and distributing power to the device 1000.

[0099] The multimedia component 1008 includes a screen that provides an output interface between the device 1000 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touchscreen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensors may sense not only the boundaries of the touch or swipe action but also the duration and pressure associated with the touch or swipe operation. In some embodiments, the multimedia component 1008 includes a front-facing camera and / or a rear-facing camera. When the device 1000 is in an operating mode, such as a shooting mode or a video mode, the front-facing camera and / or the rear-facing camera may receive external multimedia data. Each front-facing camera and rear-facing camera may be a fixed optical lens system or have focal length and optical zoom capabilities.

[0100] Audio component 1100 is configured to output and / or input audio signals. For example, audio component 1100 includes a microphone (MIC) configured to receive external audio signals when device 1000 is in an operating mode, such as call mode, recording mode, and voice recognition mode. The received audio signals may be further stored in memory 1004 or transmitted via communication component 1016. In some embodiments, audio component 1100 also includes a speaker for outputting audio signals.

[0101] I / O interface 1012 provides an interface between processing component 1002 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include, but are not limited to, home buttons, volume buttons, power buttons, and lock buttons.

[0102] Sensor assembly 1014 includes one or more sensors for providing state assessments of various aspects of device 1000. For example, sensor assembly 1014 may detect the on / off state of device 1000, the relative positioning of components such as the display and keypad of device 1000, changes in the position of device 1000 or a component of device 1000, the presence or absence of user contact with device 1000, the orientation or acceleration / deceleration of device 1000, and temperature changes of device 1000. Sensor assembly 1014 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. Sensor assembly 1014 may also include an optical sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, sensor assembly 1014 may also include an accelerometer, a gyroscope, a magnetometer, a pressure sensor, or a temperature sensor.

[0103] Communication component 1016 is configured to facilitate wired or wireless communication between device 1000 and other devices. Device 1000 can access wireless networks based on communication standards, such as WiFi, 3G, 4G, 5G, other communication standards, or combinations thereof. In some embodiments of this disclosure, communication component 1016 receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In some embodiments of this disclosure, communication component 1016 further includes a near-field communication (NFC) module to facilitate short-range communication. For example, the NFC module may be implemented based on radio frequency identification (RFID) technology, Infrared Data Association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

[0104] In some embodiments of this disclosure, the apparatus 1000 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to perform the methods described above.

[0105] In some embodiments of this disclosure, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 1004 including instructions, which can be executed by the processor 1020 of the device 1000 to complete the aforementioned data processing method or communication method. For example, the non-transitory computer-readable storage medium may be a ROM, random access memory (RAM), CD-ROM, magnetic tape, floppy disk, and optical data storage device, etc.

[0106] In some embodiments of this disclosure, a computer program product is also provided, including a computer program that, when executed by a processor, can implement the data processing method provided in the embodiments of this disclosure, or can implement the communication method provided in the embodiments of this disclosure.

[0107] Some embodiments of this disclosure also provide a chip system, such as Figure 11 As shown, the chip system includes at least one processor 1101 and at least one interface circuit 1102. The processor 1101 and the interface circuit 1102 are interconnected via lines. For example, the interface circuit 1102 can be used to receive signals from other devices (e.g., the memory of an electronic device). As another example, the interface circuit 1102 can be used to send signals to other devices (e.g., the processor 1101). Exemplarily, the interface circuit 1102 can read instructions stored in memory and send those instructions to the processor 1101. When the instructions are executed by the processor 1101, the device can perform the steps in the above embodiments. Of course, the chip system may also include other discrete devices, and some embodiments of this disclosure do not specifically limit this.

[0108] In some embodiments of this disclosure, the interface circuit 1102 can acquire data, program instructions, and / or information from the internal storage area of ​​the chip system; it can also acquire data, program instructions, and / or information from outside the chip system.

[0109] Optionally, the chip system may also include memory for storing necessary computer programs and data.

[0110] Those skilled in the art will also understand that the various illustrative logical blocks and steps listed in the embodiments of this application can be implemented by electronic hardware, computer software, or a combination of both. Whether such functionality is implemented through hardware or software depends on the specific application and the overall system design requirements. Those skilled in the art can implement the described functionality using various methods for each specific application, but such implementation should not be construed as exceeding the scope of protection of the embodiments of this application.

[0111] It should be understood that, unless otherwise specifically indicated, features of various embodiments of this disclosure described herein can be combined with each other. As used herein, the term “and / or” includes any one of the relevant listed items and any combination of any two or more; similarly, “at least one of…” includes any one of the relevant listed items and any combination of any two or more.

[0112] Although terms such as “first,” “second,” and “third” may be used herein to describe various components, parts, regions, layers, or sections, these components, parts, regions, layers, or sections are not limited to these terms. Rather, these terms are used only to distinguish one component, part, region, layer, or section from another. Therefore, without departing from the teachings of the examples described herein, the first component, part, region, layer, or section mentioned in the examples may also be referred to as the second component, part, region, layer, or section. Furthermore, the terms “first” and “second” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as “first” or “second” may explicitly or implicitly include at least one of that feature. In the description herein, “a plurality” means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0113] Furthermore, the term “exemplary” is used herein to mean serving as an example, instance, or illustration. Any aspect or design described herein as “exemplary” is not necessarily to be construed as advantageous compared to other aspects or designs. Rather, the use of the term “exemplary” is intended to present the concept in a concrete manner. As used herein, the term “or” is intended to mean an inclusive “or” rather than an exclusive “or.” That is, unless otherwise specified or clear from the context, “X applies A or B” is intended to mean any of the natural inclusive arrangements. That is, “X applies A or B” satisfies any of the foregoing instances if X applies A; X applies B; or both X applies A and B. Additionally, unless otherwise specified or clear from the context to refer to the singular form, the articles “a” and “an” as used in this application and the appended claims are generally understood to mean “one or more.”

[0114] Similarly, although this disclosure has been shown and described with respect to one or more implementations, equivalent variations and modifications will occur to those skilled in the art upon reading and understanding this specification and the accompanying drawings. This disclosure includes all such modifications and variations and is limited only by the scope of the claims. In particular, with respect to the various functions performed by the components described above (e.g., elements, resources, etc.), unless otherwise indicated, the terminology used to describe such components is intended to correspond to any component (functionally equivalent) that performs the specific function of the described component, even if structurally not equivalent to the disclosed structure. Furthermore, although specific features of this disclosure may have been disclosed with respect to only one of several implementations, such features may be combined with one or more other features of other implementations, as may be desired and advantageous to any given or particular application. Moreover, with regard to the terms “comprising,” “owning,” “having,” “having,” or variations thereof as used in the detailed description or claims, such terms are intended to be inclusive in a manner similar to the term “including.”

[0115] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the following claims.

[0116] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. A data processing method, characterized in that, include: In response to a matrix processing request, perform multiple loading processes on the first and second matrices; The matrix processing request is used to request a multiplication operation to be performed on the first matrix and the second matrix; the number of columns in the first matrix is ​​equal to the number of rows in the second matrix; the first matrix includes multiple first sub-matrices; the second matrix includes multiple second sub-matrices; each loading process is used to load a row of the first matrix that has not been loaded and a column of the second matrix that has not been loaded. For each row of the first submatrix and one column of the second submatrix loaded, a multiplication operation is performed on the first submatrix and the second submatrix loaded in that current loading operation to obtain the sub-operation result corresponding to that loading operation. Based on the sub-operation results corresponding to each loading process, the multiplication results for the first matrix and the second matrix are obtained.

2. The data processing method according to claim 1, characterized in that, Each time a submatrix is ​​loaded, the row index of the first submatrix in the first matrix is ​​the same as the column index of the second submatrix in the second matrix.

3. The data processing method according to claim 1, characterized in that, In response to the matrix processing request, multiple loading processes are performed on the first matrix and the second matrix, including: In response to the matrix processing request, the first matrix is ​​divided into the plurality of first sub-matrices, and the second matrix is ​​divided into the plurality of second sub-matrices; the number of first sub-matrices in each column is the same as the number of second sub-matrices in each row; Based on the plurality of first sub-matrices and the plurality of second sub-matrices, multiple loading processes are performed on the first matrix and the second matrix.

4. The data processing method according to claim 3, characterized in that, The multiple loading process includes N loading processes; N is greater than 1; each time a row of the first submatrix and a column of the second submatrix are loaded, a multiplication operation is performed on the first submatrix and the second submatrix loaded in that current loading process to obtain the sub-operation result corresponding to that loading process, including: The first submatrix in a row and the second submatrix in a column loaded in the i-th loading process are multiplied in parallel according to the corresponding positions of the row and column to obtain the sub-operation result corresponding to the i-th loading process; 1≤i≤N.

5. The data processing method according to claim 4, characterized in that, The step of performing parallel multiplication of a row of the first submatrix and a column of the second submatrix loaded in the i-th loading process according to their corresponding row and column positions to obtain the sub-operation result corresponding to the i-th loading process includes: Multiply the first submatrix in the k-th column loaded in the i-th loading process with the second submatrix in the k-th row to obtain the k-th intermediate result corresponding to the i-th loading process; 1≤k≤M; M is the number of the first submatrix loaded in the i-th loading process; The intermediate results corresponding to the i-th loading process are summed to obtain the sub-operation result corresponding to the i-th loading process.

6. The data processing method according to claim 4, characterized in that, The step of obtaining the multiplication result of the first matrix and the second matrix based on the sub-operation result corresponding to each loading process includes: Based on the sub-operation result corresponding to the i-th loading process, update the position of the sub-block in the result matrix corresponding to the i-th loading process; The updated result matrix obtained from the sub-operation results based on N loading processes is determined as the result of the multiplication operation between the first matrix and the second matrix.

7. The data processing method according to claim 6, characterized in that, Also includes: Initialize the result matrix and update the initialized result matrix based on the sub-operation results of the N loading processes; The number of rows in the result matrix is ​​the same as the number of rows in the first matrix, and the number of columns in the result matrix is ​​the same as the number of columns in the second matrix.

8. A communication method, characterized in that, include: In response to a signal transmission request, obtain the first matrix; The first matrix is ​​the data matrix to be sent; A matrix processing request is generated, and data processing is performed on the first matrix and the second matrix based on the data processing method according to any one of claims 1-7 to obtain a processing result; The second matrix is ​​either a precoding matrix or a channel coding matrix; Based on the processing results, a communication signal is generated; The communication signal is sent to the receiving device.

9. A communication method, characterized in that, include: In response to receiving a communication signal, a first matrix is ​​extracted from the communication signal; The first matrix is ​​the data matrix corresponding to the communication signal; A matrix processing request is generated to perform data processing on the first matrix and the second matrix based on the data processing method of any one of claims 1-7, and to obtain a processing result; the matrix processing request is used to request a multiplication operation to be performed on the first matrix and the second matrix; the second matrix is ​​a channel estimation matrix or a reference signal matrix.

10. An apparatus, characterized in that, include: processor; Memory used to store processor-executable instructions; The processor is configured to execute the executable instructions to implement the data processing method according to any one of claims 1-7, or to implement the communication method according to claim 8 or 9.

11. A non-transitory computer-readable storage medium, characterized in that, When the instructions in the storage medium are executed by the processor, the processor is able to perform the data processing method according to any one of claims 1-7, or implement the communication method according to claim 8 or 9.

12. A computer program product, characterized in that, It includes a computer program that, when executed by a processor, implements the data processing method according to any one of claims 1-7, or implements the communication method according to claim 8 or 9.

13. A chip system, characterized in that, The chip system includes a processing unit and an interface circuit. The processing unit obtains program instructions through the interface circuit, and the program instructions are executed by the processing unit. The processing unit is used to execute the data processing method according to any one of claims 1-7, or to implement the communication method according to any one of claims 15-17.

Images