Multi-source event priority arbitration device and method

Abstract

This invention discloses a multi-source event priority arbitration device and method. The device includes a hardware priority encoder, a central hardware arbitrator, an anti-starvation counting unit, and a deadlock detection and recovery unit. Priority arbitration is performed entirely in hardware, with low latency to prevent blocking, automatic deadlock reset, and priorities that cannot be modified. This invention improves response speed and scheduling stability, and is suitable for smartphone bus scheduling scenarios.

Description

Technical Field

[0001] This invention relates to the field of hardware scheduling technology, specifically to a purely hardware-based multi-source event priority arbitration device and execution method. Background Technology

[0002] Existing multi-source event arbitration uses software algorithm scheduling, which has drawbacks such as high response latency, blocking of low-priority tasks, unrecoverable bus deadlocks, and easy modification of scheduling rules, resulting in low equipment operational stability. Summary of the Invention

[0003] This invention provides a multi-source event priority arbitration device and method, in which hardware completes priority encoding and event adjudication, a counting unit balances task responses, a detection circuit identifies bus deadlock and triggers hardware reset, priority parameters are permanently stored, and there is no software scheduling throughout the entire process.

[0004] Differences from existing technologies 1. Existing technology uses software algorithm scheduling; this solution employs a pure copper foil logic architecture, with direct level flow for decision-making. 2. Existing technologies dynamically adjust priorities, while the fuse curing parameters and scheduling rules in this solution cannot be changed for life. 3. Existing technologies lack a balanced scheduling structure; this solution uses hardware polling to ensure response for all priority tasks. 4. Existing technologies rely on software reset for recovery, while this solution features automatic hardware reset, requiring no manual intervention. Beneficial effects

[0005] 1. Hardware pass-through decision-making results in low response latency and improved event processing speed; 2. A balanced scheduling structure avoids long-term blocking of low-priority tasks, ensuring smooth operation; 3. Hardware reset structure to restore bus deadlock state and improve system stability; 4. Priority is permanently stored, reducing the risk of scheduling logic being modified; 5. Parallel processing architecture, adaptable to multi-path concurrent event scheduling, improving processing efficiency. Detailed Implementation

[0006] This device is used in a smartphone bus scheduling system, receiving multiple concurrent signals of touch events, display events, call events, and background notification events; the binary copper foil encoder maps event priorities, and the parameter fuses are fixed and cannot be changed; the central arbitrator directly arbitrates concurrent events, eliminating data queuing delays.

[0007] The anti-starvation counting unit periodically polls and balances the scheduling of low-priority tasks; the deadlock detection circuit monitors the bus status in real time and automatically resets the hardware after identifying blockages; the entire domain has no software scheduling and no programming interface, ensuring stable and smooth bus scheduling for smartphones.

Claims

1. A multi-source event priority arbitration device, comprising a hardware priority encoder, a central hardware arbitrator, and a multi-source event input interface, characterized in that: The hardware priority encoder performs priority encoding on concurrent multi-source events; The central hardware arbitrator performs event arbitration based on a fixed priority table; the device is equipped with a hardware anti-starvation counting unit to balance the response of low-priority events; the device has a built-in hardware deadlock detection and automatic recovery unit; the priority mapping relationship is fixed in a one-time programmable storage unit; the arbitration result is directly output to the corresponding functional domain; the hardware deadlock detection unit is used to identify bus blocking and trigger hardware reset.

2. The apparatus according to claim 1, characterized in that, The hardware priority encoder uses binary copper foil lines and logic, with no operations, and priority levels are directly mapped.

3. The apparatus according to claim 1, characterized in that, The hardware anti-starvation counting unit is a periodic pulse direct-through unit with no software scheduling, and the anti-starvation level automatically switches through.

4. The apparatus according to claim 1, characterized in that, The hardware deadlock detection unit has a fixed hardware duration and no configuration; in the deadlock state, the copper foil passes through and automatically resets.

5. The apparatus according to claim 1, characterized in that, The automatic recovery unit is triggered by a direct-pass circuit and requires no reset command, resulting in zero manual intervention during the recovery process.

6. The apparatus according to claim 1, characterized in that, One-time programmable memory cells are fixed by fuses and cannot be modified; priority mapping relationships are physically bound for life.

7. A multi-source event priority arbitration method, applied to the apparatus of claim 1, characterized in that, include: Multiple events are input in parallel to the hardware priority encoder; The encoder completes level pass-through priority encoding; The central hardware arbitrator directly adjudicates concurrent events based on a fixed priority table; The hardware anti-starvation counting unit uses periodic pulse equalization to balance the response sequence; the hardware deadlock detection unit monitors the blocking status in real time; in the event of a deadlock, a pass-through triggers automatic hardware recovery; the decision result is passed-through for execution; the process is a parallel pass-through sequence with no queuing, and the output cannot be intercepted by software.

8. The method according to claim 7, characterized in that, The device is a priority arbitration chip with no logic programming interface and full arbitration rule copper foil hard-wired fuse.