Integrated electronic systems and spacecraft

Abstract

This application provides an integrated electronic system and spacecraft, applicable to the field of spacecraft electronic system technology. The integrated electronic system includes a slave processing unit and a main processing unit. The slave processing unit is electrically connected to multiple individual units of the spacecraft via interfaces. The slave processing unit parses the interface data of each interface through a low-level interface protocol and outputs the parsed data. The main processing unit is electrically connected to the slave processing unit and processes the parsed data output by the slave processing unit. In this embodiment, the slave processing unit outputs the parsed data from each individual unit to the same main processing unit for processing, eliminating the need for each individual unit to have its own independent processor, memory, and software, and avoiding information exchange through complex buses. This embodiment separates computation from interfaces, achieving functional decoupling and maximizing efficiency, saving computational resources, and effectively eliminating functional boundaries.

Description

Technical Field

[0001] This application relates to the field of spacecraft electronic systems technology, and in particular to integrated electronic systems and spacecraft. Background Technology

[0002] Traditional satellite electronic systems typically employ a functionally separate, stand-alone architecture, such as a satellite computer, attitude control computer, telemetry and command transponder, GNSS receiver, and power controller. Each unit has its own independent processor, memory, and software, and communicates with other units via a complex bus system. This architecture suffers from problems such as equipment redundancy, large size and weight, long development cycles, and difficulty in dynamically allocating onboard resources.

[0003] With the development of microelectronics technology, some designs have proposed the concept of integrated electronics, but most of them still focus on physically integrating multiple single machines into one chassis. Their internal logic is still multiple independent "black box" systems, which has not fundamentally eliminated the redundancy of computing resources and functional limitations. Summary of the Invention

[0004] In view of this, embodiments of this application provide an integrated electronic system and spacecraft to solve the problems of redundant computing resources and functional limitations caused by the functionally discrete single-machine architecture of spacecraft in the prior art.

[0005] A first aspect of this application provides an integrated electronic system, comprising: The processing unit is electrically connected to multiple individual units of the spacecraft via interfaces. It is used to parse the interface data of each interface through the underlying interface protocol and output the parsed data. The main processing unit, electrically connected to the slave processing unit, is used to process the parsed data output by the slave processing unit.

[0006] In one possible implementation, the main processing unit is electrically connected to the artificial intelligence module; The main processing unit is used to schedule the artificial intelligence module; the artificial intelligence module is used for intelligent image processing or fault diagnosis.

[0007] In one possible implementation, the processing unit includes a first slave processor and a second slave processor; The first connection is made electrically between the processor and the space interface and power interface; The first slave processor is used to parse and output the data from the space service interface and the power interface; the space service interface is used to transmit ground commands, and the power interface is used to transmit electrical signal data and power control data. The second part is electrically connected to the processor, the attitude control interface, and the thermal control interface; The second slave processor is used to parse and output the data from the attitude control interface and the thermal control interface; the attitude control interface is used to transmit the spacecraft's attitude control data, and the thermal control interface is used to transmit the spacecraft's temperature control data.

[0008] In one possible implementation, the first slave processor is connected to a storage device, and the first slave processor is also used to boot and load the system.

[0009] In one possible implementation, the master processing unit and the slave processing unit transmit data via a bidirectional parallel bus protocol; the bidirectional parallel bus protocol supports the synchronous exchange of multi-source data.

[0010] In one possible implementation, the main processing unit includes a status acquisition module and a configuration loading module; The status acquisition module is used to acquire data from various sensors on the spacecraft and generate loading decisions based on the acquired data; The configuration loading module is used to load configurations based on loading decisions, obtain at least one driver configuration, and output the corresponding configuration of at least one driver.

[0011] In one possible implementation, the drive configuration includes at least one of the following: satellite service configuration, attitude control configuration, telemetry and command configuration, data transmission configuration, global navigation satellite system (GNSS) configuration, and payload configuration.

[0012] In one possible implementation, the main processing unit also includes a bad block management module; The bad block management module is used to identify the bad block level of each storage block electrically connected to the main processing unit and obtain the identification level of each storage block; based on each identification level, storage management is performed on each storage block.

[0013] In one possible implementation, the bad block management module is used to enable redundant error correction codes for the storage block and perform data migration on the storage block if the identification level of the storage block is a substandard block; if the identification level of the storage block is a bad block, the storage block is removed from the available space and the bad block list is updated based on the storage block.

[0014] A second aspect of this application provides a spacecraft, including: an integrated electronic system as described in the first aspect.

[0015] Compared with the prior art, the embodiments of this application have at least the following technical effects: The integrated electronic system provided in the first aspect of this application includes a slave processing unit and a main processing unit. The slave processing unit is electrically connected to multiple individual units of the spacecraft via interfaces. The slave processing unit parses the interface data of each interface through a low-level interface protocol and outputs the parsed data, thereby enabling data from multiple individual units to interact with the slave processing unit through the interfaces. The main processing unit is electrically connected to the slave processing unit and processes the parsed data output by the slave processing unit. The parsed data from each individual unit can be output to the same main processing unit for processing through the slave processing unit, eliminating the need for each individual unit to have its own independent processor, memory, and software, thus avoiding information exchange through complex buses. This application separates computation from interfaces, achieving functional decoupling and maximizing efficiency, saving computational resources, and effectively eliminating functional boundaries.

[0016] It is understandable that the beneficial effects of the second aspect mentioned above can be found in the relevant descriptions in the first aspect mentioned above, and will not be repeated here. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the framework of an existing electronic system provided in an embodiment of this application; Figure 2 This is a schematic diagram of the framework of an integrated electronic system provided in an embodiment of this application; Figure 3 This is a schematic diagram of the framework of another integrated electronic system provided in the embodiments of this application; Figure 4 This is a schematic diagram of the main processing unit functional reconfiguration framework of an integrated electronic system provided in this application embodiment; Figure 5 This is a flowchart of an automatic storage block management method provided in an embodiment of this application. Detailed Implementation

[0019] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0020] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0021] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0022] In the description of this application, unless otherwise stated, the " / " used in this specification and appended claims indicates that the related objects are in an "or" relationship. For example, A / B can mean A or B. The "and / or" in this application merely describes the relationship between the related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. Furthermore, in the description of this application, unless otherwise stated, "multiple" means two or more. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, a and b, a and c, b and c, or a, b, and c. Here, a, b, and c can be single or multiple.

[0023] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if detected [the described condition or event]" may be interpreted, depending on the context, as meaning "once determined," "in response to determination," "once detected [the described condition or event]," or "in response to detection [the described condition or event]."

[0024] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0025] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0026] See Figure 1 As shown in the figure, this application provides a schematic diagram of the framework of a conventional electronic system. Conventional electronic systems are implemented using a stacked configuration of multiple boards with internal connectors. Each board also has external connector ports, facilitating functional expansion and ensuring optimal allocation of computational resources among multiple processors.

[0027] like Figure 1 As shown, the existing electronic system consists of the following multiple boards: a spacecraft processing board, an expansion control / baseband processing board, an expansion AI (Artificial Intelligence) module / high-capacity solid-state storage board, a power control board, and a measurement and control / data transmission front-end driver board. The main components of the existing electronic system framework include: (1) Layered stacked internal structure The system consists of multiple functional boards coupled via a bus and employs a cold / hot backup mechanism. Satellite Management Board (A / B Unit): Responsible for overall satellite scheduling, protocol distribution, and mission management.

[0028] GNSS board (A / B unit): integrates navigation and positioning functions, providing a high-precision spatiotemporal reference.

[0029] Power control board (A / B unit): manages solar panels, battery packs and PCU, and realizes power distribution for the entire satellite.

[0030] Expansion Module (AI / Solid Storage): Innovatively, an AI module and a large-capacity solid storage are integrated within the integrated electronics to support intelligent on-orbit data processing and massive payload data storage.

[0031] (2) Extremely rich external interface integration (plugins) The system integrates the functions of multiple traditional subsystems into a single physical enclosure through external plug-ins in four directions: Attitude control actuator drive: Direct output to drive and control equipment such as flywheels (*4), gyroscopes (*2), magnetometers, and electric propulsion.

[0032] Sensor acquisition: It integrates multiple terasensitive and star-sensor interfaces, as well as high-precision thermistor acquisition (*35 channels) and ADC acquisition (*20 channels).

[0033] Complex commands and communications support up to 18 RS422, RS485, LVDS, OC command outputs (*48 channels) and OneWire bus.

[0034] Mechanism driving capability: It has the ability to directly drive and monitor the status of high-current mechanisms such as electric explosion valves, solenoid valves, and venting valves.

[0035] (3) End-to-end redundancy design Figure 1 The A / B machine identifiers (such as the A / B dual-machine backup for satellite navigation, GNSS (Global Navigation Satellite System), antenna, and power control) ensure the system's survivability in the event of a single point of failure.

[0036] The technical solution of this application and how it solves the above-mentioned technical problems are described in detail below with specific embodiments. It should be noted that the following embodiments can be referenced, learned from, or combined with each other, and the same terms, similar features, and similar implementation steps in different embodiments will not be described again.

[0037] See Figure 2 As shown, this application provides a schematic diagram of the framework of an integrated electronic system 10. Figure 2 As shown, the integrated electronic system 10 includes a slave processing unit 11 and a main processing unit 12.

[0038] The processing unit 11 is electrically connected to multiple individual units of the spacecraft through interfaces. The processing unit 11 is used to parse the interface data of each interface through the underlying interface protocol and output the parsed data. The main processing unit 12 is electrically connected to the slave processing unit 11. The main processing unit 12 is used to process the parsed data output by the slave processing unit 11.

[0039] The integrated electronic system 10 of this application embodiment is a novel integrated, highly integrated, highly reliable, streamlined, and reconfigurable spaceborne integrated electronic system. The integrated electronic system 10 of this application embodiment includes a slave processing unit 11 and a main processing unit 12. The slave processing unit 11 is electrically connected to multiple individual units of the spacecraft via interfaces. The slave processing unit 11 is used to parse the interface data of each interface through the underlying interface protocol and output the parsed data, thereby enabling data from multiple individual units to interact with the slave processing unit 11 through the interfaces.

[0040] Furthermore, the main processing unit 12 is electrically connected to the slave processing unit 11. The main processing unit 12 is used to process the parsed data output by the slave processing unit 11. The parsed data from each unit can be output to the same main processing unit 12 for processing. This eliminates the need for each unit to have its own independent processor, memory, and software, thereby avoiding information exchange through a complex bus.

[0041] Furthermore, the embodiments of this application separate computation from the interface, thereby achieving functional decoupling and maximizing efficiency, saving computing resources, and effectively eliminating functional boundaries.

[0042] The integrated electronic system 10 of this application embodiment can adopt a multi-board stacked structure. The boards are interconnected through inter-board connectors to realize internal bus interconnection. The connected internal plug-ins realize internal bus. Each board has external plug-ins, which can realize external bus connection. The backplane design is eliminated. Each board is directly stacked, reducing signal transfer paths.

[0043] In some embodiments, the processing unit 11 includes a first slave processor and a second slave processor.

[0044] The first part is electrically connected to the processor, the space service interface, and the power interface.

[0045] The first slave processor is used to parse and output data from the space service interface and the power interface; the space service interface is used to transmit ground commands, and the power interface is used to transmit electrical signal data and power control data.

[0046] The second part is electrically connected to the processor, the attitude control interface, and the thermal control interface.

[0047] The second slave processor is used to parse and output the data from the attitude control interface and the thermal control interface; the attitude control interface is used to transmit the spacecraft's attitude control data, and the thermal control interface is used to transmit the spacecraft's temperature control data.

[0048] See Figure 3 As shown in the figure, this application provides a schematic diagram of the framework of another integrated electronic system 10. For example... Figure 3As shown, the integrated electronic system 10 is controlled by multiple processors in parallel, achieving maximum utilization and simplification. The main control SOC FPGA handles both complex baseband and attitude control algorithms, and is reconfigurable and refreshable. Two FLASH FPGAs (Field-Programmable Gate Arrays) are used for high reliability in bootstrapping and interface expansion. Specifically, FLASH FPGA 1 and FLASH FPGA 2 correspond to the first and second slave processors, respectively, and the SOC FPGA corresponds to the main processing unit 12, which can be the main processor. The space service I / O connects to the space service computer, the attitude control I / O connects to the attitude control computer, and the power supply I / O connects to the power controller.

[0049] In some embodiments, the main processing unit 12 is electrically connected to the artificial intelligence module; the main processing unit 12 is used to schedule the artificial intelligence module; the artificial intelligence module is used for intelligent image processing or fault diagnosis.

[0050] In some embodiments, a first slave processor is connected to a storage device, and the first slave processor is also used to boot the system. The storage device may employ non-volatile flash memory technology.

[0051] In some embodiments, the main processing unit 12 and the slave processing unit 11 transmit data via a bidirectional parallel bus protocol; the bidirectional parallel bus protocol supports synchronous exchange of multi-source data.

[0052] The embodiments of this application can solve the problems of obvious single-machine limitations, redundant computing resources, and insufficient integration in the prior art. They are based on a software-defined architecture and are designed around processor reuse.

[0053] See Figure 3 As shown, this embodiment employs three processors working in parallel to ensure a maximum balance between system resources and efficiency, while guaranteeing a certain degree of redundancy and scalability in the interfaces. (Comparison) Figure 3 Compared to existing electronic systems, the integrated electronic system 10 of this application embodiment has a significantly reduced number of interfaces. The integrated electronic system 10 of this application embodiment mainly includes the following technical contents: (1) Heterogeneous three-core parallel processing architecture This application's embodiments abandon the traditional single-processor mode and adopt a heterogeneous topology structure of "one master and two slaves": Core layer (SOC FPGA): As the main processing unit of the system, it uses its embedded soft-core processor to handle complex baseband signal processing, advanced attitude and trajectory control algorithms, and scheduling of AI modules.

[0054] Support layer (FLASH FPGA 1 and FLASH FPGA 2): Employs FPGAs based on Flash technology. Leveraging their non-volatility and strong resistance to single-event transients, they are specifically responsible for parsing and booting the underlying interface protocols (spacecraft I / O, power I / O, attitude control I / O).

[0055] (2) Functional decoupling and efficiency maximization Decoupling computation and interface: Two FLASH FPGAs separate the cumbersome low-level I / O (Input / Output) communication from the SOC FPGA, allowing the SOC FPGA to focus on high-intensity data processing.

[0056] Booting and Reconfiguration Mechanism: FLASH FPGA 1 connects to Norflash (a storage device using non-volatile flash memory technology) and is responsible for the boot loading of the entire system. Due to the on-orbit reconfigurability of the SOC FPGA, FLASH FPGA 1 and FLASH FPGA 2 can serve as reliable refresh monitoring units, enabling software-defined satellite function updates.

[0057] (3) Dedicated expansion module integration AI Module Empowerment: The SOC FPGA connects to the AI ​​module via a dedicated bus, enabling intelligent image processing or autonomous fault diagnosis at the edge. High-Speed ​​Link Support: Direct connection to RF and Ethernet ports via a high-speed bus (GTH) and DA interface supports broadband data transmission requirements.

[0058] Based on the framework structure of the integrated electronic system 10 according to the embodiments of this application, at least the following technical effects can be achieved: (1) Parallelism and simplification principle: By assigning deterministic tasks (IO control) to FLASH FPGA and nondeterministic high computational tasks (algorithm / AI) to SOC FPGA, the system utilization is maximized while reducing the complexity of single-machine hardware.

[0059] (2) Combination of dynamic reconfiguration and high reliability: A high-reliability boot and dynamic refresh mode is adopted. The physical characteristics of FLASHFPGA are used to ensure the absolute safety of the initial boot, while supporting on-orbit refresh of baseband and attitude control algorithms of the main processor SOC FPGA.

[0060] (3) Heterogeneous bus interconnection: a bidirectional parallel bus protocol between the SOC FPGA and two FLASH FPGAs. This protocol supports the synchronous exchange of multi-source data, ensuring the real-time performance of key data such as attitude control and power supply.

[0061] (4) Radiation resistance optimization: FLASH FPGA does not require configuration chips in the space environment and has better anti-interference performance than traditional SRAM type, acting as a "gatekeeper" to protect the core SOC FPGA.

[0062] (5) High integration: Through three core chips and peripheral circuits, the functions of the four subsystems of traditional satellite data management, attitude control, data transmission and thermal control are integrated.

[0063] In some embodiments, the main processing unit 12 includes a status acquisition module and a configuration loading module.

[0064] The status acquisition module is used to acquire data from various sensors on the spacecraft and generate loading decisions based on the acquired data; The configuration loading module is used to load configurations based on loading decisions, obtain at least one driver configuration, and output the corresponding configuration of at least one driver.

[0065] In some embodiments, the drive configuration includes at least one of the following: satellite service configuration item, attitude control configuration item, telemetry and command configuration item, data transmission configuration item, global navigation satellite system (GNSS) configuration item, and payload configuration item.

[0066] See Figure 4 As shown in the figure, this application embodiment provides a schematic diagram of the functional reconfiguration framework of the main processing unit 12 of an integrated electronic system 10. (See figure) Figure 4 As shown, this embodiment of the application can implement different configuration items for decision loading based on the actual on-orbit situation, thereby achieving multiple functions. Here, SOC-PS represents the status acquisition module, and SOC-PL represents the configuration loading module.

[0067] During on-orbit operation, the main processing unit 12 can dynamically allocate SOC resources according to mission requirements (for example, when approaching the target, the telemetry and control mission is paused, and all computing power is used for image compression and AI target recognition; when approaching the ground station, the telemetry and control mission is resumed), enabling functions to change with the software. In on-orbit reconfiguration scenarios, such as when a certain payload peripheral device is damaged and cannot be used, a new module function can be switched and reconfigured to achieve another payload function.

[0068] Optionally, the satellite configuration items can define the priority of data packets, routing tables, and the downlink cycle of telemetry parameters (such as temperature and voltage), involving satellite I / O, bus, and thermal control interface (monitoring satellite temperature).

[0069] The attitude control configuration includes PID (Proportional-Integral-Derivative) control parameters, calibration coefficients of the momentum wheel / magnetic torque generator, and the effective angle range of the solar sensor / star sensor, involving attitude control I / O, star sensor interface, solar sensor interface, and flywheel drive.

[0070] The measurement and control configuration items can define the uplink and downlink frequency points, modulation methods, and encryption verification algorithms, involving radio frequency ports, measurement and control front-ends, and remote control command parsing.

[0071] The data transmission configuration items can define the compression ratio, error correction code (LDPC), and data transmission rate for high-speed data transmission, involving data playback strategies for high-speed buses, Ethernet / GTH, and solid-state storage.

[0072] The GNSS configuration items include the ephemeris data of the navigation satellite, the positioning update frequency, and the UTC time calibration parameters, which are related to the GNSS receiver interface.

[0073] Payload configuration options determine the power-on timing, gain control, and imaging mode of a SAR (Synthetic Aperture Radar) or optical camera, and involve the high-speed data stream configuration of the payload interface and AI module (image preprocessing). In some embodiments, the main processing unit 12 further includes a bad block management module.

[0074] The bad block management module is used to identify the bad block level of each storage block electrically connected to the main processing unit 12, and obtain the identification level of each storage block; based on each identification level, it performs storage management on each storage block.

[0075] In some embodiments, the bad block management module is used to enable redundant error correction codes for the storage block and perform data migration on the data of the storage block if the identification level of the storage block is a substandard block; if the identification level of the storage block is a bad block, the storage block is removed from the available space and the bad block list is updated based on the storage block.

[0076] See Figure 5 As shown, this application embodiment provides a flowchart for automatic storage block management. (As illustrated...) Figure 5 As shown, in solid-state storage, in order to address the shortcomings of traditional bad block management methods, this application proposes an automatic bad block management method, which mainly involves in-depth analysis and fine classification of solid-state storage. The purpose is to ensure system reliability and data integrity, while also accurately classifying the blocks of solid-state storage to improve the utilization rate of solid-state storage.

[0077] See Figure 5 As shown, the automatic storage block management process in this application embodiment includes the following: (1) The embodiments of this application can report bad blocks when reading the internal registers of the fixed memory, but instead deeply analyze the growth curve of the number of ECC error correction bits when reading the data; by establishing a "health decay model", when the bit flip rate of a certain block reaches 50% of the ECC error correction limit, the software automatically starts data migration and adds the target block to the observation list. When the block reaches 80% of the error correction limit, the block is marked as a bad block and directly isolated. This can significantly reduce the risk of data loss due to sudden physical damage.

[0078] (2) In this embodiment, not all reported blocks are physically damaged; many are misjudged due to high-voltage interference. After detecting a failed write operation on a storage block, it is not immediately marked as a bad block. Instead, an automatic testing process is initiated, attempting multiple erases, adjusting the read voltage, and performing a full physical scan. This distinguishes between permanent physical damage and software logic errors. If it is a software logic error, the system recovers it through deep erasure after data migration; if it is permanent physical damage, the storage block is permanently blocked. This significantly improves the utilization rate of the storage and avoids wasted storage capacity due to transient interference.

[0079] (3) In the bad block replacement process of this application embodiment, the key is to ensure that the front-end business does not slow down or lag. A dynamic mapping table between logical and physical addresses is used. Idle time is utilized for background data migration. Bad block data is copied to a spare block in the background, and the mapping pointer is switched instantaneously in milliseconds. For the front-end application, read and write operations are never interrupted, and the underlying data migration is completely imperceptible, emphasizing the high availability and low latency of the system.

[0080] (4) The embodiments of this application may employ a linked wear leveling algorithm. When a bad block is generated and needs to be replaced, the system does not randomly select a spare block, but makes the optimal selection based on the number of erases and writes and the physical location of the spare block, ensuring that the replaced block will not be damaged again quickly due to excessive load, thereby extending the mean time between failures of the entire disk.

[0081] This application provides a spacecraft, including: an integrated electronic system 10 according to this application.

[0082] It should be noted that the information interaction and execution process between the above-mentioned devices / units are based on the same concept as the method embodiments of this application. For details on their specific functions and technical effects, please refer to the method embodiments section, and they will not be repeated here.

[0083] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0084] If the integrated units described above are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include at least: any entity or device capable of carrying computer program code to a device / terminal equipment, a recording medium, a computer memory, a read-only memory (ROM), a random access memory (RAM), an electrical carrier signal, a telecommunication signal, and a software distribution medium. Examples include USB flash drives, portable hard drives, magnetic disks, or optical disks.

[0085] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0086] In the embodiments provided in this application, it should be understood that the disclosed apparatus / network devices and methods can be implemented in other ways. For example, the apparatus / network device embodiments described above are merely illustrative. For instance, the division of modules or units described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0087] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0088] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. An integrated electronic system, characterized in that, include: The processing unit is electrically connected to multiple individual units of the spacecraft via interfaces, and is used to parse the interface data of each interface through the underlying interface protocol and output the parsed data. The main processing unit is electrically connected to the slave processing unit and is used to process the parsed data output by the slave processing unit.

2. The integrated electronic system according to claim 1, characterized in that, The main processing unit is electrically connected to the artificial intelligence module; The main processing unit is used to schedule the artificial intelligence module; the artificial intelligence module is used for intelligent image processing or fault diagnosis.

3. The integrated electronic system according to claim 1, characterized in that, The slave processing unit includes a first slave processor and a second slave processor; The first slave processor is electrically connected to the space interface and the power interface; The first slave processor is used to parse and output the data from the space service interface and the power interface; the space service interface is used to transmit ground commands, and the power interface is used to transmit electrical signal data and power control data. The second slave processor is electrically connected to the attitude control interface and the thermal control interface; The second slave processor is used to parse and output the data from the attitude control interface and the thermal control interface; the attitude control interface is used to transmit the attitude control data of the spacecraft, and the thermal control interface is used to transmit the temperature control data of the spacecraft.

4. The integrated electronic system according to claim 3, characterized in that, The first slave processor is connected to a storage device, and the first slave processor is also used to boot and load the system.

5. The integrated electronic system according to claim 1, characterized in that, The main processing unit and the slave processing unit transmit data through a bidirectional parallel bus protocol; the bidirectional parallel bus protocol supports synchronous exchange of multi-source data.

6. The integrated electronic system according to claim 1, characterized in that, The main processing unit includes a status acquisition module and a configuration loading module; The status acquisition module is used to acquire data from various sensors of the spacecraft and generate loading decisions based on the acquired data. The configuration loading module is used to load configurations based on the loading decision, obtain at least one driver configuration, and output at least one of the driver configurations.

7. The integrated electronic system according to claim 6, characterized in that, The drive configuration includes at least one of the following: satellite service configuration, attitude control configuration, telemetry and command configuration, data transmission configuration, Global Navigation Satellite System (GNSS) configuration, and payload configuration.

8. The integrated electronic system according to any one of claims 1-7, characterized in that, The main processing unit also includes a bad block management module; The bad block management module is used to identify the bad block level of each storage block electrically connected to the main processing unit, and obtain the identification level of each storage block; based on the identification level, it performs storage management on each storage block.

9. The integrated electronic system according to claim 8, characterized in that, The bad block management module is used to enable redundant error correction codes for the storage block and perform data migration for the storage block if the identification level of the storage block is a substandard block; if the identification level of the storage block is a bad block, the storage block is removed from the available space and the bad block list is updated based on the storage block.

10. A spacecraft, characterized in that, include: The integrated electronic system as described in any one of claims 1-9.

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