Systems and methods that provide built-in self-test correction actions during runtime.

Abstract

This disclosure relates to systems and methods for providing built-in self-test correction actions during runtime. The invention provides a computer system (100) that includes the functionality to provide built-in self-test BIST management and correction actions during runtime. The computer system may include a plurality of processor cores (101 to 104), wherein at least one of those processor cores (101) is dedicated to running BIST management software and correction software (131). During runtime of an application program (132) on the processor core, another processor core dedicated to running the BIST management software and correction software may cause a BIST operation to be performed, and then a correction action may be performed in response to the result of the BIST operation.

Description

Technical Field

[0001] This disclosure generally relates to computer systems, and more specifically, to systems and methods for providing built-in self-test (BIST) correction actions during runtime in a computer system. Background Technology

[0002] Safety protocols are used to ensure safety in electrical and / or electronic systems. For example, the International Organization for Standardization (ISO) 26262 is an international standard for the functional safety of electrical and / or electronic systems in automobiles. Such safety protocols analyze the risks associated with electronic failures (e.g., a combination of the frequency of injury and the severity of said injury). Failures corresponding to electronic components can be random or systematic. Random failures can correspond to hardware-related permanent or transient failures due to the loss of functionality of system components. Systematic failures can correspond to design flaws, incorrect specifications, and / or inapplicability errors in software. Such safety protocols analyze the electrical risks associated with hardware components that can handle signals to improve vehicle safety. Summary of the Invention

[0003] In one arrangement, a method includes: executing computer-executable code for a first application, wherein the first application includes receiving data from hardware components of a computer system on which the first application runs; during runtime of the first application, executing computer-executable code for a second application, wherein the computer-executable code for the second application causes a built-in self-test (BIST) operation to be performed on the hardware components; and, through the second application and during runtime of the first application, performing a correction action on the hardware components based on the result of the BIST operation.

[0004] In another arrangement, a system includes: a first processor core; a second processor core; and a real-time address translation (RAT) circuit coupled between the second processor core and random access memory (RAM), wherein the RAT circuit is configured to translate addresses of the RAM in transactions from the second processor core; wherein the first processor core is configured to change settings of the RAT circuit via hardware signals to configure the RAT circuit for address translation during the runtime of an application on the second processor core.

[0005] In another arrangement, an integrated circuit (IC) includes: a first processor core; a second processor core; a hardware module coupled to the first processor core and configured to transfer data to the first processor core during the runtime of a first application running on the first processor core; and tightly coupled memory (TCM) circuitry disposed within the second processor core and configured to store computer-executable code for built-in self-test (BIST) management software, wherein the BIST management software is configured to perform BIST operations on the hardware module during the runtime of the first application. Attached Figure Description

[0006] Having thus generally described the invention, reference will now be made to the accompanying drawings, in which:

[0007] Figure 1 These are illustrations of example systems based on some embodiments.

[0008] Figure 2 This is an illustration of an example architecture, based on some embodiments, that can be used to enable a processor core to run security software.

[0009] Figure 3 This is a diagram illustrating an example architecture of a real-time address translation circuit according to some embodiments.

[0010] Figure 4 This is an illustration of example methods that can be executed by a processor core when it is running security software, according to some embodiments.

[0011] Figure 5 This is an illustration of an example method that can be executed by security software according to some embodiments.

[0012] Figure 6 This is an illustration of an example method that can be executed by security software according to some embodiments. Detailed Implementation

[0013] This disclosure is described with reference to the accompanying drawings. The drawings are not drawn to scale and are provided for illustrative purposes only. Several aspects of this disclosure are described below with reference to illustrative example applications. It should be understood that numerous specific details, relationships, and methods are set forth to provide an understanding of this disclosure. This disclosure is not limited to the order of the activities or events shown, as some activities may occur in a different order and / or simultaneously with other activities or events. Furthermore, not all of the described actions or events are required to implement the methods according to this disclosure.

[0014] Automotive Safety Integrity Levels (ASIL) fall under the scope of ISO 26262 and specify the safety level of automotive components. ASIL compliance may require systems to have a high level of failure detection. Examples of failure detection may include Built-in Self-Test (BIST), where a hardware test module (e.g., a BIST module) can run tests on other hardware modules (e.g., memory circuitry, analog-to-digital converters). In the context of ASIL, BIST operation may be referred to as safety or functional safety.

[0015] Various embodiments may include systems and methods that allow BIST operations and corrections to be performed during runtime. Some embodiments may also include a separate processor core (or multiple processor cores) for BIST management and correction, thereby allowing other processor cores to run the application without degrading application performance.

[0016] In one example, a method includes executing computer-executable code for a first application. The first application may contain functionality for industrial or automotive use. For example, various levels of ASIL may be designed for systems where failure could cause damage, such as in industrial machinery, automotive airbag systems, automatic braking systems, etc. The first application provides such functionality where there may be a need or even a legal requirement to reduce failures (e.g., malfunctions) and to detect failures before they cause damage.

[0017] Additionally, in this example, the first application may run on the first processor core. The first application may include receiving data from hardware components such as memory circuitry (e.g., SRAM, DRAM), analog-to-digital converters (ADCs), digital logic (e.g., sequential logic, logic gates), etc.

[0018] Continuing the example, during the runtime of the first application, another processor core can execute computer-executable code for a second application. The second application can provide BIST management and correction functionality. For example, the second application can cause BIST operations to run on hardware components. In the example use case, the second application can transmit hardware signals or use another technique to cause BIST circuitry to perform BIST operations on the hardware components and return the results of the BIST operations to the second application running on the second processor core.

[0019] After receiving the results of the BIST operation, the second application can then perform calibration actions on the hardware components in response to the results of the BIST operation. One example of the possible calibration actions includes configuring the real-time address translation circuitry of the first processor core to bypass memory sections indicated as malfunctioning by the BIST operation. Another example includes performing fine-tuning operations on the ADC for calibration operations in response to a malfunction indicated on the ADC by the BIST result. Yet another example includes reducing the resolution level or sampling rate of the ADC in response to the BIST result.

[0020] In some implementations, the correction action may cause a decrease in some characteristics of the performance of the first application, while allowing the first application to continue operating. For example, reducing the sampling rate or resolution level of the ADC may be accompanied by some performance degradation of the first application, but the first application may still be able to provide acceptable performance. In some examples, this mode may be referred to as limp mode.

[0021] Various embodiments offer advantages over other solutions. For example, some systems may provide BIST operations during runtime, but may not provide corrective actions in response to the results of the BIST operations. In such cases, on-chip security applications may simply render the system inoperable. In contrast, various embodiments allow the first application to continue operating, thereby allowing further use of the system.

[0022] Another advantage may include separating the execution of BIST management and calibration software from the execution of other applications. For example, some embodiments allow the main application processor core to not run the BIST management and calibration software, instead separating the BIST management and calibration software onto one or more separate processor cores. Such an architecture allows the main application to execute without competing for processor capacity with the BIST management and calibration software. In other words, such an architecture allows for faster processing of the main application.

[0023] Figure 1 This is an illustration of an example system 100 according to some embodiments. Example system 100 may be implemented as one or more integrated circuits. For example, each of components 101 to 118 may be contained on the same semiconductor die with additional components (not shown), as a system-on-a-chip (SoC). In another example, processor cores 101 to 104 may be implemented on a semiconductor die, and interconnects 117 and memory devices 107, 108 may be implemented on one or more other semiconductor dies. One or more given semiconductor dies may be contained within a semiconductor package, and the package may be mounted to a printed circuit board or other components.

[0024] In addition, although Figure 1Four processor cores 101 to 104 are shown, but the scope of the implementation may include systems with more or fewer processor cores. Furthermore, the amount of interconnects (e.g., 117), memory devices (e.g., 107, 108), and peripheral devices (e.g., 118) can be scaled as needed to accommodate any appropriate number and type of memory devices and / or peripheral devices.

[0025] Each processor core 101 to 104 may contain any suitable processor core depending on any suitable processor architecture. For example, a given processor core may be implemented as a general-purpose processor core, a special-purpose processor, a reduced instruction set computer, a graphics processing unit, or other processor core.

[0026] In this example, processor core 102 can be used as the main central processing unit (CPU) and can be configured to execute main application 132. For example, main application 132 may contain computer-executable code that performs specific functions of an automotive, industrial machine, or other use case, where the execution of functions may be subject to regulations. As described above, industrial machine operation, braking systems, airbag deployment systems, steering systems, etc., can be use cases for main application 132.

[0027] Additionally, in this example, read-only memory (ROM) 113 may contain a basic input / output system (BIOS) or other boot software, which can be read and executed by processor core 102 at boot time. Once booted, processor core 102 can then read and execute computer-executable code from non-volatile memory (NVM) 107. For example, NVM 107 may store code implementing an operating system (OS), one or more applications (e.g., main application 132), etc. In this example, random access memory (RAM) circuitry 108 may include multiple sets of RAM or other suitable memory circuitry for use by processor cores 101 to 104 during runtime. Direct memory access (DMA) circuitry 105 may be used by any of processor cores 101 to 104 to read computer-executable code and / or data or write it to NVM 107 and / or RAM 108.

[0028] Interconnect 117 may include a bus or other suitable set of conductors and a bus controller (not shown) that can operate according to any suitable protocol. In this example, each of processor cores 101 to 104 can communicate with each other and with any of the other components 105 to 112, 118 via interconnect 117.

[0029] Analog-to-digital converter (ADC) 118 can receive analog information from on-chip or off-chip and can convert the analog information into digital data. For example, ADC 118 can convert analog input into digital data and then provide the digital data to another component (e.g., processor core 102) via interconnect 117. ECC engine 112 can perform error correction code (ECC) operation to support any of the various components of system 100.

[0030] Firewall circuitry 106 can be configured to perform the functions of access management circuitry. For example, firewall circuitry 106 may include hardware logic configured to assign priority access levels to and enforce these priority access levels among various components and processor cores 101 to 104. Enforcing priority access levels may, for example, include allowing or disallowing communication or actions based on priority access levels. Each of the different processor cores 101 to 104 and other components of system 100 may include hardware logic (not shown) configured to work with firewall circuitry 106 such that firewall circuitry 106 can manage and enforce assigned priority access levels. Firewall circuitry 106 may include a memory-mapped register (MMR) 114, to which firewall circuitry 106 can write data indicating priority access levels and access the data therefrom. Firewall circuitry 106 can communicate with other components of system 100 via interconnect 117 and also with processor core 101 via hardware signals on conductor 116.

[0031] Conductor 115 represents a conductor separate from interconnect 117 that carries hardware signals (e.g., sideband signals) from processor core 101 to Real-Time Address Translation (RAT) and Overlay (OVLY) (hereinafter, RAT) circuits 122 to 125. The following will discuss... Figure 3 As explained, processor core 101 can configure each of RAT circuits 122 to 125 based on the results of BIST operations.

[0032] BIST circuits 109 to 111 may include hardware or firmware logic for performing BIST operations on various components of system 100.

[0033] In this example, processor core 101 is configured to execute computer-executable code to perform the functions of security software 131. Security software 131 may include BIST management and correction, as described in more detail below. For example, security software 131 may manage the start and stop times of BIST components 109 to 111, receive the results of BIST operations from BIST components 109 to 111 (via interconnect 117), analyze the results of BIST operations, and perform correction actions in response to the results of BIST operations.

[0034] Various implementations can use any suitable BIST operation. In one example, PBIST circuit 111 can perform a BIST operation on a memory device such as RAM circuit 108. For example, PBIST circuit 111 may have a test pattern generation function, which can generate digital bit patterns and apply the patterns to the circuit under test (e.g., RAM circuit 108) via interconnect 117. For the purpose of testing RAM circuit 108, RAM circuit 108 may receive the bit patterns as part of a write operation, wherein it can write the bit patterns to one or more memory addresses, and then read the bit patterns back to PBIST circuit 111. PBIST circuit 111 can then compare the data read from RAM circuit 108 with a known test pattern, and then provide the test results to security software 131.

[0035] In another example, logic BIST 110 can be used to test flip-flops or other combinational logic, which may be present in any of various components, such as processor cores 101 to 104, DMA circuitry 105, interconnect 117, etc. For example, logic BIST 110 can use a test mode or other appropriate test to write data to combinational logic and then retrieve the data from the combinational logic under test. Logic BIST 110 can then compare the received data with the test mode and then provide the test result to security software 131.

[0036] In another example, the analog BIST 109 can perform BIST operations on an analog circuit system (such as ADC 118, a digital-to-analog converter (DAC, not shown)) or other peripheral devices that may have analog circuit systems. In the example where ADC 118 is the circuit under test, the analog BIST 109 can transmit a ramp signal or other suitable signal to ADC 118 and then receive the digital output from ADC 118. The analog BIST circuit 109 can compare the output of ADC 118 with the expected correct output and then transmit the test result to the security software 131.

[0037] The security software 131 can be configured to cause the BIST circuits 109 to 111 to perform BIST operations periodically or on demand. In some examples, the security software 131 can be configured to perform BIST operations multiple times per second during the runtime of the main application 132. The security software 131 can receive the results of the BIST operations and then perform correction actions as needed.

[0038] In this example, processor core 101 runs security software and does not run the main application 132. In other words, in this example, the execution of security software 131 is decoupled from processor core 101, while the execution of other applications can be decoupled from any one or more of processor cores 102 to 104. In this way, the execution of security software 131 may not consume processing capacity from other processor cores 102 to 104. Furthermore, although... Figure 1 The example only shows a single application 132 running on processor core 102. It should be understood that various embodiments may run any appropriate number of applications simultaneously on any of the processor cores 102 to 104.

[0039] Furthermore, various implementation schemes allow the security software 131 to perform corrective actions based on the results of the BIST operation, such as regarding Figures 3 to 6 To describe in more detail.

[0040] Figure 2 It is available according to some embodiments. Figure 1 An illustration of an example architecture for processor core 101 is provided. In this example, processor core 101 includes a dual-core lockstep component, illustrated by two separate cores 201 to 202. For example, cores 201 to 202 may have the same or similar hardware circuitry and may execute the same computer-executable code at each clock cycle. Furthermore, cores 201 to 202 may have the functionality to check the output of each of cores 201 to 202 to confirm that each of cores 201 to 202 is performing correctly. In some use cases, regulations, standards bodies, or contracts may require a dual-core lockstep architecture. However, the concepts of this disclosure are adaptable for use in processor cores with only a single core or with more than two cores.

[0041] Each of cores 201 to 202 may have less functionality than a general-purpose processor or a digital signal processor. For example, each of cores 201 to 202 may be a reduced instruction set computer, and in some cases may even be a functionally simplified version of a reduced instruction set computer. However, the scope of the implementation is suitable for using any suitable processor core as processor core 101.

[0042] In this example, each of cores 201 to 202 can independently execute code to provide the functionality of security software 131. Interconnect 204 may contain conductors and logic to communicatively couple cores 201 to 202 to other components. For example, tightly coupled memory (TCM) 205 may be configured to be accessible only by processor core 101 and not by other components. Figure 1 Other cores 102 to 104 access the system, at least during runtime. In some examples, at boot time, processor core 101 may read computer-executable code from memory circuitry 107 and then load that code into TCM 205. Processor core 101 (e.g., cores 201 to 202) may then access the computer-executable code from TCM 205 to run security software 131.

[0043] During the execution of security software 131, security software 131 may cause processor core 101 to access general-purpose timer 207, wherein security software 131 may use general-purpose timer 207 to time BIST operations of BIST circuits 109 to 111. Security software 131 may use watchdog timer 206 to confirm whether a BIST operation has not yet exceeded its timeout period or whether the time between BIST operations has not yet exceeded its timeout period.

[0044] MMR circuit 208 may be configured to store BIST operation results, failure codes for comparison with BIST operation results, and component status (operable, idle), etc. MMR circuit 208 may contain memory addresses that can be mapped for use by cores 201 to 202 and other cores 102 to 104 of system 100.

[0045] Event scheduler 209 may include hardware or firmware logic that can read control signals (e.g., BIST_REQ) from MMR circuit 208 and write control signals to the MMR circuit, and can also transmit and receive the control signals to manage BIST operation. In other words, security software 131 may be configured to use event scheduler 209 to transmit signals to BIST circuits 109 to 111 to start BIST operation, stop BIST operation, and receive signals from BIST circuits 109 to 111. (Regarding...) Figures 4 to 6 Describe the control signals in more detail.

[0046] Event scheduler 209 can communicate with BIST circuits 109 to 111 via interconnects 204 and 117 and / or on conductors separate from interconnects 204 and 117. Processor core 101 also includes an interrupt controller 203, which can be configured to communicate with other processor cores 102 to 104. For example, upon encountering a BIST operation result, security software 131 can immediately generate an interrupt for one or more of the other processor cores 102 to 104. Interrupt controller 203 can communicate with other processor cores 102 to 104 as needed via interconnects 204 and 117 or through some other conductor.

[0047] Figure 3 According to some embodiments Figure 1 A diagram illustrating an example architecture of the RAT circuit 122. Furthermore, although... Figure 3 The description is for RAT circuit 122, but it should be understood that the architecture and operation can be applied to any RAT circuit, such as Figure 1 Any one of 122 to 125.

[0048] RAT circuitry 122 can be configured to intercept transactions to and from processor core 102, enabling address translation logic 301 to parse address data and, where appropriate, modify the address data based on one or more zone configurations 302. RAT circuitry 122 can translate addresses destined for RAM circuitry 108, NVM 107, memory-mapped peripherals, and other destinations within or coupled to system 100. In one example use case, security software 131 can determine that a specific address range within RAM circuitry 108 is defective. In response, security software 131 can set zone configuration 302 such that addresses are changed from defective addresses to addresses specified in zone configuration 302.

[0049] For example, if security software 131 determines that the address range AAAA-BBBB is defective within RAM circuit 108, then security software 131 can determine to use another address range within RAM circuit 108, such as the address range CCCC-DDDD. Security software 131 can write to the zone configuration 302 using sideband signals on conductor 115. The input address field can identify the malfunctioning address range by its start address AAAA, the output address field can identify the substituted address range by its start address CCCC, and the zone size field can identify the size of the substituted address range or the malfunctioning address range. In other words, the address range is obtained by adding the zone size to the start address. The zone control field can specify whether the zone configuration 302 is valid and available.

[0050] Address translation logic 301 may receive an address on an incoming transaction from processor core 102, wherein the address may be associated with a read operation, a write operation, or some other appropriate operation. Address translation logic 301 may analyze the incoming transaction to determine whether the address data of the transaction falls within a malfunctioning address range. If the address data of the transaction does not fall within a malfunctioning address range, then address translation logic 301 may output the transaction as an outgoing transaction without modifying the address data. However, if the address data of the transaction does fall within a malfunctioning address range, then address translation logic 301 may output the transaction as an outgoing transaction by modifying the address data to an address within the replaced address range.

[0051] although Figure 3 Only one zone configuration 302 is shown, but it should be understood that any appropriate number of zone configurations may be included in a given RAT circuitry 122 to 125, some of which may be valid or invalid. Furthermore, security software 131 running on processor core 101 may configure zone configuration 302 in response to the results of a BIST operation. In one example, security software 131 may request access from firewall circuitry 106 to write to zone configuration 302. Firewall circuitry 106 may include hardware logic configured to allow processor core 101 to write to RAT circuitry 122 when appropriate. Therefore, firewall circuitry 106 may then change the priority access state of processor core 101 to allow processor core 101 to write to RAT circuitry 122. For example, firewall circuitry 106 may include authorization to allow data as part of MMR circuitry 114 and allow access to MMR circuitry 114 via conductor 116. Any of the processor cores 101 to 104 and the DMA circuit 105 may be able to read the contents of the MMR circuit 114 to determine whether the processor core 101 has priority access to write to one of the RAT circuits 122 to 125.

[0052] Assuming processor core 101 is granted priority access to write to RAT circuitry 122, security software 131 can then write to fields of zone configuration 302 (or another zone configuration, not shown) to identify malfunctioning address ranges and alternative address ranges. As noted above, in some examples, conductor 115 may be decoupled from interconnect 117 and may carry sideband signals. In other words, processor core 101 can use sideband signals instead of in-band signals to write to fields in the zone configuration. However, other implementations can use any suitable technique to configure the zone configuration.

[0053] Figure 4This is an illustration of an example method 400 that can be executed by processor core 101 when it runs security software 131, according to some embodiments. Method 400 is an example method applicable to a single BIST operation. It should be understood that method 400 can be executed for each appropriate BIST operation in system 100. For example, for a particular BIST operation to be executed by analog BIST circuit 109, security software 131 can execute an instantiation of method 400, and for a particular BIST operation to be executed by PBIST circuit 111, security software 131 can execute another instantiation of method 400, and various instantiations of method 400 can be executed simultaneously.

[0054] At action 402, security software 131 may check general-purpose timer 207 to determine if it is time to perform the BIST operation. Action 402 may be performed every clock cycle, every X clock cycles (where X is an appropriate integer), or at another appropriate time. If the value of general-purpose timer 207 does not indicate that it is time to perform the BIST operation, then action 402 may be repeated. If it is time to perform the BIST operation, then method 400 moves to action 404, where event scheduler 209 asserts the BIST_REQ signal on interconnect 117. In this example, the BIST_REQ signal contains an identifier [comp_id] that identifies a specific component of the tested component for the BIST operation.

[0055] Other processor cores 102 to 104 and DMA circuit 105 can receive signals on interconnect 117 and then respond with an acknowledgment signal BIST_ACK[comp_id], which is received by event scheduler 209. Each of processor cores 102 to 105 and DMA circuit 105 can execute any part of the code that requires the use of the identified component after receiving BIST_REQ, and then respond with an acknowledgment signal.

[0056] Once a suitable acknowledgment signal has been received, the security software 131 can then use the event scheduler 209 at action 408 to assert the BIST_IN_PRG[comp_id] signal on interconnect 117. As long as the BIST_IN_PRG[comp_id] signal is high, other processor cores 102 to 104 and DMA circuitry 105 are configured to treat the identified component as unavailable. Action 408 may also include revoking the assertion of the BIST_REQ signal. In some examples, action 408 may also include the security software 131 writing a device state (e.g., idle) to MMR circuitry 208 to indicate that a particular component is unavailable.

[0057] BIST circuits 109 to 111 can be configured to analyze BIST signals from event scheduler 209 and perform BIST operations as appropriate. For example, if the BIST_IN_PRG[comp_id] signal identifies ADC 118, then analog BIST circuit 109 can be configured to begin BIST operations for ADC 118 immediately upon receiving the signal. Similarly, other BIST circuits 110 to 111 can be configured to ignore the BIST_IN_PRG[comp_id] signal if they identify a component that cannot be tested by the BIST circuit. If the BIST_IN_PRG[comp_id] signal identifies RAM circuit 108, then PBIST circuit 111 can be configured to begin BIST operations immediately upon receiving the signal, while other BIST circuits 109 to 110 can be configured to ignore the signal. If the BIST_IN_PRG[comp_id] signal identifies combinational logic, then logic BIST110 can be configured to begin BIST operation on the identified component, while other BIST circuits 109 and 111 can be configured to ignore the signal.

[0058] In this example, while security software 131 waits at action 410 for the BIST_DONE signal to be received by event scheduler 209, the appropriate BIST circuits 109, 110, or 111 can then perform a BIST operation on the identified component. Once the appropriate BIST circuit has completed its BIST operation, it can assert the BIST_DONE signal received by event scheduler 209.

[0059] In this example, each of the BIST circuits 109 to 111 can be configured to generate a BIST_FAIL signal in response to a component failing the BIST operation. Alternatively, each of the BIST circuits 109 to 111 can be configured to indicate that a component has successfully passed the BIST operation by asserting the BIST-DONE signal without asserting the BIST_FAIL signal.

[0060] If security software 131 determines at action 412 that the BIST_FAIL signal has not yet been received, then security software 131 may then proceed to action 416. At action 416, security software 131 causes event scheduler 209 to rescind the assertion of the BIST_IN_PROG signal, thereby freeing the component for use by other processor cores 102 to 104 and DMA circuitry 105. In some examples, action 416 may also include security software 131 writing device state (e.g., operable) to MMR circuitry 208 to indicate that a particular component is available. Action 416 may also include security software 131 refreshing its counters for the next scheduled BIST operation.

[0061] However, in this example, if security software 131 determines that event scheduler 209 has received the BIST_FAIL signal at action 412, then security software 131 may then proceed to action 414. Action 414 may include security software 131 writing to MMR circuitry 208 to indicate a failure and a failure code, wherein the failure code may be received along with the BIST_FAIL signal. Security software 131 may also cause event scheduler 209 to rescind the assertion of the BIST_IN_PROG signal. Furthermore, security software 131 may also cause interrupt controller 203 to generate an interrupt for one or all of the appropriate processor cores 102 to 104 and DMA circuitry 105. The interrupt may indicate device unavailability for a device that has not passed BIST operation. One or all of the appropriate processor cores 102 to 104 and DMA circuitry 105 may then take appropriate action in response to receiving the interrupt. Figure 6 Describe the interruption in more detail.

[0062] Action 414 may also include performing a calibration action. For example, security software 131 may compare the failure code in the BIST_FAIL signal with a failure code stored in MMR circuit 208. For example, MMR circuit 208 may contain multiple failure codes mapped to appropriate calibration actions, and security software 131 may use the received failure code as a key within MMR circuit 208 to determine the appropriate calibration action. Once the appropriate calibration action has been performed by security software 131, security software 131 may then indicate the availability of the component as appropriate, for example, by writing the device state (e.g., operability) to MMR circuit 208, generating an interrupt, or using other techniques. Figures 5 to 6 Describe an example correction action.

[0063] Figure 5 This is an illustration of an example method 500, which can be executed by security software 131 running on processor core 101 according to some embodiments. Method 500 illustrates an example of controlling a BIST operation to be performed on RAM circuitry 108 and performing a correction action based on the result of the BIST operation.

[0064] At action 502, security software 131 can cause PBIST circuit 111 to perform a BIST operation on RAM circuit 108. For example, as described above with respect to method 400, security software 131 can cause event scheduler 209 to issue appropriate signals and can also write appropriate operating states (e.g., idle) to MMR circuit 208.

[0065] At action 504, the security software 131 determines whether the RAM circuit 108 has successfully passed the BIST operation (e.g., no address range failure). For example, in the example of method 400, receiving the BIST_DONE signal but not the BIST_FAIL signal indicates that the RAM circuit 108 has successfully passed. On the other hand, receiving the BIST_FAIL signal indicates that the RAM circuit 108 has failed (e.g., exhibiting some malfunction in one or more address ranges).

[0066] If the security software 131 determines that the RAM circuit 108 has successfully passed the BIST operation, then the security software 131 may move to action 506. Action 506 may include refreshing the counter to wait for another BIST operation, jumping to the next test, or other appropriate actions.

[0067] If security software 131 determines at action 504 that RAM circuitry 108 has failed, then event scheduler 209 may have received a BIST_FAIL signal with a failure code and may have stored the failure code in MMR circuitry 208. Security software 131 may then move to action 508 in response to the BIST operation result. Action 508 may include recording the BIST operation result to another component, such as memory circuitry 107 or other suitable storage device.

[0068] Security software 131 may further proceed to action 510 in response to a malfunction in the BIST operation result indication function or otherwise indicating a failed BIST operation. Action 510 may include security software 131 clearing the error address buffer (not shown) in processor core 101 and further performing a correction action. Performing the correction action may include programming RAT circuitry, such as the one described above. Figure 3 The RAT circuit discussed. In this example, the security software 131 can write to the zone configuration in the RAT circuit at the processor core or DMA circuit, rather than performing memory repair directly on the RAM circuit 108.

[0069] Although not shown in method 500, the correction action may further include writing the appropriate component state (e.g., operable) to release system 100 for normal use of RAM circuit 108.

[0070] Furthermore, method 500 may include any appropriate programming of the RAT circuit (e.g., RAT circuit 122). For example, Figure 3The examples illustrate replacing a malfunctioning address range with an alternative address range of the same size. However, some embodiments may replace a malfunctioning address range or multiple malfunctioning address ranges with memory blocks or multiple memory blocks that may be larger than the overall malfunctioning address range. For example, one embodiment may include activating a previously deactivated RAM group and using the activated RAM group for transactions that would otherwise point to the malfunctioning address range. Using the activated RAM group may include appropriately programming RAT circuitry.

[0071] Furthermore, the correction action for RAM circuit 108 may include handling multiple different malfunctioning address ranges in different ways. For example, an address range of size X may malfunction, and an address range of size Y may also malfunction, and the security software 131 may assign alternative address ranges of different sizes as needed. In fact, the scope of the implementation may include programming the RAT circuitry in any appropriate manner to resolve malfunctioning address ranges.

[0072] In yet another example, security software 131 may determine that there is no available alternative memory space as much or more as the malfunctioning memory space. In such an example, security software 131 may cause interrupt controller 203 to generate an interrupt signal to one (or all) of the appropriate processor cores 102 to 104 and DMA circuitry 105. The interrupt signal may cause the appropriate software or firmware to operate in limp mode.

[0073] Figure 6 This is an illustration of an example method 600, according to some embodiments, that can be executed by security software 131 running on processor core 101. In this example, method 600 can be used to resolve a malfunction detected relative to an analog component. For example, analog BIST circuitry 109 can perform BIST operation on an ADC or DAC or some other analog device, and method 600 illustrates how the success or failure of said device can be resolved.

[0074] At action 602, the security software 131 causes the BIST operation to be carried out by the BIST circuitry (in this case, the ADC) on the analog component. The security software 131 can cause the transmission and reception of appropriate signals and can cause the preservation of appropriate component states, such as those mentioned above. Figure 4 As described.

[0075] At action 604, the security software 131 receives the result of the BIST operation and determines whether the ADC has passed or failed. For example, as mentioned above... Figure 4 As described, the BIST_FAIL signal indicates a malfunction and may be accompanied by a failure code. On the other hand, the BIST_DONE signal, which does not have a BIST_FAIL signal, indicates that the component has passed successfully (e.g., no malfunction).

[0076] Assuming the component has passed, security software 131 may move to action 606, which may include waiting or jumping to the next BIST operation, such as returning to action 602 or performing a different BIST operation. Alternatively, if security software 131 determines at action 604 that the component has failed, then security software 131 may move to one or more of actions 612, 618, 622, or 628. In one example, actions 612, 618, 622, and 628 represent failure codes, which may be stored in MMR circuit 208 and searched by security software 131 using the received failure codes as search terms or keys. Continuing the example, each of subsequent actions 614, 620, 624, 630, and 626 may be a corrective action that can be associated with a failure code in MMR circuit 208.

[0077] If the failure code corresponds to a malfunction of the high integral nonlinearity (INL) and high differential nonlinearity (DNL) at action 612, then the corresponding correction action may include readjusting the capacitors of the ADC at action 614. The safety software 131 may perform the readjustment operation on the capacitors and then test the ADC again at action 616.

[0078] If the failure code at action 618 corresponds to a high INL and low DNL malfunction, then the corresponding correction action may include calibration of some components of the ADC. For example, safety software 131 may perform recalibration of the filter or low-frequency subcircuit at action 620. Once action 620 has been performed, safety software 131 may retest the ADC at action 616.

[0079] After action 616, action 608 may be used to check whether the retest resulted in a successful pass or failure (e.g., malfunction). If the BIST result indicates a failure, then safety software 131 may move to action 610, which may include an indication of unavailability of the component under test (ADC). Safety software 131 may indicate unavailability by, for example, generating an interrupt by interrupt controller 203 to be received by one (or all) of the appropriate processor cores 102 to 104 and DMA circuitry 105.

[0080] Returning to action 608, if the BIST operation result indicates that the tested component has passed, then security software 131 can move to action 606.

[0081] If the failure code at action 622 corresponds to a dynamic error (e.g., a non-repeating bit flip), then the corresponding corrective action may include reconfiguring the component under test (BAT) to operate at a lower sampling rate at action 624. For example, security software 131 may include functionality to reprogram the settings of the BAT at action 624. If the failure code corresponds to the number of significant bits (ENOB) at action 628, then the corresponding corrective action may include reconfiguring the BAT to operate at a lower resolution. For example, security software 131 may include functionality to reprogram the settings of the BAT at action 630. In other words, if a setting (e.g., sampling rate or resolution) is detected to cause a first-level malfunction, then security software 131 may reprogram the settings of the BAT to a lower level.

[0082] In this example, security software 131 may proceed to action 626 after any or both of actions 624 and 630. Action 626 may include generating an interrupt via interrupt controller 203 to an appropriate one (or all) of processor cores 102 to 104 and DMA circuitry 105. The appropriate one (or all) of processor cores 102 to 104 and DMA circuitry 105 may then respond to the interrupt by, for example, by changing software or firmware settings to accommodate a lower sampling rate and / or lower resolution.

[0083] Following actions 624 and 630, security software 131 may then proceed to actions 616, 608, 610 and / or 606 (as described above).

[0084] One advantage of some implementations is that the security software 131 running on processor core 101 can execute methods 400, 500, and 600 during the runtime of the main application 132 on processor core 102. Therefore, in the example of system 100, the main application 132 does not compete for processing power with the security software 131. Another advantage of some implementations is that some detected malfunctions can be corrected during the runtime of the main application 132 on processor core 102, thereby allowing continued operation and, in some cases even extending lifespan by preventing system 100 from becoming obsolete.

[0085] In addition, although Figures 5 to 6Examples involve corrective actions that can be taken for RAM and analog components, but the scope of the implementation may include any corrective actions to be performed on components in response to a BIST operation. For example, if combinational logic circuitry fails to pass a BIST operation performed by logic BIST circuitry 110, security software 131 may indicate the unavailability of the combinational logic circuitry. For example, security software 131 may generate an interrupt. The interrupt may cause one (or all) of the appropriate processor cores 102 to 104 and DMA circuitry 105 to operate in limp mode.

[0086] This document uses the term "semiconductor die". A semiconductor device can be a discrete semiconductor device, such as a bipolar transistor, a plurality of discrete devices, such as a pair of power FET switches fabricated together on a single semiconductor die, or a semiconductor die can be an integrated circuit having multiple semiconductor devices (e.g., multiple capacitors in an ADC). A semiconductor device can include passive devices (e.g., resistors, inductors, and filters), sensors, and / or active devices such as transistors. A semiconductor device can be an integrated circuit having hundreds or thousands of transistors coupled to form functional circuitry, such as a microprocessor or memory device. A semiconductor device may also be referred to herein as a semiconductor device or an integrated circuit (IC) die.

[0087] This document uses the term "semiconductor package". A semiconductor package has at least one semiconductor die electrically coupled to terminals and a package body that protects and covers the semiconductor die. In some arrangements, multiple semiconductor dies may be packaged together. For example, a power metal-oxide-semiconductor (MOS) field-effect transistor (FET) semiconductor device and a second semiconductor device (e.g., a gate driver die or a controller die) may be packaged together to form a single packaged electronic device. Additional components, such as passive components (e.g., capacitors, resistors, and inductors or coils), may be included in the packaged electronic device. The semiconductor die is mounted on a package substrate that provides conductive leads. A portion of the conductive leads forms terminals for the packaged device. In wire bonding integrated circuit packages, bonding wires couple the conductive leads of the package substrate to bonding pads on the semiconductor die. The semiconductor die may be mounted to the package substrate with the device-side surface facing away from the substrate and the back-side surface facing the die pads of the package substrate and mounted to said die pads. Semiconductor packages may have a package body formed from a thermosetting epoxy molding compound in a molding process or by using an epoxy resin, plastic, or resin that is liquid at room temperature and subsequently cures. The package body provides a hermetically sealed enclosure for use in a packaged device. The package body may be formed in a mold using an encapsulation process; however, a portion of the leads of the package substrate is not covered during encapsulation, and these exposed lead portions form terminals for the semiconductor package. Semiconductor packages may also be referred to as “integrated circuit packages,” “microelectronic device packages,” or “semiconductor device packages.”

[0088] Although various examples of this disclosure have been described above, it should be understood that they are presented by way of example only and not by way of limitation. Many changes may be made to the disclosed examples in accordance with the disclosure herein without departing from the spirit or scope of this disclosure. Modifications to the described examples are possible within the scope of the claims, and other examples are also possible. Therefore, the breadth and scope of the invention should not be limited to any of the examples described above. In fact, the scope of this disclosure should be defined by the appended claims and their equivalents.

Claims

1. A method comprising: Execute computer-executable code for a first application, wherein the first application includes receiving data from hardware components of a computer system on which the first application runs; Simultaneously with the execution of the computer-executable code for the first application, computer-executable code for the second application is executed, which causes the built-in self-test BIST operation to run on the hardware component. as well as The hardware components are corrected based on the results of the BIST operation through the second application and during the runtime of the first application.

2. The method of claim 1, wherein receiving data from the hardware component comprises performing a read operation on the random access memory (RAM) circuitry.

3. The method of claim 2, wherein performing the correction action comprises: Configure the address translation circuit of the processor core configured to run the first application, wherein configuring the address translation circuit includes causing the address translation circuit to translate the address in the read operation based on the BIST operation.

4. The method of claim 1, wherein receiving data from the hardware component comprises receiving data from an analog-to-digital converter (ADC).

5. The method of claim 4, wherein performing the correction action comprises: The capacitor of the ADC is fine-tuned based on the result of the BIST operation.

6. The method of claim 4, wherein performing the correction action comprises: This causes the ADC to operate at a sampling rate lower than that indicated by the BIST operation, resulting in a malfunction, and transmits an interrupt signal to the processor core running the first application to indicate the correction action.

7. The method of claim 4, wherein performing the correction action comprises: This causes the ADC to operate at a resolution lower than that indicated by the BIST operation, resulting in a malfunction, and transmits an interrupt signal to the processor core running the first application to indicate the correction action.

8. The method of claim 1, wherein performing the correction action comprises: transmitting an interrupt signal to the processor core running the first application to indicate a limp operation mode of the first application.

9. A system comprising: First processor core; Second processor core; as well as Address translation circuitry coupled between the second processor core and memory circuitry, wherein the address translation circuitry is configured to translate the address of the memory circuitry in transactions originating from the second processor core; The first processor core is configured to change the settings of the address translation circuit via hardware signals to configure the address translation circuit to translate addresses during the runtime of the application by the second processor core.

10. The system of claim 9, further comprising: An access management circuit coupled to the first processor core and the second processor core, wherein the access management circuit is configured to authorize access to the first processor core to change the settings of the address translation circuit.

11. The system of claim 9, wherein the first processor core includes a dual-core lockstep assembly.

12. The system of claim 9, further comprising: An interconnect configured to couple the second processor core to the memory circuit, wherein the second processor core is configured to access the memory circuit via the interconnect for transactions originating from the second processor core, and further wherein the first processor core is configured to transmit the hardware signals on a conductor separate from the interconnect.

13. The system of claim 9, wherein the first processor core is configured to: execute computer-executable code such that the first processor core causes a test to run on the memory circuit; receive the result of the test; and change the settings of the address translation circuit in response to the result of the test.

14. The system of claim 9, wherein the second processor core is configured to run the application, and wherein the application is associated with the transaction from the second processor core, further wherein the first processor core is configured to run another application, the other application causing the first processor core to change the settings of the address translation circuit via the hardware signal, further wherein the runtime of the application overlaps with the runtime of the other application.

15. The system of claim 14, wherein the first processor core includes tightly coupled memory circuitry, wherein the tightly coupled memory circuitry is configured to store computer-executable code of the other application, and wherein the second processor core is configured to load the computer-executable code into the tightly coupled memory circuitry during system startup.

16. An integrated circuit IC, comprising: First processor core; Second processor core; A hardware module coupled to the first processor core and configured to transfer data to the first processor core during the runtime of a first application, the first application running on the first processor core; as well as A tightly coupled memory (TCM) circuit is disposed within the second processor core and configured to store computer-executable code for built-in self-test BIST management software, wherein the BIST management software is configured to perform BIST operations on the hardware module during the runtime of the first application.

17. The IC of claim 16, wherein the TCM circuitry is further configured to store computer-executable code for performing correction actions on the hardware module in response to the BIST operation and during the runtime of the first application.

18. The IC of claim 17, wherein the hardware module includes an analog-to-digital converter (ADC), and wherein the computer-executable code for performing the calibration action includes computer-executable code for performing calibration or fine-tuning operations on the ADC.

19. The IC of claim 17, wherein the hardware module includes an analog-to-digital converter (ADC), and wherein the computer-executable code for performing the correction action includes computer-executable code for reducing the resolution or sampling rate of the ADC.

20. The IC of claim 17, wherein the hardware module includes a random access memory (RAM) circuit, and wherein the first processor core includes a real-time address translation circuit configured to translate addresses within the RAM circuit for transactions from the RAM circuit, and wherein the computer-executable code for performing the correction action includes computer-executable code for configuring the real-time address translation circuit.

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