A method and system for automated chip testing and troubleshooting
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-03-30
- Publication Date
- 2026-08-14
Smart Images
Figure CN122570253A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of chip testing technology, specifically relating to a method and system for troubleshooting automated chip testing anomalies. Background Technology
[0002] Currently, commonly used automated chip testing platforms can generally monitor the yield rate and failure rate of different categories of products online. However, when testing is interrupted due to anomalies, the typical approach is to pause testing – wait for engineers to analyze the anomaly – engineers determine the cause of the anomaly – attempt to debug and resolve the anomaly – and then resume testing after the anomaly is resolved. In this process, the automated testing equipment only provides engineers with the storage of test data and sample statistics; it cannot assist engineers in determining the location and cause of the anomaly. Furthermore, engineers' ability to find and resolve anomalies depends on their individual skills and experience, often making it difficult to quickly and accurately pinpoint the cause, and sometimes even failing to identify the cause altogether. Therefore, more automated methods are needed to help engineers analyze and interpret data, enabling them to locate the problem's location and cause more quickly and accurately. Summary of the Invention
[0003] The technical problem solved by this invention is to provide a method and system for troubleshooting chip automated testing anomalies, which can effectively narrow the scope of engineers' troubleshooting, improve the efficiency of handling test anomalies, reduce the error rate of human judgment, and shorten the anomaly processing time.
[0004] Technical Solution: To solve the above-mentioned technical problems, the present invention adopts the following technical solution:
[0005] A method for automated chip testing anomaly troubleshooting includes the following steps:
[0006] S1. Record the Z pins related to all test items of the chip, and record the total number of times each pin appears after one test process of the chip, respectively denoted as Pin1_total, Pin2_total up to PinZ_total;
[0007] S2. When the automated chip test is paused due to yield alarm, the test data of N chips are loaded backward from the test data of the last chip, and the acquired test data is identified as the test anomaly section.
[0008] In the test data of S3 and N chips, for each failure test item, the count of all pins corresponding to that test item is incremented by one. After reviewing the entire test abnormality occurrence section, the number of times each pin appears is defined as the failure association number, which is recorded as Pin1_fail, Pin2_fail up to PinZ_fail.
[0009] S4. The ratio of the number of failure associations to the total number of failures is defined as the potential risk rate, denoted as α, i.e.:
[0010]
[0011] In the formula, i represents the i-th pin, i = (1, 2, ..., Z), α i This represents the potential risk rate of the i-th pin, and N represents the number of chips loaded with test data.
[0012] S5. Arrange the Z pins in descending order of potential risk rate.
[0013] Preferably, in step S2, test data is loaded backward from the test data of the last chip until the test yield of nearly M chips is higher than the current yield, and test data of N chips are loaded in total, where N≥M.
[0014] Preferably, M≥50.
[0015] Preferably, M is calculated using the following formula:
[0016]
[0017] In the formula, the target yield is a preset yield value, where 98% ≤ target yield < 100%.
[0018] Preferably, the yield alarm in S2 is achieved by setting a threshold for the real-time yield lower limit of chip testing and the yield lower limit of the test of the last B chips. When the actual yield of chip testing or the yield of the test of the last B chips is lower than the set threshold, the test will be interrupted.
[0019] Preferably, B ≥ 50.
[0020] This invention also provides a chip automated test anomaly troubleshooting system for implementing the above-mentioned chip automated test anomaly troubleshooting method, comprising:
[0021] Test database: Raw test data automatically stored on the server during the testing process;
[0022] Data access module: responsible for receiving data from the test database and converting its format;
[0023] Data caching: caching the raw data received;
[0024] Data filtering: Filter out valid data based on the abnormal data filtering method;
[0025] Valid data pool: Valid data that has been filtered out and is ready for processing;
[0026] Chip information database: Loads chip pins and test plans;
[0027] Data processing module: Retrieves data from the valid data pool and performs logical processing;
[0028] Feature data extraction: Extracting potential risk rates;
[0029] Results Displayer: Shows the magnitude of risk for each pin in sequence.
[0030] Beneficial effects: Compared with the prior art, the present invention has the following advantages:
[0031] 1. By statistically analyzing the occurrence frequency of relevant pins in failure test items and ranking them by potential risk rate, the pins with the highest potential risk are also the most likely to fail. Staff can check them in order, and targeted checks help improve the efficiency of anomaly detection.
[0032] 2. It can quickly locate the location and cause of anomalies after they occur in automated testing, helping engineers to find and solve problems as soon as possible and resume automated testing. Therefore, it can quickly resolve test anomalies and improve the intelligence and efficiency of automated testing. Attached Figure Description
[0033] Figure 1 This is a schematic diagram of the method flow of an embodiment of the present invention;
[0034] Figure 2 This is a schematic diagram of the system structure according to an embodiment of the present invention. Detailed Implementation
[0035] The present invention will be further illustrated below with reference to specific embodiments. These embodiments are implemented based on the technical solutions of the present invention, and it should be understood that these embodiments are only used to illustrate the present invention and are not intended to limit the scope of the present invention.
[0036] Example
[0037] like Figure 1 As shown, a method for automated chip testing anomaly troubleshooting includes the following steps:
[0038] S1. Record the Z pins related to all test items of the chip, and record the total number of times each pin appears after one test process of the chip, respectively denoted as Pin1_total, Pin2_total up to PinZ_total;
[0039] In this embodiment, the preliminary preparation work includes creating a test plan and a pin map in the chip's specifications. This determines which chip pins are associated with each test item, continuing until all Z pins related to each test item are recorded, forming a product information table. Based on this table, the total number of times each pin appears after one test cycle is recorded, denoted as Pin1_total, Pin2_total, up to PinZ_total. Taking an RF front-end chip from Company A as an example, its test items include open / short circuit, quiescent current, operating current, leakage current, gain, harmonics, and vector amplitude error. There are 5 power supply pins, 11 ground pins, and 22 I / O pins, Z = 5 + 11 + 22. The pins associated with each test item are recorded in the table. Taking leakage current as an example, all associated pins for each test are sequentially recorded in the product information table. Table 1 is a selected portion of the product information table, where Test_No. represents the serial number of the test item, Test_Item represents the name of the test item, Related Pins represents the pins involved in the test item (determined according to TestPlan), and Leakage_3.4V represents the test item: leakage current.
[0040] Table 1: Selected portion of the product information table
[0041]
[0042] The leakage current test item is associated with Pin8, Pin28, Pin29, and Pin30, meaning the number of times each of Pin8, Pin28, Pin29, and Pin30 appears is incremented by one. After one test cycle of this RF front-end chip, the total number of times each pin appears is recorded as Pin1_total, Pin2_total, up to PinZ_total.
[0043] S2. When the automated chip test is paused due to yield alarm (the automated test platform will set a threshold for the real-time yield of chip testing and the yield of the last 100 chips; if the actual yield of chip testing or the yield of the last 100 chips is lower than the threshold set by the machine, the test will be interrupted), test data is loaded backward from the test data of the last chip until the yield of the last M chips is higher than the current yield (test data is loaded backward until M consecutive Pass products appear (it is determined that the abnormal segment data has been captured at this time, and the normal test segment is entered), set M=1 / (1-target yield), for example, if the target yield is 98%, then M=1 / (1-0.98)=50, that is, if 50 consecutive Pass products are captured, the data capture will stop), a total of N chip test data are loaded, N≥M, M≥50, and the acquired test data segment is identified as the test abnormality segment;
[0044] In this embodiment, when the chip automated testing equipment alarms due to abnormal yield and suspends testing, it begins to investigate the anomaly. It selects the test data document and the corresponding product information table where the anomaly occurred, and automatically analyzes and captures the data segment. The method is to load the test data from the last chip back to the beginning, until the test yield of nearly one hundred chips is higher than the current yield, and the captured test data segment is identified as the test anomaly occurrence segment.
[0045] In the test data of S3 and N chips, for each failure test item, the count of all pins corresponding to that test item is incremented by one. After reviewing the entire test abnormality occurrence section, the number of times each pin appears is defined as the failure association number, which is recorded as Pin1_fail, Pin2_fail up to PinZ_fail.
[0046] In this embodiment, in the test data of the last to last pin (denoted as N) of the test anomaly occurrence segment, for each failure test item that occurs, i.e. the test data is not within the test threshold range (limits, i.e. the upper and lower limits set for the test item, such as the leakage current Leakage_icc of VCC, the upper limit is 1uA and the lower limit is 0uA. If the measured value is 1.5uA, it is not within this test threshold, which means that the test item fails), the count of all pins corresponding to the test item is incremented by one. After reviewing the entire data segment, the number of times each pin appears is defined as the failure association count, which is recorded as Pin1_fail, Pin2_fail up to PinZ_fail. If the Leakage_3.4V test data in Table 1 is not within the threshold, then Pin8, Pin28, Pin29, and Pin30 are each counted as one failure. That is, the Pin8_fail count is incremented by one, the Pin28_fail count is incremented by one, the Pin29_fail count is incremented by one, and the Pin30_fail count is incremented by one. After reviewing the entire data segment, the number of times each pin appears is defined as the failure association count, which is recorded as Pin1_fail, Pin2_fail, up to PinZ_fail.
[0047] S4. The ratio of the number of failure associations to the total number of failures is defined as the potential risk rate, denoted as α, i.e.:
[0048]
[0049] In the formula, i represents the i-th pin, i = (1, 2, ..., Z), α i This represents the potential risk rate of the i-th pin, and N represents the number of chips loaded with test data.
[0050] After calculating for all pins, the potential risk rates α1, α2, and α3 for each pin are obtained. i , ..., αz .
[0051] S5. Arrange the Z pins in descending order of potential risk rate.
[0052] The potential risk rates of all pins are sorted from highest to lowest and displayed on the results interface. The pins with the highest potential risk are also the most likely to fail. Engineers can significantly improve the efficiency of troubleshooting by checking in order, and can conduct targeted troubleshooting.
[0053] like Figure 2 As shown, this embodiment also provides a chip automated test anomaly troubleshooting system, used to implement the chip automated test anomaly troubleshooting method of this embodiment, including:
[0054] Test database (server): Raw test data automatically stored on the server during the test;
[0055] Data access module: responsible for receiving data from the database and converting it into CSV format that the system (the operating system that accompanies the automated testing platform, such as IG-XL on the J750 platform or iTest on the NOVA platform) can recognize;
[0056] Data caching: caching the raw data received;
[0057] Data filtering: Valid data is filtered out according to the abnormal data filtering method (i.e., in step S2, test data is loaded from the last chip's test data backwards until the test yield of nearly M chips is higher than the current yield, and the captured test data is identified as the test abnormality segment).
[0058] Valid data pool: Valid data that has been filtered out and is ready for processing;
[0059] Chip Information Database: A chip information database that integrates chip pins and test plans (referring to the chip's test plan and pin definition diagram in the datasheet).
[0060] Data processing module: Obtains data from the "effective data pool" and performs logical processing (i.e., S2-S5 in the "chip information database") based on the rules and knowledge in the "chip information database" (i.e., determining which chip pins are associated with each test item in the method of this embodiment, until all Z pins related to the test items are recorded to form a product information table, and recording the total number of times each pin appears after one test process based on the product information table).
[0061] Feature data extraction: Extracting the most critical feature information, namely the potential risk rate;
[0062] Results Display: Shows the risk level of each pin in sequence.
[0063] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.
Claims
1. A method for automated chip testing anomaly troubleshooting, characterized in that, Includes the following steps: S1. Record the Z pins related to all test items of the chip, and record the total number of times each pin appears after one test process of the chip, respectively denoted as Pin1_total, Pin2_total up to PinZ_total; S2. When the automated chip test is paused due to yield alarm, the test data of N chips are loaded backward from the test data of the last chip, and the acquired test data is identified as the test anomaly section. In the test data of S3 and N chips, for each failure test item, the count of all pins corresponding to that test item is incremented by one. After reviewing the entire test abnormality occurrence section, the number of times each pin appears is defined as the failure association number, which is recorded as Pin1_fail, Pin2_fail up to PinZ_fail. S4. The ratio of the number of failure associations to the total number of failures is defined as the potential risk rate, denoted as α, i.e.: ； In the formula, i represents the i-th pin, i = (1, 2, ..., Z), α i This represents the potential risk rate of the i-th pin, and N represents the number of chips loaded with test data. S5. Arrange the Z pins in descending order of potential risk rate.
2. The chip automated testing anomaly troubleshooting method according to claim 1, characterized in that, In step S2, test data is loaded backward from the test data of the last chip until the test yield of nearly M chips is higher than the current yield, and test data of N chips are loaded in total, where N≥M.
3. The chip automated testing anomaly troubleshooting method according to claim 2, characterized in that, M≥50。 4. The chip automated testing anomaly troubleshooting method according to claim 2, characterized in that, M is calculated using the following formula: ； In the formula, the target yield is a preset yield value, where 98% ≤ target yield < 100%.
5. The chip automated testing anomaly troubleshooting method according to claim 1, characterized in that, The yield alarm in S2 is achieved by setting thresholds for the real-time yield lower limit of chip testing and the yield lower limit of the test of the last B chips. When the actual yield of chip testing or the yield of the test of the last B chips is lower than the set threshold, the test will be interrupted.
6. The chip automated testing anomaly troubleshooting method according to claim 5, characterized in that, B≥50。 7. A chip automated testing anomaly troubleshooting system, used to implement the chip automated testing anomaly troubleshooting method as described in any one of claims 1 to 6, characterized in that, include: Test database: Raw test data automatically stored on the server during the testing process; Data access module: responsible for receiving data from the test database and converting its format; Data caching: caching the raw data received; Data filtering: Filter out valid data based on the abnormal data filtering method; Valid data pool: Valid data that has been filtered out and is ready for processing; Chip information database: Loads chip pins and test plans; Data processing module: Retrieves data from the valid data pool and performs logical processing; Feature data extraction: Extracting potential risk rates; Results Displayer: Shows the magnitude of risk for each pin in sequence.