Test adapters, test systems and test methods for storage devices

Abstract

This application provides a test adapter, test system, and test method for a storage device, relating to the field of storage technology. The test adapter includes a first interface circuit, a second interface circuit, a third interface circuit, a fourth interface circuit, a first bridge chip, and a second bridge chip. The first and third interface circuits are configured to be connected to a host. The second interface circuit is configured to be connected to a debug information interface circuit of the storage device. The fourth interface circuit is configured to be connected to a data interface circuit of the storage device. The first bridge chip is configured to be connected to both the first and second interface circuits. The second bridge chip is configured to be connected to both the first and fourth interface circuits. The first and second bridge chips are configured to perform test operations on the storage device according to test control commands sent by the host.

Description

Technical Field

[0001] This application relates to the field of storage technology, and in particular to a test adapter, test system and test method for storage devices. Background Technology

[0002] During the development of storage devices, it is usually necessary to test the various functions and performance of the storage devices to verify whether the storage devices meet the design requirements.

[0003] During the testing of storage devices, developers can use test cards that integrate a microcontroller unit (MCU) to perform tests on the storage devices. Summary of the Invention

[0004] This application provides a test adapter, test system, and test method for storage devices, which can simplify the complexity of testing storage devices and improve the testing efficiency. The technical solution is as follows:

[0005] On one hand, a test adapter for a storage device is provided. The test adapter includes a first interface circuit, a second interface circuit, a third interface circuit, a fourth interface circuit, a first bridge chip, and a second bridge chip. The first interface circuit and the third interface circuit are respectively configured to be connected to a host. The second interface circuit is configured to be connected to a debug information interface circuit of the storage device. The fourth interface circuit is configured to be connected to a data interface circuit of the storage device. The first bridge chip is configured to be connected to the first interface circuit and also to the second interface circuit. The second bridge chip is configured to be connected to the first interface circuit and also to the fourth interface circuit. The first bridge chip and the second bridge chip are configured to perform test operations on the storage device according to test control commands sent by the host.

[0006] In an optional embodiment, the test adapter further includes at least one system management bus slave device; the second bridge chip is configured to be connected to the at least one system management bus slave device; and the at least one system management bus slave device is configured to be connected to the fourth interface circuit.

[0007] In an optional embodiment, the first bridging chip is configured to receive a first control command from the host from the first interface circuit, convert the format of the first control command into the format of the protocol corresponding to the second interface circuit, and then send it to the storage device through the second interface circuit; the first control command instructs the storage device to perform a test-related first operation; the first bridging chip is configured to receive debugging information sent by the storage device from the second interface circuit, convert the format of the debugging information into the format of the protocol corresponding to the first interface circuit, and then send it to the host through the first interface circuit.

[0008] In an optional embodiment, the first control instruction includes at least one of the following instructions: an instruction to perform a Universal Asynchronous Receiver / Transmitter (UART) test; an instruction to perform a Joint Test Team (JTAG) test; and an instruction to perform a Non-Volatile Memory Extension Management Interface (NVMe-MI) test related to the Peripheral Component Interconnect Extension (PCI-E).

[0009] In an optional embodiment, the second bridge chip is configured to receive a second control command from the host from the first interface circuit, convert the format of the second control command into the format of the system management bus protocol, and send it to a target slave device, wherein the target slave device is one or more of the at least one system management bus slave device; the target slave device is configured to perform a test-related second operation according to the second control command.

[0010] In an optional embodiment, the at least one system management bus slave device includes a digital-to-analog converter (DAC) chip and a power supply chip; the second bridge chip is configured to be connected to the DAC chip, the DAC chip is configured to be connected to the power supply chip, and the power supply chip is configured to be connected to the fourth interface circuit; when the second control command includes a bias control command, the second bridge chip is configured to convert the format of the bias control command into the format of the system management bus protocol and then send it to the DAC chip; the DAC chip is configured to convert the digital voltage signal corresponding to the bias control command into an analog voltage signal and then send it to the power supply chip; the power supply chip is configured to control the voltage output to the fourth interface circuit according to the analog voltage signal.

[0011] In an optional embodiment, the at least one system management bus slave device further includes an analog-to-digital converter (ADC) chip and a sampling resistor; the second bridge chip is configured to be connected to the ADC chip, the ADC chip is configured to be connected to the sampling resistor, and the sampling resistor is located on the circuit between the power supply chip and the fourth interface circuit; when the second control instruction includes a sampling instruction, the second bridge chip is configured to convert the format of the sampling instruction into the format of the system management bus protocol and then send it to the ADC chip; the ADC chip is configured to sample at least one of the voltage and current of the sampling resistor to obtain a sampled analog signal, convert the sampled analog signal into a sampled digital signal, and send the sampled digital signal to the second bridge chip according to the sampling instruction; the second bridge chip is further configured to convert the format of the sampled digital signal to the format of the protocol corresponding to the first interface circuit and then send the sampled digital signal to the host through the first interface circuit.

[0012] In an optional embodiment, the test adapter further includes a first general purpose input / output (GPIO) interface circuit and a first switch; the first GPIO interface circuit is configured to be connected to a first target chip, and the first GPIO interface circuit is configured to be connected to the first switch, the first switch being located on the power supply circuit of the test adapter to the storage device; the first target chip is one of a first bridge chip and a second bridge chip; the first target chip is configured to receive a third control command from the host from the first interface circuit, and trigger the first GPIO interface circuit to send a first level signal to the first switch according to the third control command, the first level signal being configured to trigger the first switch to disconnect or connect, thereby controlling the power-on and power-off of the storage device.

[0013] In an optional embodiment, the test adapter further includes a second GPIO interface circuit; the second GPIO interface circuit is configured to be connected to a second target chip, and the second GPIO interface circuit is also configured to be connected to the fourth interface circuit; the second target chip is one of the first bridge chip and the second bridge chip; the second target chip is configured to receive a fourth control command from the host from the first interface circuit, and trigger the second GPIO interface circuit to send a second level signal to the storage device through the fourth interface circuit according to the fourth control command.

[0014] In an optional embodiment, the first bridge chip has a first connector; the first connector is configured to connect to a programming device so that the programming device can rewrite the firmware of the first bridge chip through the first connector; and / or, the second bridge chip has a second connector; the second connector is configured to connect to a programming device so that the programming device can rewrite the firmware of the second bridge chip through the second connector.

[0015] On the other hand, a testing system for a storage device is provided, the testing system comprising: a test adapter and a host; the test adapter includes a first interface circuit, a second interface circuit, a third interface circuit, a fourth interface circuit, a first bridge chip, and a second bridge chip; the first interface circuit and the third interface circuit are respectively configured to be connected to the host; the second interface circuit is configured to be connected to a debug information interface circuit of the storage device; the fourth interface circuit is configured to be connected to a data interface circuit of the storage device; the first bridge chip is configured to be connected to the first interface circuit and also to the second interface circuit; the second bridge chip is configured to be connected to the first interface circuit and also to the fourth interface circuit; the host is configured to send test control commands to the test adapter; the test adapter is configured to perform test operations on the storage device according to the test control commands via the first bridge chip and the second bridge chip.

[0016] In an optional embodiment, the test adapter further includes at least one system management bus slave device; the second bridge chip is configured to be connected to the at least one system management bus slave device; and the at least one system management bus slave device is configured to be connected to the fourth interface circuit.

[0017] In an optional embodiment, the test adapter is configured to receive a first control command from the host via the first bridge chip, convert the format of the first control command into the format of the protocol corresponding to the second interface circuit, and then send it to the storage device via the second interface circuit; the first control command instructs the storage device to perform a test-related first operation; the test adapter is configured to receive debugging information sent by the storage device via the second interface circuit via the first bridge chip, convert the format of the debugging information into the format of the protocol corresponding to the first interface circuit, and then send it to the host via the first interface circuit.

[0018] In an optional embodiment, the first control instruction includes at least one of the following instructions: an instruction to perform a Universal Asynchronous Receiver / Transmitter (UART) test; an instruction to perform a Joint Test Team (JTAG) test; and an instruction to perform a Non-Volatile Memory Extension Management Interface (NVMe-MI) test related to the Peripheral Component Interconnect Extension (PCI-E).

[0019] In an optional embodiment, the test adapter is configured to receive a second control command from the host from the first interface circuit via the second bridge chip, convert the format of the second control command into the format of the system management bus protocol, and send it to a target slave device, wherein the target slave device is one or more of the at least one system management bus slave device; the test adapter is configured to perform a test-related second operation via the target slave device according to the second control command.

[0020] In an optional embodiment, the at least one system management bus slave device includes a digital-to-analog converter (DAC) chip and a power supply chip; the second bridge chip is configured to be connected to the DAC chip, the DAC chip is configured to be connected to the power supply chip, and the power supply chip is configured to be connected to the fourth interface circuit; when the second control command includes a bias control command, the test adapter is configured to convert the format of the bias control command into the format of the system management bus protocol via the second bridge chip and then send it to the DAC chip; the test adapter is configured to convert the digital voltage signal corresponding to the bias control command into an analog voltage signal via the DAC chip and then send it to the power supply chip; the test adapter is configured to control the voltage output to the fourth interface circuit according to the analog voltage signal via the power supply chip.

[0021] In an optional embodiment, the at least one system management bus slave device further includes an analog-to-digital converter (ADC) chip and a sampling resistor; the second bridge chip is configured to be connected to the ADC chip, the ADC chip is configured to be connected to the sampling resistor, and the sampling resistor is located on the circuit between the power supply chip and the fourth interface circuit; when the second control command includes a sampling command, the test adapter is configured to convert the format of the sampling command into the format of the system management bus protocol via the second bridge chip and then send it to the ADC chip; the test adapter is configured to sample at least one of the voltage and current of the sampling resistor via the ADC chip to obtain a sampled analog signal, convert the sampled analog signal into a sampled digital signal, and send the sampled digital signal to the second bridge chip according to the sampling command; the test adapter is also configured to convert the format of the sampled digital signal into the format of the protocol corresponding to the first interface circuit via the second bridge chip and then send the sampled digital signal to the host via the first interface circuit.

[0022] In an optional embodiment, the test adapter further includes a first general purpose input / output (GPIO) interface circuit and a first switch; the first GPIO interface circuit is configured to be connected to a first target chip, and the first GPIO interface circuit is configured to be connected to the first switch, the first switch being located on the power supply circuit of the test adapter to the storage device; the first target chip is one of a first bridge chip and a second bridge chip; the test adapter is configured to receive a third control command from the host through the first target chip from the first interface circuit, and trigger the first GPIO interface circuit to send a first level signal to the first switch according to the third control command, the first level signal being configured to trigger the first switch to disconnect or connect, thereby controlling the power-on and power-off of the storage device.

[0023] In an optional embodiment, the test adapter further includes a second GPIO interface circuit; the second GPIO interface circuit is configured to be connected to a second target chip, and the second GPIO interface circuit is also configured to be connected to the fourth interface circuit; the second target chip is one of the first bridge chip and the second bridge chip; the test adapter is configured to receive a fourth control command from the host through the second target chip from the first interface circuit, and trigger the second GPIO interface circuit to send a second level signal to the storage device through the fourth interface circuit according to the fourth control command.

[0024] In an optional embodiment, the first bridge chip has a first connector; the first connector is configured to connect to a programming device so that the programming device can rewrite the firmware of the first bridge chip through the first connector; and / or, the second bridge chip has a second connector; the second connector is configured to connect to a programming device so that the programming device can rewrite the firmware of the second bridge chip through the second connector.

[0025] On the other hand, a testing method for a storage device is provided, the method being executed by a test adapter, the test adapter including a first interface circuit, a second interface circuit, a third interface circuit, a fourth interface circuit, a first bridge chip, and a second bridge chip; the first interface circuit and the third interface circuit are respectively configured to be connected to a host; the second interface circuit is configured to be connected to a debug information interface circuit of the storage device; the fourth interface circuit is configured to be connected to a data interface circuit of the storage device; the first bridge chip is configured to be connected to the first interface circuit and also to the second interface circuit; the second bridge chip is configured to be connected to the first interface circuit and also to the fourth interface circuit; the method includes: receiving test control commands sent by a host through the first bridge chip and the second bridge chip; and performing test operations on the storage device according to the test control commands through the first bridge chip and the second bridge chip.

[0026] In an optional embodiment, the test adapter further includes at least one system management bus slave device; the second bridge chip is connected to the at least one system management bus slave device; and the at least one system management bus slave device is connected to the fourth interface circuit.

[0027] In an optional embodiment, receiving test control commands sent by the host through the first bridging chip and the second bridging chip includes: receiving a first control command from the host through the first interface circuit via the first bridging chip, converting the format of the first control command into the format of the protocol corresponding to the second interface circuit, and then sending it to the storage device through the second interface circuit; the first control command instructing the storage device to perform a test-related first operation; receiving debugging information sent by the storage device through the second interface circuit via the first bridging chip, converting the format of the debugging information into the format of the protocol corresponding to the first interface circuit, and then sending it to the host through the first interface circuit.

[0028] In an optional embodiment, the first control instruction includes at least one of the following instructions: an instruction to perform a Universal Asynchronous Receiver / Transmitter (UART) test; an instruction to perform a Joint Test Team (JTAG) test; and an instruction to perform a Non-Volatile Memory Extension Management Interface (NVMe-MI) test related to the Peripheral Component Interconnect Extension (PCI-E).

[0029] In an optional embodiment, receiving test control commands sent by the host through the first bridge chip and the second bridge chip includes: receiving a second control command from the host through the second bridge chip from the first interface circuit, converting the format of the second control command into the format of the system management bus protocol, and sending it to a target slave device, wherein the target slave device is one or more of the at least one system management bus slave device; and performing a test-related second operation through the target slave device according to the second control command.

[0030] In an optional embodiment, the at least one system management bus slave device includes a digital-to-analog converter (DAC) chip and a power supply chip; a second bridge chip is configured to be connected to the DAC chip, the DAC chip is configured to be connected to the power supply chip, and the power supply chip is configured to be connected to the fourth interface circuit; the step of converting the format of the second control command into the format of the system management bus protocol and sending it to the target slave device includes: if the second control command includes a bias control command, converting the format of the bias control command into the format of the system management bus protocol through the second bridge chip and then sending it to the DAC chip; the step of the target slave device performing a test-related second operation according to the second control command includes: converting the digital voltage signal corresponding to the bias control command into an analog voltage signal through the DAC chip and then sending it to the power supply chip; and controlling the voltage output to the fourth interface circuit through the power supply chip according to the analog voltage signal.

[0031] In an optional embodiment, the at least one system management bus slave device further includes an analog-to-digital converter (ADC) chip and a sampling resistor; the second bridge chip is configured to be connected to the ADC chip, the ADC chip is configured to be connected to the sampling resistor, and the sampling resistor is located on the circuit between the power supply chip and the fourth interface circuit; the step of converting the format of the second control instruction into the format of the system management bus protocol and sending it to the target slave device includes: if the second control instruction includes a sampling instruction, converting the format of the sampling instruction into the format of the system management bus protocol through the second bridge chip and then sending it to the ADC chip; the step of the target slave device performing a test-related second operation according to the second control instruction includes: sampling at least one of the voltage and current of the sampling resistor through the ADC chip to obtain a sampled analog signal, converting the sampled analog signal into a sampled digital signal, and sending the sampled digital signal to the second bridge chip according to the sampling instruction; the method further includes: converting the format of the sampled digital signal to the format of the protocol corresponding to the first interface circuit through the second bridge chip, and then sending the sampled digital signal to the host through the first interface circuit.

[0032] In an optional embodiment, the test adapter further includes a first general purpose input / output (GPIO) interface circuit and a first switch; the first GPIO interface circuit is configured to be connected to a first target chip, and the first GPIO interface circuit is configured to be connected to the first switch, the first switch being located on the power supply circuit of the test adapter to the storage device; the first target chip is one of a first bridge chip and a second bridge chip; receiving test control commands sent by the host through the first bridge chip and the second bridge chip includes: receiving a third control command from the host through the first interface circuit via the first target chip; performing test operations on the storage device according to the test control command through the first bridge chip and the second bridge chip includes: triggering the first GPIO interface circuit to send a first level signal to the first switch through the first target chip according to the third control command, the first level signal being configured to trigger the first switch to disconnect or connect, thereby controlling the power-on and power-off of the storage device.

[0033] In an optional embodiment, the test adapter further includes a second GPIO interface circuit; the second GPIO interface circuit is configured to be connected to a second target chip, and the second GPIO interface circuit is also configured to be connected to the fourth interface circuit; the second target chip is one of the first bridge chip and the second bridge chip; receiving test control commands sent by the host through the first bridge chip and the second bridge chip includes: receiving a fourth control command from the host through the second target chip from the first interface circuit; performing test operations on the storage device according to the test control command through the first bridge chip and the second bridge chip includes: triggering the second GPIO interface circuit to send a second level signal to the storage device through the fourth interface circuit through the fourth interface circuit via the second target chip according to the fourth control command.

[0034] The technical solution provided in this application may include the following beneficial effects:

[0035] This application provides a test adapter for testing storage devices. The test adapter connects to both the host and the storage device via four interface circuits. Internally, the test adapter includes a first bridge chip and a second bridge chip connected to each of the four interface circuits. During storage device testing, the first and second bridge chips in the test adapter execute test operations on the storage device according to test control commands sent by the host. In this solution, the test adapter does not rely on an MCU; instead, it uses bridge chips to test the storage device. Compared to test cards that rely on an MCU, the test adapter provided in this application has lower circuit complexity. Consequently, using this test adapter to test storage devices does not require complex software control logic, thus reducing testing complexity and improving testing efficiency. Attached Figure Description

[0036] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0037] Figure 1 This is a schematic diagram of a system provided in one embodiment of this application;

[0038] Figure 2 This is a schematic diagram of the structure of a memory card involved in this application;

[0039] Figure 3This is a schematic diagram of the structure of a solid-state driver involved in this application;

[0040] Figure 4 This is a block diagram of a memory device illustrated in an exemplary embodiment of this application;

[0041] Figure 5 This is a schematic circuit diagram of a memory device shown in an exemplary embodiment of this application;

[0042] Figure 6 This is a cross-sectional side view of a storage string shown in an exemplary embodiment of this application;

[0043] Figure 7 This is a structural diagram of a test adapter for a storage device provided in an exemplary embodiment of this application;

[0044] Figure 8 This is a structural diagram of a test adapter for a storage device provided in an exemplary embodiment of this application;

[0045] Figure 9 This is a structural diagram of a test adapter for a storage device provided in an exemplary embodiment of this application;

[0046] Figure 10 This is a structural diagram of a test adapter for a storage device provided in an exemplary embodiment of this application;

[0047] Figure 11 This is a structural diagram of a test adapter for a storage device provided in an exemplary embodiment of this application;

[0048] Figure 12 This is a structural diagram of a test adapter for a storage device provided in an exemplary embodiment of this application;

[0049] Figure 13 This is a structural diagram of a test adapter for a storage device provided in an exemplary embodiment of this application;

[0050] Figure 14 This is a structural diagram of a test adapter according to an embodiment of this application;

[0051] Figure 15 This is a partial structural schematic diagram of the test connector involved in the embodiments of this application;

[0052] Figure 16 This is a partial structural schematic diagram of the test connector involved in the embodiments of this application;

[0053] Figure 17 This is a schematic diagram of the power-on / power-off control implementation process involved in the embodiments of this application;

[0054] Figure 18This is a schematic diagram of the bias control implementation process involved in the embodiments of this application;

[0055] Figure 19 This is a schematic diagram of the bias control implementation process involved in the embodiments of this application;

[0056] Figure 20 This is a schematic diagram of the bias control implementation process involved in the embodiments of this application;

[0057] Figure 21 This is a flowchart of a testing method for a storage device provided in an exemplary embodiment of this application. Detailed Implementation

[0058] The embodiments of this application will now be described in further detail with reference to the accompanying drawings.

[0059] The system for the storage device application involved in the embodiments of this application may include a host and a storage system. The storage system may include a 3D memory device, such as a 3D NAND flash memory.

[0060] Figure 1 This is a schematic diagram of a system provided in one embodiment of this application. For example... Figure 1 As shown, the computer system 10 includes: one or more memory devices 100, and a controller 200 coupled to the memory devices 100 and configured to control the memory devices 100. The controller 200 may also be referred to as a memory controller.

[0061] The controller 200 can be configured to control operations performed by the memory device 100, such as read, erase, and program operations. The controller 200 can also be configured to manage various functions related to data stored or to be stored in the memory device 100, including but not limited to bad block management, garbage collection, logical address to physical address translation, wear leveling, etc. Optionally, the controller 200 can also be configured to process error correcting codes (ECCs) for data read from or written to the memory device 100. The controller 200 can also perform any other suitable functions, such as formatting the memory device 100.

[0062] The controller 200 can also communicate with external devices according to a specific communication protocol. For example, the controller 200 can communicate with external devices through at least one of various interface protocols. The interface protocol can be Universal Serial Bus (USB) protocol, Multi-Media Card (MMC) protocol, Peripheral Component Interconnect (PCI) protocol, PCI-E protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer System Interface (SCSI) protocol, Enhanced Small Drive Interface (ESDI) protocol, Integrated Development Environment (IDE) protocol, FireWire protocol, etc.

[0063] In an optional embodiment, the controller 200 and one or more memory devices 100 can be integrated into various types of electronic devices. These electronic devices can be mobile phones, desktop computers, laptop computers, tablet computers, vehicle computers, game consoles, printers, positioning devices, wearable electronic devices, smart sensors, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic device having storage therein. In this scenario, such as... Figure 1 As shown, the computer system 10 also includes a host 300. A controller 200 is coupled to the host 300. The controller 200 can manage data stored in the memory device 100 and communicate with the host 300 to perform the functions of the aforementioned electronic device.

[0064] In other embodiments, the controller 200, and one or more memory devices 100, can be integrated into various types of storage devices.

[0065] As an example, Figure 2 This is a schematic diagram of the structure of a memory card involved in this application. Figure 2As shown, the controller 200 and a single memory device 100 can be integrated into the memory card 40. The memory card 40 may include PCMCIA (PC) cards, Compact Flash (CF) cards, Smart Media (SM) cards, memory sticks, Multi-Media Cards (MMC), RS-MMC, micro-MMC, Secure Digital (SD) cards, Universal Flash Storage (UFS), etc. Figure 2 As shown, the memory card 40 may also include a connector 410 for coupling the memory card 40 to the host.

[0066] As another example Figure 3 This is a schematic diagram of the structure of a solid-state drive involved in this application. Figure 3 As shown, the controller 200 and multiple memory devices 100 can be integrated into a solid-state drive (SSD) 50. The solid-state drive 50 may also include a connector 510 for coupling the solid-state drive 50 to the host. The storage capacity and / or operating speed of the solid-state drive 50 is greater than that of the memory card 40.

[0067] also, Figures 1 to 3 The memory device 100 can be any memory device involved in the embodiments of this application. For example, it can be a 3D NAND (NAND gate) memory device. The structure of the memory device 100 will be explained below.

[0068] Figure 4 This is a block diagram illustrating a memory device according to an exemplary embodiment of this application. (Reference) Figure 4 The memory device 400 may include a memory cell array 401, a page buffer 404, a column decoder 406, a row decoder 408, a voltage generator 410, control logic 412, a register 414, and input / output circuitry 416. It should be understood that in some examples, it may also include... Figure 4 Additional peripheral circuitry not shown.

[0069] Page buffer 404 can be configured to read data from memory cell array 401 and program (write) data to memory cell array 401 according to control signals from control logic 412. In one example, page buffer 404 can store data to be programmed into selected pages of memory cell array 401 (write data). In another example, page buffer 404 can output read data in a programming verification operation to ensure that data has been correctly programmed into the corresponding memory cell coupled to the selected word line of memory cell array 401. Column decoder 406 can operate in response to control signals provided by control logic to select one or more memory strings in memory cell array 401. Row decoder can operate in response to control signals provided by control logic and select / deselect selected rows of memory cell array 401. Row decoder can also be configured to supply voltage generated from voltage generator 410 to selected and unselected word lines of memory cell array 401. As described in detail below, row decoder / word line driver 408 is configured to perform erase operations on memory cells coupled to one or more selected word lines of memory cell array 401. Voltage generator 410 can use external or internal power supply voltages to generate various voltages required by the memory device, such as programming voltage, read voltage, pass voltage, verification voltage, bit line voltage, and combinations thereof.

[0070] Control logic 412 can be coupled to voltage generator 410, page buffer 404, column decoder 406, row decoder 408, and input / output circuitry 416, etc., and is configured to control the operation of each peripheral circuit. The control logic can generate operation signals in response to commands or control signals from the memory controller. Register 414 can be coupled to control logic 412 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Input / output circuitry 416 can be coupled to control logic 412 and acts as a control buffer to buffer inputs from external devices (e.g., ...). Figure 1 The host 300 or controller 200 receives control commands and relays them to control logic 412, and buffers status information received from control logic 412 and relays it to the host. Input / output circuitry 416 can also be coupled to column decoder and act as data input / output interface and data buffer to buffer data and relay it to or from memory cell array 401.

[0071] Figure 5 This is a schematic circuit diagram of a memory device shown in an exemplary embodiment of this application. Figure 5As shown, the memory device 500 may include a memory cell array 501 and peripheral circuitry 502 coupled to the memory cell array 501. The memory cell array 501 may be a NAND flash memory cell array, wherein memory cells 506 are provided in the form of an array of memory strings 508, each memory string 508 extending vertically above a substrate (not shown). In some embodiments, each memory string 508 includes a plurality of memory cells 506 coupled in series and stacked vertically. Each memory cell 506 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor. In some embodiments, each memory cell 506 is a single-level cell (SLC) capable of storing one bit of data and having two possible storage states (or storage conditions). For example, a first storage state "0" may correspond to a first voltage range, and a second storage state "1" may correspond to a second voltage range. In some embodiments, each memory cell 506 is a multilevel cell capable of storing more than a single bit of data in more than two storage states. For example, each cell can store two bits (i.e., Multi-Level Cell (MLC)), three bits (i.e., Triple-Level Cell (TLC)), or four bits (i.e., Quad-Level Cell (QLC)).

[0072] like Figure 5 As shown, each memory string 508 may include at least one source select transistor 510 at its source end and at least one drain select transistor 512 at its drain end. The source select transistor 510 and drain select transistor 512 may be configured to activate the selected memory string 508 during read and program operations. In some embodiments, the sources of memory strings 508 in the same block 504 are coupled via the same source line (SL). According to some embodiments, the drain select transistor 512 of each memory string 508 is coupled to a corresponding bit line 516. In some embodiments, each memory string 508 is configured to be selected or deselected by applying a select voltage or deselect voltage (e.g., 0V) to the corresponding drain select transistor 512 via one or more drain select lines and / or by applying a select voltage or deselect voltage (e.g., 0V) to the corresponding source select transistor 510 via one or more source select lines.

[0073] like Figure 5 As shown, the storage cell array may include multiple blocks. In some embodiments, each block 504 is the basic data unit for the erase operation, that is, all storage cells 506 on the same block 504 are erased simultaneously.

[0074] Figure 6 This is a cross-sectional side view of a memory cell array 501 including memory strings 508, as shown in one embodiment of this application. See also Figure 6 The storage string 508 can extend vertically through the stacked layer 620 above the semiconductor layer 610. The semiconductor layer 610 is coupled to the source line. In some embodiments, the semiconductor layer 610 is an N-type doped semiconductor layer, and the semiconductor layer 610 can serve as a substrate, i.e., an N-type substrate. In other embodiments, the semiconductor layer 610 is a P-type doped semiconductor layer, and the semiconductor layer 610 can serve as a P-well in the substrate, in which case the substrate is a P-type substrate.

[0075] Stacked layer 620 includes a plurality of conductive layers 630 and a plurality of dielectric layers 640 stacked alternately. The logarithm of the conductive layers 630 and dielectric layers 640 in stacked layer 620 can affect the number of memory cells in the memory string. Conductive layers 630 may include conductive materials, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicides, or any combination thereof. In one possible implementation, each conductive layer 630 includes a metal layer, such as a tungsten layer. In some implementations, each conductive layer 630 includes a doped polysilicon layer. Each conductive layer 630 may include a gate surrounding a memory cell and may extend laterally at the top of stacked layer 620 as a drain select line (DSL), at the bottom of stacked layer 620 as a source select line (SSL), or between DSL and SSL as a word line (WL).

[0076] like Figure 6 As shown, the memory string 508 includes a channel structure 650 extending vertically through the stacked layer 620. The channel structure 650 includes channel vias filled with at least one semiconductor material (such as a semiconductor channel) and at least one dielectric material (such as a memory film). In some embodiments, the semiconductor channel includes silicon (such as a memory film). In some embodiments, the memory film is a composite dielectric layer including a tunnel layer, a trap layer, and a barrier layer. The channel structure 650 may have a cylindrical shape (such as a pillar shape). According to some embodiments, the semiconductor channel, the trap layer (also referred to as the memory layer), and the barrier layer are arranged radially from the center of the pillar toward the outer surface of the pillar in this order. The tunnel layer may include silicon oxide, silicon oxynitride, or any combination thereof. The trap layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide.

[0077] For any technical details not disclosed in the above hardware embodiments related to the memory device, please refer to the description of the computer system embodiments and method embodiments of this application for understanding.

[0078] The storage devices involved in the various embodiments of this application may include the storage system described above, or the storage devices involved in the embodiments of this application may include the memory devices in the storage system described above.

[0079] For example, the aforementioned storage device can be a solid state disk (SSD), such as an enterprise SSD (eSSD) or a consumer SSD (cSSD).

[0080] In some embodiments, during the testing of storage devices, testers can use different testing tools to perform tests on different functions or test items of the storage device. For example, for testing the serial port function and Universal Asynchronous Receiver / Transmitter (UART) function of the storage device, testers can use a serial port and a Joint Test Action Group (JTAG) test card; for testing the Peripheral Component Interconnect Express (PCIe) function of the storage device, testers can use a PCIe test card; for voltage biasing and voltage / current sampling functions, testers can use an adapter card and external acquisition devices (such as current and voltage testers). The testing of some of the above functions requires execution by an MCU. For example, if the test card / adapter card has an MCU, testers can develop MCU-based test commands. During testing, the host sends test commands to the MCU in the test card / adapter card, and the MCU in the test card / adapter card executes the test commands to perform the corresponding tests on the storage device.

[0081] However, in the solutions shown in the above embodiments of this application, the development process of MCU-based test instructions is relatively complex, which leads to a cumbersome testing process for storage devices and affects the testing efficiency of storage devices.

[0082] To address the aforementioned issues, the solutions presented in subsequent embodiments of this application provide a test adapter for storage devices. This test adapter does not rely on an MCU but instead uses a bridge chip to perform tests on storage devices, thereby simplifying the complexity of testing storage devices and improving the efficiency of testing storage devices.

[0083] Please refer to Figure 7 This is a structural diagram of a test adapter for a storage device provided in an exemplary embodiment of this application. Figure 7 As shown, the test adapter 720 may include:

[0084] The circuit consists of a first interface circuit 720a, a second interface circuit 720b, a third interface circuit 720c, a fourth interface circuit 720d, a first bridge chip 720e1, and a second bridge chip 720e2.

[0085] In the aforementioned first interface circuit 720a, second interface circuit 720b, third interface circuit 720c, and fourth interface circuit 720d, each interface circuit can correspond to one of multiple different communication interface standards. These multiple different communication interface standards may include, but are not limited to: Universal Serial Bus (USB) interface standards (such as USB 2.0, USB 3.0, Type-C, etc.), High Definition Multimedia Interface (HDMI) standards, Micro HDMI standards, U.2 interface standards, M.2 interface standards, and Add-In-Card (AIC) interface standards.

[0086] The first bridge chip 720e1 and the second bridge chip 720e2 mentioned above are two independent bridge chips; a bridge chip, also known as a bridge connector chip, is an integrated circuit used to connect interfaces / devices / systems of different types or standards.

[0087] The first interface circuit 720a and the third interface circuit 720c are respectively configured to be connected to the host 710; the second interface circuit 720b is configured to be connected to the debugging information interface circuit of the storage device 730; and the fourth interface circuit 720d is configured to be connected to the data interface circuit of the storage device 730.

[0088] In some embodiments, the host 710 is a host in a test platform used to perform tests on the storage device; in other embodiments, the host 710 is... Figure 1 The host in the middle is 300.

[0089] The first interface circuit 720a and the third interface circuit 720c are respectively configured to be connected to the interface circuits in the host 710 that correspond to the interface standards of the first interface circuit 720a and the third interface circuit 720c.

[0090] For example, if the first interface circuit 720a is a USB interface standard interface circuit (such as a Type-C interface circuit) and the third interface circuit 720c is a U.2 interface circuit (also known as a U.2 connector), the first interface circuit 720a is configured to connect to the Type-C interface circuit in the host, and the third interface circuit 720c is configured to connect to the U.2 interface circuit in the host.

[0091] The debugging information interface circuit of the aforementioned storage device 730 is an interface circuit in the storage device 730 used to receive debugging signals and output debugging information.

[0092] The data interface circuit of the aforementioned storage device 730 is an interface circuit used for sending and receiving data in the storage device 730.

[0093] Among them, the interface standard of the second interface circuit 720b corresponds to the interface standard of the debugging information interface circuit, and the interface standard of the fourth interface circuit 720d corresponds to the interface standard of the data interface circuit.

[0094] For example, the second interface circuit 720b and the debugging information interface circuit mentioned above are both HDMI interface circuits or MicroHDMI interface circuits, and the fourth interface circuit 720d and the data interface circuit mentioned above are both U.2 interface circuits or M.2 interface circuits.

[0095] The first bridging chip 720e1 is configured to be connected to the first interface circuit 720a, and the first bridging chip 720e1 is configured to be connected to the second interface circuit 720b; the second bridging chip 720e2 is configured to be connected to the first interface circuit 720a, and the second bridging chip 720e2 is configured to be connected to the fourth interface circuit 720d.

[0096] The first bridging chip 720e1 connects the first interface circuit 720a and the second interface circuit 720b. The first bridging chip 720e1 can realize data transmission, communication or coordination operation between the debugging information interface circuit of the host 710 and the storage device 730.

[0097] The first bridging chip 720e1 and the first interface circuit 720a can be directly connected or indirectly connected; the first bridging chip 720e1 and the second interface circuit 720b can be directly connected or indirectly connected.

[0098] The second bridging chip 720e2 is connected to the first interface circuit 720a and the fourth interface circuit 720d. The second bridging chip 720e2 can realize data transmission, communication or coordination operation between the data interface circuits of the host 710 and the storage device 730.

[0099] The second bridging chip 720e2 can be directly or indirectly connected to the first interface circuit 720a; the second bridging chip 720e2 can be directly or indirectly connected to the fourth interface circuit 720d.

[0100] The aforementioned indirect connection refers to the existence of other integrated circuits or components between the bridging chip and the interface circuit.

[0101] In some embodiments, the first bridging chip 720e1 and the second bridging chip 720e2 can be connected to the first interface circuit 720a through a hub chip; specifically, the first interface circuit 720a is connected to one port / pin of the hub chip, and the first bridging chip 720e1 and the second bridging chip 720e2 are respectively connected to the other two ports / pins of the hub chip.

[0102] The first bridging chip 720e1 and the second bridging chip 720e2 are configured to perform test operations on the storage device 730 according to test control commands sent by the host 710.

[0103] In the embodiments of this application, the first bridge chip 720e1 and the second bridge chip 720e2 can control the test operation on the storage device 730 when implementing data transmission, communication or coordination operations between different interface circuits.

[0104] In summary, the embodiments of this application provide a test adapter for testing storage devices. This test adapter connects to both the host and the storage device via four interface circuits. Internally, the test adapter includes a first bridge chip and a second bridge chip connected to each of the four interface circuits. During the testing of the storage device, the first and second bridge chips in the test adapter can execute test operations on the storage device according to test control commands sent by the host. In this solution, the test adapter does not rely on an MCU; instead, it uses bridge chips to test the storage device. Compared to test cards that rely on an MCU, the test adapter provided in this application has lower circuit complexity. Consequently, using this test adapter to test the storage device does not require complex software control logic, thus reducing testing complexity and improving testing efficiency.

[0105] Based on the solutions shown in any one or more of the above embodiments, please refer to the following embodiments in some cases. Figure 8 It shows a structural diagram of a test adapter according to an embodiment of this application; as follows: Figure 8As shown, the test adapter 720 also includes at least one System Management Bus (SMBus) slave device 720f; a second bridge chip 720e2 is configured to be connected to at least one System Management Bus slave device 720f; and at least one System Management Bus slave device 720f is configured to be connected to a fourth interface circuit 720d.

[0106] Among them, the aforementioned system management bus slave device 720f is an integrated circuit / component that supports the SMBus communication protocol, and different system management bus slave devices 720f can have different circuit functions.

[0107] In this embodiment of the application, one or more system management bus slave devices 720f can be set between the second bridge chip 720e2 and the fourth interface circuit 720d in the test adapter 720. Different system management bus slave devices 720f can implement different extended functions, thereby enabling the testing methods of storage devices through the test adapter 720 to be expanded.

[0108] Based on the solutions shown in any one or more of the above embodiments, in some embodiments, the first bridging chip 720e1 is configured to receive a first control command from the host 710 from the first interface circuit 720a, convert the format of the first control command into the format of the protocol corresponding to the second interface circuit 720b, and then send it to the storage device 730 through the second interface circuit 720b; the first control command instructs the storage device 730 to perform a first operation related to testing; the first bridging chip 720e1 is configured to receive debugging information sent by the storage device 730 from the second interface circuit 720b, convert the format of the debugging information into the format of the protocol corresponding to the first interface circuit 720a, and then send it to the host 710 through the first interface circuit 720a.

[0109] The aforementioned debugging information may be information related to the first operation in the storage device 730; for example, the debugging information may include records of the storage device 730 performing the first operation, operation results, and other information; optionally, the aforementioned debugging information may also include other information besides the information related to the first operation, for example, the aforementioned debugging information may include one or more specified status information of the storage device 730.

[0110] In this embodiment, when a tester needs to trigger the storage device 730 to perform a test-related first operation, the host 710 can send a first control command to the first interface circuit 720a in the test adapter 720. The first bridge chip 720e1 can receive the first control command from the first interface circuit 720a. Based on the identifier of the first control command (e.g., the destination address), it is determined that the first control command is sent to the storage device 730 through the second interface circuit 720b. At this time, the first bridge chip 720e1 can perform format conversion on the first control command, converting the first control command from the format of the protocol corresponding to the first interface circuit 720a to the format of the protocol corresponding to the second interface circuit 720b, and then sending the format-converted first control command to the storage device 730 through the second interface circuit 720b, so that the storage device 730 can parse the first control command and perform the first operation based on the first control command.

[0111] Correspondingly, the storage device 730 can transmit to the host 710 through the second interface circuit 720b and the first interface circuit 720a. For example, the storage device 730 can send debugging information to the second interface circuit 720b in the test adapter 720. The first bridge chip 720e1 can receive the debugging information from the second interface circuit 720b. Based on the identifier of the debugging information (such as the destination address), it determines that the debugging information is an instruction sent to the host 710 through the first interface circuit 720a. Then, the format of the debugging information is converted from the protocol format of the second interface circuit 720b to the protocol format of the first interface circuit 720a, and the format-converted debugging information is sent to the host 710 through the first interface circuit 720a so that the host 710 can parse the debugging information.

[0112] For example, assuming the first interface circuit 720a is a Type-C interface circuit and the second interface circuit 720b is a Micro HDMI interface circuit, the host 710 can send a first control command (USB protocol format) to the first interface circuit 720a in the test adapter 720. The first bridge chip 720e1 can receive the first control command (USB protocol format) from the first interface circuit 720a, convert the first control command (USB protocol format) to UART protocol format, and send the converted first control command (UART protocol format) to the storage device 730 through the second interface circuit 720b. Correspondingly, the storage device 730 sends debugging information (UART protocol format) to the second interface circuit 720b, and the first bridge chip 720e1 converts the debugging information from UART protocol format to USB protocol format and sends the debugging information (USB protocol format) to the host 710 through the first interface circuit 720a.

[0113] In the solution shown in the above embodiments of this application, the first bridge chip 720e1 can perform format conversion and transmission of control instructions and debugging information between the host 710 and the storage device 730, thereby enabling accurate transmission of test-related control instructions and debugging information between the host 710 and the storage device 730. It can realize the control of the storage device and the reading of debugging information without relying on the MCU, which can simplify the complexity of testing the storage device and improve the testing efficiency of the storage device.

[0114] Based on the solutions shown in any one or more of the above embodiments, in some embodiments, the first control instruction includes at least one of the following instructions: an instruction to perform a Universal Asynchronous Receiver / Transmitter (UART) test; an instruction to perform a Joint Test Group (JTAG) test; and an instruction to perform a Non-Volatile Memory Extension Management Interface (NVMe-MI) test related to the Peripheral Component Interconnect Extension (PCI-E).

[0115] The aforementioned instruction to perform UART testing can instruct the storage device 730 to perform operations related to UART communication testing, such as performing a specified transmission operation through the UART serial port.

[0116] The above instructions to execute the joint test working group's JTAG test can instruct the storage device 730 to perform JTAG test-related operations. The information of the JTAG test-related operations (such as test mode, test parameters, etc.) can be set in advance by the tester in the host 710 and transmitted to the storage device 730 through the JTAG test instructions.

[0117] The aforementioned instructions to perform PCI-E related NVMe-MI tests can instruct the storage device 730 to perform NVMe-MI test-related operations, such as instructing the storage device 730 to send data to the host 710 based on NVMe-MI, etc.

[0118] In the solution shown in the above embodiments of this application, the first bridge chip 720e1 enables the transmission of control commands for test items such as UART testing, JTAG testing, and NVMe-MI protocol testing between the host 710 and the storage device 730. In other words, the test adapter provided in this application embodiment can realize a variety of different test items without requiring testers to use different test cards / adapter cards to implement different test functions, thereby simplifying the complexity of testing storage devices and improving the testing efficiency of storage devices.

[0119] Based on the solutions shown in any one or more of the above embodiments, in some embodiments, the second bridge chip 720e2 is configured to receive a second control command from the host 710 from the first interface circuit 720a, convert the format of the second control command into the format of the system management bus protocol, and send it to the target slave device, wherein the target slave device is one or more of at least one system management bus slave device 720f; the target slave device is configured to perform a test-related second operation according to the second control command.

[0120] In this context, the system management bus slave device 720f is an integrated circuit / component that supports the SMBus protocol. However, the format of the instructions sent by the host 710 to the first interface circuit 720a is usually not in the SMBus protocol format. Therefore, when the tester needs to trigger the target slave device to perform a test-related second operation, the host 710 can send a second control command to the first interface circuit 720a in the test adapter 720. The second bridge chip 720e2 can receive the second control command from the first interface circuit 720a and determine that the second control command is sent to the target slave device based on the identifier of the second control command (such as the destination address). At this time, the second bridge chip 720e2 can perform a format conversion on the second control command, converting the second control command from the format of the protocol corresponding to the first interface circuit 720a to the SMBus protocol format, and then send the format-converted second control command to the target slave device so that the target slave device can parse the second control command and perform the second operation based on the second control command.

[0121] The second operation mentioned above can be any of the functional operations that the target has or is designed to perform from the device itself.

[0122] In this embodiment, the second bridge chip 720e2 enables the format conversion and transmission of control commands and debugging information between the host 710 and the storage device 730. This allows for the accurate transmission of test-related control commands between the host 710 and the system management bus slave device 720f, triggering the system management bus slave device 720f to execute corresponding test operations. This enables flexible control of the specified slave device in the test adapter to execute specified test operations, improving the flexibility of testing the storage device.

[0123] Based on the solutions shown in any one or more of the above embodiments, please refer to the following embodiments in some cases. Figure 9 It shows a structural diagram of a test adapter according to an embodiment of this application; as follows: Figure 9As shown, at least one system management bus slave device 720f includes a digital-to-analog converter (DAC) chip 720f1 and a power supply chip 720f2; a second bridge chip 720e2 is configured to be connected to the DAC chip 720f1, the DAC chip 720f1 is configured to be connected to the power supply chip 720f2, and the power supply chip 720f2 is configured to be connected to the fourth interface circuit 720d; when the second control command includes a bias control command, the second bridge chip 720e2 is configured to convert the format of the bias control command into the format of the system management bus protocol and then send it to the DAC chip 720f1; the DAC chip 720f1 is configured to convert the digital voltage signal corresponding to the bias control command into an analog voltage signal and then send it to the power supply chip 720f2; the power supply chip 720f2 is configured to control the voltage output to the fourth interface circuit 720d according to the analog voltage signal.

[0124] The DAC chip 720f1 has the function of digital-to-analog conversion (converting digital signals into analog signals); the power supply chip 720f2 has the function of supplying power to the fourth interface circuit.

[0125] In the above embodiment, the tester can control the system management bus in the test adapter via the host 710 to perform bias control test operations from the device 720f. Specifically, for example, the tester can send a bias control command to the first interface circuit 720a in the test adapter 720 through the host 710. The second bridge chip 720e2 can receive the bias control command from the first interface circuit 720a. Based on the identifier of the bias control command (such as the destination address), it is determined that the bias control command is sent to the DAC chip 720f1. At this time, the second bridge chip 720e2 can perform format conversion on the bias control command, converting the bias control command from the format of the protocol corresponding to the first interface circuit 720a to the format of the SMBus protocol, and send the format-converted bias control command to the DAC chip 720f1 so that the DAC chip 720f1 can parse and identify the digital voltage signal in the bias control command. After the DAC chip 720f1 converts the digital voltage signal into an analog voltage signal, it sends it to the power chip 720f2 to control the power chip 720f2 to output the voltage corresponding to the analog voltage signal to the fourth interface circuit 720d.

[0126] For example, taking the first interface circuit 720a as a Type-C interface circuit, the host 710 can send a bias control command (USB protocol format) to the first interface circuit 720a in the test adapter 720. The second bridge chip 720e2 can receive the bias control command (USB protocol format) from the first interface circuit 720a, convert the bias control command (USB protocol format) into SMBus protocol format, and send the converted bias control command (SMBus protocol format) to the DAC chip 720f1. The DAC chip 720f1 converts the digital voltage signal in the bias control command into an analog voltage signal and sends it to the power supply chip 720f2.

[0127] In this embodiment of the application, by embedding a DAC chip 720f1 and a power chip 720f2 in the test adapter, and by accurately transmitting the target voltage set on the host 710 side to the power chip 720f2 through the second bridge chip 720e2, the accuracy and flexibility of bias control during the test process are ensured.

[0128] Based on the solutions shown in any one or more of the above embodiments, please refer to the following embodiments in some cases. Figure 10 It shows a structural diagram of a test adapter according to an embodiment of this application; as follows: Figure 10 As shown, at least one system management bus slave device 720f also includes an analog-to-digital converter (Analog to Digital). A converter (ADC) chip 720f3 and a sampling resistor 720f4 are included; a second bridge chip 720e2 is configured to be connected to the ADC chip 720f3, and the ADC chip 720f3 is configured to be connected to the sampling resistor 720f4, which is located in the circuit between the power supply chip 720f2 and the fourth interface circuit 720d; when the second control instruction includes a sampling instruction, the second bridge chip 720e2 is configured to convert the format of the sampling instruction into the format of the system management bus protocol and then send it to the ADC chip 720f3; the ADC chip 720f3 is configured to sample at least one of the voltage and current of the sampling resistor 720f4 to obtain a sampled analog signal, convert the sampled analog signal into a sampled digital signal, and send the sampled digital signal to the second bridge chip 720e2 according to the sampling instruction; the second bridge chip 720e2 is also configured to convert the format of the sampled digital signal to the format of the protocol corresponding to the first interface circuit 720a and then send the sampled digital signal to the host 710 through the first interface circuit 720a.

[0129] The aforementioned ADC chip 720f3 has the function of analog-to-digital conversion (converting analog signals into digital signals); simultaneously, the ADC chip 720f3 also has the function of performing voltage / current acquisition based on the sampling resistor 720f4; wherein, when the aforementioned sampled analog signal includes an analog signal of sampling point voltage, the sampling point voltage can be the supply voltage output by the power chip 720f2 to the fourth interface circuit 720d, or the sampling point voltage can be the voltage across the sampling resistor 720f4, and the host 710 can infer / calculate the supply voltage output by the power chip 720f2 to the fourth interface circuit 720d based on the voltage across the sampling resistor 720f4; when the aforementioned sampled analog signal includes an analog signal of sampling current, the sampling current can be the current supplying power to the storage device through the fourth interface circuit 720d.

[0130] In the above embodiment, the tester can control the system management bus in the test adapter via the host 710 to perform voltage / current sampling test operations on the device 720f. Specifically, the tester can send a sampling command to the first interface circuit 720a in the test adapter 720 via the host 710. The second bridge chip 720e2 can receive the sampling command from the first interface circuit 720a and determine that the sampling command is sent to the ADC chip 720f3 based on the identifier (e.g., destination address). At this time, the second bridge chip 720e2 can perform format conversion on the sampling command, converting it from the format of the protocol corresponding to the first interface circuit 720a to the format of the SMBus protocol, and then send the converted sampling command to the ADC chip 720f3 so that the ADC chip 720f3 can... The ADC chip 720f3 can analyze and identify the sampling instruction; it can sample at least one of the voltage and current of the sampling resistor 720f4 to obtain a sampled analog signal, convert the sampled analog signal into a sampled digital signal, and send the sampled digital signal to the second bridge chip 720e2; the second bridge chip 720e2 identifies the sampled digital signal as a signal to be sent to the host 710 based on the identifier of the sampled digital signal (such as source address, destination address, or signal type), converts the format of the sampled digital signal to the format of the protocol corresponding to the first interface circuit 720a, and then sends the sampled digital signal to the host 710 through the first interface circuit 720a.

[0131] For example, taking the first interface circuit 720a as a Type-C interface circuit, the host 710 can send a sampling command (USB protocol format) to the first interface circuit 720a in the test adapter 720. The second bridge chip 720e2 can receive the sampling command (USB protocol format) from the first interface circuit 720a, convert the sampling command (USB protocol format) into SMBus protocol format, and send the format-converted sampling command (SMBus protocol format) to the ADC chip 720f3. The ADC chip 720f3 samples the current or voltage sampling analog signal from the sampling resistor 720f4, converts the sampling analog signal into a sampling digital signal (SMBus protocol format), and sends it to the second bridge chip 720e2. The second bridge chip 720e2 converts the format of the sampling digital signal into USB protocol format and sends it to the host 710 through the first interface circuit 720a.

[0132] In this embodiment, by embedding an ADC chip 720f3 and a sampling resistor 720f4 in the test adapter, and accurately transmitting the sampling signal set by the host 710 to the ADC chip 720f3 through the second bridge chip 720e2, and accurately transmitting the sampled digital signal obtained by the ADC chip 720f3 to the host 710, the voltage and current of the storage device can be sampled with the help of an external acquisition device, simplifying the complexity of voltage and current sampling and ensuring the efficiency and flexibility of voltage and current sampling during the test process.

[0133] Based on the solutions shown in any one or more of the above embodiments, please refer to the following embodiments in some cases. Figure 11 It shows a structural diagram of a test adapter according to an embodiment of this application; as follows: Figure 11 As shown, the test adapter 720 also includes a first general-purpose input / output (GPIO) interface circuit 720g and a first switch 720h; the first GPIO interface circuit 720g is configured to be connected to a first target chip, and the first GPIO interface circuit 720g is configured to be connected to the first switch 720h, the first switch 720h being located on the power supply circuit of the test adapter 720 to the storage device 730; the first target chip is one of a first bridge chip 720e1 and a second bridge chip 720e2. Figure 11The first target chip is configured to receive a third control command from the host 710 from the first interface circuit 720a, and trigger the first GPIO interface circuit 720g to send a first level signal to the first switch 720h according to the third control command. The first level signal is configured to trigger the first switch 720h to disconnect or connect, so as to realize the power-on and power-off control of the storage device 730.

[0134] The first switch 720h mentioned above can be a metal-oxide-semiconductor field-effect transistor (MOSFET). Alternatively, the first switch 720h mentioned above can also be other components that are turned on or off upon triggering by a level signal.

[0135] In this embodiment, the test adapter 720 may be equipped with GPIO interface circuitry and switches to control the power-on and power-off of the storage device 730 during testing. In an exemplary embodiment, such as... Figure 11 As shown, when the tester needs to control the power-on / power-off of the storage device 730, the host 710 can send a power-on / power-off command (i.e., the aforementioned third control command, USB protocol format) to the first interface circuit 720a in the test adapter 720. The first bridge chip 720e1 receives the power-on / power-off command (USB protocol format) from the first interface circuit 720a, identifies the command type / command content of the power-on / power-off command, determines that it is a command to control the power-on or power-off of the storage device 730, generates a corresponding trigger signal according to the power-on / power-off command (the trigger signal is used to trigger the first GPIO interface circuit 720g to generate a corresponding level signal), and sends the trigger signal to the first GPIO interface circuit 720g. The first GPIO interface circuit 720g generates a first level signal according to the trigger signal and sends the first level signal to the first switch 720h. The first switch 720h is disconnected or connected under the trigger of the first level signal.

[0136] For example, taking the first switch 720h being turned on at a low level and turned off at a high level as an example, when the tester needs to control the power-on of the storage device 730, the host 710 can send a power-on command to the first interface circuit 720a. The first bridge chip 720e1 receives the power-on command from the first interface circuit 720a, generates a power-on trigger signal, and sends the trigger signal to the first GPIO interface circuit 720g. The first GPIO interface circuit 720g generates a low-level signal according to the trigger signal and sends the low-level signal to the first switch 720h. The first switch 720h is connected (or turned on) under the trigger of the low-level signal, thereby realizing the power-on of the storage device 730. Correspondingly, when the tester needs to power down the storage device 730, the host 710 can send a power-down command to the first interface circuit 720a. The first bridge chip 720e1 receives the power-down command from the first interface circuit 720a, generates a power-down trigger signal, and sends the trigger signal to the first GPIO interface circuit 720g. The first GPIO interface circuit 720g generates a high-level signal based on the trigger signal and sends the high-level signal to the first switch 720h. The first switch 720h is opened under the trigger of the high-level signal, thereby powering down the storage device 730.

[0137] In this embodiment, by embedding a first GPIO interface circuit 720g and a first switch 720h in the test adapter, and by using a bridge chip to trigger the first GPIO interface circuit 720g to send a level signal to the first switch 720h according to the power-on / off signal set on the host 710 side, the power-on / off of the storage device 730 is accurately and conveniently controlled, simplifying the complexity of the power-on / off control process of the storage device and ensuring the execution efficiency and flexibility of power-on / off control during the test process.

[0138] Based on the solutions shown in any one or more of the above embodiments, please refer to the following embodiments in some cases. Figure 12 It shows a structural diagram of a test adapter according to an embodiment of this application; as follows: Figure 12 As shown, the test adapter 720 also includes a second GPIO interface circuit 720i; the second GPIO interface circuit 720i is configured to be connected to the second target chip, and the second GPIO interface circuit 720i is configured to be connected to the fourth interface circuit 720d; the second target chip is one of the first bridge chip 720e1 and the second bridge chip 720e2. Figure 12 The second target chip is shown as the second bridge chip 720e2; the second target chip is configured to receive a fourth control command from the host 710 from the first interface circuit 720a, and trigger the second GPIO interface circuit 720i to send a second level signal to the storage device 730 through the fourth interface circuit 720d according to the fourth control command.

[0139] The second level signal mentioned above may include, but is not limited to, a PCIe Sideband signal; in some embodiments, the PCIe Sideband signal is used to implement PCIe Sideband control function during the testing of the storage device 730.

[0140] In one exemplary embodiment, such as Figure 12 As shown, when the tester needs to control the execution of PCIe Sideband management, the host 710 can send a PCIe Sideband management command (i.e., the fourth control command mentioned above, in USB protocol format) to the first interface circuit 720a in the test adapter 720. The second bridge chip 720e2 receives the PCIe Sideband management command (USB protocol format) from the first interface circuit 720a, identifies the command type / command content of the PCIe Sideband management command, determines that it is a command to execute PCIe Sideband management, generates the corresponding level signal (i.e., the second level signal mentioned above) according to the PCIe Sideband management command, and sends the level signal to the fourth interface circuit 720d to realize PCIe Sideband management.

[0141] In this embodiment, by embedding a second GPIO interface circuit 720i in the test adapter and using a bridge chip, the corresponding level signal of the PCIe Sideband control function is triggered according to the PCIe Sideband control signal set on the host 710 side, so as to accurately and conveniently trigger the PCIe Sideband control function, simplify the complexity of implementing the PCIe Sideband control function, and ensure the execution efficiency and flexibility of the PCIe Sideband control function during the test process.

[0142] Based on the solutions shown in any one or more of the above embodiments, please refer to the following embodiments in some cases. Figure 13 It shows a structural diagram of a test adapter according to an embodiment of this application; as follows: Figure 13 As shown, the first bridging chip 720e1 has a first connector 720e3; the first connector 720e3 is configured to connect to a programming device so that the programming device can rewrite the firmware of the first bridging chip 720e1 through the first connector 720e3; and / or, the second bridging chip 720e2 has a second connector 720e4; the second connector 720e4 is configured to connect to a programming device so that the programming device can rewrite the firmware of the second bridging chip 720e2 through the second connector 720e4.

[0143] In this embodiment, the bridging chip in the test connector 720 can reserve an external connector. When testers need to expand or modify the function of the test connector 720, they can connect the connector of the bridging chip through a programming device and rewrite the firmware of the bridging chip through the programming device, thereby flexibly expanding the function of the test connector 720 and improving the scalability of the test connector 720.

[0144] Based on the solutions shown in any one or more of the above embodiments, please refer to the following embodiments in some cases. Figure 14 It shows a structural diagram of a test adapter according to an embodiment of this application; as follows: Figure 14 As shown, the test adapter externally includes a Type-C interface 1401 (corresponding to the first interface circuit 720a), a DHMI interface 1402 (corresponding to the second interface circuit 720b), a PCI-E gold finger 1403 (corresponding to the third interface circuit 720c), and a U.2 connector 1404 (corresponding to the fourth interface circuit 720d); internally, the test adapter includes a USB bridge chip 1 (corresponding to the first bridge chip 720e1), a USB bridge chip 2 (corresponding to the second bridge chip 720e2), and an SMBus slave device 1405 (corresponding to one or more SMBus slave devices 720f); wherein, the USB bridge chip 1 and the USB bridge chip 2 are respectively connected via USB The HUB chip is connected to the Type-C interface 1401, and the USB bridge chip 1 is connected to the DHMI interface 1402. The SMBus slave device 1405 includes an ADC chip (corresponding to the aforementioned ADC chip 720f3), a sampling resistor (corresponding to the aforementioned sampling resistor 720f4), a DAC chip (corresponding to the aforementioned DAC chip 720f1), and a power supply chip (corresponding to the aforementioned power supply chip 720f2). Optionally, the SMBus slave device 1405 may also include other slave devices. The aforementioned USB bridge chip 1 and USB bridge chip 2 are respectively connected to GPIO circuits (not limited to the aforementioned first GPIO interface circuit 720g and second GPIO interface circuit 720i) and / or MOS (not limited to the aforementioned first switch 720h). In addition, the aforementioned USB bridge chip 1 and USB bridge chip 2 are respectively provided with connectors (not limited to the aforementioned first connector 720e3 and second connector 720e4) consisting of measurement points, PIN frames, and switching circuits. Figure 14 In the diagram, the double arrows indicate signal transmission lines, and the bolded lines indicate power transmission lines.

[0145] The above Figure 14 The test adapter shown has the following advantages:

[0146] 1) A test adapter integrates the circuits or components required to achieve a variety of different test functions; specifically, it uses an adapter card in the form of AIC-U2 as a carrier to integrate UART, JTAG, power-on / off, voltage biasing, current sampling and other functional circuits.

[0147] 2) Use two USB bridge chips instead of MCU or CPU to complete the above-mentioned test functions.

[0148] 3) By rationally allocating PCB resources and reserving DIP switch and connector positions (corresponding to the first connector 720e3 and the second connector 720e4 mentioned above), the hardware allows testers to perform secondary development according to their own needs.

[0149] Please refer to Figure 15 It shows a partial structural schematic diagram of the test connector involved in the embodiments of this application; as shown Figure 15 As shown in the embodiment of this application, the solution uses a Type-C interface to connect to the control PC (i.e., the host 710 mentioned above), and is split into two paths via a USB hub, each connected to a bridge chip. USB bridge chip 1 converts the SSD's UART signal into a USB signal to manage the SSD's debug information; simultaneously, USB bridge chip 2 converts the USB signal into an SMBus signal for PCIe-related NVMe-MI testing, voltage biasing, and sampling functions. In addition, both USB bridge chip 1 and USB bridge chip 2 have their own extended I / O. Testers can modify the driver code to implement various I / O configurations and basic controls. Furthermore, functions such as SSD power-off and PCIe Sideband management are also handled by GPIO.

[0150] Please refer to Figure 16 It shows a partial structural schematic diagram of the test connector involved in the embodiments of this application; as shown Figure 16 As shown, it illustrates the structure in the test connector that implements voltage biasing, voltage, and current sampling functions. The implementation scheme of the above-mentioned voltage biasing, voltage, and current sampling functions is based on the driver development of USB bridge chip 2 at the software level. The USB bridge chip 2 converts the USB command into an SMBus signal to control the DAC chip and ADC chip.

[0151] 1) Voltage bias function: The output of the DAC chip is connected to the FB pin of the power supply chip (such as the Buck-Boost chip). The host can control the output of the DAC chip through the USB bridge chip 2 to linearly adjust the output of the BUCK-Boost power supply.

[0152] 2) Voltage and current sampling function: The voltage value across the sampling resistor is transmitted to the ADC chip. The USB bridge chip 2 reads the analog voltage value through SMBus, and then converts it to obtain digital voltage and current values ​​before transmitting them to the host.

[0153] Based on the above Figures 14 to 16 The structure shown below will be used as an example to introduce the software implementation process of SSD testing based on the above test adapter, taking the four test functions of power-down control, bias control initialization, bias control and voltage sampling as examples.

[0154] I. Power-on / Power-off control implementation process.

[0155] Please refer to Figure 17 This diagram illustrates the power-on / power-off control implementation process according to an embodiment of this application. Figure 17 As shown, the power-on / power-off control process requires determining the GPIO signal values ​​based on the hardware connection scheme and then sending GPIO signals to power on and off the SSD. Specifically, the test software in the host needs to determine the serial port number used for power-off control and open the corresponding USB serial port (step S1701). If the USB serial port is occupied, opening will fail. If opening is successful, the test software first sets the power supply mode corresponding to the SSD (step S1702), and then configures the reset mode and level initialization state of the GPIO used (step S1703). Correct chip configuration is the basis for controlling power-on and power-off. Next, based on the GPIO configuration, the GPIO values ​​for the power-on and power-off states are calculated respectively. The operating system calls a function to send I / O signals (i.e., GPIO signals, containing the corresponding GPIO values ​​for the power-on or power-off states, corresponding to the third control instruction mentioned above) to the driver to control the power switch (step S1704). The driver sends power-on / power-off signals to the test adapter to realize the power-on and power-off of the test adapter and the SSD.

[0156] II. Bias control initialization implementation process.

[0157] Please refer to Figure 18 This diagram illustrates the bias control implementation process according to an embodiment of this application. Figure 18As shown, the bias control initialization process mainly initializes the chip. First, the test software queries the device handle (step S1801) to obtain the operation handle for the device (which can be a test adapter or a chip / circuit related to bias control within the test adapter). Specifically, for example, the test software searches the system for the required device based on the VID (supplier ID) and PID (product ID) of the bias control-related chip. If it does not exist, the software exits directly, confirming that the chip cannot be found. If the chip is found, the software confirms that the device has been discovered. At this point, the software can obtain the library version called by the software (step S1802) and check whether the version meets the requirements. If the requirements are met, the chip's I2C function and GPIO status are configured (step S1803) to initialize the chip.

[0158] III. Bias control implementation process.

[0159] Please refer to Figure 19 This diagram illustrates the bias control implementation process according to an embodiment of this application. Figure 19 As shown, the bias control implementation process mainly includes: controlling the slave device DAC chip to achieve bias output through the bridge chip, and controlling the slave device ADC chip to sample the bias output, so as to confirm whether the expected bias result has been achieved through the sampling result.

[0160] Specifically, when the tester inputs the desired analog voltage value, the test software first calculates the digital signal corresponding to the input analog voltage value according to the designed rules (step S1901), then sends a write request to the address of the slave device's ADC chip (step S1902), writing the digital signal value to the device. After successful writing, the software obtains the data transmission status of the current device (i.e., the aforementioned test adapter) (step S1903), and determines the current device's busy status based on the obtained result. If the device is busy, it indicates that the current command has failed. If the device is idle, the output voltage can be sampled (step S1904), and the sampled result can be checked to see if it matches the input voltage. If they match, it indicates that the voltage setting is successful, completing the entire closed-loop operation. This solution sets up a voltage sampling process, making it convenient for users to determine whether the voltage setting is successful and facilitating the implementation of automated testing processes.

[0161] IV. Voltage sampling implementation process.

[0162] Please refer to Figure 20 This diagram illustrates the bias control implementation process according to an embodiment of this application. Figure 20As shown, after the user successfully sets the bias voltage, the voltage sampling process begins. First, the test software sends a write request to the address of the slave device's ADC chip (step S2001), notifying the ADC chip to prepare data for the specific address. After successful writing, the software obtains the current data transmission status of the device (step S2002) and determines the current device's busy status based on the obtained result. If the device is busy, it indicates that the current command has failed. If the device is idle, the next step can be performed: a read request is sent to the address of the slave device's ADC chip (step S2003), and the read byte is sent (step S2004). Finally, the read result is obtained (step S2005), and the analog voltage value corresponding to the current obtained result is calculated according to the designed rules (step S2006), which is then provided to the next step to check the consistency between the sampled result and the input voltage.

[0163] An exemplary embodiment of this application also provides a testing system for a storage device. The testing system includes: a test adapter and a host; the test adapter includes a first interface circuit, a second interface circuit, a third interface circuit, a fourth interface circuit, a first bridge chip, and a second bridge chip; the first interface circuit and the third interface circuit are respectively configured to be connected to the host; the second interface circuit is configured to be connected to a debug information interface circuit of the storage device; the fourth interface circuit is configured to be connected to a data interface circuit of the storage device; the first bridge chip is configured to be connected to the first interface circuit and also to the second interface circuit; the second bridge chip is configured to be connected to the first interface circuit and also to the fourth interface circuit; the host is configured to send test control commands to the test adapter; the test adapter is configured to perform test operations on the storage device according to the test control commands via the first bridge chip and the second bridge chip.

[0164] The connection method between the host and the test adapter, the connection method between the test adapter and the storage device, and the internal structure of the test adapter can be referred to the above. Figures 7 to 16 The structure shown.

[0165] Based on the solutions shown in any one or more of the above embodiments, in some embodiments, the test adapter further includes at least one system management bus slave device; the second bridge chip is configured to be connected to the at least one system management bus slave device; the at least one system management bus slave device is configured to be connected to the fourth interface circuit.

[0166] Based on the solutions shown in any one or more of the above embodiments, in some embodiments, the test adapter is configured to receive a first control command from the host through the first bridge chip, convert the format of the first control command into the format of the protocol corresponding to the second interface circuit, and then send it to the storage device through the second interface circuit; the first control command instructs the storage device to perform a test-related first operation; the test adapter is configured to receive debugging information sent by the storage device from the second interface circuit through the first bridge chip, convert the format of the debugging information into the format of the protocol corresponding to the first interface circuit, and then send it to the host through the first interface circuit.

[0167] Based on the solutions shown in any one or more of the above embodiments, in some embodiments, the first control instruction includes at least one of the following instructions: an instruction to perform a Universal Asynchronous Receiver / Transmitter (UART) test; an instruction to perform a Joint Test Group (JTAG) test; and an instruction to perform a Non-Volatile Memory Extension Management Interface (NVMe-MI) test related to the Peripheral Component Interconnect Extension (PCI-E).

[0168] Based on the solutions shown in any one or more of the above embodiments, in some embodiments, the test adapter is configured to receive a second control command from the host through the second bridge chip, convert the format of the second control command into the format of the system management bus protocol, and send it to a target slave device, which is one or more of the at least one system management bus slave device; the test adapter is configured to perform a test-related second operation through the target slave device according to the second control command.

[0169] Based on the solutions shown in any one or more of the above embodiments, in some embodiments, the at least one system management bus slave device includes a digital-to-analog converter (DAC) chip and a power supply chip; the second bridge chip is configured to be connected to the DAC chip, the DAC chip is configured to be connected to the power supply chip, and the power supply chip is configured to be connected to the fourth interface circuit; when the second control command includes a bias control command, the test adapter is configured to convert the format of the bias control command into the format of the system management bus protocol through the second bridge chip and then send it to the DAC chip; the test adapter is configured to convert the digital voltage signal corresponding to the bias control command into an analog voltage signal through the DAC chip and then send it to the power supply chip; the test adapter is configured to control the voltage output to the fourth interface circuit according to the analog voltage signal through the power supply chip.

[0170] Based on the solutions shown in any one or more of the above embodiments, in some embodiments, the at least one system management bus slave device further includes an analog-to-digital converter (ADC) chip and a sampling resistor; the second bridge chip is configured to be connected to the ADC chip, the ADC chip is configured to be connected to the sampling resistor, and the sampling resistor is located on the circuit between the power supply chip and the fourth interface circuit; when the second control command includes a sampling command, the test adapter is configured to convert the format of the sampling command into the format of the system management bus protocol through the second bridge chip and then send it to the ADC chip; the test adapter is configured to sample at least one of the voltage and current of the sampling resistor through the ADC chip to obtain a sampled analog signal, convert the sampled analog signal into a sampled digital signal, and send the sampled digital signal to the second bridge chip according to the sampling command; the test adapter is also configured to convert the format of the sampled digital signal into the format of the protocol corresponding to the first interface circuit through the second bridge chip and then send the sampled digital signal to the host through the first interface circuit.

[0171] Based on the solutions shown in any one or more of the above embodiments, in some embodiments, the test adapter further includes a first general purpose input / output (GPIO) interface circuit and a first switch; the first GPIO interface circuit is configured to be connected to a first target chip, and the first GPIO interface circuit is configured to be connected to the first switch, the first switch being located on the power supply circuit of the test adapter to the storage device; the first target chip is one of the first bridge chip and the second bridge chip; the test adapter is configured to receive a third control command from the host through the first target chip from the first interface circuit, and trigger the first GPIO interface circuit to send a first level signal to the first switch according to the third control command, the first level signal being configured to trigger the first switch to disconnect or connect, so as to realize the power-on and power-off control of the storage device.

[0172] Based on the solutions shown in any one or more of the above embodiments, in some embodiments, the test adapter further includes a second GPIO interface circuit; the second GPIO interface circuit is configured to be connected to a second target chip, and the second GPIO interface circuit is configured to be connected to the fourth interface circuit; the second target chip is one of the first bridge chip and the second bridge chip; the test adapter is configured to receive a fourth control command from the host through the second target chip from the first interface circuit, and trigger the second GPIO interface circuit to send a second level signal to the storage device through the fourth interface circuit according to the fourth control command.

[0173] Based on the solutions shown in any one or more of the above embodiments, in some embodiments, the first bridge chip has a first connector; the first connector is configured to connect to a programming device so that the programming device can rewrite the firmware of the first bridge chip through the first connector; and / or, the second bridge chip has a second connector; the second connector is configured to connect to a programming device so that the programming device can rewrite the firmware of the second bridge chip through the second connector.

[0174] Please refer to Figure 21 This document illustrates a flowchart of a testing method for a storage device provided in an exemplary embodiment of this application. The method is executed by a test adapter, which includes a first interface circuit, a second interface circuit, a third interface circuit, a fourth interface circuit, a first bridge chip, and a second bridge chip. The first and third interface circuits are respectively configured to be connected to a host. The second interface circuit is configured to be connected to a debug information interface circuit of the storage device. The fourth interface circuit is configured to be connected to a data interface circuit of the storage device. The first bridge chip is configured to be connected to the first interface circuit and also to the second interface circuit. The second bridge chip is configured to be connected to the first interface circuit and also to the fourth interface circuit. The connection method between the host and the test adapter, the connection method between the test adapter and the storage device, and the internal structure of the test adapter can be referenced above. Figures 7 to 16 The structure shown. (As illustrated) Figure 21 As shown, the method includes steps 2101 and 2102.

[0175] Step 2101: Receive test control commands sent by the host through the first bridge chip and the second bridge chip.

[0176] Step 2102: Through the first bridge chip and the second bridge chip, perform test operations on the storage device according to the test control command.

[0177] Based on the solutions shown in any one or more of the above embodiments, in some embodiments, the test adapter further includes at least one system management bus slave device; the second bridge chip is connected to the at least one system management bus slave device; and the at least one system management bus slave device is connected to the fourth interface circuit.

[0178] Based on the solutions shown in any one or more of the above embodiments, in some embodiments, receiving test control commands sent by the host through the first bridge chip and the second bridge chip includes: receiving a first control command from the host through the first interface circuit through the first bridge chip, converting the format of the first control command into the format of the protocol corresponding to the second interface circuit, and then sending it to the storage device through the second interface circuit; the first control command instructing the storage device to perform a test-related first operation; receiving debugging information sent by the storage device through the second interface circuit through the first bridge chip, converting the format of the debugging information into the format of the protocol corresponding to the first interface circuit, and then sending it to the host through the first interface circuit.

[0179] Based on the solutions shown in any one or more of the above embodiments, in some embodiments, the first control instruction includes at least one of the following instructions: an instruction to perform a Universal Asynchronous Receiver / Transmitter (UART) test; an instruction to perform a Joint Test Group (JTAG) test; and an instruction to perform a Non-Volatile Memory Extension Management Interface (NVMe-MI) test related to the Peripheral Component Interconnect Extension (PCI-E).

[0180] Based on the solutions shown in any one or more of the above embodiments, in some embodiments, receiving test control commands sent by the host through the first bridge chip and the second bridge chip includes: receiving a second control command from the host through the second bridge chip, converting the format of the second control command into the format of the system management bus protocol, and sending it to a target slave device, wherein the target slave device is one or more of the at least one system management bus slave device; and performing a test-related second operation through the target slave device according to the second control command.

[0181] Based on the solutions shown in any one or more of the above embodiments, in some embodiments, the at least one system management bus slave device includes a digital-to-analog converter (DAC) chip and a power supply chip; the second bridge chip is configured to be connected to the DAC chip, the DAC chip is configured to be connected to the power supply chip, and the power supply chip is configured to be connected to the fourth interface circuit; the conversion of the format of the second control command into the format of the system management bus protocol and sending it to the target slave device includes: if the second control command includes a bias control command, converting the format of the bias control command into the format of the system management bus protocol through the second bridge chip and sending it to the DAC chip; the execution of a test-related second operation by the target slave device according to the second control command includes: converting the digital voltage signal corresponding to the bias control command into an analog voltage signal through the DAC chip and sending it to the power supply chip; and controlling the voltage output to the fourth interface circuit by the power supply chip according to the analog voltage signal.

[0182] Based on the solutions shown in any one or more of the above embodiments, in some embodiments, the at least one system management bus slave device further includes an analog-to-digital converter (ADC) chip and a sampling resistor; the second bridge chip is configured to be connected to the ADC chip, the ADC chip is configured to be connected to the sampling resistor, and the sampling resistor is located on the circuit between the power supply chip and the fourth interface circuit; the step of converting the format of the second control instruction into the format of the system management bus protocol and sending it to the target slave device includes: when the second control instruction includes a sampling instruction, converting the format of the sampling instruction into the format of the system management bus protocol through the second bridge chip and then sending it to the ADC chip; the step of the target slave device performing a test-related second operation according to the second control instruction includes: sampling at least one of the voltage and current of the sampling resistor through the ADC chip to obtain a sampled analog signal, converting the sampled analog signal into a sampled digital signal, and sending the sampled digital signal to the second bridge chip according to the sampling instruction; the method further includes: converting the format of the sampled digital signal to the format of the protocol corresponding to the first interface circuit through the second bridge chip, and then sending the sampled digital signal to the host through the first interface circuit.

[0183] Based on the solutions shown in any one or more of the above embodiments, in some embodiments, the test adapter further includes a first general purpose input / output (GPIO) interface circuit and a first switch; the first GPIO interface circuit is configured to be connected to a first target chip, and the first GPIO interface circuit is configured to be connected to the first switch, the first switch being located on the power supply circuit of the test adapter to the storage device; the first target chip is one of the first bridge chip and the second bridge chip; receiving test control commands sent by the host through the first bridge chip and the second bridge chip includes: receiving a third control command from the host through the first interface circuit via the first target chip; performing test operations on the storage device according to the test control command through the first bridge chip and the second bridge chip includes: triggering the first GPIO interface circuit to send a first level signal to the first switch through the first target chip according to the third control command, the first level signal being configured to trigger the first switch to disconnect or connect, so as to realize the power-on and power-off control of the storage device.

[0184] Based on the solutions shown in any one or more of the above embodiments, in some embodiments, the test adapter further includes a second GPIO interface circuit; the second GPIO interface circuit is configured to be connected to a second target chip, and the second GPIO interface circuit is configured to be connected to the fourth interface circuit; the second target chip is one of the first bridge chip and the second bridge chip; receiving test control commands sent by the host through the first bridge chip and the second bridge chip includes: receiving a fourth control command from the host through the second target chip from the first interface circuit; performing test operations on the storage device according to the test control command through the first bridge chip and the second bridge chip includes: triggering the second GPIO interface circuit to send a second level signal to the storage device through the fourth interface circuit through the fourth interface circuit via the second target chip according to the fourth control command.

[0185] In this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. The term "at least one" refers to one or more, and the term "multiple" refers to two or more, unless otherwise expressly defined. The term "and / or" in this application is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Furthermore, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0186] The above description is merely an exemplary embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A test adapter for a storage device, characterized in that, The test adapter includes a first interface circuit, a second interface circuit, a third interface circuit, a fourth interface circuit, a first bridge chip, and a second bridge chip. The first interface circuit and the third interface circuit are respectively configured to be connected to the host; the second interface circuit is configured to be connected to the debug information interface circuit of the storage device; the fourth interface circuit is configured to be connected to the data interface circuit of the storage device. The first bridging chip is configured to be connected to the first interface circuit, and the first bridging chip is configured to be connected to the second interface circuit; the second bridging chip is configured to be connected to the first interface circuit, and the second bridging chip is configured to be connected to the fourth interface circuit. The first bridging chip and the second bridging chip are configured to perform test operations on the storage device according to test control commands sent by the host.

2. The test adapter according to claim 1, characterized in that, The test adapter also includes at least one system management bus slave device; The second bridge chip is configured to connect to the at least one system management bus slave device; the at least one system management bus slave device is configured to connect to the fourth interface circuit.

3. The test adapter according to claim 1 or 2, characterized in that, The first bridging chip is configured to receive a first control command from the host from the first interface circuit, convert the format of the first control command into the format of the protocol corresponding to the second interface circuit, and then send it to the storage device through the second interface circuit; the first control command instructs the storage device to perform a test-related first operation; The first bridging chip is configured to receive debugging information sent by the storage device from the second interface circuit, convert the format of the debugging information into the format of the protocol corresponding to the first interface circuit, and then send it to the host through the first interface circuit.

4. The test adapter according to claim 3, characterized in that, The first control command includes at least one of the following commands: Instructions to perform a Universal Asynchronous Receiver / Transmitter (UART) test; Instructions to execute JTAG tests by the Joint Test Working Group; Instructions are given to perform NVMe-MI tests on the peripheral component interconnect expansion PCI-E related non-volatile memory expansion management interface circuitry.

5. The test adapter according to claim 2, characterized in that, The second bridge chip is configured to receive a second control command from the host from the first interface circuit, convert the format of the second control command into the format of the system management bus protocol, and then send it to a target slave device, wherein the target slave device is one or more of the at least one system management bus slave device; The target device is configured to perform a second test-related operation according to the second control command.

6. The test adapter according to claim 5, characterized in that, The at least one system management bus slave device includes a digital-to-analog converter (DAC) chip and a power supply chip; The second bridge chip is configured to be connected to the DAC chip, the DAC chip is configured to be connected to the power chip, and the power chip is configured to be connected to the fourth interface circuit. When the second control command includes a bias control command, the second bridge chip is configured to convert the format of the bias control command into the format of the system management bus protocol and then send it to the DAC chip. The DAC chip is configured to convert the digital voltage signal corresponding to the bias control command into an analog voltage signal and then send it to the power supply chip. The power chip is configured to control the voltage output to the fourth interface circuit according to the analog voltage signal.

7. The test adapter according to claim 6, characterized in that, The at least one system management bus slave device also includes an analog-to-digital converter (ADC) chip and a sampling resistor; The second bridge chip is configured to be connected to the ADC chip, the ADC chip is configured to be connected to the sampling resistor, and the sampling resistor is located in the circuit between the power chip and the fourth interface circuit; When the second control command includes a sampling command, the second bridge chip is configured to convert the format of the sampling command into the format of the system management bus protocol and then send it to the ADC chip. The ADC chip is configured to sample at least one of the voltage and current of the sampling resistor to obtain a sampled analog signal, convert the sampled analog signal into a sampled digital signal, and send the sampled digital signal to the second bridge chip according to the sampling instruction. The second bridge chip is further configured to convert the format of the sampled digital signal to the format of the protocol corresponding to the first interface circuit, and then send the sampled digital signal to the host through the first interface circuit.

8. The test adapter according to claim 1 or 2, characterized in that, The test adapter also includes a first general-purpose input / output (GPIO) interface circuit and a first switch; The first GPIO interface circuit is configured to be connected to the first target chip, and the first GPIO interface circuit is configured to be connected to the first switch, which is located on the power supply circuit of the test adapter to the storage device; the first target chip is one of the first bridge chip and the second bridge chip; The first target chip is configured to receive a third control command from the host from the first interface circuit, and trigger the first GPIO interface circuit to send a first level signal to the first switch according to the third control command. The first level signal is configured to trigger the first switch to disconnect or connect, so as to realize the power-on and power-off control of the storage device.

9. The test adapter according to claim 1 or 2, characterized in that, The test adapter also includes a second GPIO interface circuit; The second GPIO interface circuit is configured to be connected to the second target chip, and the second GPIO interface circuit is also configured to be connected to the fourth interface circuit; the second target chip is one of the first bridge chip and the second bridge chip. The second target chip is configured to receive a fourth control command from the host from the first interface circuit, and trigger the second GPIO interface circuit to send a second level signal to the storage device through the fourth interface circuit according to the fourth control command.

10. The test adapter according to claim 1 or 2, characterized in that, The first bridge chip has a first connector; the first connector is configured to connect to a programming device so that the programming device can rewrite the firmware of the first bridge chip through the first connector; And / or, The second bridge chip has a second connector; the second connector is configured to connect to a programming device so that the programming device can rewrite the firmware of the second bridge chip through the second connector.

11. A testing system for a storage device, characterized in that, The testing system includes: a test adapter and a host computer; The test adapter includes a first interface circuit, a second interface circuit, a third interface circuit, a fourth interface circuit, a first bridge chip, and a second bridge chip. The first interface circuit and the third interface circuit are respectively configured to be connected to the host; the second interface circuit is configured to be connected to the debug information interface circuit of the storage device; the fourth interface circuit is configured to be connected to the data interface circuit of the storage device. The first bridging chip is configured to be connected to the first interface circuit, and the first bridging chip is configured to be connected to the second interface circuit; the second bridging chip is configured to be connected to the first interface circuit, and the second bridging chip is configured to be connected to the fourth interface circuit. The host is configured to send test control commands to the test adapter; The test adapter is configured to perform test operations on the storage device according to the test control instructions via the first bridge chip and the second bridge chip.

12. The testing system according to claim 11, characterized in that, The test adapter also includes at least one system management bus slave device; The second bridge chip is configured to connect to the at least one system management bus slave device; the at least one system management bus slave device is configured to connect to the fourth interface circuit.

13. The testing system according to claim 11 or 12, characterized in that, The test adapter is configured to receive a first control command from the host through the first bridge chip, convert the format of the first control command into the format of the protocol corresponding to the second interface circuit, and then send it to the storage device through the second interface circuit; the first control command instructs the storage device to perform a test-related first operation; The test adapter is configured to receive debugging information sent by the storage device from the second interface circuit through the first bridge chip, convert the format of the debugging information into the format of the protocol corresponding to the first interface circuit, and then send it to the host through the first interface circuit.

14. The testing system according to claim 13, characterized in that, The first control command includes at least one of the following commands: Instructions to perform a Universal Asynchronous Receiver / Transmitter (UART) test; Instructions to execute JTAG tests by the Joint Test Working Group; Instructions are given to perform NVMe-MI tests on the peripheral component interconnect expansion PCI-E related non-volatile memory expansion management interface circuitry.

15. The testing system according to claim 12, characterized in that, The test adapter is configured to receive a second control command from the host through the second bridge chip, convert the format of the second control command into the format of the system management bus protocol, and send it to a target slave device, wherein the target slave device is one or more of the at least one system management bus slave device; The test adapter is configured to perform a second test-related operation via the target slave device, according to the second control command.

16. The testing system according to claim 15, characterized in that, The at least one system management bus slave device includes a digital-to-analog converter (DAC) chip and a power supply chip; The second bridge chip is configured to be connected to the DAC chip, the DAC chip is configured to be connected to the power chip, and the power chip is configured to be connected to the fourth interface circuit. When the second control command includes a bias control command, the test adapter is configured to convert the format of the bias control command into the format of the system management bus protocol via the second bridge chip and then send it to the DAC chip. The test adapter is configured to convert the digital voltage signal corresponding to the bias control command into an analog voltage signal via the DAC chip and then send it to the power supply chip. The test adapter is configured to control the voltage output to the fourth interface circuit via the power chip, based on the analog voltage signal.

17. The testing system according to claim 16, characterized in that, The at least one system management bus slave device also includes an analog-to-digital converter (ADC) chip and a sampling resistor; The second bridge chip is configured to be connected to the ADC chip, the ADC chip is configured to be connected to the sampling resistor, and the sampling resistor is located in the circuit between the power chip and the fourth interface circuit; When the second control command includes a sampling command, the test adapter is configured to convert the format of the sampling command into the format of the system management bus protocol via the second bridge chip and then send it to the ADC chip. The test adapter is configured to sample at least one of the voltage and current of the sampling resistor through the ADC chip to obtain a sampled analog signal, convert the sampled analog signal into a sampled digital signal, and send the sampled digital signal to the second bridge chip according to the sampling instruction. The test adapter is further configured to convert the format of the sampled digital signal into the format of the protocol corresponding to the first interface circuit via the second bridge chip, and then send the sampled digital signal to the host via the first interface circuit.

18. The testing system according to claim 11 or 12, characterized in that, The test adapter also includes a first general-purpose input / output (GPIO) interface circuit and a first switch; The first GPIO interface circuit is configured to be connected to the first target chip, and the first GPIO interface circuit is configured to be connected to the first switch, which is located on the power supply circuit of the test adapter to the storage device; the first target chip is one of the first bridge chip and the second bridge chip; The test adapter is configured to receive a third control command from the host through the first target chip and the first interface circuit, and trigger the first GPIO interface circuit to send a first level signal to the first switch according to the third control command. The first level signal is configured to trigger the first switch to disconnect or connect, so as to control the power-on and power-off of the storage device.

19. The testing system according to claim 11 or 12, characterized in that, The test adapter also includes a second GPIO interface circuit; The second GPIO interface circuit is configured to be connected to the second target chip, and the second GPIO interface circuit is also configured to be connected to the fourth interface circuit; the second target chip is one of the first bridge chip and the second bridge chip. The test adapter is configured to receive a fourth control command from the host through the second target chip from the first interface circuit, and trigger the second GPIO interface circuit to send a second level signal to the storage device through the fourth interface circuit according to the fourth control command.

20. The testing system according to claim 11 or 12, characterized in that, The first bridge chip has a first connector; the first connector is configured to connect to a programming device so that the programming device can rewrite the firmware of the first bridge chip through the first connector; And / or, The second bridge chip has a second connector; the second connector is configured to connect to a programming device so that the programming device can rewrite the firmware of the second bridge chip through the second connector.

21. A testing method for a storage device, characterized in that, The method is performed by a test adapter, which includes a first interface circuit, a second interface circuit, a third interface circuit, a fourth interface circuit, a first bridge chip, and a second bridge chip. The first interface circuit and the third interface circuit are respectively configured to be connected to the host; the second interface circuit is configured to be connected to the debug information interface circuit of the storage device; the fourth interface circuit is configured to be connected to the data interface circuit of the storage device; the first bridging chip is configured to be connected to the first interface circuit and the second interface circuit; the second bridging chip is configured to be connected to the first interface circuit and the fourth interface circuit. The method includes: The test control commands sent by the host are received through the first bridge chip and the second bridge chip. The test operation on the storage device is executed according to the test control command through the first bridge chip and the second bridge chip.

22. The method according to claim 21, characterized in that, The test adapter also includes at least one system management bus slave device; The second bridge chip is connected to the at least one system management bus slave device; the at least one system management bus slave device is connected to the fourth interface circuit.

23. The method according to claim 21 or 22, characterized in that, The step of receiving test control commands sent by the host through the first bridging chip and the second bridging chip includes: The first control command is received from the host through the first bridge chip and converted into the format of the protocol corresponding to the second interface circuit. Then, it is sent to the storage device through the second interface circuit. The first control command instructs the storage device to perform a test-related first operation. The first bridging chip receives debugging information sent by the storage device from the second interface circuit, converts the format of the debugging information into the format of the protocol corresponding to the first interface circuit, and then sends it to the host through the first interface circuit.

24. The method according to claim 23, characterized in that, The first control command includes at least one of the following commands: Instructions to perform a Universal Asynchronous Receiver / Transmitter (UART) test; Instructions to execute JTAG tests by the Joint Test Working Group; Instructions are given to perform NVMe-MI tests on the peripheral component interconnect expansion PCI-E related non-volatile memory expansion management interface circuitry.

25. The method according to claim 22, characterized in that, The step of receiving test control commands sent by the host through the first bridging chip and the second bridging chip includes: The second bridge chip receives a second control command from the host from the first interface circuit, converts the format of the second control command into the format of the system management bus protocol, and sends it to the target slave device, wherein the target slave device is one or more of the at least one system management bus slave device; The target device performs a test-related second operation according to the second control command.

26. The method according to claim 25, characterized in that, The at least one system management bus slave device includes a digital-to-analog converter (DAC) chip and a power supply chip; The second bridge chip is configured to be connected to the DAC chip, the DAC chip is configured to be connected to the power chip, and the power chip is configured to be connected to the fourth interface circuit. The step of converting the format of the second control command into the format of the system management bus protocol and sending it to the target slave device includes: When the second control command includes a bias control command, the second bridge chip converts the format of the bias control command into the format of the system management bus protocol and then sends it to the DAC chip. The second test-related operation performed by the target slave device according to the second control command includes: The DAC chip converts the digital voltage signal corresponding to the bias control command into an analog voltage signal and then sends it to the power supply chip. The power chip controls the voltage output to the fourth interface circuit based on the analog voltage signal.

27. The method according to claim 26, characterized in that, The at least one system management bus slave device also includes an analog-to-digital converter (ADC) chip and a sampling resistor; The second bridge chip is configured to be connected to the ADC chip, the ADC chip is configured to be connected to the sampling resistor, and the sampling resistor is located in the circuit between the power chip and the fourth interface circuit; The step of converting the format of the second control command into the format of the system management bus protocol and sending it to the target slave device includes: When the second control command includes a sampling command, the second bridge chip converts the format of the sampling command into the format of the system management bus protocol and then sends it to the ADC chip. The second test-related operation performed by the target slave device according to the second control command includes: The ADC chip samples at least one of the voltage and current of the sampling resistor to obtain a sampled analog signal, converts the sampled analog signal into a sampled digital signal, and sends the sampled digital signal to the second bridge chip according to the sampling instruction. The method further includes: After the second bridging chip converts the format of the sampled digital signal to the format of the protocol corresponding to the first interface circuit, the sampled digital signal is sent to the host through the first interface circuit.

28. The method according to claim 21 or 22, characterized in that, The test adapter also includes a first general-purpose input / output (GPIO) interface circuit and a first switch; The first GPIO interface circuit is configured to be connected to the first target chip, and the first GPIO interface circuit is configured to be connected to the first switch, which is located on the power supply circuit of the test adapter to the storage device; the first target chip is one of the first bridge chip and the second bridge chip; The step of receiving test control commands sent by the host through the first bridging chip and the second bridging chip includes: The first target chip receives a third control command from the host computer through the first interface circuit. The step of performing test operations on the storage device according to the test control instructions through the first bridge chip and the second bridge chip includes: The first target chip triggers the first GPIO interface circuit to send a first level signal to the first switch according to the third control instruction. The first level signal is configured to trigger the first switch to disconnect or connect, so as to control the power-on and power-off of the storage device.

29. The method according to claim 21 or 22, characterized in that, The test adapter also includes a second GPIO interface circuit; The second GPIO interface circuit is configured to be connected to the second target chip, and the second GPIO interface circuit is also configured to be connected to the fourth interface circuit; the second target chip is one of the first bridge chip and the second bridge chip. The step of receiving test control commands sent by the host through the first bridging chip and the second bridging chip includes: The second target chip receives a fourth control command from the host computer from the first interface circuit. The step of performing test operations on the storage device according to the test control instructions through the first bridge chip and the second bridge chip includes: The second target chip triggers the second GPIO interface circuit to send a second level signal to the storage device through the fourth interface circuit according to the fourth control instruction.

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