Hybrid observation methods, devices, and systems supporting dual-path observation

Abstract

This application discloses a hybrid observation method, apparatus, and system supporting dual-pathway operation. The method includes: receiving a target operation request, which is either a request received from the system layer in the running convergence path or a request based on a reconfigurable scanning network mechanism received in the test access path; parsing the target operation request into a target standard internal transaction packet, determining the target logical address space of the target observation point corresponding to the target standard internal transaction packet at the observation point layer, and performing conflict detection and arbitration processing on the target observation point, wherein the target logical address space is a globally unified logical address space; and obtaining observation values ​​and their data validity from the target observation point according to the target logical address space. This application solves the technical problem of concurrent conflicts between the scanning access path and the running convergence path in related technologies.

Description

Technical Field

[0001] This application relates to the field of chip technology, and more specifically, to a hybrid observation method, apparatus, and system that supports dual-pathway observation. Background Technology

[0002] This section is intended to provide background or context for the content set forth in the claims or specification, and the content described herein is not acknowledged as prior art simply because it is included in this section.

[0003] With the exponential growth in the integration of System-on-Chip (SoC) and multiprocessor systems, integrated circuits at advanced process nodes face severe physical and operational challenges, including process deviations, aging effects, dynamic voltage drops, and complex uneven thermal distribution. To achieve full silicon lifecycle management, from chip manufacturing and testing to yield improvement and actual field operation, modern SoC architectures integrate a massive number of on-chip observation points. These observation points are used to collect real-time telemetry data such as temperature, voltage, path delay margin, and signal crosstalk within the chip to support Dynamic Voltage and Frequency Scaling (DVFS), Adaptive Voltage Scaling (AVS), and predictive maintenance.

[0004] However, existing on-chip observation infrastructures suffer from severe fragmentation in their data access path design. Typically, there are two completely independent observation and configuration paths within a chip: the first is a reconfigurable serial scan test path (or scan access path) based on the IEEE 1149.1 (JTAG) and IEEE 1687 (IJTAG) standards, designed specifically for manufacturing test and external debugger / ATE equipment; the second is a converged runtime path based on system memory-mapped buses (such as AMBA, AXI, and APB buses) and direct memory access (DMA), designed specifically for the on-chip embedded operating system or system controller processor (SCP) runtime.

[0005] This binary opposition in the architecture leads to the following technical problems: First, the semantics and control of the observation path are highly separated, which can easily lead to fatal concurrent conflicts. In existing designs, the address space, trigger semantics, and read / write timing of the scan test path and the bus operation path are completely independent and unaware of each other. When an external test probe attempts to read or reconfigure a certain underlying hardware observation point through the scan chain, if the internal software of the system happens to also initiate an access to the same hardware register through the system bus, data races will inevitably occur due to the lack of a unified control plane and hardware-level anti-collision arbitration mechanism. Such concurrent operations will disrupt the state machine inside the observation point, resulting in the reading of metastable garbled data, or even causing the system bus to hang or an unrecoverable system-level failure.

[0006] Second, data consistency and topology state across power domains are difficult to guarantee. Modern low-power SoC designs are typically divided into dozens or even hundreds of independent power domains and clock domains. During complex system power management scheduling, when a power domain containing a large number of observation nodes is dynamically power-gated or its clock is clock-gated, if the system software's DMA controller or external test links still attempt to access that area, not only will illegal bus responses occur, but the topology state of IEEE 1687-based scan network segment insertion will also be completely lost. Traditional two-stage trigger synchronization schemes or simple level clamp isolation schemes cannot automatically restore complex routing topologies after power-on, leading to a disconnect between hardware and software states.

[0007] There is currently no effective solution to the above problems. Summary of the Invention

[0008] This application provides a hybrid observation method, apparatus, and system that supports dual-pathway operation, so as to at least solve the technical problem of concurrent conflicts between the scanning access path and the running convergence path in related technologies.

[0009] According to one aspect of the embodiments of this application, a hybrid observation system supporting dual paths is provided, comprising: a running convergence path for receiving target operation requests from the system layer; a test access path for receiving target operation requests based on a reconfigurable scanning network mechanism; an observation point layer for providing observation values ​​of target observation points and their data validity; and a unified addressing and control layer for: parsing the target operation request into a target standard internal transaction packet, determining the target logical address space of the target observation point corresponding to the target standard internal transaction packet in the observation point layer, and performing conflict detection and arbitration processing on the target observation point, wherein the target logical address space is a globally unified logical address space.

[0010] Optionally, the unified addressing and control layer includes: a unified transaction abstraction center, used to parse target operation requests into target standard internal transaction packets; an observation address mapper, used to find the target logical address space of the target observation point corresponding to the target standard internal transaction packet; and a global arbitration and latching unit, used to arbitrate and intercept operation requests that access the same target observation point using hardware transaction monitoring and exclusive access mechanisms.

[0011] Optionally, the unified transaction abstraction center has a built-in instruction parser for parsing operation requests. The instruction parser records the mapping relationship between various operations in the operation request and standard internal transaction packets. The standard internal transaction packet includes the source identifier, transaction type, address of the target monitoring group, offset of the physical node, and standard internal micro-instructions of the data payload. The observation addressing mapper has a built-in LUT lookup table, which is used to map physical nodes to a globally unified logical address space. The observation addressing mapper uses the LUT lookup table to find the target logical address space of the target observation point corresponding to the target standard internal transaction packet. The global arbitration and latching unit is used to: record the identifier of the master device initiating the access and the logical address space being accessed when the target standard internal transaction packet indicates an exclusive read transaction; during the processing of the exclusive read transaction, if a write instruction to the accessed logical address space is received from another device, the write instruction is rejected; when multiple devices initiate access to the accessed logical address space, the lower priority among the multiple devices is physically blocked by using the handshake backpressure mechanism of the bus protocol or by forcing the TAP state machine to suspend.

[0012] Optionally, the observation point layer includes multiple monitoring groups and corresponding monitoring group interfaces. Each monitoring group includes multiple physical nodes, and each physical node includes: a sensor for collecting observation signals from the observation point; a local monitoring interface for converting the observation signals from the observation point into observation values; and an SIB module for providing the dynamic network topology bypass and cut-in capabilities required based on the reconfigurable scanning network mechanism.

[0013] Optionally, the running convergence path includes: a DMA ring buffer manager, which maintains a base address, depth, hardware tail pointer, and software head pointer at the hardware layer. This is used to write aligned burst data directly to system memory with zero copy through hardware pointer increment and modular rollback for consumption by the operating system or SCP. After the monitoring group interface collects and packages the burst data, the DMA ring buffer manager uses AXI incremental addressing to write the payload to the physical memory pointed to by the hardware tail pointer and automatically increments the address. When the hardware tail pointer reaches the set boundary, the hardware comparator uses a modular rollback circuit to force it to roll back and reset to the base address. The aligned burst data includes observations.

[0014] Optionally, the test access path includes: a TAP controller for compatibility with standard JTAG timing finite state machines, thereby supporting ATE devices or low-level security debug probes in the manufacturing plant; and a bridge for compatibility with IEEE 1149.1 and IEEE 1687 protocols.

[0015] According to another aspect of the embodiments of this application, a hybrid observation method supporting dual paths is also provided, comprising: receiving a target operation request, wherein the target operation request is a request received from the system layer in the running convergence path or a request based on a reconfigurable scanning network mechanism received in the test access path; parsing the target operation request into a target standard internal transaction packet, determining the target logical address space of the target observation point corresponding to the target standard internal transaction packet at the observation point layer, and performing conflict detection and arbitration processing on the target observation point, wherein the target logical address space is a globally unified logical address space; and obtaining the observation value and its data validity from the target observation point according to the target logical address space.

[0016] Optionally, conflict detection and arbitration are performed on the target observation point, including: when the transaction packet within the target standard indicates an exclusive read transaction, recording the identifier of the master device initiating the access and the accessed logical address space; during the processing of the exclusive read transaction, if a write instruction to the accessed logical address space is received from another device, the write instruction is rejected; when multiple devices initiate access to the logical address space, the lower priority among the multiple devices is physically blocked by using the handshake backpressure mechanism of the bus protocol or by forcing the TAP state machine to suspend.

[0017] According to another aspect of the embodiments of this application, a hybrid observation device supporting dual paths is also provided, comprising: a receiving unit, configured to receive a target operation request, wherein the target operation request is a request received from the system layer in the running convergence path or a request based on a reconfigurable scanning network mechanism received in the test access path; a control unit, configured to parse the target operation request into a target standard internal transaction packet, determine the target logical address space of the target observation point corresponding to the target standard internal transaction packet at the observation point layer, and perform conflict detection and arbitration processing on the target observation point, wherein the target logical address space is a globally unified logical address space; and an acquisition unit, configured to acquire observation values ​​and their data validity from the target observation point according to the target logical address space.

[0018] According to another aspect of the embodiments of this application, a computer-readable storage medium is also provided, the storage medium including a stored program that executes the above-described method when the program is run.

[0019] According to another aspect of the embodiments of this application, an electronic device is also provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor performs the above-described method through the computer program.

[0020] According to one aspect of this application, a computer program product or computer program is provided, comprising computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform the steps of any of the embodiments of the methods described above.

[0021] In this embodiment, a target operation request is received. The target operation request is a request received from the system layer in the running convergence path or a request based on the reconfigurable scanning network mechanism received in the test access path. The target operation request is parsed into a target standard internal transaction packet. The target logical address space of the target observation point corresponding to the target standard internal transaction packet in the observation point layer is determined. Conflict detection and arbitration are performed on the target observation point. The target logical address space is a globally unified logical address space. The observation value and its data validity are obtained from the target observation point according to the target logical address space, thereby solving the technical problem of concurrent conflicts between the scanning access path and the running convergence path in related technologies. Attached Figure Description

[0022] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings: Figure 1 This is a flowchart of a hybrid observation method supporting dual paths according to an embodiment of this application; Figure 2 This is a schematic diagram of a hybrid observation system supporting dual paths according to an embodiment of this application; Figure 3 This is a schematic diagram of a hybrid observation device supporting dual paths according to an embodiment of this application; Figure 4 This is a structural block diagram of a terminal according to an embodiment of this application. Detailed Implementation

[0023] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0024] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0025] First, some nouns or terms that appear in the description of the embodiments of this application shall be interpreted as follows: The IEEE 1687 Reconfigurable Scan Network (IJTAG) mechanism addresses the issue that in traditional integrated circuit testing, the test data registers (TDRs) of all on-chip instruments are typically chained together in a very long JTAG boundary scan chain. As the number of on-chip instruments increases dramatically, the shifting time becomes unacceptable. To address this, the IEEE 1687 standard defines a Reconfigurable Scan Network (RSN) architecture. This architecture introduces a Segment Insertion Bit (SIB) as a core programmable element. The SIB is essentially a hardware selector controlled by the scan chain. When a scan instruction configures a specific SIB to an "asserted" (logic 1) state, the local sub-scan chain connected to that SIB (containing specific sensor TDRs) is dynamically added to the main scan path; when configured to an "de-asserted" (logic 0) state, the sub-chain is bypassed. Through hierarchical cascading of SIBs, the test software can dynamically reconfigure the length and direction of the scan chain according to current needs, significantly shortening the data shifting path.

[0026] DMA Hardware Ring Buffer Architecture: In system runtime, to efficiently process the high-frequency telemetry data continuously generated by on-chip sensors, a mechanism combining a Direct Memory Access (DMA) controller and a memory ring buffer can be used. A ring buffer refers to a fixed-size contiguous address space allocated in the system main memory (DDR or SRAM). The DMA hardware internally maintains a pair of core registers: a head pointer and a tail pointer. Once the hardware peripheral generates a telemetry data packet, the DMA controller takes over the bus, writes the data to memory according to the address indicated by the tail pointer, and automatically increments the tail pointer at the hardware level. When the tail pointer reaches the set memory block boundary, the hardware automatically rolls back to the base address of the buffer through modulo operations. Simultaneously, the system CPU reads the head pointer to consume the data and updates the head pointer after processing. This separation of read and write pointers and the circular chasing mechanism achieves zero-copy ownership transfer between hardware and software, avoiding frequent CPU interrupt overhead.

[0027] Synchronization and Isolation Techniques Across Clock and Power Domains: In multi-clock domain system design, asynchronous signals may exhibit metastability when crossing boundaries. This is an unstable phenomenon where the output is at an intermediate level due to violations of flip-flop setup / hold times. Common techniques often employ synchronizers composed of two or more cascaded D flip-flops to reduce the probability of metastability, thereby exponentially improving the system's mean time between failures (MTBF). Furthermore, when signals cross different power domains, level shifters and isolation units are required. When the source power domain is powered off, the isolation unit clamps the output to a known safe level (such as logic 0) to prevent floating signals from causing short-circuit currents or logic corruption in the target power domain.

[0028] Security mechanisms for the basic JTAG port: Several defensive measures are included to address potential security vulnerabilities posed by the test interface. The most brute-force method is to permanently disconnect the JTAG physical circuitry using an electronic fuse before factory packaging, but this prevents subsequent field debugging. A more advanced and well-known solution involves adding a challenge-response circuit to the front end of the JTAG controller (TAP): When an external device requests debugging access, the hardware randomly generates a challenge code. The tester must use a pre-shared security key combined with a hash algorithm (such as SHA-256) to calculate the correct response code and compare it internally. Only after successful comparison can the TAP controller's internal command access be unlocked.

[0029] Related technical solutions: Option A: Access can be made purely for testing (1149.1 / 1687 reconfigurable serial access network). Its advantages include standard compatibility and mature DFT / ATE process integration. Disadvantages include significant serial shift and configuration overhead, with access sequence and network configuration impacting overall time; multiple power domains require power safety scheduling; and scanning accessibility introduces security risks, necessitating additional access management and authorization mechanisms.

[0030] Option B: Pure runtime bus register access (bus configuration + sampled data write to memory). Its advantages include fast runtime access and easy integration with system software; the publicly available framework has demonstrated the feasibility of "group-level interface + DMA memory write + trigger / packaging + power domain management." However, its disadvantages include the need for separate test paths for manufacturing testing and failure analysis; the potential for separation between the "test-side object model / namespace / trigger semantics" and the "runtime-side object model," leading to maintenance costs and consistency issues. Furthermore, the exposure of telemetry data must be handled with care to avoid introducing additional security vulnerabilities.

[0031] Solution C: General Packet / General Acceleration / High-Bandwidth Scanning Solutions. These solutions propose improving serial test network throughput through high-speed parallel networks / switching interface devices, or converting between synchronous JTAG signals and asynchronous packet domains in a packetized manner, or carrying test operations on a general communication interface via bridging. These solutions attempt to connect the test instrument network to the system bus, with typical implementations such as "JTAG-to-AXI Bridge" or "APB-to-JTAG Master" IP cores. In these solutions, the on-chip observation point configuration relies on the bridge translating memory-mapped read / write transactions from the AMBA AXI / APB bus into serial shift sequences for the TAP controller, or conversely, encapsulating serial data input from JTAG pins into read / write payloads for the AXI bus.

[0032] In scenarios such as chip aging and timing margin monitoring, the number of observation points is large and widely distributed, spanning multiple power or clock domains. This requires support for both manufacturing testing / failure analysis (standardized test access, automated toolchains) and in-service high-frequency / real-time sampling (low latency, high throughput, and replayability). Solutions A and B only support single scenarios, while Solution C makes limited improvements at the data transfer or signal bridging level. However, when dealing with system-level hybrid observation networks, it lacks global transaction abstraction and anti-collision arbitration capabilities.

[0033] According to one aspect of the embodiments of this application, a method embodiment supporting a hybrid observation method with dual pathways is provided.

[0034] Optionally, in this embodiment, the above-described dual-path hybrid observation method can be applied to the dual-path hybrid observation system of this application. It includes: The system comprises a convergence path for receiving target operation requests from the system layer; a test access path for receiving target operation requests based on a reconfigurable scanning network mechanism; an observation point layer for providing observation values ​​and data validity of target observation points; and a unified addressing and control layer for: parsing target operation requests into target standard internal transaction packets, determining the target logical address space of the target observation point corresponding to the target standard internal transaction packet at the observation point layer, and performing conflict detection and arbitration processing on the target observation point, wherein the target logical address space is a globally unified logical address space.

[0035] The above solution enables unified access through dual channels: both system software and external test equipment can access the same set of observation points through their respective familiar protocols (AXI / IJTAG), eliminating the need to maintain two separate sets of register mappings and driver code, thus significantly reducing engineering maintenance costs; zero tolerance for conflicts: through hardware-level arbitration, data corruption or bus hangs caused by concurrent access from dual master devices are completely avoided, ensuring extremely high reliability of observable data during chip field operation.

[0036] In an optional embodiment, the above-mentioned convergence path includes: a DMA ring buffer manager, which maintains a base address, depth, hardware tail pointer, and software head pointer at the hardware layer. This DMA ring buffer manager is used to directly write aligned burst data to system memory using zero-copy through hardware pointer increment and modular rollback for consumption by the operating system or SCP. After the monitoring group interface collects and packages the burst data (i.e., the data to be collected), the DMA ring buffer manager uses AXI incremental addressing to write the payload (i.e., the aforementioned data) to the physical memory pointed to by the hardware tail pointer and automatically increments the address. When the hardware tail pointer reaches a set boundary, the hardware comparator uses a modular rollback circuit to force it to roll back and reset to the base address. The aligned burst data includes observations. The above-mentioned test access path includes: a TAP controller, used for compatibility with standard JTAG timing finite state machines, thereby supporting ATE equipment in manufacturing plants or low-level security debugging probes; and a bridge, used for compatibility with IEEE 1149.1 and IEEE 1687 protocols.

[0037] In the test access path, when the unified addressing and control layer issues a read request (the target logical address points to a node within the group), the monitoring group interface performs the following operations: parses the node offset in the request to determine that the Kth physical node within the group is to be accessed; through SIB segment configuration, the node is switched into the scan path, and other nodes are bypassed; performs a complete scan shift operation, reads the data packet (containing observations and validity flags) from the local monitoring interface of the node; and returns the data packet to the unified addressing and control layer.

[0038] This solution enables large-scale node management: through grouping and SIB dynamic reconfiguration, a single physical scan chain can support hundreds of observation points, reducing the scan length from a fixed N times (N = total number of nodes) to a dynamic M times (M = number of nodes in a single group), thus shortening the scan time; power domain isolation is supported: the status register of the local monitoring interface records the power-on status of the nodes, and when a power domain is turned off, access requests to nodes within that domain can be quickly identified and returned as "invalid," avoiding illegal bus responses; it fully complies with the IEEE 1687 standard and can directly interface with existing DFT toolchains without the need for additional development tools.

[0039] In the running convergence path, the monitoring group interface completes a batch sampling (for example, collecting the values ​​of 16 sensors at once, totaling 512 bits of data) and sends a "data ready" pulse to the DMA ring buffer manager; the DMA ring buffer manager requests AXI bus access permissions; after obtaining bus authorization, it writes 512 bits of data to the address in incremental address mode (AXI INCR burst transfer).

[0040] This solution enables zero-copy data transfer: sensor data is directly written from DMA to memory without CPU / SCP intervention; the interrupt frequency is significantly reduced, while traditional solutions trigger an interrupt with each sampling (1MHz sampling rate corresponds to 1 million interrupts per second), this solution only interrupts when the buffer is almost full; hardware automatic rollback: the module rollback circuit is implemented purely in hardware without software intervention, avoiding data overflow and loss due to software response delay.

[0041] In an optional embodiment, the unified addressing and control layer described above includes: 1) A unified transaction abstraction center is used to parse target operation requests into target standard internal transaction packages.

[0042] The aforementioned unified transaction abstraction center has a built-in instruction parser for resolving operation requests. The instruction parser records the mapping relationship between various operations in the operation request and standard internal transaction packets. The standard internal transaction packet includes a source identifier (an coded field recorded in the header of the standard internal transaction packet, used to uniquely identify the physical path source of the initiating master device of the current access request; specifically, it distinguishes whether the request originates from a running convergence path, such as the system CPU, system controller SCP, or DMA controller, or from a test access path, such as an external ATE test device or JTAG debug probe), a transaction type (an opcode field recorded in the standard internal transaction packet, used to indicate the specific hardware operation to be performed in this access request; this field includes, but is not limited to: read (acquiring data from sensor registers), write (configuring parameters to sensor registers), configuration (reconstructing the SIB network topology), and exclusive read (used to initiate an operation requiring a specific source). The standard internal microinstructions include: the read-modify-write sequence of the sub-protection, the address of the target monitoring group (a high-order address field in the standard internal transaction packet, used to point to the global logical number of the monitoring group / sub-group to which the target physical node belongs in the hierarchical logical topology, based on the chip functional modules, such as CPU cores, caches, and memory controllers, which divide the set of physical nodes), the offset of the physical node (a low-order address field in the standard internal transaction packet, used to indicate the specific sequence number of the target physical node in its monitoring group or the relative displacement in the SIB chain segment; after locking the specific monitoring group through the target monitoring group address, the hardware uses this offset to accurately locate the unique node to be operated among multiple cascaded physical nodes (sensor + SIB combination) in the group), and the data payload (a field in the standard internal transaction packet that carries the specific transmission content, used to carry the write data, configuration parameters, or data return bit width space reserved for the read operation).

[0043] 2) Observation address mapper, used to find the target logical address space of the target observation point corresponding to the target standard internal transaction packet.

[0044] The aforementioned observation addressing mapper incorporates a LUT lookup table. This LUT lookup table maps physical nodes to a globally unified logical address space. The observation addressing mapper uses the LUT lookup table to find the target logical address space of the target observation point corresponding to the target standard internal transaction packet. 3) Global arbitration and latching unit, used to arbitrate and intercept operation requests that access the same target observation point by utilizing hardware transaction monitoring and exclusive access mechanisms.

[0045] Specifically, when the target standard internal transaction packet indicates an exclusive read transaction, the identifier of the master device initiating the access and the accessed logical address space are recorded; during the processing of the exclusive read transaction, if a write instruction to the accessed logical address space is received from another device, the write instruction is rejected; when multiple devices initiate access to the accessed logical address space, the lower priority among the multiple devices is physically blocked by using the handshake backpressure mechanism of the bus protocol or by forcing the TAP state machine to suspend.

[0046] The specific implementation of the observation addressing mapper: The LUT lookup table uses a programmable register array, such as 256 entries. Each entry contains: physical power domain ID, physical clock domain ID, SIB chain depth offset, logical group address, logical node offset, etc. Mapping process: When a standard internal transaction packet is received, the group address and node offset are extracted and compared in parallel within the LUT (up to 256-way parallel comparison). If a match is found, the corresponding physical coordinates are output.

[0047] The specific implementation of the global arbitration and latching unit is as follows: A hardware monitor table with a depth of 16 is maintained. Each entry records: Master Device ID, the accessed logical address, and the monitoring status (1 = active, 0 = inactive). When an exclusive read transaction arrives, a free entry is allocated, recording the Master Device ID and the target address, and its status is set to active. If a write request from any other master device subsequently arrives, the arbitrator compares the write address with the addresses in all active entries in parallel. If a match is found, immediately: ① the response signal for the write request is forced to "normal OK" (not EXOKAY); ② the status of the entry is set to inactive; ③ optionally, a "conflict" interrupt is returned to the master device that initiated the write. When the master device that initiated the exclusive read subsequently sends an exclusive write, the arbitrator checks the corresponding entry: if the entry is still active, the write is allowed and EXOKAY is returned; if it is inactive, the write is rejected and normal OK is returned. In multi-device contention scenarios (such as CPU0, CPU1, and TAP simultaneously requesting access to the same address), the arbiter has a built-in priority strategy: the debug interface (TAP) has the lowest default priority. When the bus load exceeds the threshold, the arbiter will forcibly suspend the TAP's TCK clock through gating and simultaneously pull down the TAP's TRST signal to reset its state machine. The clock will be restored after the bus is idle. This process is completed in nanoseconds (approximately 5-20ns).

[0048] The technical solution offers the following advantages: 1) Standardized transaction conversion: Operations from any source are converged into a unified format, subsequent processing logic can be reused, and hardware design complexity is low; 2) Fine-grained exclusive access: Compared with traditional AMBA locking access (blocking the entire bus), this solution only blocks conflicting addresses, significantly improving bus bandwidth utilization; 3) Nanosecond-level priority blocking: The physical blocking of debug probes is completed at the nanosecond level, which will not cause JTAG timeouts and avoids the risk of bus hang.

[0049] In an optional embodiment, the observation point layer includes multiple monitoring groups and corresponding monitoring group interfaces. Each monitoring group includes multiple physical nodes, and each physical node includes: a sensor for collecting observation signals at the observation point; a local monitoring interface for converting the observation signals at the observation point into observation values; and an SIB module for providing the dynamic network topology bypass and cut-in capabilities required based on the reconfigurable scanning network mechanism.

[0050] The workflow of the monitoring group interface is as follows: Each monitoring group interface maintains an intra-group SIB chain segment with a length greater than or equal to the number of physical nodes in the group; when the unified addressing and control layer issues a read request (the target logical address points to a node in the group), the monitoring group interface performs the following operations: parses the node offset in the request to determine that the Kth physical node in the group needs to be accessed; through the SIB chain segment configuration, the node is switched into the scan path, and other nodes are bypassed; performs a complete scan shift operation to read the data packet (containing observations and validity flags) from the local monitoring interface of the node; and returns the data packet to the unified addressing and control layer.

[0051] Figure 1 This is a flowchart of a hybrid observation method supporting dual-path observation according to an embodiment of this application, as shown below. Figure 1 As shown, the method may include the following steps: Step S110: Receive a target operation request. The target operation request is a request received from the system layer in the running convergence path or a request based on the reconfigurable scanning network mechanism received in the test access path.

[0052] Step S120: Parse the target operation request into a target standard internal transaction packet, determine the target logical address space of the target observation point corresponding to the target standard internal transaction packet at the observation point layer, and perform conflict detection and arbitration processing on the target observation point. The target logical address space is a globally unified logical address space.

[0053] When a transaction packet within the target standard indicates an exclusive read transaction, the identifier of the master device initiating the access and the accessed logical address space are recorded. During the processing of the exclusive read transaction, if a write instruction to the accessed logical address space is received from another device, the write instruction is rejected. In the case of multiple devices initiating access to the logical address space, the lower priority among the multiple devices is physically blocked by using the handshake backpressure mechanism of the bus protocol or by forcing the TAP state machine to suspend.

[0054] Step S130: Obtain the observation values ​​and their data validity from the target observation point according to the target logical address space.

[0055] Through the above steps, a target operation request is received. This target operation request is either a request received from the system layer in the running convergence path or a request based on the reconfigurable scanning network mechanism received in the test access path. The target operation request is parsed into a target standard internal transaction packet. The target logical address space of the target observation point corresponding to the target standard internal transaction packet at the observation point layer is determined. Conflict detection and arbitration are performed on the target observation point. The target logical address space is a globally unified logical address space. The observation value and its data validity are obtained from the target observation point according to the target logical address space. This can solve the technical problem of concurrent conflicts between the scanning access path and the running convergence path in related technologies.

[0056] As an optional embodiment, the technical solution of this application is further described in detail below with reference to specific embodiments: 1) System Overall Architecture Figure 2 The diagram shows the overall system architecture of this application. The entire on-chip aging monitoring framework is rigorously divided into three core logical layers from top to bottom. This architecture enables seamless flow from distributed physical nodes to a unified control hub, and then to multi-protocol distribution paths: 1.1) Bottom Layer: Monitoring Group Interface and Observation Point Layer Above the architecture, a massive number of distributed physical nodes are deployed. Each basic node consists of a sensor (such as a temperature, voltage, or aging delay sensor) and a composite module of "local monitoring interface + SIB (segment insertion bit)".

[0057] These underlying nodes are encapsulated within multiple large monitoring groups through serial and cascade connections, with each monitoring group having a monitoring group interface.

[0058] The local monitoring interface is responsible for performing preliminary high-frequency sampling and bit-width shaping on the fragmented analog or digital signals generated by the sensors; while the tightly coupled SIB module gives the node the ability to bypass or insert dynamic network topologies in accordance with the IEEE 1687 standard.

[0059] The data and control flows between the interfaces of each monitoring group and between nodes within the group (as shown by the dashed arrows) ultimately converge downwards to the middle layer control plane.

[0060] 1.2) Middle Layer: Unified Addressing and Control Plane As the core neural hub of the entire system, the unified addressing and control plane, located at the center of the architecture, connects the upper and lower layers, completely eliminating the semantic fragmentation of traditional independent networks. This control plane contains three crucial sub-modules: The observation addressing mapper (with built-in LUT lookup table) is responsible for mapping the relative offsets or physical network segments of a massive number of top-level physical nodes to a globally unified logical address space (such as Node ID and Group ID) through a lookup table (LUT). Addressing requests from both the test and runtime environments must be translated through this mapper.

[0061] Unified Transaction Abstraction Center (Built-in Command Parser): This module receives heterogeneous requests from the underlying layer and uses its internal command parser to abstract and transform read, write, and configuration operations from different sources into standardized internal transaction packages. This ensures absolute consistency between the triggering and sampling semantics of both paths.

[0062] Global Arbitration and Latching Unit (Built-in Concurrency Processing Logic): To prevent multiple master devices from simultaneously reading and writing to the same top-level sensor node, the concurrency processing logic of this unit achieves zero-cycle conflict interception and arbitration through underlying hardware transaction monitoring and exclusive access mechanisms, completely eliminating dirty data writes.

[0063] 1.3) Top-level: Multi-protocol distribution and aggregation pathways The middle-layer hub completes instruction parsing, address translation and arbitration, and connects to two independent access paths clearly defined by large dashed boxes (corresponding to the two main left and right module areas at the bottom of the architecture): The convergence path (large dashed box on the left) is designed for high-bandwidth operation of system software. Internally, it contains a DMA ring buffer manager that outputs to System Memory DDR / SRAM. After processed batch telemetry data is sent to this path, the DMA manager uses hardware pointer incrementing and modulo rollback to directly write aligned burst data to main memory with zero copies, allowing efficient consumption by the operating system or SCP.

[0064] Test access path (large dashed box on the right): Designed specifically for traditional low-level debugging protocols and heterogeneous bus ecosystems. This path is further divided into two collaborative branches: the left branch directly interfaces with the "TAP controller," retaining compatibility with the standard JTAG timing finite state machine (FSM), thereby supporting deep intervention by ATE equipment in the manufacturing plant or low-level security debugging probes; the right branch (optional) uses an "IEEE 1149.1 / 1687 compatible bridge," enabling the system to seamlessly translate and mount unified transactions to the bottom "SPI, I2C and other bus protocols," thus achieving plug-and-play integration of on-chip legacy IPs and various microcontrollers.

[0065] Through the tight integration of the above three-layer architecture, this application constructs a hybrid observation network on a single chip substrate that combines high bandwidth, strong real-time performance, high security, and extreme consistency. The following sections will provide an in-depth breakdown of the key technologies within this architecture.

[0066] 2) Design of a unified transaction abstraction mechanism In modern highly integrated mixed-signal SoC design, network topology design determines data flow efficiency. Traditional chip design presents a strict binary opposition in observability networks: the first network is a serial scan chain designed specifically for the manufacturing test phase, relying on Test Access Ports (TAPs) and reconfigurable scan network standards. Its advantage lies in its extremely high physical penetration, but its disadvantages are high configuration overhead and lack of awareness of the system's operating state; the second network is a system-level runtime bus based on memory-mapped input / output. Its advantages are high bandwidth and ease of system software linkage, but it lacks penetration for low-level hardware debugging.

[0067] The unified addressing and control plane of this application not only performs the translation from physical address to logical address, but also serves as the "nerve center" of the entire architecture, responsible for abstracting the underlying independent hardware observation points into a consistent hierarchical logical topology model of "group / sub-group / node". For example... Figure 2 As shown, the runtime convergence path on the left connects to the control plane via a high-level extensible interface, while the test access path on the right interfaces to the control plane via a serial gateway and bridge. The unified transaction abstraction mechanism enables parallel read / write requests on the runtime side and serial shift sequences on the test side to be seamlessly translated into completely equivalent and homogeneous transaction packets at the hardware level. Regardless of whether the external transaction originates from pointer dereference operations in system software or from serial bitstream input from a JTAG probe, the control plane resolves it into standard internal microinstructions containing the source identifier, transaction type, target group address, node offset, and data payload.

[0068] The following table compares in detail the behavioral differences between traditional standalone networks and the unified transaction mapping surface of this application when processing access to underlying aging sensors, as shown in Table 1: Table 1

[0069] This architecture completely eliminates the engineering disconnect between the "test-side object model / trigger semantics" and the "runtime-side object model," achieving extremely high data consistency throughout the chip's entire lifecycle, from manufacturing testing and field debugging to long-term in-service monitoring. Specifically, during manufacturing testing and field debugging, test paths can be used to acquire test data via JTAG / IJTAG interfaces; while during actual chip service, test data can be accessed using bus protocols. Through the architecture and consistency semantics method of this application, the various sensor monitoring points used in both approaches are identical, and the acquired monitoring data is also consistent.

[0070] 3) Zero concurrency conflicts: Exclusive access mechanism based on global arbitration and latching units. In traditional SoC architectures without a unified control plane, external debug probes and internal system buses operate independently. When two concurrent read or configuration commands are sent to the same underlying aging monitor register within a certain time window, data corruption will inevitably occur, and even fatal system hangs may result due to bus protocol state machine violations.

[0071] By integrating the global arbitration and latching units in the system architecture, the core control plane of this application deeply integrates global read-write locks and concurrent processing logic based on advanced bus protocols. In the evolution of bus arbitration technology, the early AMBA protocol adopted a "locked access" mechanism, which forcibly monopolizes the bus channel by pulling the AxLOCK signal high. Although it guarantees atomicity, it severely blocks system interconnect bandwidth. Therefore, it has been phased out in the modern AXI4 protocol and downgraded to be only for legacy compatibility.

[0072] This application abandons inefficient coarse-grained locking and adopts fine-grained exclusive access combined with non-blocking concurrent processing logic of hardware transaction monitor. This mechanism is specifically designed for multi-master environments (i.e., concurrent TAP-bridged master devices and system CPU master devices) with underlying hardware customization.

[0073] The specific interaction flow mechanism of the global arbitrator is as follows: Interactive flow mechanism 1, exclusive read initiation: When the system software is about to read or reset the status register of an aging sensor, the CPU will initiate an exclusive read transaction through the running convergence path. At this time, the underlying hardware monitor is activated, accurately recording the identifier of the master device (the system CPU master device) and the range of target addresses to be accessed (recording the register access addresses of the sensor data, i.e., corresponding to which sensor data to be acquired).

[0074] Interactive flow mechanism 2, illegal overwrite intervention (collision detection): In the gap where the system software has not yet completed the closed loop (i.e., initiated the corresponding exclusive write update), suppose the external probe of the right-side test access path happens to trigger a control command on the instrument within the same address range via the serial network. At this time, the monitor will immediately capture this sudden state modification, determine that the target area has been "contaminated," and remove or mark the tracking status of the master device from the monitor list. The monitor list is used to record which master device is accessing which addresses at the current moment; the significance of the tracking status is to record whether a conflict has occurred; if a master device has already initiated a write operation to the target address, and another master device initiates a write operation to the same address, a competition will occur, leading to an uncertain write status. In the global arbitration and latching unit, if such a conflict occurs, it will prevent further write operations, and the control command will not actually take effect.

[0075] Interactive flow mechanism 3, hardware-level failure notification and spin: When the system software subsequently initiates an exclusive write attempt to complete the atomic operation, the arbitrator will prevent the data from being written to the underlying register because it detects that the monitoring record has expired (it will expire in the case of access contention / conflict, corresponding to the trace status flag in the previous section). It will also force the return of an OKAY response on the write response channel, which represents a normal success but not an exclusive success, instead of an EXOKAY response that represents the success of the atomic operation (one represents that it will be executed successfully when there are no concurrent operations, and the other is due to the failure of actual execution caused by concurrency conflict).

[0076] Interactive flow mechanism 4, hard blocking feedback: If a large number of contentious accesses continue to occur, the arbitration logic will also utilize the handshake backpressure mechanism of the underlying bus protocol (specifically, when the receiver receives data but cannot process it or the state has not recovered, it actively sends a signal to make the sender stop sending until the receiver recovers its ability), or force the TAP state machine to suspend, implementing nanosecond-level physical blocking on the lower priority end (achieving high-efficiency concurrency has certain conditions; when accessing different addresses, or performing read-only operations on the same address, parallel operations can be performed directly. However, when there are contention conflicts, relevant processing mechanisms need to be considered. Interactive flow mechanisms 1-3 are equivalent to the processing methods in most cases where there is little contention; interactive flow mechanism 4 is equivalent to when contention occurs very frequently, and the cost of judging some states is not worthwhile compared to the parallel operation, at which point parallel execution will directly degenerate into serial execution. The simplest way to implement physical blocking in hardware is to actively suspend the device and enter a paused state).

[0077] This system-level arbitration completely eliminates the physical conditions that could lead to illegal concurrent timing conflicts, ensuring extremely high fidelity of telemetry data throughout the silicon lifecycle while maximizing the release of the system's interconnect bus bandwidth.

[0078] 4) Eliminate stop-and-wait overhead: High-concurrency DMA ring buffer architecture like Figure 2 As shown, in terms of eliminating system overhead and improving throughput, this solution designs a hardware-autonomous DMA ring buffer network for the running convergence path.

[0079] As shown in the large dashed box at the bottom left of the architecture, this application deploys a customized "DMA ring buffer manager" that interfaces with "System Memory DDR / SRAM". In traditional software polling mechanisms, the CPU must frequently interrupt the normal workflow to read sensor data. The DMA controller in this application maintains the base address, depth, hardware tail pointer, and software head pointer at the hardware layer. When the upper-layer "monitoring group interface" collects and packages burst data, the DMA hardware directly requests the bus, uses AXI incremental addressing to write the payload to the physical memory pointed to by the tail pointer, and automatically increments the address. Using a customized modular rollback circuit, the hardware comparator forces the tail pointer to roll back and reset to the base address when it reaches a set boundary (this is a customized DMA hardware function). Pointer maintenance, AXI incremental addressing, hardware comparison judgment, and modular rollback address reset are all executed independently by the DMA hardware circuit, without real-time CPU intervention.

[0080] Zero-copy is a characteristic of DMA. The raw data, after being collected and packaged, is directly written to the target physical memory by the DMA hardware in one go. There is no secondary copying or transfer of data between memory buffers. An interrupt is triggered to notify the CPU only when the buffer is about to overflow, thus completing the zero-copy high-speed transfer. This achieves zero-copy transfer. Only when the tail pointer approaches the head pointer and there is a risk of overflow will the CPU intervene through an interrupt notification, freeing up core computing power.

[0081] The architecture design of this application breaks through the traditional approach of separating software observation and hardware testing. By integrating unified resource control in the underlying logic, it generates many advantages that are not available in traditional JTAG-AXI bridging systems.

[0082] 1) Consistent semantics reduces engineering fragmentation: Public frameworks emphasize managing monitor sampling through standardized interfaces and reducing software overhead; this application, based on this, connects test access and runtime convergence through unified addressing and unified transaction abstraction, reducing the engineering fragmentation cost caused by "inconsistent object models between the test side and the runtime side"; 2) Extremely high data consistency guarantee and zero data contention characteristics: In traditional architectures without a unified transaction plane, because the CPU of the operation bus operates at a clock frequency of hundreds of megahertz, while the external probe of the debug interface operates asynchronously at a lower frequency (such as 10MHz), the two operate independently. When two paths concurrently write or read values ​​to the same monitor register within a certain clock cycle, the classic data corruption problem will be encountered. This application sets up a unified addressing and translation center, and any operation intention will be converted into mutually bound homogeneous structure images; 3) Extremely low software overhead combined with excellent continuous high bandwidth aggregation performance: Traditional runtime sensor data acquisition heavily relies on interrupt-driven CPU intervention polling, which greatly consumes the valuable computing power of the core processor. However, when monitoring via JTAG, the serial shift characteristics are limited by the finite physical bandwidth of the link, which cannot meet the needs of real-time massive analysis. This application customizes a highly cohesive DMA ring buffer manager and a hardware-level modular rollback circuit. This means that the entire ownership transfer of the data flow to DRAM physical memory is completed entirely by autonomous hardware. Software and hardware notifications are only generated when the head and tail pointers meet the overflow calculation boundaries.

[0083] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, as some steps may be performed in other orders or simultaneously according to this application. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily essential to this application.

[0084] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0085] According to another aspect of the embodiments of this application, a hybrid observation apparatus supporting dual paths is also provided for implementing the above-described hybrid observation method supporting dual paths. Figure 3 This is a schematic diagram of a hybrid observation device supporting dual paths according to an embodiment of this application, as shown below. Figure 3 As shown, the device may include: The receiving unit 31 is used to receive a target operation request, wherein the target operation request is a request received from the system layer in the running convergence path or a request based on the reconfigurable scanning network mechanism received in the test access path. The control unit 32 is used to parse the target operation request into a target standard internal transaction packet, determine the target logical address space of the target observation point corresponding to the target standard internal transaction packet at the observation point layer, and perform conflict detection and arbitration processing on the target observation point, wherein the target logical address space is a globally unified logical address space. The acquisition unit 33 is used to acquire the observation value and its data validity from the target observation point according to the target logical address space.

[0086] The above modules receive target operation requests, which are requests received from the system layer in the running convergence path or requests based on the reconfigurable scanning network mechanism in the test access path. The target operation request is parsed into a target standard internal transaction packet. The target logical address space of the target observation point corresponding to the target standard internal transaction packet at the observation point layer is determined, and conflict detection and arbitration are performed on the target observation point. The target logical address space is a globally unified logical address space. Observations and their data validity are obtained from the target observation point according to the target logical address space. This can solve the technical problem of concurrent conflicts between the scanning access path and the running convergence path in related technologies.

[0087] It should be noted that the examples and application scenarios implemented by the above modules and corresponding steps are the same, but are not limited to the content disclosed in the above embodiments. It should also be noted that the above modules, as part of a device, can operate in environments such as... Figure 2 The hardware environment shown can be implemented through software or hardware, and the hardware environment includes the network environment.

[0088] According to another aspect of the embodiments of this application, a server or terminal for implementing the above-described hybrid observation method supporting dual paths is also provided.

[0089] Figure 4 This is a structural block diagram of a terminal according to an embodiment of this application, such as... Figure 4 As shown, the terminal may include: one or more (only one is shown in the figure) processors 401, memory 403, and transmission devices 405, such as... Figure 4 As shown, the terminal may also include input / output devices 407.

[0090] The memory 403 can be used to store software programs and modules, such as the program instructions / modules corresponding to the dual-path hybrid observation method and apparatus in this embodiment. The processor 401 executes various functional applications and data processing by running the software programs and modules stored in the memory 403, thereby realizing the aforementioned dual-path hybrid observation method. The memory 403 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 403 may further include memory remotely located relative to the processor 401, and these remote memories can be connected to the terminal via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0091] The aforementioned transmission device 405 is used to receive or send data via a network, and can also be used for data transfer between the processor and memory. Specific examples of the network described above may include wired networks and wireless networks. In one example, the transmission device 405 includes a Network Interface Controller (NIC), which can be connected to other network devices and a router via a network cable to communicate with the Internet or a local area network. In another example, the transmission device 405 is a radio frequency (RF) module used for wireless communication with the Internet.

[0092] Specifically, memory 403 is used to store application programs.

[0093] The processor 401 can invoke the application program stored in the memory 403 via the transmission device 405 to perform the following steps: The system receives a target operation request, wherein the target operation request is a request received from the system layer in the running convergence path or a request based on a reconfigurable scanning network mechanism received in the test access path; the target operation request is parsed into a target standard internal transaction packet, the target logical address space of the target observation point corresponding to the target standard internal transaction packet at the observation point layer is determined, and conflict detection and arbitration are performed on the target observation point, wherein the target logical address space is a globally unified logical address space; the observation value and its data validity are obtained from the target observation point according to the target logical address space.

[0094] Optionally, specific examples in this embodiment can refer to the examples described in the above embodiments, and will not be repeated here.

[0095] Those skilled in the art will understand that Figure 4 The structure shown is for illustrative purposes only. The terminal can be a smartphone (such as an Android phone, an iOS phone, etc.), a tablet computer, a PDA, a mobile internet device (MID), a PAD, or other terminal devices. Figure 4 This does not limit the structure of the aforementioned electronic device. For example, the terminal may also include components that are more... Figure 4 The more or fewer components shown (such as network interfaces, display devices, etc.), or having the same Figure 4 The different configurations shown.

[0096] Those skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be implemented by a program instructing the hardware related to the terminal device. The program can be stored in a computer-readable storage medium, which may include: flash drive, read-only memory (ROM), random access memory (RAM), disk or optical disk, etc.

[0097] Embodiments of this application also provide a storage medium. Optionally, in this embodiment, the storage medium can be used to execute program code supporting a dual-path hybrid observation method.

[0098] Optionally, in this embodiment, the storage medium may be located on at least one of the network devices in the network shown in the above embodiment.

[0099] Optionally, in this embodiment, the storage medium is configured to store program code for performing the following steps: The system receives a target operation request, wherein the target operation request is a request received from the system layer in the running convergence path or a request based on a reconfigurable scanning network mechanism received in the test access path; the target operation request is parsed into a target standard internal transaction packet, the target logical address space of the target observation point corresponding to the target standard internal transaction packet at the observation point layer is determined, and conflict detection and arbitration are performed on the target observation point, wherein the target logical address space is a globally unified logical address space; the observation value and its data validity are obtained from the target observation point according to the target logical address space.

[0100] Optionally, specific examples in this embodiment can refer to the examples described in the above embodiments, and will not be repeated here.

[0101] Optionally, in this embodiment, the storage medium may include, but is not limited to, various media capable of storing program code, such as USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0102] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0103] If the integrated units in the above embodiments are implemented as software functional units and sold or used as independent products, they can be stored in the aforementioned computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause one or more computer devices (which may be personal computers, servers, or network devices, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application.

[0104] In the above embodiments of this application, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0105] In the several embodiments provided in this application, it should be understood that the disclosed client can be implemented in other ways. The device embodiments described above are merely illustrative; for example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces, indirect coupling or communication connection between units or modules, and may be electrical or other forms.

[0106] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0107] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0108] The above description is only a preferred embodiment of this application. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of this application, and these improvements and modifications should also be considered within the scope of protection of this application.

Claims

1. A hybrid observation method supporting dual-path observation, characterized in that, include: Receive a target operation request, wherein the target operation request is a request received from the system layer in the running convergence path or a request based on the reconfigurable scanning network mechanism received in the test access path. The target operation request is parsed into a target standard internal transaction packet, the target logical address space of the target observation point corresponding to the target standard internal transaction packet at the observation point layer is determined, and conflict detection and arbitration are performed on the target observation point. The target logical address space is a globally unified logical address space. The observation values ​​and their data validity are obtained from the target observation point according to the target logical address space.

2. The hybrid observation method according to claim 1, characterized in that, The collision detection and arbitration process for the target observation points includes: When the transaction packet within the target standard indicates an exclusive read transaction, the identifier of the master device initiating the access and the accessed logical address space are recorded; during the processing of the exclusive read transaction, if a write instruction to the accessed logical address space is received from another device, the write instruction is rejected. When multiple devices initiate access to the logical address space, the lower-priority devices among the multiple devices are physically blocked by using the handshake backpressure mechanism of the bus protocol or by forcing the TAP state machine to suspend.

3. A hybrid observation device supporting dual-path observation, characterized in that, include: A receiving unit is configured to receive a target operation request, wherein the target operation request is a request received from the system layer in the running convergence path or a request based on a reconfigurable scanning network mechanism received in the test access path. The control unit is used to parse the target operation request into a target standard internal transaction packet, determine the target logical address space of the target observation point corresponding to the target standard internal transaction packet at the observation point layer, and perform conflict detection and arbitration processing on the target observation point, wherein the target logical address space is a globally unified logical address space. The acquisition unit is used to acquire observation values ​​and their data validity from the target observation point according to the target logical address space.

4. A hybrid observation system supporting dual-path observation, characterized in that, include: Run the aggregation path to receive target operation requests from the system layer; Test access path, used to receive target operation requests based on a reconfigurable scanning network mechanism; The observation point layer is used to provide the observation values ​​of the target observation points and their data validity. A unified addressing and control layer is used to: parse a target operation request into a target standard internal transaction packet, determine the target logical address space of the target observation point corresponding to the target standard internal transaction packet at the observation point layer, and perform conflict detection and arbitration processing on the target observation point, wherein the target logical address space is a globally unified logical address space.

5. The hybrid observation system according to claim 4, characterized in that, The unified addressing and control layer includes: A unified transaction abstraction center is used to parse the target operation request into the target standard internal transaction package; An observation addressing mapper is used to find the target logical address space of the target observation point corresponding to the target standard internal transaction packet; The global arbitration and latching unit is used to arbitrate and intercept operation requests that access the same target observation point by utilizing hardware transaction monitoring and exclusive access mechanisms.

6. The hybrid observation system according to claim 5, characterized in that, The unified transaction abstraction center has a built-in instruction parser for parsing operation requests. The instruction parser records the mapping relationship between various operations in the operation request and standard internal transaction packets. The standard internal transaction packets include source identifier, transaction type, address of target monitoring group, offset of physical node, and standard internal micro-instructions of data payload. The observation addressing mapper has a built-in LUT lookup table, which is used to map physical nodes to a globally unified logical address space. The observation addressing mapper uses the LUT lookup table to look up the target logical address space of the target observation point corresponding to the target standard internal transaction packet. The global arbitration and latching unit is used to: record the identifier of the master device initiating the access and the accessed logical address space when the internal transaction packet of the target standard indicates an exclusive read transaction; during the processing of the exclusive read transaction, if a write instruction to the accessed logical address space is received from another device, the write instruction is rejected; when multiple devices initiate access to the accessed logical address space, the lower priority among the multiple devices is physically blocked by using the handshake backpressure mechanism of the bus protocol or by forcing the TAP state machine to suspend.

7. The hybrid observation system according to claim 4, characterized in that, The observation point layer includes multiple monitoring groups and corresponding monitoring group interfaces. Each monitoring group includes multiple physical nodes, and each physical node includes: Sensors are used to collect observation signals at the observation point. The local monitoring interface is used to convert the observation signals from the observation points into observation values. The SIB module provides the dynamic network topology bypass and cut-in capabilities required by the reconfigurable scanning network mechanism.

8. The hybrid observation system according to claim 4, characterized in that, The operational convergence path includes: A DMA ring buffer manager maintains a base address, depth, hardware tail pointer, and software head pointer at the hardware layer. It is used to write aligned burst data directly to system memory using zero-copy through hardware pointer incrementing and modular rollback for consumption by the operating system or SCP. After the burst data is collected and packaged by the monitoring group interface, the DMA ring buffer manager uses AXI incremental addressing to write the payload to the physical memory pointed to by the hardware tail pointer and automatically increments the address. When the hardware tail pointer reaches a set boundary, the hardware comparator uses a modular rollback circuit to force it to roll back and reset to the base address. The aligned burst data includes observations.

9. The hybrid observation system according to any one of claims 4 to 8, characterized in that, The test access path includes: TAP controllers are designed to be compatible with standard JTAG timing finite state machines, thereby supporting ATE devices or low-level security debug probes in manufacturing plants. A bridge for compatibility with IEEE 1149.1 and IEEE 1687 protocols.

10. A computer-readable storage medium, characterized in that, The storage medium includes a stored program, wherein the program executes the method described in claim 1 or 2 above when it is run.

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