A verifiable conversion factor generation method and system for computing power token production capability

Abstract

This invention discloses a verifiable conversion factor generation method and system for computing power token production capabilities, belonging to the field of automated computing power and hardware benchmark testing technology. Addressing industry pain points such as reliance on manual review of existing computing power metrics, inconsistent conversion standards for heterogeneous computing power, low reliability of test data, and easy degradation of static conversion accuracy, this invention constructs a hardware-fixed, fully automated closed-loop conversion architecture with deep software and hardware collaboration. Relying on hardware-level fixed testing programs, hardware identity encryption and notarization, layered cross-architecture adaptive calibration, firmware-locked weighted calculation, and intelligent iteration mechanisms, this invention achieves unmanned, verifiable, reproducible, and adaptive conversion of all categories of heterogeneous computing power token production capabilities. This invention avoids the defects of human intervention from the hardware level, ensuring the fairness and reliability of computing power, and is suitable for large-scale AI computing power trading and automated reliable settlement scenarios.

Description

Technical Field

[0001] This invention relates to the field of automated computing power and hardware benchmark testing technology, specifically to a verifiable conversion factor generation method and system for computing power token output capability. It is applicable to standardized calibration of token output capability of various heterogeneous AI computing power hardware, unified quantification of computing power across devices, automated and reliable settlement of computing power transactions, and stable operation of computing power measurement under network outages, hardware failures, and high-concurrency complex extreme conditions. Background Technology

[0002] As a standardized unit of measurement for large-scale model inference computing power, tokens are widely used in various AI computing power trading, computing power quantitative settlement, and computing power leasing scenarios. Currently, the industry's token computing power quantitative, conversion, and verification work relies on manually formulated rules and standards, human screening and verification processes, and institutional management norms. This is a typical intellectual activity and human management logic, lacking a fully automated technical support system with hardware and software collaboration. It has many inherent technical defects and cannot adapt to the needs of large-scale, highly reliable, and comprehensive computing power measurement.

[0003] The shortcomings of existing technical solutions are specifically reflected in four aspects: First, the computing power conversion mode is highly dependent on manual rule judgment. There is no unified hardware-fixed automated testing and calibration architecture in the industry. It is necessary to manually set comparison standards, screen test data, and classify computing power levels. It is impossible to independently complete the horizontal calibration of all categories of heterogeneous computing power, and the data adaptability of heterogeneous computing power is poor. Second, the data verification process relies on manual review and system publicity. There is no hardware-level anti-tampering and reproducible technical mechanism. The authenticity and integrity of test data depend on human supervision, which poses risks of data tampering, environment falsification, and test data reuse. Third, the conversion parameters and calibration standards are static specifications formulated manually. They lack adaptive dynamic iteration capabilities and cannot adapt to changes in computing power characteristics brought about by hardware iteration and large model algorithm upgrades. The conversion accuracy continues to decline with long-term use. Fourth, the existing technology has poor adaptability to working conditions. It does not set up fault tolerance mechanisms for extreme scenarios such as network outages, temporary hardware failures, and high-concurrency operation. Under complex working conditions, the converted data is prone to failure and the process is prone to interruption. Moreover, it is only compatible with a small number of mainstream computing power hardware and cannot cover niche computing power chips, thus limiting the scope of hardware compatibility.

[0004] The aforementioned human-driven, static, and limited measurement model results in low standardization, poor credibility, weak adaptability, and insufficient operational stability of existing token conversion schemes, which cannot meet the technical implementation requirements of automation, standardization, high credibility, and high stability in the current large-scale AI computing power trading scenario. Summary of the Invention

[0005] (a) Technical problems to be solved This invention aims to completely eliminate the shortcomings of existing token conversion systems that rely on manual rules, processes, and institutional management. It addresses five core technical problems: lack of unified automated calibration technology for heterogeneous computing power, lack of hardware technology to ensure the reliability of test data, inability to adaptively iterate conversion parameters, lack of fault tolerance mechanisms for extreme operating conditions, and lack of hardware adaptation for niche computing power. The invention constructs an automated computing power conversion technology system that features full-process software and hardware collaboration, adaptation to all types of computing power, compatibility with all operating conditions, and purely technical, uninterrupted operation, thereby achieving standardized, reliable, adaptive, and stable implementation of computing power measurement.

[0006] (II) Technical Solution To achieve the above technical objectives, this invention provides a purely technical, fully automated, all-category adaptable, and all-condition fault-tolerant computing power token conversion solution. It completely eliminates all manual management rules, institutional constraints, and human operation processes, and adopts a proprietary architecture with deep software and hardware collaboration at the underlying level. This avoids the creative defects of simple reuse of general computer programs, forming a proprietary, closed-loop, and highly stable automated computing power technology system, thereby fundamentally avoiding the risk of rejection during intellectual property activity review.

[0007] This invention embeds a standardized benchmark testing program set adapted to a general large-scale model architecture at the underlying firmware of various computing power testing hardware. The hardware device autonomously completes multi-architecture inference testing and computing power data collection, completely eliminating manual parameter configuration and process control. This invention establishes a hardware read-only fingerprint automatic collection and encrypted evidence storage link, achieving strong binding and tamper-proof evidence storage of test hardware identity, operating environment, and test data. A hierarchical heterogeneous computing power calibration system is constructed, achieving unified standardized mapping of heterogeneous computing power data through intelligent hardware architecture grouping, adaptive normalization within the same architecture, and cross-architecture bridging calibration. Through a multi-index weighted calculation model permanently embedded in the firmware, using steady-state measured hardware data as the sole input, standardized token conversion coefficients are generated automatically. This invention configures a dual-mode adaptive iteration mechanism, including fixed-cycle regular iteration and intelligent expedited iteration driven by hardware availability, automatically adapting to computing power hardware and model algorithm iteration updates. Simultaneously, a full-dimensional extreme condition fault tolerance mechanism is configured, enabling network outage cache resumption, hardware anomaly identification, and abnormal data rollback. Combined with a third-party automated reproduction and verification system, a fully automated, highly reliable, and highly stable computing power conversion closed loop is formed.

[0008] (III) Beneficial Effects Compared to existing technical solutions that rely on artificial intelligence and institutional management, this invention has significant substantial technological advancements and comprehensive advantages in adaptability to various scenarios: First, this invention breaks through the traditional manual system and intellectual activity control model, forming a dedicated automated calculation architecture with a fixed hardware-level program and embedded algorithms that are fully linked. There are no manual adjustment or intervention ports, and it is not a simple reuse of general computer programs. It locks the entire process operation logic from the hardware level, completely solves the technical bias of relying on human experience for judgment in the industry for a long time, completely avoids the risk of rejection of intellectual activities, realizes pure technical unmanned operation of the entire computing power measurement process, and greatly improves the objectivity and standardization of computing power measurement.

[0009] Second, this invention constructs a multi-layered closed-loop trusted protection system that features unique hardware identity binding, chain-based encrypted evidence storage, third-party fully automated reproduction verification, and extreme working condition fault tolerance. This differs from existing industry technologies that rely on single blockchain evidence storage or only collect hardware information in a fragmented manner. Through multi-module collaborative linkage, it eliminates multiple problems such as data tampering, test environment forgery, data reuse, and abnormal working condition failures from the hardware root, significantly improving the security and operational stability of computing power.

[0010] Third, this invention features a unique adaptive iterative triggering mechanism for monitoring the distribution of hardware across the entire network, breaking through the technical limitations of traditional fixed static conversion standards. It eliminates the need for manually setting iteration cycles and updating calibration rules, using the distribution ratio of hardware models across the entire network as an objective criterion. It autonomously adapts to performance changes brought about by hardware iterations and large model algorithm upgrades, ensuring long-term stable conversion accuracy and effectively overcoming the inherent defect of continuous accuracy decay in static metering schemes.

[0011] Fourth, this invention features a unique pre-set extreme value and novel hardware adaptive fitting hierarchical normalization heterogeneous computing power adaptation logic, which is not a simple application of the general Min-Max normalization algorithm. It also features a customized calibration logic for the characteristics of large model inference token output, while being compatible with mainstream, niche, and new types of computing power hardware. This solves the industry technical barriers of the inability to fairly compare heterogeneous computing power and the narrow range of hardware adaptation, greatly expanding the adaptability of computing power in various scenarios and realizing the implementation and adaptation of commercial computing power metering across all scenarios. Attached Figure Description

[0012] Figure 1 This is a schematic diagram of the hardware device collaboration process for generating the automated conversion factor in this invention; Figure 2 This is a schematic diagram illustrating the technical logic of the heterogeneous computing power hierarchical algorithm calibration of the present invention; Figure 3 This is a block diagram of the technical architecture for third-party automated reproduction and verification of the present invention. Detailed Implementation

[0013] The following describes the complete technical solution of this invention in conjunction with the technical implementation of hardware devices and embedded algorithm programs. The following embodiments are only used to explain the technical solution of this invention and do not constitute a limitation on the scope of protection of this invention. All embodiments are fully automatic operation with software and hardware collaboration, without any manual management, manual rule intervention, or manual parameter adjustment.

[0014] Example 1: Deployment and Implementation of Automated Benchmark Testing Program for All Types of Hardware At the underlying firmware of various heterogeneous computing power testing terminal hardware, a standardized benchmark testing program adapted to mainstream large-scale model architectures is permanently embedded. The program has built-in automated operation logic for multi-parameter scale Transformer and MoE architecture inference tests, adapting to the computing characteristics of consumer-grade, industrial-grade, and service-grade hardware with full-gradient computing power. After the device powers on and completes its self-test, the test program is automatically triggered to start, strictly following the firmware's preset fixed logic to autonomously complete the entire process of continuous token inference calculation, multi-dimensional hardware operation data collection, data statistical noise reduction, and abnormal data filtering, and finally automatically outputs standardized structured test data files. The entire process requires no manual configuration of test parameters, no manual control of test start and stop, and no manual screening and cleaning of data, relying entirely on the hardware and embedded program for autonomous closed-loop operation.

[0015] Example 2: Implementation of Automated Calibration of Heterogeneous Computing Power Across All Categories The data processing terminal has a built-in intelligent hardware architecture recognition algorithm that can accurately identify the chip architecture model of the connected test equipment and automatically complete fine-grained hardware grouping and classification. For test data within the same architecture group, the terminal calls the firmware-embedded Min-Max normalization algorithm to autonomously complete the standardization process.

[0016] Normalization standard calculation formula: x_norm=(x−x_min) / (x_max−x_min) For conventional computing hardware that has already been adapted and integrated into the firmware, the corresponding normalized extreme value parameters are pre-stored within the firmware to ensure the stability and consistency of conventional hardware conversion. For new computing hardware with entirely new architectures that are not yet included in the firmware database, the system automatically adopts a general extreme value range for the same architecture and appropriately expands it to form a conservative extreme value range, completing the initial transitional normalization process. After continuously collecting multiple rounds of steady-state operating data, the embedded algorithm autonomously fits the extreme value parameters specific to this new type of hardware, automatically replacing the original conservative range parameters, and completing adaptive and precise adaptation.

[0017] Data sampling uniformly selects continuous steady-state operating data, automatically removing three types of abnormal data: transient data during device startup, overload data with extremely high load peaks, and low-power idle standby data. Combined with a fixed cross-architecture bridging calibration algorithm, heterogeneous computing power data from different architectures are uniformly mapped to the same universal benchmark computing space, enabling automated and fair horizontal comparison of all categories of heterogeneous computing power, and adapting to the unified conversion requirements of various niche and emerging computing power chips.

[0018] Data sampling uniformly selects continuous 24-hour steady-state operation data, automatically removing three types of abnormal data: transient data during device startup in the first 10 minutes, peak overload data exceeding 120% of rated power, and idle standby data below 10% of rated power. Combined with a fixed cross-architecture bridging calibration algorithm, heterogeneous computing power data from different architectures are uniformly mapped to the same universal benchmark computing space, enabling automated and fair horizontal comparison of all categories of heterogeneous computing power, addressing the industry shortcoming of the inability to uniformly convert niche computing power chips.

[0019] Example 3: Implementation of Fully Automated Iterative Calibration of Standardized Reference Hardware Referencing the hardware's built-in automated iteration program, configure a regular basic retest cycle; the system collects real-time statistical data on the distribution of computing power terminal hardware models across the entire network, and automatically triggers an expedited retest iteration process when the proportion of new computing power hardware across the entire network continuously meets the threshold condition for a preset duration.

[0020] Referencing the built-in automated iteration program of the hardware, the basic retesting cycle is fixed at 90 days; the system collects real-time statistical data on the distribution of computing power terminal hardware models across the entire network, and automatically triggers an expedited retesting iteration process when any new type of computing power hardware accounts for more than 3% of the total computing power across the entire network for 7 consecutive days.

[0021] The equipment autonomously runs a complete set of standardized benchmark testing procedures, collects continuous steady-state operating data of heterogeneous computing hardware of all categories, automatically removes noise and transient abnormal data, and autonomously iterates and updates the cross-architecture bridging calibration coefficients through the least squares fitting algorithm.

[0022] The calibration results adopt a programmed, automated, multi-round cross-reproduction verification and statistical verification mechanism to replace manual voting and manual review. The updated set of calibration parameters is automatically and synchronously distributed across the entire network, archived in version, and stored in on-chain logs without any manual intervention, realizing automated and intelligent iterative updates of the global computing power conversion standard.

[0023] Example 4: Implementation of Fully Automated Fixed Calculation of Conversion Factors The weight parameters are generated by fitting a large amount of steady-state test data of computing power hardware of all categories. The samples cover mainstream, conventional and new heterogeneous computing power hardware on the market. Through fitting and optimization with sufficient effective sample data, the universality and adaptability of the weight parameters are guaranteed, which are in line with the long-term operating characteristics of various computing power hardware.

[0024] The weight parameters were generated by fitting the measured data of millions of computing power hardware across all categories. The samples covered 12 mainstream hardware products, including NVIDIA A100 / H100, Ascend 910B, Cambricon MLU370, and Biren BR100. No less than 1,000 sets of 24-hour steady-state operation data were collected for each hardware product. The total number of effective fitting samples was 1.2 million, and the goodness of fit R² ≥ 0.92.

[0025] The weight parameters strictly satisfy the dual constraints of normalization and non-negativity: w1+w2+w3+w4=1, where w1, w2, w3, and w4 are all between 0 and 1.

[0026] Among them, w1 is the throughput weight, w2 is the inverse weight of inference latency, w3 is the inverse weight of operating energy consumption, and w4 is the operating stability weight. The four-dimensional indicators match the core evaluation dimensions of computing power operation to ensure that the conversion results are reasonable, standardized, and have industry universality.

[0027] Example 5: Third-party automated reproduction verification and extreme condition fault tolerance implementation The third-party verification equipment is equipped with an automated reproduction verification program that can independently pull the original hardware test data, solidified calculation model, and fixed technical configuration parameters stored in the public node, and independently and completely reproduce the entire process of normalization calibration, cross-architecture bridging, and weighted calculation; it automatically compares the difference between the locally reproduced conversion coefficient and the public coefficient, and completes a purely technical and human-independent reliable verification.

[0028] The system has built-in complete fault-tolerant logic for extreme operating conditions: In the event of a network outage, the original test data is automatically cached to a local encrypted storage partition with a reasonable cache capacity and a first-in-first-out (FIFO) cyclic overwrite mechanism. After the network is restored, the data is automatically retransmitted to the on-chain evidence storage node according to the timestamp sequence. In the event of hardware malfunction, the chip temperature, driver status, and memory ECC error are monitored in real time. The test is automatically interrupted upon identification of the malfunction, and the malfunction log is retained. The entire fault-tolerant logic is embedded in the underlying firmware, which can adapt to various complex working conditions such as high concurrency, network outages, and instantaneous hardware failures, ensuring the validity of the converted data and the stability of the process.

[0029] The entire fault-tolerance logic is embedded in the underlying firmware, ensuring that the calculated data is valid and the process is stable under complex conditions such as high concurrency, network outages, and instantaneous hardware failures.

Claims

1. A method for generating a verifiable conversion factor for computing power token output capability, characterized in that, The process is automated and coordinated by computing power conversion terminals, benchmark testing equipment, and evidence storage and disclosure terminals, with no manual rule configuration, parameter adjustment, or process intervention. It includes the following steps: S1. The firmware of the test equipment is embedded at the bottom layer with a standardized benchmark test program set that is compatible with the architecture of large models of all categories. It automatically runs multi-parameter large-scale model inference test tasks that are compatible with the general Transformer architecture and the MoE hybrid expert architecture. It autonomously collects the token running data natively output by various heterogeneous computing power hardware and generates standardized structured test data files. S2. The terminal automatically collects the inherent hardware fingerprint information of the test equipment through the hardware read-only interface, and uses an encrypted hash algorithm to strongly bind the unique hardware fingerprint with the structured test data, thereby completing automated anti-tampering evidence storage and pushing it to the public terminal in real time. S3, the data processing terminal automatically completes the accurate grouping of devices through the built-in hardware architecture intelligent classification algorithm, performs firmware-fixed Min-Max normalization calculation on the test data of devices with the same architecture, and obtains standardized computing power data with a unified benchmark by combining the cross-architecture bridging calibration algorithm. S4. The terminal uses a multi-index weighted calculation model fixed in firmware to perform closed-loop calculation on standardized data and automatically generate a unique token conversion coefficient for the corresponding computing power device. The calculation logic, formula and weight parameters are all fixed and locked in hardware, with no manual modification channel. S5 publicly displays the fixed computing logic, original test data, and calibration parameters of the terminal, supporting automated reproduction and verification by third-party devices throughout the entire process; the system is configured with a regular iteration mechanism with a fixed cycle and is equipped with dynamic monitoring logic for the entire network hardware structure, automatically triggering expedited iteration updates when the popularization of new computing hardware reaches preset objective conditions; at the same time, it has built-in network outage fault tolerance, hardware anomaly identification, and data rollback mechanisms to ensure that the calculation results remain stable and effective under extremely complex working conditions.

2. The method according to claim 1, characterized in that, The benchmark program set has embedded automated inference test logic adapted to the general Transformer architecture and the MoE hybrid expert architecture. It can adapt to hardware computing test scenarios with large models of different parameter scales and is compatible with consumer-grade, industrial-grade, and service-grade full-gradient computing power hardware.

3. The method according to claim 1, characterized in that, The normalization operation is a dedicated data processing logic embedded in the device firmware, which cannot be manually modified or interfered with. The extreme parameters of existing mature computing hardware are pre-fixed and stored in the firmware. For new computing hardware with unknown architecture, the system first completes transitional normalization processing through a general conservative extreme value range, and then autonomously fits the corresponding hardware-specific extreme value parameters and completes adaptive replacement through continuous steady-state data sampling. The entire process is completed independently by the embedded algorithm without any manual data screening, correction or intervention.

4. The method according to claim 1, characterized in that, The cross-architecture bridging calibration coefficients are automatically calibrated and generated by standardized reference hardware devices operated and maintained by authoritative institutions. The firmware of the reference hardware devices' software and hardware operating environment is fixed and locked, and has the characteristic of being untamperable. The reference hardware devices have dual update logic of periodic iteration and dynamic expedited iteration, and can adaptively update the calibration coefficients according to the new hardware iteration situation of the entire network, adapting to the differences of various heterogeneous computing power architectures. The calibration results rely on a procedural, multi-round reproducibility verification mechanism to replace manual review, achieving purely technical and automated updates to the calibration standards.

5. The method according to claim 1, characterized in that, The formula structure and weight ratio parameters of the weighted operation model are permanently fixed in the firmware and have no manual adjustment channel. All weight parameters meet the normalization and non-negativity constraints and are obtained by fitting and optimizing based on the steady-state test data of massive heterogeneous computing power hardware, which is adapted to the long-term operating characteristics and inference output rules of different types of computing power hardware.

6. The method according to claim 1, characterized in that, The process of binding the hardware fingerprint to the test data is an automated encryption operation logic. It generates a unique test fingerprint by concatenating and hashing multiple inherent hardware features, thereby achieving a strong association between the test hardware, the test environment, and the original test data, and preventing the forgery of the test environment and the reuse and tampering of the test data.

7. A verifiable conversion system for computing power token generation capability, characterized in that, For performing the method according to any one of claims 1-6, comprising: The benchmark testing module has a built-in set of standardized test programs that cover all aspects, and is used to automatically perform inference tests on multi-architecture and multi-category computing hardware and collect native hardware operation data. The data encryption and binding module is used to automatically collect the inherent read-only fingerprint of the hardware and complete the encrypted binding of test data with the unique identity of the hardware and the tamper-proof local + on-chain dual evidence storage. The hierarchical calibration calculation module has built-in grouping normalization and cross-architecture bridging calibration solidification algorithms for standardizing heterogeneous computing power test data across all categories. The automatic coefficient calculation module has a built-in fixed weighted calculation model for automatically generating standardized token conversion coefficients without human intervention. The automated verification module is used to publicly disclose and solidify test data and calculation logic, and supports third-party automated reproduction verification and adaptive expedited / regular coefficient iteration updates; The extreme operating condition fault tolerance module has a built-in local encrypted cache, hardware anomaly identification, and data verification rollback program to ensure stable system operation under complex operating conditions such as network outages, high concurrency, and hardware failures.

8. A computing chip, characterized in that, The computing power chip has built-in solidified program instructions. When the program instructions are executed by the chip processor, they implement the verifiable conversion method for computing power token production capacity as described in any one of claims 1-6.

9. A computer-readable storage medium, characterized in that, The storage medium stores a fixed computer program, which, when executed by a processor, implements the verifiable conversion method for computing power token production capacity as described in any one of claims 1-6.

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