System-on-a-Chip and Electronic Devices

Abstract

This application provides a system-on-a-chip (SoC) and an electronic device. The SoC includes: a processor cluster comprising multiple processor cores and a secondary cache controller shared by the multiple processor cores. The secondary cache array includes multiple cache paths; a bus structure coupled between at least one functional module and a slave bus port of the secondary cache controller; the secondary cache controller is configured to configure a portion of the multiple cache paths in cache mode and another portion in general-purpose memory mode according to configuration information; the cache paths in cache mode are used as a shared secondary cache for the multiple processor cores; the cache paths in general-purpose memory mode are mapped to general-purpose random access memory in the SoC address space via the slave bus port for access by the functional module via the bus structure. By employing the above technical solution, the usage mode of the secondary cache can be switched, improving the utilization rate of the secondary cache.

Description

Technical Field

[0001] This application relates to the field of computer technology, and more specifically, to a system-on-a-chip and electronic device. Background Technology

[0002] In a system-on-a-chip, a processor cluster typically includes multiple processor cores and a secondary cache (L2 cache) shared by the multiple processor cores.

[0003] Typically, the size of a secondary cache is quite large, usually ranging from hundreds of KB to MB. However, during actual system-on-a-chip operation, depending on the load, the number of processor cores running may be much smaller than the total number of processor cores. This results in lower utilization of the secondary cache.

[0004] The information disclosed in the background section is only intended to enhance the understanding of the background of this application, and therefore may contain information that is not part of the prior art known to those skilled in the art. Summary of the Invention

[0005] This application provides a system-on-a-chip and an electronic device that can switch the usage mode of the second-level cache and improve the utilization rate of the second-level cache.

[0006] A first aspect of the embodiments of this application provides an on-chip system, comprising: A processor cluster, comprising multiple processor cores and a secondary cache controller shared by the multiple processor cores; A secondary cache storage array, coupled to the secondary cache controller, includes multiple cache paths, each cache path including a storage unit for storing cached data; A bus structure is coupled between at least one functional module and the slave bus port of the secondary cache controller; wherein the functional module is used to initiate access transactions; The secondary cache controller is configured to configure a portion of the plurality of cache paths as cache mode and another portion as general-purpose memory mode according to configuration information; the cache path in cache mode is used as a shared secondary cache for the plurality of processor cores; the cache path in general-purpose memory mode is mapped to general-purpose random access memory in the on-chip system address space via the slave device bus port, so that the functional modules can access it via the bus structure.

[0007] Optionally, the secondary cache controller is configured to isolate cache paths in the general memory mode when processing secondary cache access initiated by the multiple processor cores, so that cache paths in the general memory mode do not participate in the secondary cache tag matching, cache line hit determination, cache line filling and replacement path selection; and cache paths in the cache mode continue to participate in the secondary cache access shared by the multiple processor cores.

[0008] Optionally, the secondary cache controller is configured to, during the process of switching a target cache path from the cache mode to the general memory mode, first prohibit new cache line filling operations and replacement operations from selecting the target cache path, then perform a write-back operation on the dirty cache lines in the target cache path, and invalidate the tag entry corresponding to the target cache path after completing the write-back operation; wherein, the target cache path is at least one cache path to be switched to the general memory mode.

[0009] Optionally, the secondary cache controller is further configured to generate an availability status indication when the dirty cache line write-back of the target cache path is completed, the tag entry invalidation is completed, and the target cache path can be accessed via the slave device bus port; the availability status indication is used to indicate that the target cache path has switched from the cache mode to the general memory mode.

[0010] Optionally, the secondary cache controller is configured to, in response to an access transaction received via the slave device bus port, determine whether the address of the access transaction hits the address window corresponding to the general random access memory; and, in response to the address of the access transaction hitting the address window, access the storage unit in the cache path of the general memory mode according to the offset of the address of the access transaction relative to the address window.

[0011] Optionally, the secondary cache controller is configured to determine a target cache path and an in-path location within the target cache path based on the offset; wherein the in-path location is used to determine at least one of a memory bank, memory row, memory column, or byte location in the target cache path, so as to convert consecutive address accesses in the on-chip system address space into accesses to memory cells within the target cache path.

[0012] Optionally, the bus structure is configured to route access transactions that hit the address region corresponding to the general random access memory to the slave bus port of the secondary cache controller, so that the functional modules coupled to the bus structure can access the storage units corresponding to the cache path in the general memory mode.

[0013] Optionally, the secondary cache controller is configured to receive an access transaction at the slave device bus port and, in response to the access transaction not hitting an address region mapped to the general random access memory, or the cache path corresponding to the access transaction not being in the general memory mode, return an error response via the slave device bus port.

[0014] Optionally, at least one of the plurality of processor cores is configured to access a cache path in the general memory mode by accessing an address in the address space corresponding to the general random access memory; wherein, in response to the address being within an address range starting from a preset base address, the secondary cache controller determines and accesses the cache path corresponding to the address offset based on the address offset of the address relative to the preset base address.

[0015] Optionally, the secondary cache controller is configured to, during the process of switching the target cache path from the general memory mode back to the cache mode, first disable access to the target cache path by the slave device bus port, and wait for the access transaction for the target cache path already received by the slave device bus port to complete; after the access transaction is completed, invalidate the tag entry corresponding to the target cache path, and initialize at least one of the valid bit, dirty bit, replacement status information, error check code information or parity information corresponding to the target cache path, so that the target cache path can be used as the secondary cache again.

[0016] Optionally, the system-on-chip is configured to generate the configuration information based on runtime load information to trigger the switching of the plurality of cache paths between the cache mode and the general memory mode; wherein the runtime load information includes at least one of L2 cache utilization, main device storage requirements, system idle state, or application scenario identifier.

[0017] Optionally, in response to the cache path being configured to the general memory mode, the system on-chip allocates at least a portion of the memory units in the cache path to the target functional module on the bus structure, and records the correspondence between the master device identifier of the target functional module and the general memory address region corresponding to the allocated memory unit; The secondary cache controller is configured to, upon receiving an access transaction to the general random access memory, determine whether the functional module initiating the access transaction is the target master device corresponding to the address region of the general random access memory, based on the master device identifier carried in the access transaction and the address of the access transaction. If the determination result is yes, the access transaction is allowed to access the memory cell corresponding to the general memory address region via the slave device bus port; if the determination result is no, the access transaction is prevented from accessing the general memory address region.

[0018] A second aspect of this application provides an electronic device, including: a system-on-a-chip as described in any of the foregoing embodiments.

[0019] Compared with the prior art, the technical solution of this application embodiment has the following beneficial effects: In the on-chip system provided in this application embodiment, the L2 cache controller is coupled to the L2 cache memory array. Based on the written configuration information, the L2 cache controller can configure a portion of the multiple cache paths in the L2 cache memory array as cache mode and another portion as general-purpose memory mode. The cache paths in cache mode can be used as a shared L2 cache for multiple processor cores, while the cache paths in general-purpose memory mode are mapped to general-purpose random access memory in the on-chip system address space via a device bus port, allowing functional modules to access them via the bus structure. Thus, when the processor cluster is under light load or idle, at least a portion of the L2 cache can be made available to other components, thereby improving the utilization rate of the L2 cache. Furthermore, the memory capacity configured for these components can be reduced accordingly, thereby reducing the area of ​​the on-chip system. Attached Figure Description

[0020] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings: Figure 1 This is a schematic diagram of a system-on-a-chip. Figure 2 This is a schematic diagram of the structure of a system-on-a-chip provided in an embodiment of this application; Figure 3 This is a schematic diagram illustrating the principle of cache path access mode partitioning provided in an embodiment of this application. Detailed Implementation

[0021] See Figure 1 , Figure 1 This is a schematic diagram of a system-on-a-chip.

[0022] System-on-a-chip 100 includes: a processor cluster 110, which includes multiple processor cores (e.g., Figure 1 The schematic shows processor core 101, processor core 102, ..., processor core 10N (where N is an integer greater than 1) and a secondary cache 120 shared by multiple processor cores.

[0023] Normally, L2 cache 120 is used by all processor cores, so L2 cache 120 is set to a large storage capacity.

[0024] In real-world applications, the load on a processor cluster can vary depending on the application.

[0025] For example, in high-performance computing scenarios, multiple processor cores (e.g., processor core 101, processor core 102, ..., processor core 10N) may run simultaneously, resulting in high demand for L2 cache.

[0026] For example, the L2 cache may be underutilized in scenarios where it is idle, lightly loaded, some processor cores are shut down (e.g., only processor core 101 is running), or peripherals or hardware accelerators require temporary data buffers.

[0027] In practical applications, peripherals, direct memory access controllers, image processors, display controllers, neural network processors, communication controllers, or hardware accelerators in a system-on-a-chip often require a certain amount of on-chip memory as a data buffer, descriptor storage area, or intermediate data storage area during operation.

[0028] Dedicated SRAM for these functional modules would increase chip area and power consumption; using external memory could introduce significant access latency and bus bandwidth consumption.

[0029] Therefore, how to reuse a portion of the storage resources in the L2 cache array as on-chip general-purpose memory when the processor cluster has low demand for L2 cache, and switch back to L2 cache use when needed, is a technical problem that urgently needs to be solved.

[0030] Based on this, embodiments of this application provide a system-on-a-chip (SoC) that can switch the usage mode of the L2 cache according to the current load, thereby improving the utilization of the L2 cache. For example, a portion of multiple cache paths can be configured as cache mode for use by the processor core, while another portion can be configured as general-purpose memory mode for use by functional modules.

[0031] To make the technical solutions and advantages of the embodiments of this application clearer, the exemplary embodiments of this application will be described in further detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not an exhaustive list of all embodiments. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other.

[0032] See Figure 2 , Figure 2 This is a schematic diagram of the structure of a system-on-a-chip provided in an embodiment of this application. For example... Figure 2 As shown, the on-chip system 200 may include: Processor cluster 210 includes multiple processor cores (e.g., Figure 2 The schematic includes processor core 201, processor core 202, ..., processor core 20N (where N is an integer greater than 1) and a secondary cache controller 220 shared by the plurality of processor cores; Level 2 cache storage array 230, coupled to the level 2 cache controller 220, includes multiple cache paths (see...). Figure 3 The schematic cache path is 0, cache path 1, cache path 2, cache path 3, ..., cache path D, where D is an integer greater than 0. Each cache path includes a storage unit for storing cached data, that is, each cache path provides a portion of storage space. Bus structure 240, coupled to at least one functional module ( Figure 2 (Not shown) and the slave bus port of the secondary cache controller 220; wherein, the functional module is used to initiate access transactions.

[0033] In some embodiments, the processor core (CPU core) can be a homogeneous processor core or a heterogeneous processor core. For example, the processor core may include one or more high-performance processor cores, one or more low-power processor cores, or processor cores with different instruction set extension capabilities. This application does not impose any limitations on this.

[0034] Among them, cache access requests initiated by multiple processor cores can be sent to the secondary cache controller 220, which performs operations such as tag matching, hit determination, cache line filling, cache line replacement, dirty line write-back, and state maintenance.

[0035] The secondary cache storage array 230 may include multiple cache paths, i.e., multiple ways. Each cache path may include storage units for storing cached data. Each cache path may include one or more banks, and each bank may include multiple storage rows and storage columns.

[0036] The capacity of each cache path can be determined based on the total capacity of the L2 cache, the number of cache paths, the size of cache lines, and the number of groups.

[0037] For example, if the total capacity of the second-level cache is 512KB and the second-level cache includes 16 cache paths, then the data storage capacity corresponding to each cache path can be 32KB. If the size of each cache line is 64 bytes, then each cache path can include multiple storage units organized in units of cache lines.

[0038] It should be noted that the above-mentioned capacity, number of cache paths, and cache line size are merely illustrative examples and do not constitute a limitation on this application.

[0039] In this case, the secondary cache controller 220 is configured to configure a portion of the plurality of cache paths as cache mode and another portion as general-purpose memory mode according to configuration information; the cache path in cache mode is used as a secondary cache shared by the plurality of processor cores; the cache path in general-purpose memory mode may not be used as the secondary cache and may be mapped to general-purpose random access memory in the on-chip system address space via the slave device bus port, so that the functional modules can access it via the bus structure.

[0040] Specifically, in cached mode, multiple cache paths are used together as the second-level cache. After the processor core initiates an access request, the second-level cache controller accesses the corresponding group based on the index field in the access address and reads the tag entries in multiple cache paths for matching. If the tag entry in a cache path matches the access address and the valid bit indicates that it is valid, a cache hit is determined.

[0041] It should be noted that the embodiments of this application do not change the physical structure of the secondary cache storage array, but set configurable cache path attributes in the secondary cache controller, so that some cache paths in the secondary cache storage array can switch from cache mode to general memory mode at runtime.

[0042] In other words, switching the L2 cache to general-purpose memory mode does not mean physically moving the cache path to a peripheral device, nor does it mean changing its physical properties. Instead, it means isolating the cache path from the cache access path through the configuration logic of the L2 cache controller and exposing it as a segment of general-purpose RAM space in the on-chip system address space to the master device on the bus structure through the slave device bus port.

[0043] In some embodiments, the general-purpose memory mode can also be called CLM mode, which stands for Cluster Local Memory mode. The data SRAM corresponding to the cache path in CLM mode can be temporarily not used to store L2 cache data, but instead used as on-chip RAM resources near the processor cluster.

[0044] In this embodiment, the system-on-chip is configured to generate the configuration information based on runtime load information to trigger the switching of the multiple cache paths between the cache mode and the general memory mode; wherein, the runtime load information includes at least one of L2 cache utilization, main device storage requirements, system idle state, or application scenario identifier.

[0045] Specifically, when multiple processor cores are operating under high load, all cache paths can be configured in cache mode, allowing the entire L2 cache array to be used as a shared L2 cache. In this case, the slave device bus port can be disabled, or it can return an error response even if an access transaction is received.

[0046] When the processor cluster is under light load (corresponding to some processor cores being in operation) and the L2 cache miss rate or L2 cache utilization is low, some cache paths can be configured to general memory mode.

[0047] For example, for a 16-way L2 cache, way4 to way15 can be configured as general memory mode, while way0 to way3 can continue to be configured as cache mode.

[0048] At this time, the cache path in cache mode continues to provide L2 cache capability for the processor core, while the cache path in general memory mode can be used as on-chip RAM for functional modules via the slave device bus port.

[0049] Furthermore, in certain application scenarios, even if the processor cores are still running, all or most of the cache paths can be configured in general-purpose memory mode. This is because each processor core typically still has a Level 1 cache (L1Cache), so in some applications with low cache requirements, the processor cluster can operate without a shared Level 2 cache or with a small shared Level 2 cache capacity, thereby reusing more Level 2 cache storage array resources as CLM.

[0050] In this embodiment, the functional module can initiate access transactions as a master device. The functional module may include at least one of a peripheral device, a direct memory access controller, an image processor, a display controller, a neural network processor, a communication controller, or a hardware accelerator.

[0051] Specifically, the direct memory access controller can use the memory unit corresponding to the cache path in general memory mode as a DMA descriptor storage area or a data transfer buffer; the image processor can use it as an image line buffer, block buffer, or intermediate pixel data storage area; the display controller can use it as a temporary buffer for display data; the neural network processor can use it as a storage area for intermediate feature maps, weight segments, or intermediate calculation results; the communication controller can use it as a data transmission and reception buffer, message buffer, or queue descriptor storage area; and the hardware accelerator can use it as a temporary storage area for computation input data, intermediate data, or output data.

[0052] Because this general-purpose random access memory is located inside the system-on-chip and reuses resources from the original L2 cache array, the master device can obtain lower access latency and higher on-chip access bandwidth compared to accessing external memory. Compared to configuring a dedicated RAM for each master device, it can reduce the chip area and improve the utilization rate of L2 cache storage resources in different application scenarios.

[0053] In some embodiments, the secondary cache controller is configured to isolate cache paths in the general memory mode when processing secondary cache access initiated by the plurality of processor cores, so that cache paths in the general memory mode do not participate in the secondary cache tag matching, cache line hit determination, cache line filling and replacement path selection; and cache paths in the cache mode continue to participate in the secondary cache access shared by the plurality of processor cores.

[0054] Specifically, when some cache paths are in general memory mode, during the tag matching stage, the secondary cache controller may not read the tag entry corresponding to that cache path, or even if it reads the tag entry, it may mask the tag matching result of that cache path as a miss.

[0055] During the cache hit determination phase, the secondary cache controller will not consider this cache path as a candidate for a hit; during the cache line filling phase, the secondary cache controller will not fill this cache path with data obtained from external memory or the next level of storage; during the replacement path selection phase, the replacement algorithm will not select this cache path as the cache path to be replaced.

[0056] Correspondingly, cache paths in cache mode are still used as normal L2 cache resources and can continue to participate in tag matching, cache hit determination, cache line filling, and replacement path selection initiated by the processor core.

[0057] By implementing the access isolation described above, the same physical storage unit can be prevented from being used as both a cache and general-purpose RAM, thereby avoiding data overwriting, mislabeling, or consistency errors.

[0058] The following describes the process of switching from cache mode to general memory mode.

[0059] In some embodiments, the secondary cache controller is configured to, during the process of switching a target cache path from the cache mode to the general memory mode, first disable new cache line filling and replacement operations from selecting the target cache path, then perform a write-back operation on the dirty cache lines in the target cache path, and invalidate the tag entry corresponding to the target cache path after completing the write-back operation; wherein, the target cache path is at least one cache path to be switched to the general memory mode.

[0060] Specifically, the system determines whether the switching conditions are met based on the state of the processor cluster. For example, it checks whether the processor cluster is idle or whether the target functional module is about to start and requires an on-chip RAM buffer. Furthermore, it can control relevant processor cores to perform synchronization operations to reduce the probability of the target cache path being frequently accessed during the switching process.

[0061] Once the switching conditions are met, a command register can be written to the L2 cache controller to indicate the target cache path to be switched to in general-purpose memory mode. The target cache path can be a contiguous cache path or a non-contiguous cache path.

[0062] For example, in a 16-way L2 cache, the target cache path can be way4 to way15, or it can be way0, way3, way5, and way10. To simplify address mapping and improve access efficiency, contiguous cache paths are preferred for use as a general memory mode; however, this application does not require that the physical cache paths must be contiguous.

[0063] After receiving a switching command, the secondary cache controller can block the target cache path in the replacement path selection logic, so that the target cache path will no longer be selected as a candidate path for filling new cache lines; at the same time, for newly occurring cache miss requests, the secondary cache controller can select a replacement path only from non-target cache paths.

[0064] After disabling the target cache path from participating in new filling and replacement, the secondary cache controller can perform cleanup operations on existing cache lines in the target cache path. This cleanup operation can include writing back dirty cache lines and invalidating tags. For valid cache lines in the target cache path with a dirty bit indicating they are dirty, the secondary cache controller can write the data of that cache line back to external memory or the next level of storage in the corresponding consistency domain. For valid but not dirty cache lines in the target cache path, the secondary cache controller can directly invalidate their tags.

[0065] In some embodiments, the secondary cache controller can traverse all cache lines in the target cache path according to the group number and check the target cache path tag entries in each group. If the tag entry is valid and the dirty bit is 1, a write-back operation is performed; if the tag entry is valid and the dirty bit is 0, an invalidation operation is performed; if the tag entry itself is invalid, its status bits can be skipped or reinitialized.

[0066] Thus, by performing dirty cache line write-back and tag invalidation operations when switching from cache mode to general memory mode, the loss of dirty data in the cache can be avoided, and the general RAM space after the switch will no longer contain valid cache semantics.

[0067] In some embodiments, the secondary cache controller is further configured to generate an availability status indication when the dirty cache line write-back of the target cache path is completed, the tag entry invalidation is completed, and the target cache path is accessible via the slave device bus port; the availability status indication is used to indicate that the target cache path has switched from the cache mode to the general memory mode.

[0068] Specifically, the secondary cache controller can update the write-back completion status bit in the status register after a write-back operation is completed; and update the tag invalidation completion status bit after a tag entry is invalidated. The software can read the status register to confirm that the old cached data in the target cache path has been processed.

[0069] After completing the dirty cache line write-back and tag invalidation, the Level 2 cache controller can set the mode bit of the target cache path to general memory mode and make the slave bus port accessible for the address window corresponding to the target cache path. The Level 2 cache controller can also initialize the error check code information or parity information required when the target cache path is used as RAM to avoid indeterminate parity errors on the first access.

[0070] When the dirty cache line write-back of the target cache path is completed, the tag invalidation is completed, and the target cache path can be accessed via the slave bus port, the secondary cache controller can generate an availability status indication. The availability status indication can be represented by the READY bit in the status register, a completion interrupt, an event signal, or a hardware handshake signal. Once the software reads the availability status indication, it can confirm that the RAM region is available for allocation to the processor core or functional module.

[0071] In some embodiments, the secondary cache controller is configured to, in response to an access transaction received via the slave device bus port, determine whether the address of the access transaction hits the address window corresponding to the general random access memory; and, in response to the address of the access transaction hitting the address window, access a storage cell in the cache path of the general memory mode according to the offset of the address of the access transaction relative to the address window.

[0072] Specifically, the secondary cache controller can configure one or more general random access memory address windows for cache paths in general memory mode. Each address window may include a base address, a window size, and a set of cache paths corresponding to that address window.

[0073] When the secondary cache controller receives an access transaction from the bus structure via the slave device bus port, the secondary cache controller can first parse the access address carried by the access transaction and determine whether the access address hits the configured general random access memory address window.

[0074] If the access address does not hit any configured address window, the secondary cache controller can reject the access or return an error response; if the access address hits an address window, the secondary cache controller can calculate the offset of the access address relative to the base address of that address window.

[0075] Subsequently, the L2 cache controller can access the corresponding memory cell in the cache path configured in general memory mode based on this offset. In other words, an access to a contiguous address region in the on-chip system address space by a functional module or processor core can be translated by the L2 cache controller into an access to a cache path in the L2 cache array configured in general memory mode. In this way, cache paths in general memory mode can be presented externally as ordinary RAM addresses, without requiring the initiating functional module to understand the internal implementation details of cache paths, banks, sets, or cache lines.

[0076] More specifically, the secondary cache controller is configured to determine a target cache path and an in-path location within the target cache path based on the offset; wherein the in-path location is used to determine at least one of a memory bank, memory row, memory column, or byte location within the target cache path, so as to convert consecutive address accesses in the on-chip system address space into accesses to memory cells within the target cache path.

[0077] In some embodiments, a portion of the high bits of the offset can be used to determine the logical cache path number, a portion of the middle bits of the offset can be used to determine the storage bank, storage row, or storage column within the cache path, and the low bits of the offset can be used to determine the byte position or byte enable information.

[0078] The secondary cache controller can further determine the actual physical cache path based on the logical cache path number and the cache path mapping table.

[0079] For example, if each cache path has a capacity of 32KB and way4 through way7 are configured in general memory mode, then the first 32KB address space starting from the base address can be mapped to way4, the second 32KB address space can be mapped to way5, the third 32KB address space can be mapped to way6, and the fourth 32KB address space can be mapped to way7.

[0080] For example, when the access address is the base address plus a certain offset, the secondary cache controller can first determine which logical RAM segment it falls into based on the offset, then convert the logical RAM segment into the corresponding physical way, and determine the bank, row, column or byte position in the way based on the remaining bits in the offset.

[0081] In other words, the following mapping method can be used: determine the logical cache path number based on the high-order bits of the offset, determine the bank, set, or row address in the target cache path based on the middle bits of the offset, and determine the column address or byte position based on the low-order bits of the offset. The logical cache path number can then be converted to the actual physical cache path number using a cache path mapping table.

[0082] Therefore, contiguous address accesses in the on-chip system address space can be converted into accesses to internal memory units of one or more cache paths. Even if cache paths actually configured in general-purpose memory mode are not physically contiguous, they can still be presented as contiguous RAM space externally through cache path mapping tables or address remapping logic.

[0083] Accordingly, the bus structure is configured to route access transactions that hit the address region corresponding to the general random access memory to the slave bus port of the secondary cache controller, so that the functional modules coupled to the bus structure can access the memory cells corresponding to the cache path in the general memory mode.

[0084] Specifically, when a cache path in general memory mode is mapped to a general RAM address region in the on-chip system address space, the bus structure can configure that general RAM address region as a slave bus port pointing to the secondary cache controller.

[0085] In this way, when a functional module on the bus structure initiates an access transaction and the address of the access transaction hits the address region corresponding to the general random access memory, the bus structure can route the access transaction to the slave bus port of the secondary cache controller according to the address decoding result, instead of routing it to the external memory controller, general on-chip SRAM or other slave devices.

[0086] After receiving the access transaction from the device bus port, the secondary cache controller accesses the memory cell corresponding to the cache path in general memory mode based on the access address, address window, and cache path mapping relationship. The above routing relationship in the bus structure can be fixedly configured during the chip design phase or dynamically configured through the bus address mapping register.

[0087] Through this routing mechanism, master devices coupled to the bus architecture can access the L2 cache storage resources that have been switched to general memory mode using standard bus access methods.

[0088] In some embodiments, in response to the cache path being configured in the general memory mode, the system-on-chip allocates at least a portion of the memory units in the cache path to a target functional module on the bus structure, and records the correspondence between the master device identifier of the target functional module and the general memory address region corresponding to the allocated memory unit; wherein, the secondary cache controller is configured to, upon receiving an access transaction to access the general random access memory, determine whether the master device initiating the access transaction is the target functional module corresponding to the general memory address region based on the master device identifier carried by the access transaction and the address of the access transaction; in response to the determination result being yes, allow the access transaction to access the memory unit corresponding to the general memory address region via the slave device bus port; in response to the determination result being no, prevent the access transaction from accessing the general memory address region.

[0089] Specifically, when certain cache paths are configured in general memory mode, the system on-chip can further allocate all or part of the memory units in the cache path to the target functional module on the bus structure, and record the correspondence between the master device identifier of the target functional module and the general memory address region corresponding to the allocated memory unit.

[0090] This mapping can be recorded in the permission register, address window configuration register, access control table, or access permission configuration unit of the bus structure of the secondary cache controller. The master device identifier can be the master ID, port number, security domain identifier, virtual channel identifier, or other information that can distinguish the access initiator carried in the access transaction.

[0091] When the secondary cache controller receives an access transaction for general random access memory, it can determine whether the master device initiating the access transaction is the target functional module corresponding to the address region of the general random access memory based on the master device identifier and access address carried in the access transaction.

[0092] If the determination result is yes, the secondary cache controller allows the access transaction to access the memory unit corresponding to the corresponding address region via the slave device bus port; if the determination result is no, the secondary cache controller prevents the access transaction from accessing the corresponding memory unit and may return an error response or a permission exception response.

[0093] For example, a 64KB RAM address region formed by way4 and way5 can be allocated to the DMA controller, and a 32KB RAM address region formed by way6 can be allocated to the image processor. The master device identifiers of the DMA controller and the image processor and their corresponding address regions can be recorded in the access control table, respectively.

[0094] Therefore, even if multiple functional modules can reach the slave bus port of the secondary cache controller through the bus structure, only the authorized target master device can access the general RAM area allocated to it, thereby realizing dynamic allocation and access isolation of on-chip storage resources.

[0095] In some embodiments, the secondary cache controller is configured to receive an access transaction at the slave device bus port and, in response to the access transaction missing an address region mapped to the general random access memory, or the cache path corresponding to the access transaction not being in the general memory mode, return an error response via the slave device bus port.

[0096] In short, if an access transaction is received from the device bus port, but the address of the access transaction does not hit any configured general random access memory address window, or the access transaction hits an address window but its corresponding cache path is not in general memory mode, the secondary cache controller can return an error response.

[0097] For example, it can return SLVERR, DECERR, or other error response signals from the bus protocol. This prevents the master device from accidentally accessing L2 cache storage resources that are not open or not configured as RAM.

[0098] In some embodiments, even if a portion of the cache path is in general memory mode, at least one processor core can still access the cache path.

[0099] Specifically, at least one of the plurality of processor cores is configured to access a cache path in the general memory mode by accessing an address in the address space corresponding to the general random access memory; wherein, in response to the address being within an address range starting from a preset base address, the secondary cache controller determines and accesses the cache path corresponding to the address offset based on the address offset of the address relative to the preset base address.

[0100] Specifically, when the processor core accesses a cache path that is used as general-purpose random access memory, it can access a cache path in general-purpose memory mode by configuring the accessed address. Meanwhile, when the processor core accesses a normal cacheable address, the L2 cache controller can still use the cache path in cache mode to access the L2 cache.

[0101] In other words, when cache paths are configured as general-purpose random access memory, an address is assigned as a base address for these cache paths. If the processor core accesses based on this base address, the secondary cache controller can map this base address to the corresponding cache path.

[0102] Similarly, if the secondary cache controller is for a regular cache path, then normal access will be to a cache path that is not configured as a CLM.

[0103] The following describes the process of switching back from general-purpose memory mode to cache mode.

[0104] In some embodiments, the secondary cache controller is configured to, during the process of switching a target cache path from the general memory mode back to the cache mode, first disable access to the target cache path by the slave device bus port, and wait for the access transaction for the target cache path already received by the slave device bus port to complete; after the access transaction is completed, invalidate the tag entry corresponding to the target cache path, and initialize at least one of the valid bit, dirty bit, replacement status information, error check code information, or parity information corresponding to the target cache path, so that the target cache path can be used as the secondary cache again.

[0105] Specifically, when switching a target cache path from general-purpose memory mode back to cache mode, first ensure that the functional module using that general-purpose RAM area has stopped accessing it or has completed its corresponding task. For example, DMA transfers can be stopped, the hardware accelerator can be allowed to complete its computation, or the allocation of the relevant address area can be revoked.

[0106] Subsequently, a switch command is written to the secondary cache controller, indicating the target cache path to be switched back to cache mode. In response to this command, the secondary cache controller first disables new access to the target cache path from the device bus port. For example, the secondary cache controller can close the corresponding address window or mark the address window as inaccessible.

[0107] After prohibiting new access, the secondary cache controller can wait for in-transit access transactions for the target cache path that have already been received by the slave device bus port to complete. In-transit access transactions can include received but not yet completed data read transactions, write transactions, or burst transactions. The secondary cache controller can determine whether in-transit transactions have been cleared by using an internal counter or the transaction queue status.

[0108] After confirming that the access transaction for the target cache path is completed on the slave device bus port, the secondary cache controller can invalidate the tag entry corresponding to the target cache path and initialize at least one of the valid bit, dirty bit, replacement status information, error check code information or parity information corresponding to the target cache path.

[0109] It should be noted that when switching back from general-purpose memory mode to cache mode, data written during the general-purpose memory mode is typically used as RAM data and does not have L2 cache tag semantics. Therefore, when switching back to cache mode, it is generally not necessary to write this RAM data back to external memory as cache data; if it is necessary to retain this RAM data, it needs to be copied or moved to another storage area before the switch. The L2 cache controller primarily ensures that the tag and cache state of the target cache path are in an invalid and deterministic initial state when switching back to cache mode.

[0110] After the target cache path's tag entry is invalidated and its status information is initialized, the L2 cache controller can set the target cache path's mode bit to cache mode and allow the replacement path selection logic and cache line filling logic to reselect the target cache path. Afterward, the target cache path can be reused as part of the L2 cache shared by multiple processor cores.

[0111] In some embodiments, the secondary cache controller can generate a cache availability status indication after a switchback is completed. The software can confirm that the target cache path has been re-added to the secondary cache by reading the status register or receiving an interrupt.

[0112] See Figure 3 , Figure 3 This is a schematic diagram illustrating the principle of cache path access mode partitioning provided in an embodiment of this application.

[0113] See Figure 3 The processor cluster 210 includes processor core 0, processor core 1, processor core 2, ..., processor core M, and the shared secondary cache storage array is divided into cache path 0, cache path 1, cache path 2, cache path 3, ..., cache path D. M and D are both integers greater than 0.

[0114] Furthermore, cache path 0, cache path 1, and cache path 2 are configured in general memory mode, so that peripheral 0, peripheral 1, and peripheral 2 can use cache path 0, cache path 1, and cache path 2 via bus structure 240 (e.g., BUS Fabric).

[0115] Cache path 3, ..., cache path D are configured in cache mode and continue to be used as a shared L2 cache for the processor cores.

[0116] It is understood that the above embodiments provide multiple implementation schemes, and these implementation schemes can be combined and cross-referenced with each other without conflict, thereby extending to multiple possible implementation schemes. These can all be considered as the implementation schemes disclosed and made public in this application.

[0117] This application also provides an electronic device, which may include: the system-on-a-chip described in any of the foregoing embodiments.

[0118] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0119] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A system-on-a-chip, characterized in that, include: A processor cluster, comprising multiple processor cores and a secondary cache controller shared by the multiple processor cores; A secondary cache storage array, coupled to the secondary cache controller, includes multiple cache paths, each cache path including a storage unit for storing cached data; A bus structure is coupled between at least one functional module and the slave bus port of the secondary cache controller; the functional module is used to initiate access transactions; The secondary cache controller is configured to configure a portion of the plurality of cache paths as cache mode and another portion as general-purpose memory mode according to configuration information; the cache path in cache mode is used as a shared secondary cache for the plurality of processor cores; the cache path in general-purpose memory mode is mapped to general-purpose random access memory in the on-chip system address space via the slave device bus port, so that the functional modules can access it via the bus structure.

2. The system-on-a-chip according to claim 1, characterized in that, The secondary cache controller is configured to isolate cache paths in the general memory mode when processing secondary cache access initiated by the multiple processor cores, so that cache paths in the general memory mode do not participate in secondary cache tag matching, cache line hit determination, cache line filling and replacement path selection; and cache paths in the cache mode continue to participate in secondary cache access shared by the multiple processor cores.

3. The system-on-a-chip according to claim 1, characterized in that, The secondary cache controller is configured to, during the process of switching a target cache path from the cache mode to the general memory mode, first disable new cache line filling and replacement operations from selecting the target cache path, then perform a write-back operation on the dirty cache lines in the target cache path, and invalidate the tag entry corresponding to the target cache path after completing the write-back operation; wherein, the target cache path is at least one cache path to be switched to the general memory mode.

4. The system-on-a-chip according to claim 3, characterized in that, The secondary cache controller is also configured to generate an availability status indication when the dirty cache line write-back of the target cache path is completed, the tag entry invalidation is completed, and the target cache path can be accessed via the slave device bus port; the availability status indication is used to indicate that the target cache path has switched from the cache mode to the general memory mode.

5. The system-on-a-chip according to claim 1, characterized in that, The secondary cache controller is configured to, in response to an access transaction received via the slave device bus port, determine whether the address of the access transaction hits the address window corresponding to the general random access memory; and, in response to the address of the access transaction hitting the address window, access the memory cell in the cache path of the general memory mode according to the offset of the address of the access transaction relative to the address window.

6. The system-on-a-chip according to claim 5, characterized in that, The secondary cache controller is configured to determine a target cache path and an in-path location within the target cache path based on the offset; wherein the in-path location is used to determine at least one of a memory bank, memory row, memory column, or byte location within the target cache path, so as to convert consecutive address accesses in the on-chip system address space into accesses to memory units within the target cache path.

7. The system-on-a-chip according to claim 1, characterized in that, The bus structure is configured to route access transactions that hit the address region corresponding to the general random access memory to the slave bus port of the secondary cache controller, so that the functional modules coupled to the bus structure can access the storage units corresponding to the cache path in the general memory mode.

8. The system-on-a-chip according to claim 1, characterized in that, The secondary cache controller is configured to receive an access transaction at the slave device bus port and, in response to the access transaction missing an address region mapped to the general random access memory, or the cache path corresponding to the access transaction not being in the general memory mode, return an error response via the slave device bus port.

9. The system-on-a-chip according to claim 1, characterized in that, At least one of the plurality of processor cores is configured to access a cache path in the general memory mode by accessing an address in the address space corresponding to the general random access memory; wherein, in response to the address being within an address range starting from a preset base address, the secondary cache controller determines and accesses the cache path corresponding to the address offset based on the address offset of the address relative to the preset base address.

10. The system-on-a-chip according to claim 1, characterized in that, The secondary cache controller is configured to, during the process of switching the target cache path from the general memory mode back to the cache mode, first disable access to the target cache path by the slave device bus port, and wait for the access transaction for the target cache path already received by the slave device bus port to complete. After the access transaction is completed, the tag entry corresponding to the target cache path is made invalid, and at least one of the valid bit, dirty bit, replacement status information, error check code information or parity information corresponding to the target cache path is initialized so that the target cache path can be used as the secondary cache again.

11. The system-on-a-chip according to claim 1, characterized in that, The on-chip system is configured to generate the configuration information based on runtime load information to trigger the switching of the multiple cache paths between the cache mode and the general memory mode; The runtime load information includes at least one of the following: secondary cache utilization rate, main device storage requirements, system idle status, or application scenario identifier.

12. The system-on-a-chip according to claim 1, characterized in that, In response to the cache path being configured to the general memory mode, the system on-chip allocates at least a portion of the memory units in the cache path to the target functional module on the bus structure, and records the correspondence between the master device identifier of the target functional module and the general memory address region corresponding to the allocated memory unit; The secondary cache controller is configured to, upon receiving an access transaction to the general random access memory, determine whether the master device initiating the access transaction is the target functional module corresponding to the address region of the general random access memory, based on the master device identifier carried in the access transaction and the address of the access transaction. If the determination result is yes, the access transaction is allowed to access the memory cell corresponding to the general memory address region via the slave device bus port; if the determination result is no, the access transaction is prevented from accessing the general memory address region.

13. An electronic device, characterized in that, include: The system-on-a-chip as described in any one of claims 1 to 12.

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