Management systems and methods for inter-chip data transmission, electronic devices

Abstract

This disclosure provides a management system and method for inter-chip data transmission, and an electronic device. The system includes at least two chips for data interaction, each chip being configured with a transmitting module and a receiving module. By setting a credit metering unit in the transmitting module of the first chip and a credit recovery unit in the receiving module of the second chip, the system deducts the corresponding credit limit when the transmitting module sends data to the receiving module. After the receiving module completes the buffer release of received data, the credit limit is accumulated according to the amount of data released. When the accumulated credit limit reaches a preset threshold, it is sent to the transmitting module. The transmitting module bypasses the receiving module and transmits the accumulated credit limit to a delayed path on the control bus. The transmitting module then adds the received accumulated credit limit to the credit metering unit. By establishing dynamic feedback of the credit limit between the transmitting and receiving modules, the data transmission throughput between the chips is improved.

Description

Technical Field

[0001] This disclosure relates to the field of chip technology, and in particular to a management system and method for inter-chip data transmission, and an electronic device. Background Technology

[0002] In a chip system integrating multiple chips, the chips interact with each other through a target link. Each chip is equipped with a sending module and a receiving module to send and receive data. However, in practical applications, the round-trip delay of cross-chip data transmission is relatively large. If the buffer capacity of the receiving module is insufficient, it will usually cause transmission interruption, thereby reducing the overall data transmission throughput between chips. Summary of the Invention

[0003] This disclosure provides a management system and method for inter-chip data transmission, as well as an electronic device, to solve the problem in the related art where the round-trip delay of data transmission across chips is large, and if the buffer capacity of the receiving module is insufficient, it will usually cause transmission interruption, thereby reducing the overall data transmission throughput between chips.

[0004] According to a first aspect of this disclosure, a management system for inter-chip data transmission is provided. The system includes at least two chips for data interaction, each chip being configured with a transmitting module and a receiving module. The sending module includes a credit metering unit, used to deduct the credit limit corresponding to the data when the sending module of the first core sends data to the receiving module of the second core; wherein, the initial value of the credit metering unit is matched with the buffer carrying capacity of the receiving module of the second core; The receiving module includes a credit recovery unit, which is used to accumulate credit limits according to the amount of data released when the receiving module of the second core completes the buffer release of the received data, and send the accumulated credit limits to the sending module of the first core when the accumulated credit limits reach a preset threshold; wherein the sending module bypasses the receiving module to transmit the accumulated credit limits to the delay path of the control bus; The sending module is used to add the received accumulated credit limit to the credit measurement unit.

[0005] In some embodiments of this disclosure, the transmitting module further includes a transmitting channel control unit, and the receiving module further includes a receiving channel control unit. Each transmitting channel control unit is configured with a corresponding credit measurement unit, and each receiving channel control unit is configured with a corresponding credit recovery unit. The sending channel control unit is configured to send the data and trigger the credit measurement unit to deduct the credit limit corresponding to the data when the current credit limit in the credit measurement unit is greater than zero; and to pause sending the data when the current credit limit is equal to zero. The receiving channel control unit is used to trigger the credit recovery unit to accumulate the credit limit corresponding to the data after receiving the data through the target link, and then transmit the bus signal to the control bus after restoring the received data to a bus signal format that matches the control bus.

[0006] In some embodiments of this disclosure, the receiving module is further configured to, The accumulated credit limit is transmitted to the sending module through redundant bits in the data payload of the data bus; wherein, the data payload is the data portion of the data bus that carries cross-core transmission data, and the redundant bits are the remaining bits in the data payload that are not involved in the data valid bits; The data payload is divided into at least two transmission bearer segments, each of which is an independent bit region within the data payload. The write access transmission channel occupies the first transmission bearer segment, while the read request channel, read data channel, and write response channel time-multiplex the second transmission bearer segment. The bit width of the first transmission bearer segment is greater than the bit width of the second transmission bearer segment. The second transmission bearer segment is provided with a credit limit bit and a channel indicator bit. The channel indicator bit is used to identify the channel type to which the credit limit carried by the credit limit bit belongs. The channel type includes the write access transmission channel, the read request channel, the read data channel, and the write response channel.

[0007] In some embodiments of this disclosure, the credit recovery unit is used for, When the data transmission frequency is greater than or equal to a preset frequency, the preset threshold is lowered to increase the credit limit return speed. When the data transmission frequency is lower than the preset frequency, the preset threshold is increased to reduce the frequency of credit limit feedback.

[0008] In some embodiments of this disclosure, the transmitting module is used to parse the accumulated credit limit from the data payload transmitted by the receiving module; wherein the delay path is the path that the receiving module takes to restore the received data into a bus signal adapted to the control bus.

[0009] In some embodiments of this disclosure, the transmitting channel control unit and the receiving channel control unit are used to construct at least one virtual transmission channel between the transmitting channel and the receiving channel, wherein the virtual transmission channel is a transmission channel formed by mapping the transmitting channel control unit and the corresponding receiving channel control unit; The at least one virtual transmission channel is used to independently configure the corresponding credit measurement unit and credit recovery unit.

[0010] In some embodiments of this disclosure, the transmitting module includes a register unit, a data bus master interface unit is provided between the transmitting module and the data bus, and a data bus slave interface unit is provided between the receiving module and the data bus; the transmitting module and the receiving module constitute a conversion module; wherein... The register unit is used to cache the encoded and packaged data to be sent; The data bus master interface unit is used to read data from the register unit and generate a data bus write access, which is then transmitted to the data bus slave interface unit via the data bus and the target link between the cores. The data bus slave interface unit is used to receive the data bus write access transmitted via the target link and the data bus, separate the data payload from the data bus write access, and transmit it to the receiving module.

[0011] According to a second aspect of this disclosure, a method for managing inter-chip data transmission is provided, the method being applied to a credit metering unit, comprising: The current credit limit is checked. If the current credit limit is greater than zero, the sending module of the first core is triggered to send data and deduct the credit limit corresponding to the data. The initial value of the credit limit is matched with the buffer carrying capacity of the receiving module of the second core. The sending module bypasses the receiving module and transmits the accumulated credit limit to the delay path of the control bus. Receive the accumulated credit limit from the second chip and add the accumulated credit limit to the current credit limit.

[0012] According to a third aspect embodiment of this disclosure, a method for managing inter-chip data transmission is provided, the method being applied to a credit recovery unit, comprising: Once the receiving module of the second chip has completed the buffer release of received data, the credit limit is accumulated according to the amount of data released; Determine whether the accumulated credit limit has reached the preset threshold; When it is determined that the accumulated credit limit reaches the preset threshold, the accumulated credit limit is encoded into the data payload of the data bus and fed back to the first core; wherein, the transmitting module bypasses the receiving module to transmit the accumulated credit limit to the delay path of the control bus.

[0013] According to a fourth aspect of this disclosure, a management device for inter-chip data transmission is provided, the device being applied to a credit metering unit, comprising: The checking unit is used to check the current credit limit. If the current credit limit is determined to be greater than zero, the sending module of the first chip is triggered to send data and deduct the credit limit corresponding to the data. The initial value of the credit limit is matched with the buffer carrying capacity of the receiving module of the second chip. The sending module bypasses the receiving module and transmits the accumulated credit limit to the delay path of the control bus. The receiving unit is configured to receive the accumulated credit limit fed back by the second chip and add the accumulated credit limit to the current credit limit.

[0014] According to a fifth aspect embodiment of this disclosure, a management device for inter-chip data transmission is provided, the device being applied to a credit recovery unit, comprising: The accumulation unit is used to accumulate the credit limit based on the amount of data released when the receiving module of the second chip completes the buffer release of received data. The judgment unit is used to determine whether the accumulated credit limit has reached a preset threshold. The feedback unit is used to encode the accumulated credit limit into the data payload of the data bus and feed it back to the first core when it is determined that the accumulated credit limit has reached the preset threshold; wherein the sending module bypasses the receiving module to transmit the accumulated credit limit to the delay path of the control bus.

[0015] According to a sixth aspect of this disclosure, an electronic device is provided, comprising: At least one processor; and A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method described in the second or third aspect of the preceding embodiments.

[0016] According to a seventh aspect embodiment of the present disclosure, a non-transitory computer-readable storage medium storing computer instructions is provided, wherein the computer instructions are configured to cause the computer to perform the methods described in the second or third aspect embodiments described above.

[0017] According to an eighth aspect embodiment of the present disclosure, a computer program product is provided, including a computer program that, when executed by a processor, implements the method described in the foregoing second or third aspect embodiments.

[0018] The present disclosure provides a management system and method for inter-chip data transmission, and an electronic device. The system includes at least two chips for data interaction, each chip being configured with a transmitting module and a receiving module. By setting a credit metering unit in the transmitting module of the first chip and a credit reclamation unit in the receiving module of the second chip, the initial value of the credit metering unit is matched with the buffer capacity of the receiving module of the second chip. When the transmitting module sends data to the receiving module, the corresponding credit limit is deducted. After the receiving module releases the buffer of received data, the credit limit is accumulated according to the amount of data released. When the accumulated credit limit reaches a preset threshold, it is sent to the transmitting module. The transmitting module bypasses the receiving module and transmits the accumulated credit limit to a delayed path on the control bus, whereby the transmitting module adds the received accumulated credit limit to the credit metering unit. By establishing dynamic feedback of the credit limit between the transmitting and receiving modules, the transmitting module's sending action can be adjusted according to the actual release progress of the receiving module's buffer, thereby improving the data transmission throughput between the chips.

[0019] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this application, nor is it intended to limit the scope of this application. Other features of this application will become readily apparent from the following description. Attached Figure Description

[0020] The accompanying drawings are provided to better understand this solution and do not constitute a limitation of this disclosure. Wherein: Figure 1 A schematic diagram of the structure of a management system for inter-chip data transmission provided in an embodiment of this disclosure; Figure 2 This is a schematic diagram of the overall structure of a management system for inter-chip data transmission provided in an embodiment of this disclosure; Figure 3 This is a schematic diagram of a data bus write access signal and credit limit encoding in the data payload provided in an embodiment of this disclosure; Figure 4 A flowchart illustrating a management method for inter-chip data transmission provided in an embodiment of this disclosure; Figure 5 A flowchart illustrating another method for managing inter-chip data transmission provided in this embodiment of the disclosure; Figure 6A schematic diagram of the structure of a management device for inter-chip data transmission provided in an embodiment of this disclosure; Figure 7 A schematic diagram of the structure of another management device for inter-chip data transmission provided in an embodiment of this disclosure; Figure 8 A schematic block diagram of an example electronic device provided for embodiments of this disclosure. Detailed Implementation

[0021] The exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments to aid understanding, and should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this disclosure. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.

[0022] The management system and method for inter-chip data transmission, and electronic devices according to embodiments of the present disclosure are described below with reference to the accompanying drawings.

[0023] Figure 1 This is a schematic diagram of the structure of a management system for inter-chip data transmission provided in an embodiment of this disclosure.

[0024] like Figure 1 As shown, the system includes at least two cores for data interaction, each core being configured with a transmitting module A and a receiving module B; wherein, The sending module A includes a credit measurement unit a1, which is used to deduct the credit limit corresponding to the data when the sending module A of the first core sends data to the receiving module B of the second core; wherein, the initial value of the credit measurement unit a1 is matched with the buffer carrying capacity of the receiving module B of the second core. The receiving module B includes a credit recovery unit b1, which is used to accumulate credit limits according to the amount of data released when the receiving module B of the second core completes the buffer release of the received data, and send the accumulated credit limits to the sending module A of the first core when the accumulated credit limits reach a preset threshold; wherein the sending module A bypasses the receiving module B to transmit the accumulated credit limits to the control bus via a delayed path. The sending module A is used to add the received accumulated credit limit to the credit measurement unit a1.

[0025] In some embodiments, the credit limit maintained by the credit metering unit a1 in the sending module A is initially the same as the buffer capacity of the receiving module B in the second core, so that the total amount of data that the sending module A is allowed to send matches the available buffer space of the receiving module B before the cross-core data transmission begins. When the sending module A sends data to the receiving module B, the credit metering unit a1 deducts the corresponding credit limit according to the actual amount of data sent. The deduction method includes, but is not limited to, deduction based on the number of data packets sent, or deduction based on the number of data bytes sent. In specific implementation, it can be set according to the data unit agreed upon by the two parties in the cross-core communication, and is not specifically limited.

[0026] After receiving data from the first core transmitting module A via the target link, receiving module B stores the data in its local buffer. When the internal processing logic of receiving module B retrieves the data from the buffer and restores it to a bus signal format compatible with the control bus before transmitting it to the control bus, the buffer release of the received data is complete. After each buffer release operation, credit recovery unit b1 accumulates the corresponding credit limit based on the actual amount of data released. This credit limit accumulation can be related to the number of data packets or the number of bytes released; the specific granularity of accumulation is not limited.

[0027] To reasonably control the frequency of credit limit feedback across different cores, a preset threshold is pre-configured in the credit recovery unit b1. This preset threshold is used to determine whether the currently accumulated credit limit meets the conditions for initiating feedback. When the credit recovery unit b1 detects that the currently accumulated credit limit has reached the preset threshold, it triggers the action of sending the accumulated credit limit to the sending module A of the first core. The physical path of the above sending action can be implemented through the cross-core link itself for data transmission, or it can be implemented using the attached channel of the cross-core data link. This embodiment does not limit the specific sending medium.

[0028] After receiving the accumulated credit limit from the receiving module B, the sending module A directly parses the accumulated credit limit from the data payload of the data bus write access. This parsing process bypasses the delay path of the receiving module B restoring the received data to the bus signal adapted to the control bus; that is, it does not wait for the receiving module B to generate the standard control bus access, nor does it enter the receiving module B's receive buffer. Instead, it extracts the credit limit directly from the data payload. Subsequently, the sending module A adds the parsed accumulated credit limit to its own credit measurement unit a1. This addition restores the available credit limit in credit measurement unit a1, enabling the sending module A to regain authorization to send subsequent data to the receiving module B of the second core. Based on the aforementioned cyclical process of initial matching, sending deduction, buffer release accumulation, threshold determination return, and receiving-end addition, a dynamic feedback mechanism based on the actual release progress of the receiving-end buffer is formed between credit measurement unit a1 and credit recovery unit b1.

[0029] It should be noted that the target link between the two cores in this embodiment can adopt physical communication channels including but not limited to UCIe high-speed serial links or PCIe high-speed serial links, as long as the target link can realize bidirectional data interaction between the cores. Meanwhile, the specific values ​​of the unit for credit limit deduction, the unit for accumulation, and the preset threshold can be configured based on the actual round-trip delay time of the cross-core transmission link in the current system, the buffer capacity of the receiving module B, and the bandwidth utilization of the target link. For example, in one embodiment, the preset threshold can be set to half of the buffer capacity; in another embodiment, the value of the preset threshold can be adjusted in real time according to the length of the cross-core round-trip delay period. The above examples are merely illustrative and do not limit the specific content.

[0030] Through the above structure, a dynamic credit limit feedback mechanism based on buffer release progress is established between the transmitting module of the first core and the receiving module of the second core. This mechanism allows the transmitting module's transmitting actions to be adjusted according to the actual release progress of the receiving module's buffer, thereby avoiding data transmission interruptions caused by insufficient receiving buffer, reducing the impact of cross-core round-trip delay on data transmission continuity, and improving the overall data transmission throughput between cores.

[0031] In summary, according to the inter-chip data transmission management system provided in this disclosure, the system includes at least two chips for data interaction, each chip being configured with a sending module and a receiving module. By setting a credit metering unit in the sending module of the first chip and a credit reclamation unit in the receiving module of the second chip, the system deducts the corresponding credit limit when the sending module sends data to the receiving module. After the receiving module completes the buffer release of the received data, the credit limit is accumulated according to the amount of data released. When the accumulated credit limit reaches a preset threshold, it is sent to the sending module. The sending module bypasses the receiving module and transmits the accumulated credit limit to a delayed path on the control bus, whereby the sending module adds the received accumulated credit limit to the credit metering unit. By establishing dynamic feedback of the credit limit between the sending and receiving modules, the sending action of the sending module can be adjusted according to the actual release progress of the receiving module's buffer, thereby improving the data transmission throughput between the chips.

[0032] Please continue reading. Figure 1 The sending module A further includes a sending channel control unit a2, and the receiving module B further includes a receiving channel control unit b2. Each sending channel control unit a2 is configured with a corresponding credit measurement unit a1, and each receiving channel control unit b2 is configured with a corresponding credit recovery unit b1; wherein, The sending channel control unit a2 is used to send the data and trigger the credit measurement unit to deduct the credit limit corresponding to the data when the current credit limit in the credit measurement unit a1 is greater than zero; and to pause sending the data when the current credit limit is equal to zero. The receiving channel control unit b2 is used to trigger the credit recovery unit b1 to accumulate the credit limit corresponding to the data after receiving the data through the target link, and then transmit the bus signal to the control bus after restoring the received data to a bus signal format that matches the control bus.

[0033] In some embodiments, the transmitting channel control unit a2 performs a credit limit check on the data packets to be transmitted. During the check, it first reads the current credit limit of the corresponding credit metering unit a1. If the current credit limit is greater than zero, it reads a data packet from the data queue to be transmitted, writes the data packet into the corresponding data payload transmission bearer segment, and simultaneously triggers the credit metering unit a1 to deduct the credit limit corresponding to the data packet. If the current credit limit is equal to zero, it suspends the transmission of the data until a subsequent credit limit is received to restore the available credit limit. The reading rules of the data queue to be transmitted can be set according to the bus protocol rules used across chips. For example, in an embodiment using the AXI-4 protocol, when a read request is sent to the read request channel, the transmitting channel control unit a2 performs the above-mentioned check and deduction actions. At the receiving end, after receiving data through the target link, the receiving channel control unit b2 restores the received data packet to a standard bus signal that matches the control bus. For example, it restores Ar Packet data to a standard AXI ArChannel signal and sends the signal to the control bus. Simultaneously with triggering the recovery and transmission action, the receiving channel control unit b2 triggers the corresponding credit reclamation unit b1 to accumulate credit limits for the data released this time. For the write access transmission channel, read data channel, and write response channel, the same credit measurement and reclamation execution process as the read request channel is configured. The specific configuration methods of the control units and measurement units for each channel are not limited.

[0034] Through the above structure, the channel control units inside the transmitting module A and the receiving module B realize the credit limit constraint of the transmitting action and the credit limit feedback of the receiving action, so that the cross-core data transmission presents a controllable and orderly state.

[0035] Please continue reading. Figure 1 The receiving module B is also used for, The accumulated credit limit is transmitted to the sending module A through redundant bits in the data payload of the data bus; wherein, the data payload is the data part of the data bus that carries cross-core transmission data, and the redundant bits are the remaining bits in the data payload that are not involved in the data valid bits; The data payload is divided into at least two transmission bearer segments, each of which is an independent bit region within the data payload. The write access transmission channel occupies the first transmission bearer segment, while the read request channel, read data channel, and write response channel time-multiplex the second transmission bearer segment. The bit width of the first transmission bearer segment is greater than the bit width of the second transmission bearer segment. The second transmission bearer segment is provided with a credit limit bit and a channel indicator bit. The channel indicator bit is used to identify the channel type to which the credit limit carried by the credit limit bit belongs. The channel type includes the write access transmission channel, the read request channel, the read data channel, and the write response channel.

[0036] In some embodiments, the feedback transmission of credit limits is achieved through redundant bits in the data payload of the data bus write access that are not occupied by valid data bits. During cross-core data transmission, the data payload of the data bus write access is mainly used to carry the data portion of the cross-core transmission. However, since the data bus width is usually larger than the capacity required by the actual transmission service, there will be extra remaining bits in the data payload. These remaining bits can be used as redundant bits to transmit the feedback information of the credit limit.

[0037] Since the system supports multiple parallel channel types, including write access transmission channels, read request channels, read data channels, and write response channels, in order to ensure that the credit limit feedback of each channel can be correctly identified and separated, an independent bit region is pre-divided within the data payload as a transmission bearer segment, and the credit limit of different channel types is allocated to the corresponding transmission bearer segment.

[0038] Optionally, the allocation method is as follows: the write access transmission channel occupies the first transmission bearer segment, which is used as a dedicated area in the data payload for credit limit feedback of the write access transmission channel; the read request channel, read data channel, and write response channel share the second transmission bearer segment in a time-division multiplexing manner, that is, the credit limit feedback of the above three channel types is staggered in time and transmitted sequentially in the same second transmission bearer segment. Since the write access transmission channel needs to carry both write requests and write data simultaneously, its data volume is relatively large. Therefore, the bit width of the first transmission bearer segment is larger than that of the second transmission bearer segment to adapt to the transmission requirements of this channel. The second transmission bearer segment is further provided with a credit limit bit and a channel indicator bit. The credit limit bit is used to carry the specific credit limit value, and the channel indicator bit is used to identify the channel type to which the credit limit carried by the credit limit bit belongs, thereby ensuring that the receiving end can correctly identify the source channel of the credit limit feedback.

[0039] In one feasible implementation, the data payload partitioning and credit limit encoding scheme for data bus write access can adopt a bus architecture based on the AXI-4 protocol. In this implementation, the data bus width is, for example, 1024 bits, combined with a 128-bit write byte enable (Wstrb) signal, providing a total data capacity of 1152 bits. In this implementation, the data payload is divided into 12 transmission bearer segments, including 6 first transmission bearer segments and 6 second transmission bearer segments. The first transmission bearer segments are used for write access transmission channels, and the second transmission bearer segments are time-multiplexed for read request channels, read data channels, and write response channels. In one feasible implementation, the credit limit for the 6 write access transmission channels can be carried independently by 24 bits from the write user signals of the data bus write access (e.g., the AWUSER signal in the AXI protocol). In one feasible approach, the credit limit feedback corresponding to the read request channel, read data channel, and write response channel can be implemented using time-division multiplexing. Redundant bits in the high bits of the data payload can be used for transmission. For example, 36 bits can be occupied in the high bits of the data payload, divided into 6 groups, each containing 6 bits. The lower 4 bits are used as credit limit bits to transmit the credit limit value, and the higher 2 bits are used as channel indicator bits to identify whether the current credit limit belongs to the read request channel, read data channel, or write response channel.

[0040] With the above structure, the redundant bits in the data payload of the data bus write access are used to transmit the credit limit feedback. There is no need to open up a dedicated data channel between the chips for the information exchange of the credit limit, thereby saving hardware costs and transmission resources.

[0041] Please continue reading. Figure 1 The credit recovery unit b1 is used for, When the data transmission frequency is greater than or equal to a preset frequency, the preset threshold is lowered to increase the credit limit return speed. When the data transmission frequency is lower than the preset frequency, the preset threshold is increased to reduce the frequency of credit limit feedback.

[0042] In some embodiments, the preset threshold in the credit recovery unit b1 is a software-configurable parameter. When the system detects a high frequency of cross-chip data transmission, i.e., frequent data transmission, the preset threshold is lowered to allow the credit recovery unit b1 to more frequently feed back the accumulated credit limit to the sending module A, thereby improving the sending eligibility recovery speed of the sending module A and meeting the continuous sending requirements under high-frequency transmission. When the system detects a low frequency of cross-chip data transmission, i.e., sparse data transmission, the preset threshold is raised to reduce the frequency of credit limit feedback and avoid excessive occupation of the data bus write access bandwidth due to frequent credit limit feedback. The specific value of the preset threshold can be dynamically adapted according to the actual service load of cross-chip data transmission, including but not limited to setting the threshold to half of the buffer carrying capacity of the receiving module B, or adjusting it according to the length of the cross-chip round-trip delay period. This embodiment does not limit the setting strategy and adjustment range of the preset threshold and preset frequency.

[0043] The above structure enables dynamic adjustment of the credit limit return frequency, adapting the feedback frequency to the actual business load and balancing the need for rapid credit limit return under high load with the utilization efficiency of data bus bandwidth under low load.

[0044] Please continue reading. Figure 1 The transmitting module A is used to parse the accumulated credit limit from the data payload transmitted by the receiving module B; wherein the delay path is the path that the receiving module B takes to restore the received data into a bus signal adapted to the control bus.

[0045] In some embodiments, when the sending module A receives a data bus write access returned by the receiving module B, it directly parses the data payload corresponding to the data bus write access to obtain the accumulated credit limit. This parsing process does not go through the delay path of restoring the data received in the receiving module B to the bus signal adapted to the control bus, nor does it enter the receiving buffer of the receiving module B. Specifically, after the data bus write access is transmitted to the sending module A, the sending module A directly extracts the credit limit from the data payload of the write access and directly adds it to the credit measurement unit a1. This process does not require waiting for the receiving module B to restore the data to the standard control bus access and transmit it to the control bus.

[0046] In one feasible approach, relevant theoretical analysis can verify the effectiveness of the structure. The round-trip delay for cross-chip data transmission can be expressed as the sum of a series of clock cycles. The delay from accessing the on-chip control bus to entering the transmit module A to outputting to the data bus interface is denoted as... The latency for a data bus write access from the data bus network to the target link controller is denoted as . The equivalent number of cycles of transmission delay of the target link is denoted as . The delay cycle number of the write access transmission generated by the target link controller to the data bus interface of the receiving module B on the opposite side is denoted as . The delay cycle from retrieving data from a data bus write access to generating the corresponding control bus access is denoted as . In related technologies, in scenarios without active backpressure, to maintain continuous data transmission, the buffer capacity of receiving module B must at least meet the following requirements. If we consider the delay introduced by the back pressure of the control bus request channel on the side core, then... Delay introduced by reverse voltage of the local chip control bus data channel Then the cache capacity needs to be increased to In this embodiment, since the sending module A can directly parse the credit limit from the data payload of the data bus write access, bypassing the delay path of entering the receiving buffer and generating standard control bus access, ideally, the buffer capacity of the receiving module B needs to be at least [amount missing]. Considering the delay introduced by the back pressure of the control bus request channel on the side core. At that time, the buffer capacity of receiving module B can be maintained at Furthermore, there is no need to consider the delay introduced by the reverse voltage of the local chip control bus data channel. . This represents the latency saved by sending module A directly extracting the credit limit from the write access data payload and transmitting it to credit metering unit a1.

[0047] With the above structure, the sending module A can directly extract and restore the credit limit, effectively reducing the impact of cross-core round-trip delay on transmission continuity, making data transmission less prone to interruption under the same buffer configuration.

[0048] Please continue reading. Figure 1 The transmitting channel control unit a2 and the receiving channel control unit b2 are used to construct at least one virtual transmission channel between the transmitting channel and the receiving channel. The virtual transmission channel is a transmission channel formed by mapping the transmitting channel control unit a2 and the corresponding receiving channel control unit b2. The at least one virtual transmission channel is used to independently configure the corresponding credit measurement unit a1 and credit recovery unit b1.

[0049] In some embodiments, a virtual transmission channel is formed between the sending channel control unit a2 and the receiving channel control unit b2 through a one-to-one mapping relationship. For example, a sending channel control unit a2 is dedicated to handling read requests from the read request channel, and its corresponding receiving channel control unit b2 is dedicated to handling data from the read data channel returned by the other chip. Together, they form a read request-read data virtual transmission channel. Each virtual transmission channel is independent of the others. Each virtual transmission channel is configured with an independent credit metering unit a1 and an independent credit reclamation unit b1, so that the credit deduction, accumulation, and return operations of each channel operate completely independently. This independent configuration allows the data transmission operation of the read request channel to be unconstrained by the buffer carrying capacity in the read data channel, thereby enabling independent parallel transmission between the read request channel and the read data channel. Specifically, when the sending channel control unit a2 sends a read request, it does not need to wait for the credit reclamation progress of the read data channel. Conversely, the credit reclamation feedback of the read data channel will not affect the sending operation of the read request channel. The number of virtual transmission channels is related to the number of concurrent service flows actually existing across chips. This embodiment does not limit the specific number and configuration of virtual transmission channels.

[0050] Through the above structure, credit limits can be managed independently between virtual transmission channels, eliminating the coupling and waiting relationship between transmission channels, which is conducive to improving the overall data transmission throughput in multi-channel concurrent scenarios.

[0051] Figure 2 This is a schematic diagram of the overall structure of a management system for inter-chip data transmission provided in an embodiment of this disclosure, as shown below. Figure 2As shown, the system includes a first core and a second core, which are connected via a target link. Each core contains a conversion module D, which includes a transmitting module A and a receiving module B. The transmitting module A contains a transmitting channel control unit a2 and a register unit a3. A data bus master interface unit c1 is provided between the transmitting module A and the data bus C. The receiving module B contains a receiving channel control unit b2, and a data bus slave interface unit c2 is provided between the receiving module B and the data bus C. When sending data to the other core, the data from the control bus is transmitted to the register unit a3 via the transmitting channel control unit a2. The register unit a3 is used to buffer the encoded and packaged data to be sent. The data bus master interface unit c1 reads the data to be sent from the register unit a3 and generates a data bus write access. The data bus is transmitted to the interface unit c2 of the opposite core via the data bus C, the interface, and the target link between the cores. After receiving the data bus write access transmitted via the target link and the data bus C, the data bus interface unit c2 separates the data payload from the data bus write access and transmits the data payload to the receiving channel control unit b2 of the receiving module B. The receiving channel control unit b2 restores the received data to a bus signal format that matches the control bus and then transmits the bus signal to the control bus. At the same time, the credit recovery unit in the receiving module B accumulates the credit limit after the buffer of the received data is released. The accumulated credit limit is fed back to the register unit a3 in the sending module A via the receiving module B so that the sending module A can add it to the credit metering unit, thereby restoring the available credit limit of the sending module A.

[0052] Please continue reading. Figure 1 and Figure 2 The transmitting module A includes a register unit a3, and a data bus master interface unit c1 is provided between the transmitting module A and the data bus C. The receiving module B is provided with a data bus slave interface unit c2 between the receiving module B and the data bus C. The transmitting module A and the receiving module B constitute a conversion module D. The register unit a3 is used to cache the encoded and packaged data to be sent; The data bus master interface unit c1 is used to read data from the register unit a3 and generate a data bus write access, which is then transmitted to the data bus slave interface unit c2 via the data bus C and the target link between the cores. The data bus slave interface unit c2 is used to receive the data bus write access transmitted via the target link and the data bus, separate the data payload from the data bus write access, and transmit it to the receiving module B.

[0053] In some embodiments, the transmitting module A includes a register unit a3, which receives and buffers encoded and packaged data to be transmitted. When the transmitting module A outputs data to the data bus C, the data bus main interface unit c1 reads the data to be transmitted from the register unit a3 and generates a data bus write access according to the data bus transmission protocol. This write access is transmitted to the second core via the data bus C of the core where the transmitting module A is located and the target link between cores. The data bus slave interface unit c2 on the second core side receives the data bus write access transmitted via the target link and the data bus C of the core, separates the data payload from the data payload of the received data bus write access, and transmits it to the receiving module B of the second core. The transmitting module A and the receiving module B together constitute the conversion module D on the core side. The conversion module D implements the function of sending the access request of the control bus to the other core via the data payload of the data bus, and parsing the data payload from the data bus write access of the other core to restore it to the local control bus.

[0054] In one feasible approach, the target link between the data bus master interface unit c1 and the data bus slave interface unit c2 can be implemented via a UCIe high-speed serial link.

[0055] Through the above structure, the configuration of each physical unit within the conversion module ensures a clear structural guarantee for the cross-core data transmission and data feedback paths at the physical hardware level, guaranteeing the normal transmission and reception of data payloads and credit limits.

[0056] Figure 3 This is a schematic diagram of the signal and credit limit encoding in the data payload for a data bus write access provided in an embodiment of this disclosure, as shown below. Figure 3As shown, in the data bus write access signals, a credit limit encoding area corresponding to the write access transmission channel is reserved. This area contains credit limit bits corresponding to each write access transmission channel (e.g., channel-0 credit limit, channel-1 credit limit, channel-2 credit limit, channel-3 credit limit, channel-4 credit limit, channel-5 credit limit). Each credit limit bit is used to carry the credit limit value of the corresponding write access transmission channel. In the data payload of the data bus write access, credit limit codes corresponding to the read request channel, read data channel, and write response channel are divided. The area contains multiple sets of credit limit bits and channel indicator bits (such as credit limit bits and channel indicator bits corresponding to channels -0 to -5). The credit limit bits are used to carry the credit limit value, and the channel indicator bits are used to identify the channel type to which the credit limit carried by the credit limit bit belongs. That is, it indicates whether the credit limit belongs to the read request channel, read data channel, or write response channel. This allows the receiving end to accurately identify the channel to which the credit limit belongs when parsing the data payload, thereby realizing the differentiation, decoding, and independent recovery of credit limits of different channel types.

[0057] Figure 4 This is a flowchart illustrating a method for managing inter-chip data transmission provided in an embodiment of the present disclosure.

[0058] like Figure 4 As shown, this method is applied to a credit measurement unit and includes the following steps: Step 101: Check the current credit limit. If the current credit limit is greater than zero, trigger the sending module of the first chip to send data and deduct the credit limit corresponding to the data. The initial value of the credit limit is matched with the buffer carrying capacity of the receiving module of the second chip. The sending module bypasses the receiving module and transmits the accumulated credit limit to the delay path of the control bus.

[0059] In some embodiments, before the sending module executes the sending action, the credit metering unit first reads the current credit limit value it maintains. The current credit limit represents the total data quota that the sending module has at the current moment, and its value changes reflect the dynamic relationship between the amount of data sent by the sending module and the buffer release progress of the receiving module. The credit metering unit compares the current credit limit with zero. If the current credit limit is greater than zero, it indicates that the receiving module of the second core still has available buffer space to receive new data. The credit metering unit triggers the sending module of the first core to send data and deducts the corresponding credit limit from the current credit limit based on the amount of data sent, so that the remaining credit limit in the credit metering unit decreases synchronously with the actual amount of data sent. If the current credit limit is equal to zero, it indicates that the receiving module cannot currently accept more data. At this time, the sending module needs to suspend data transmission and wait for the credit limit to be restored later. During this transmission phase, the transmitting module is configured to receive the credit limit feedback in a way that bypasses the delayed path of transmission from the receiving module to the control bus. That is, in the subsequent reception process, the transmitting module does not go through the complete control bus recovery and transmission path, but instead adopts a reception processing mode that directly extracts the credit limit from the data payload.

[0060] Using the above method, the sending module actively checks the current credit limit in the credit metering unit before sending data, avoiding buffer overflow or packet loss caused by continuing to send data when the receiving module's buffer is full, and enabling the sending action to be decided in real time based on the actual buffer space of the receiving end.

[0061] Step 102: Receive the accumulated credit limit from the second chip and add the accumulated credit limit to the current credit limit.

[0062] In some embodiments, after the receiving module of the second core completes the buffer release of received data, the credit limit accumulated by the credit recovery unit is fed back to the transmitting module of the first core via the target link. The credit metering unit receives the accumulated credit limit and adds it to the current credit limit, thereby replenishing the available credit limit in the credit metering unit. After this addition operation, the transmittable data quota of the transmitting module is restored, and it can continue to transmit data in subsequent transmission cycles.

[0063] Using the above method, the sending module can obtain the buffer release information from the receiving module in a timely manner and reflect it in its own credit metering unit in the form of credit limit, thereby maintaining the continuity of the sending action and avoiding the interruption of the sending due to the exhaustion of credit limit, effectively improving the continuity of cross-core data transmission.

[0064] Figure 5 This is a flowchart illustrating another method for managing inter-chip data transmission provided in an embodiment of this disclosure.

[0065] like Figure 5 As shown, this method is applied to a credit recovery unit and includes the following steps: Step 201: After the receiving module of the second chip completes the buffer release of received data, the credit limit is accumulated according to the amount of data released.

[0066] In some embodiments, when the receiving module of the second chip receives data sent by the transmitting module of the first chip, the processing logic inside the receiving module retrieves the data from the buffer and restores it to a bus signal format matching the control bus before transmitting it to the control bus. This process is called buffer release of received data. Each time a buffer release is completed, the credit recovery unit accumulates the corresponding credit limit based on the actual amount of data released. The unit of measurement for the accumulated credit limit can be the number of data packets, the number of bytes, or other pre-agreed measurement granularity, subject to actual implementation and not limited thereto.

[0067] Using the above method, the credit recovery unit accumulates credit limits based on objective events that trigger the release of the receiver's cache, ensuring that the accumulation of credit limits is synchronized with the recovery process of the receiver's available cache space, so that the accumulated credit limits truly reflect the cache release progress of the receiver module.

[0068] Step 202: Determine whether the accumulated credit limit has reached the preset threshold.

[0069] In some embodiments, during the accumulation of credit limits, the credit recovery unit monitors the accumulated credit limit value in real time and compares it with a pre-configured preset threshold. The preset threshold is a critical value pre-set in the credit recovery unit to control the timing of credit limit feedback; its value can be configured based on factors such as actual business load and round-trip latency of the target link. The credit recovery unit determines whether the accumulated credit limit has reached or exceeded the preset threshold.

[0070] By using the above method and setting a preset threshold, the timing of credit limit feedback is controlled, so that the feedback action is triggered in a concentrated manner when a certain credit limit is accumulated, thus avoiding the problem of too frequent feedback caused by triggering feedback with a single data release.

[0071] Step 203: When it is determined that the accumulated credit limit has reached the preset threshold, the accumulated credit limit is encoded into the data payload of the data bus and fed back to the first core; wherein, the sending module bypasses the receiving module to transmit the accumulated credit limit to the delay path of the control bus.

[0072] In some embodiments, when the credit recovery unit determines that the accumulated credit limit has reached or exceeded a preset threshold, it triggers a feedback action. This feedback process includes encoding the currently accumulated credit limit into a target signal format in the data payload of a data bus write access, and using redundant bits in the data payload of the data bus write access that are not involved in the data validity bits to carry this encoded information, which is then sent to the transmission module of the first core via the target link. Specifically, during encoding, the credit limit value and channel indication information can be embedded in corresponding bits for different channel types, so that the transmission module of the first core can accurately parse the corresponding credit limit value and its associated channel after receiving the data payload. After the feedback action is completed on the receiving side, when the transmission module of the first core receives the aforementioned feedback data bus write access, it directly parses the accumulated credit limit from the data payload of the data bus write access, thereby bypassing the delay path of transmission from the receiving module to the control bus. That is, the transmission module does not need to wait for the receiving module to restore the feedback data to a control bus signal, nor does it need to go through the slow channel that generates the control bus access, thus completing the credit limit recovery in a shorter period. Once the feedback is completed, the accumulated credit limit in the credit recovery unit is cleared to enter the next round of accumulation cycle.

[0073] Using the above method, the credit recovery unit promptly feeds back the credit limit to the first core after the accumulated credit limit reaches the preset threshold, so that the sending module can be replenished in time before the credit limit is exhausted, thereby ensuring the smooth operation of the continuous pipeline of cross-core transmission and significantly improving the data transmission throughput in multi-channel concurrent scenarios.

[0074] The beneficial effects that can be achieved by this disclosure are as follows: 1. The credit management mechanism proposed in this disclosure avoids the impact of cross-core round-trip delay by quickly returning credit limits, and maintains a high cross-core data transmission throughput under the buffer carrying capacity configuration of the receiving module.

[0075] 2. The credit limit management of each data transmission channel is independent. The sending action of the read request channel is not constrained by the cache carrying capacity in the read data channel, which can realize independent transmission of each transmission channel, thereby improving the overall data transmission throughput in multi-channel concurrent scenarios.

[0076] 3. Credit limits are transmitted via data payload accessed through the data bus. The data bus's bit width enables real-time transmission of credit limits across multiple channels, eliminating the need for additional dedicated target links between cores.

[0077] 4. Adjust the feedback frequency of the credit limit by configuring preset thresholds in the software, so that the feedback frequency of the credit limit is adapted to the actual cross-core data transmission service load.

[0078] Corresponding to the aforementioned inter-chip data transmission management method, this invention also proposes an inter-chip data transmission management device. Since the device embodiments of this invention correspond to the aforementioned method embodiments, details not disclosed in the device embodiments can be referred to the aforementioned method embodiments, and will not be repeated here.

[0079] Figure 6 This is a schematic diagram of the structure of a management device for inter-chip data transmission provided in an embodiment of this disclosure, as shown below. Figure 6 As shown, the device is applied to a credit measurement unit and includes: a checking unit 61 and a receiving unit 62.

[0080] The checking unit 61 is used to check the current credit limit. If the current credit limit is determined to be greater than zero, the sending module of the first chip is triggered to send data and deduct the credit limit corresponding to the data. The initial value of the credit limit is matched with the buffer carrying capacity of the receiving module of the second chip. The sending module bypasses the receiving module and transmits the accumulated credit limit to the delay path of the control bus. The receiving unit 62 is used to receive the accumulated credit limit fed back by the second chip and add the accumulated credit limit to the current credit limit.

[0081] Figure 7 This is a schematic diagram of the structure of a management device for inter-chip data transmission provided in an embodiment of this disclosure, as shown below. Figure 7 As shown, the device is applied to a credit recovery unit and includes: an accumulation unit 71, a judgment unit 72, and a feedback unit 73.

[0082] Accumulation unit 71 is used to accumulate credit limit according to the amount of data released when the receiving module of the second chip completes the buffer release of received data; Judgment unit 72 is used to determine whether the accumulated credit limit has reached the preset threshold; Feedback unit 73 is used to encode the accumulated credit limit into the data payload of the data bus and feed it back to the first chip when it is determined that the accumulated credit limit has reached the preset threshold; wherein, the sending module bypasses the receiving module to transmit the accumulated credit limit to the delay path of the control bus.

[0083] It should be noted that the foregoing explanation of the method embodiments also applies to the apparatus of the embodiments of this disclosure, and the principle is the same. Therefore, the embodiments of this disclosure are not limited thereto.

[0084] According to embodiments of this disclosure, this disclosure also provides an electronic device, a readable storage medium, and a computer program product.

[0085] Figure 8A schematic block diagram of an example electronic device 1200 that can be used to implement embodiments of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0086] like Figure 8 As shown, the electronic device 1200 includes a computing unit 1201, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory 1202 or a computer program loaded from a storage unit 1208 into a random access memory 1203. The random access memory 1203 may also store various programs and data required for the operation of the electronic device 1200. The computing unit 1201, the read-only memory 1202, and the random access memory 1203 are interconnected via a bus 1204. An input / output interface 1205 is also connected to the bus 1204.

[0087] Multiple components in electronic device 1200 are connected to input / output interface 1205, including: input unit 1206, such as keyboard, mouse, etc.; output unit 1207, such as various types of monitors, speakers, etc.; storage unit 1208, such as disk, optical disk, etc.; and communication unit 1209, such as network card, modem, wireless transceiver, etc. Communication unit 1209 allows electronic device 1200 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0088] The computing unit 1201 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 1201 include, but are not limited to, CPUs (Central Processing Units), GPUs (Graphics Processing Units), various special-purpose AI (Artificial Intelligence) computing chips, various computing units running machine learning model algorithms, DSPs (Digital Signal Processors), and any suitable processor, controller, microcontroller, etc. The computing unit 1201 performs the various methods and processes described above, such as methods for managing inter-chip data transfer. For example, in some embodiments, the methods for managing inter-chip data transfer may be implemented as computer software programs tangibly contained in a machine-readable medium, such as storage unit 1208. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 1200 via read-only memory 1202 and / or communication unit 1209. When a computer program is loaded into random access memory 1203 and executed by computing unit 1201, one or more steps of the method described above can be performed. Alternatively, in other embodiments, computing unit 1201 can be configured to perform the aforementioned management method for inter-chip data transfer by any other suitable means (e.g., by means of firmware).

[0089] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, FPGAs (Field Programmable Gate Arrays), ASICs (Application-Specific Integrated Circuits), ASSPs (Application-Specific Standard Products), SOCs (System-on-Chips), CPLDs (Complex Programmable Logic Devices), computer hardware, firmware, software, and / or combinations thereof. These various implementations may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0090] The program code used to implement the methods of this disclosure may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0091] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, RAM, ROM, EPROM (Electrically Programmable Read-Only Memory) or flash memory, optical fiber, CD-ROM (Compact Disc Read-Only Memory), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0092] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user (e.g., a CRT (Cathode-Ray Tube) or LCD (Liquid Crystal Display) monitor); and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0093] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or middleware components (e.g., application servers), or frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include LANs (Local Area Networks), WANs (Wide Area Networks), the Internet, and blockchain networks.

[0094] Computer systems can include clients and servers. Clients and servers are generally geographically separated and typically interact via communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. A server can be a cloud server, also known as a cloud computing server or cloud host, a hosting product within the cloud computing service system that addresses the shortcomings of traditional physical hosts and VPS (Virtual Private Server) services, such as high management difficulty and weak business scalability. Servers can also be servers for distributed systems or servers incorporating blockchain technology.

[0095] It's important to note that artificial intelligence (AI) is the study of enabling computers to simulate certain human thought processes and intelligent behaviors (such as learning, reasoning, thinking, and planning). It encompasses both hardware and software technologies. AI hardware technologies generally include sensors, dedicated AI chips, cloud computing, distributed storage, and big data processing. AI software technologies primarily include computer vision, speech recognition, natural language processing, machine learning / deep learning, big data processing, and knowledge graph technologies.

[0096] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this application can be achieved, and this is not limited herein.

[0097] The specific embodiments described above do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A management system for inter-chip data transmission, characterized in that, The system includes at least two cores for data interaction, each core being configured with a transmitting module and a receiving module; wherein, The sending module includes a credit metering unit, used to deduct the credit limit corresponding to the data when the sending module of the first core sends data to the receiving module of the second core; wherein, the initial value of the credit metering unit is matched with the buffer carrying capacity of the receiving module of the second core; The receiving module includes a credit recovery unit, which is used to accumulate credit limits according to the amount of data released when the receiving module of the second core completes the buffer release of the received data, and send the accumulated credit limits to the sending module of the first core when the accumulated credit limits reach a preset threshold; wherein the sending module bypasses the receiving module to transmit the accumulated credit limits to the delay path of the control bus; The sending module is used to add the received accumulated credit limit to the credit measurement unit.

2. The system according to claim 1, characterized in that, The sending module further includes a sending channel control unit, and the receiving module further includes a receiving channel control unit. Each sending channel control unit is configured with a corresponding credit measurement unit, and each receiving channel control unit is configured with a corresponding credit recovery unit. The sending channel control unit is configured to send the data and trigger the credit measurement unit to deduct the credit limit corresponding to the data when the current credit limit in the credit measurement unit is greater than zero; and to pause sending the data when the current credit limit is equal to zero. The receiving channel control unit is used to trigger the credit recovery unit to accumulate the credit limit corresponding to the data after receiving the data through the target link, and then transmit the bus signal to the control bus after restoring the received data to a bus signal format that matches the control bus.

3. The system according to claim 2, characterized in that, The receiving module is also used for, The accumulated credit limit is transmitted to the sending module through redundant bits in the data payload of the data bus; wherein, the data payload is the data portion of the data bus that carries cross-core transmission data, and the redundant bits are the remaining bits in the data payload that are not involved in the data valid bits; The data payload is divided into at least two transmission bearer segments, each of which is an independent bit region within the data payload. The write access transmission channel occupies the first transmission bearer segment, while the read request channel, read data channel, and write response channel time-multiplex the second transmission bearer segment. The bit width of the first transmission bearer segment is greater than the bit width of the second transmission bearer segment. The second transmission bearer segment is provided with a credit limit bit and a channel indicator bit. The channel indicator bit is used to identify the channel type to which the credit limit carried by the credit limit bit belongs. The channel type includes the write access transmission channel, the read request channel, the read data channel, and the write response channel.

4. The system according to claim 3, characterized in that, The credit recovery unit is used for, When the data transmission frequency is greater than or equal to a preset frequency, the preset threshold is lowered to increase the credit limit return speed. When the data transmission frequency is lower than the preset frequency, the preset threshold is increased to reduce the frequency of credit limit feedback.

5. The system according to claim 3, characterized in that, The transmitting module is used to parse the accumulated credit limit from the data payload transmitted by the receiving module; wherein, the delay path is the path that the receiving module takes to restore the received data into a bus signal adapted to the control bus.

6. The system according to claim 2, characterized in that, The transmitting channel control unit and the receiving channel control unit are used to construct at least one virtual transmission channel between the transmitting channel and the receiving channel. The virtual transmission channel is a transmission channel formed by mapping the transmitting channel control unit and the corresponding receiving channel control unit. The at least one virtual transmission channel is used to independently configure the corresponding credit measurement unit and credit recovery unit.

7. The system according to claim 3, characterized in that, The transmitting module includes a register unit, and a data bus master interface unit is provided between the transmitting module and the data bus. The receiving module is connected to the data bus via a data bus slave interface unit. The transmitting module and the receiving module constitute a conversion module. The register unit is used to cache the encoded and packaged data to be sent; The data bus master interface unit is used to read data from the register unit and generate a data bus write access, which is then transmitted to the data bus slave interface unit via the data bus and the target link between the cores. The data bus slave interface unit is used to receive the data bus write access transmitted via the target link and the data bus, separate the data payload from the data bus write access, and transmit it to the receiving module.

8. A method for managing inter-chip data transmission, characterized in that, The method is applied to credit measurement units, including: The current credit limit is checked. If the current credit limit is greater than zero, the sending module of the first core is triggered to send data and deduct the credit limit corresponding to the data. The initial value of the credit limit is matched with the buffer carrying capacity of the receiving module of the second core. The sending module bypasses the receiving module and transmits the accumulated credit limit to the delay path of the control bus. Receive the accumulated credit limit from the second chip and add the accumulated credit limit to the current credit limit.

9. A method for managing inter-chip data transmission, the method being applied to a credit recovery unit, characterized in that, include: Once the receiving module of the second chip has completed the buffer release of received data, the credit limit is accumulated according to the amount of data released; Determine whether the accumulated credit limit has reached the preset threshold; When it is determined that the accumulated credit limit reaches the preset threshold, the accumulated credit limit is encoded into the data payload of the data bus and fed back to the first core; wherein, the transmitting module bypasses the receiving module to transmit the accumulated credit limit to the delay path of the control bus.

10. An electronic device, characterized in that, include: At least one processor; And a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of claim 8 or 9.

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