An automated signal analysis method and system for screenless testing of LCD logic boards

Abstract

This invention proposes an automated signal analysis method and system for screenless testing of LCD logic boards, comprising: acquiring timing control signals, power rail voltage waveforms, and backlight drive pulse signals on the interface bus; extracting characteristic parameters from these data to construct a dynamic reference signal model covering a multi-dimensional feature space; establishing a virtual LCD screen model based on the dynamic reference signal model; mapping real-time signals to the virtual screen drive link to simulate the driving process of the virtual screen; comparing the signal responses generated during the virtual drive process with the dynamic reference signal model; classifying and identifying deviation characteristics; locating the functional modules and signal link nodes corresponding to abnormal signals; and outputting a diagnostic report; outputting the test conclusion of the logic board according to the abnormality level and preset judgment rules in the diagnostic report; and feeding back the signal characteristic data and test conclusion of this test to the dynamic reference signal model. This invention achieves automation and intelligence in screenless testing of LCD logic boards.

Description

Technical Field

[0001] This invention relates to the field of display technology, and specifically to an automated signal analysis method and system for screenless testing of liquid crystal logic boards. Background Technology

[0002] The TCON (Timing Controller) LCD logic board is a core component of an LCD display panel system. Its function is to receive image signals from the motherboard and perform timing control, signal conversion, and voltage regulation to drive the LCD panel to display normally. In traditional production testing, the TCON board is usually connected to an actual display screen, and its performance is determined by visually observing the test screen.

[0003] However, existing testing methods have obvious shortcomings: test results are highly dependent on human judgment, which is easily affected by subjective errors, human fatigue and experience differences, leading to a decrease in the accuracy of judgment and potentially increasing the risk of defective products being released; the testing process involves frequent manual operations, resulting in low efficiency. Summary of the Invention

[0004] Based on the above-mentioned problems, this invention proposes an automated signal analysis method and system for screenless testing of LCD logic boards. Through this invention, testing costs and screen damage risks can be reduced, the accuracy and coverage of anomaly location can be significantly improved, and the testing accuracy can be continuously improved with the accumulation of samples; thus, the entire process of screenless testing of LCD logic boards is automated and intelligent.

[0005] In view of this, one aspect of the present invention proposes an automated signal analysis method for screenless testing of liquid crystal logic boards, comprising: After powering on the LCD logic board, the timing control signals, power rail voltage waveforms and backlight drive pulse signals on each interface bus are synchronously acquired through the multi-channel signal acquisition unit. The characteristic parameters of timing control signals, power rail voltage waveforms and backlight drive pulse signals in the time domain, frequency domain and phase domain are extracted. Combined with logic board model identification and historical good product data, a dynamic reference signal model covering a multi-dimensional feature space is constructed. Based on the dynamic reference signal model, a virtual LCD screen model corresponding to the logic board under test is established in the digital twin simulation environment. The collected real-time signals are mapped to the virtual screen driving link to simulate the complete driving process of the TCON chip to the virtual screen, thereby restoring the actual driving behavior of the logic board without a physical screen. The signal response generated during the virtual driving process is compared layer by layer with the dynamic reference signal model. The deviation features are classified and identified using a trained deep learning model. The functional modules and signal link nodes corresponding to the abnormal signals are automatically located, and a structured diagnostic report containing the abnormality type, abnormality level and the location of the associated circuit is output. Based on the anomaly level and preset judgment rules in the structured diagnostic report, the system automatically outputs the test pass or fail judgment conclusion for the logic board. The signal feature data and judgment results of this test are fed back to the dynamic reference signal model to drive the adaptive iterative update of the model parameters.

[0006] Optionally, the step of extracting the characteristic parameters of the timing control signal, power rail voltage waveform, and backlight drive pulse signal in the time, frequency, and phase domains, and combining them with the logic board model identifier and historical good product data to construct a dynamic reference signal model covering a multi-dimensional feature space includes: The timing control signals, power rail voltage waveforms, and backlight drive pulse signals acquired from multiple channels are classified and stored according to the logic board model identifier, forming a raw signal dataset indexed by model. For each signal in the original signal dataset, the amplitude, rise time, and pulse width features are extracted in the time domain, the main frequency component and harmonic energy features are extracted in the frequency domain, and the phase difference features between each signal are extracted in the phase domain, forming a multi-domain feature vector corresponding to each signal. The multi-domain feature vectors are compared with the feature distribution of the corresponding models in the historical good product data. Abnormal samples that deviate from the good product feature distribution are removed, and feature vectors with confidence levels that meet the preset threshold are retained as valid modeling samples. The multi-domain feature vectors of each signal in the effective modeling sample are fused according to the three signal dimensions of timing control, power rail and backlight drive to construct a multi-dimensional feature space covering all feature dimensions of the three signal types. Based on the multidimensional feature space, a dynamic reference signal model containing the feature mean and feature tolerance range is generated for each logic board model, and the model parameters are automatically updated as new good samples are continuously added.

[0007] Optionally, the step of establishing a virtual LCD screen model corresponding to the logic board under test in a digital twin simulation environment based on the dynamic reference signal model, mapping the acquired real-time signals to the virtual screen drive link, simulating the complete drive process of the TCON chip on the virtual screen, and thus restoring the actual drive behavior of the logic board without a physical screen, includes: Based on the model identifier of the logic board under test, the corresponding screen specification parameters, including resolution, refresh rate, interface timing specifications and backlight modulation method, are read from the dynamic reference signal model. The structure and parameter initialization of the virtual LCD screen model are completed in the digital twin simulation environment. The timing control signals, power rail voltage waveforms, and backlight drive pulse signals acquired from multiple channels are connected to the digital twin simulation environment in real time. The timing alignment and amplitude normalization preprocessing are performed according to the drive link level corresponding to each signal to form a standardized input signal stream that can drive the virtual screen model. The standardized input signal stream is injected into the virtual screen driving link to simulate the source driving, gate scanning and gamma correction of the virtual screen by the TCON chip in the digital twin simulation environment, thereby generating the simulation response signals of each node of the virtual screen. The simulation response signal was checked for completeness to confirm that the TCON drive timing, frame synchronization signal and backlight enable logic were fully responded to in the virtual screen model, thus confirming that the actual driving behavior of the logic board was fully reproduced under the condition of no physical screen.

[0008] Optionally, the step of comparing the signal response generated during the virtual driving process with the dynamic reference signal model layer by layer, classifying and identifying the deviation features using a trained deep learning model, automatically locating the functional modules and signal link nodes corresponding to the abnormal signals, and outputting a structured diagnostic report containing the abnormality type, abnormality level, and location of associated circuits includes: The simulated response signal is compared layer by layer with the characteristic mean and tolerance range of the corresponding level in the dynamic reference signal model according to the three link levels of power rail, timing control and backlight drive, and the deviation feature vectors that exceed the tolerance range in each level are extracted. The deviation feature vector is input into a deep learning classification model trained on historical fault samples to identify the fault type of the deviation features and output the anomaly type label and classification confidence of each deviation feature. Based on the anomaly type label and classification confidence level, and combined with the preset anomaly level assessment rules, each anomaly type is assessed as fatal, severe, or minor, forming an anomaly assessment result that includes the anomaly type and the corresponding level. Based on the anomaly type and driving link level in the anomaly assessment results, the logic board circuit topology mapping table is retrieved to locate the anomaly signal to the corresponding functional module and signal link node, generating the circuit location information of the anomaly. The anomaly type label, anomaly level, and circuit location information are integrated according to a unified data structure to output a structured diagnostic report containing the above three types of information.

[0009] Optionally, the step of automatically outputting a test pass or fail conclusion for the logic board based on the anomaly level in the structured diagnostic report and preset judgment rules includes: Read the abnormality level of all abnormal entries in the structured diagnostic report, and count the number of abnormalities at each level (critical, severe, and minor) to form a summary of the abnormality level distribution of the current logic board under test. The distribution of the abnormal levels is summarized and matched with the judgment rules for the corresponding logic board models in the preset judgment rule library. The judgment rules specify the upper limit of the number of abnormalities at each level and the judgment priority of different combinations of abnormalities. Based on the matching results, the judgments are executed step by step according to the priority order to obtain the judgment conclusion. Specifically, if any fatal level anomaly exists, the failure conclusion is output directly; if there is no fatal anomaly but the number of severe level anomalies exceeds the allowed limit, the failure conclusion is output; if none of the above conditions are met, the pass conclusion is output. The judgment conclusion is bound and encapsulated with the anomaly level distribution summary and associated circuit location information in the structured diagnostic report to form a complete test result record containing the judgment conclusion and its basis, and then output.

[0010] Optionally, in the multi-domain feature extraction step, the fusion method for the comprehensive feature scores of each signal is as follows:

[0011] in, The comprehensive feature score of the ch-th signal; These represent the peak and trough values ​​of the time-domain amplitude, respectively. This is the baseline amplitude for good quality products; The frequency domain energy of the nth harmonic; The total energy across the entire frequency band; N is the upper limit of the harmonic order used in the calculation; Let be the phase difference between the ch-th signal and the reference signal; To allow the maximum phase deviation; These are the three domain weight coefficients, the sum of which is 1, determined by regression analysis of historical good product data; Let be the channel reliability coefficient of the ch-th signal, with a value ranging from (0,1]. It is determined based on the historical stability statistics of this channel. The worse the stability, the lower the reliability coefficient. The smaller the value, the more it suppresses the overall score; The signal-to-noise ratio of the currently acquired signal from channel ch; This is the reference signal-to-noise ratio for the good signal in this channel; This is the sensitivity coefficient for signal-to-noise ratio correction, which controls the magnitude of the correction to the score caused by the signal-to-noise ratio deviation.

[0012] Optionally, during the generation of the dynamic baseline model, the adaptive tolerance range is calculated as follows:

[0013] in, These are the upper and lower limits of the tolerance for the dim-th feature dimension, respectively; These are the mean and standard deviation of the feature values ​​of good-quality samples in this dimension, respectively. The basic tolerance expansion factor; The number of valid modeling samples for this dimension; The baseline threshold for the number of samples; This is the slope control parameter for the Sigmoid expansion factor; Let be the coefficient of variation of the good samples in the dim dimension, defined as This reflects the degree of dispersion of good samples in this feature dimension; This is a sensitivity adjustment parameter for the coefficient of variation, controlling the extent to which the degree of dispersion affects the tolerance expansion. This is the seasonal / periodic fluctuation correction factor for the dim dimension. It is determined based on the statistical fluctuation range of this feature dimension in different production periods (such as different shifts, temperature and humidity seasons) in historical data, and the value fluctuates around 1.

[0014] Optionally, during real-time signal access and preprocessing, the delay estimation method for multi-channel timing alignment is as follows:

[0015] in, The optimal alignment delay of the ch-th channel signal relative to the reference channel; The reference channel signal is sampled at time t; For the signal of channel ch at time t... The sampled value at that location; These are the start and end times of the signal segment used for time delay estimation; The signal quality weighting function at time t is determined based on the signal amplitude and the estimated local signal-to-noise ratio at that time. It assigns lower weights to sampling points in periods with poor signal quality to suppress the impact of transient interference on cross-correlation estimation. The noise variance estimate for the current acquisition segment in channel ch is obtained from statistics of the silent signal segment. The total signal variance of the currently acquired segment in channel ch; The noise suppression confidence factor reflects the proportion of effective signal energy in the total signal energy. The greater the noise, the smaller the factor, and it applies an overall confidence penalty to the time delay estimation results.

[0016] Optionally, in the anomaly level assessment, the comprehensive risk score is calculated as follows:

[0017] in, The comprehensive risk score for the anoth anomaly; The preset base hazard coefficient for this anomaly type; The classification confidence score output by the deep learning classification model; This represents the hierarchical depth of the signal link where the anomaly occurs. This represents the total number of levels in the driving link; This is the normalized distance between the feature vector of the abnormal deviation and the mean of the corresponding feature in the benchmark model; This is the distance sensitivity coefficient; These are the weighting coefficients for the three scoring components, and their sum is 1. This represents the frequency of occurrence of this anomaly type in recent test batches; This represents the baseline frequency of occurrence of this anomaly type in the entire historical dataset. This is the frequency trend sensitivity coefficient, which controls the amplification of risk scores by an upward frequency trend; when When the correction term is greater than 1, the score is adjusted upward to reflect the worsening trend of this type of anomaly; This is the amplification factor for anomaly co-occurrence. It is determined based on the historical correlation strength between other anomaly entries that co-occur with the anoth anomaly in the same batch on the current test board. When multiple anomalies frequently co-occur in historical data, this factor is greater than 1, reflecting that the actual risk of a single anomaly in a multi-anomaly co-occurrence scenario is higher than the risk when it appears in isolation.

[0018] Another aspect of the present invention provides an automated signal analysis system for screenless testing of liquid crystal logic boards, which is used to perform an automated signal analysis method for screenless testing of liquid crystal logic boards, including: a control processing unit and a multi-channel signal acquisition unit; The multi-channel signal acquisition unit is configured to synchronously acquire timing control signals, power rail voltage waveforms, and backlight drive pulse signals on each interface bus after the LCD logic board is powered on. The control processing unit is configured to: The characteristic parameters of timing control signals, power rail voltage waveforms and backlight drive pulse signals in the time domain, frequency domain and phase domain are extracted. Combined with logic board model identification and historical good product data, a dynamic reference signal model covering a multi-dimensional feature space is constructed. Based on the dynamic reference signal model, a virtual LCD screen model corresponding to the logic board under test is established in the digital twin simulation environment. The collected real-time signals are mapped to the virtual screen driving link to simulate the complete driving process of the TCON chip to the virtual screen, thereby restoring the actual driving behavior of the logic board without a physical screen. The signal response generated during the virtual driving process is compared layer by layer with the dynamic reference signal model. The deviation features are classified and identified using a trained deep learning model. The functional modules and signal link nodes corresponding to the abnormal signals are automatically located, and a structured diagnostic report containing the abnormality type, abnormality level and the location of the associated circuit is output. Based on the anomaly level and preset judgment rules in the structured diagnostic report, the system automatically outputs the test pass or fail judgment conclusion for the logic board. The signal feature data and judgment results of this test are fed back to the dynamic reference signal model to drive the adaptive iterative update of the model parameters.

[0019] The automated signal analysis method for screenless testing of LCD logic boards using the technical solution of this invention includes: after powering on the LCD logic board, synchronously acquiring timing control signals, power rail voltage waveforms, and backlight drive pulse signals on each interface bus through a multi-channel signal acquisition unit; extracting characteristic parameters of the timing control signals, power rail voltage waveforms, and backlight drive pulse signals in the time domain, frequency domain, and phase domain; combining the logic board model identifier and historical good product data to construct a dynamic reference signal model covering a multi-dimensional feature space; based on the dynamic reference signal model, establishing a virtual LCD screen model corresponding to the logic board under test in a digital twin simulation environment; mapping the acquired real-time signals to the virtual screen drive link to simulate TCO. The N-chip performs a complete driving process for the virtual screen, thus reproducing the actual driving behavior of the logic board without a physical screen. The signal responses generated during the virtual driving process are compared layer by layer with a dynamic reference signal model. A trained deep learning model is used to classify and identify deviation features, automatically locating the functional modules and signal link nodes corresponding to abnormal signals, and outputting a structured diagnostic report containing the anomaly type, anomaly level, and the location of associated circuits. Based on the anomaly level and preset judgment rules in the structured diagnostic report, the system automatically outputs a pass or fail conclusion for the logic board test. The signal feature data and judgment results of this test are fed back to the dynamic reference signal model, driving the adaptive iterative update of the model parameters. By replacing the physical screen with a digital twin virtual screen simulation, the dependence of testing on the real LCD screen is completely eliminated, reducing testing costs and the risk of screen damage. The combination of multi-dimensional reference signal modeling and deep learning anomaly recognition significantly improves the accuracy and coverage of anomaly location. The adaptive model update mechanism gives the system continuous self-evolution capabilities, allowing the test accuracy to continuously improve with the accumulation of samples. The overall solution achieves full automation and intelligence of the entire process of screenless testing of LCD logic boards. Attached Figure Description

[0020] Figure 1 This is a flowchart of an automated signal analysis method for screenless testing of a liquid crystal logic board provided in one embodiment of the present invention; Figure 2 This is a schematic block diagram of an automated signal analysis system for screenless testing of a liquid crystal logic board provided in one embodiment of the present invention. Detailed Implementation

[0021] To better understand the above-mentioned objectives, features, and advantages of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that, unless otherwise specified, the embodiments and features described in these embodiments can be combined with each other.

[0022] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and therefore the scope of protection of the invention is not limited to the specific embodiments disclosed below.

[0023] The terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.

[0024] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0025] The following reference Figures 1 to 2 This invention describes an automated signal analysis method and system for screenless testing of a liquid crystal logic board, provided by some embodiments of the present invention.

[0026] like Figure 1 As shown, one embodiment of the present invention provides an automated signal analysis method for screenless testing of a liquid crystal logic board, comprising: After powering on the LCD logic board, the timing control signals, power rail voltage waveforms and backlight drive pulse signals on each interface bus are synchronously acquired through the multi-channel signal acquisition unit. The characteristic parameters of timing control signals, power rail voltage waveforms and backlight drive pulse signals in the time domain, frequency domain and phase domain are extracted. Combined with logic board model identification and historical good product data, a dynamic reference signal model covering a multi-dimensional feature space is constructed. Based on the dynamic reference signal model, a virtual LCD screen model corresponding to the logic board under test is established in the digital twin simulation environment. The collected real-time signals are mapped to the virtual screen driving link to simulate the complete driving process of the TCON chip to the virtual screen, thereby restoring the actual driving behavior of the logic board without a physical screen. The signal response generated during the virtual driving process is compared layer by layer with the dynamic reference signal model. The deviation features are classified and identified using a trained deep learning model. The functional modules and signal link nodes corresponding to the abnormal signals are automatically located, and a structured diagnostic report containing the abnormality type, abnormality level and the location of the associated circuit is output. Based on the anomaly level and preset judgment rules in the structured diagnostic report, the system automatically outputs the test pass or fail judgment conclusion for the logic board. The signal feature data and judgment results of this test are fed back to the dynamic reference signal model to drive the adaptive iterative update of the model parameters.

[0027] The technical solution adopted in this embodiment replaces the physical screen with a digital twin virtual screen simulation, completely eliminating the dependence of testing on the real LCD screen and reducing testing costs and screen damage risks. The combination of multi-dimensional reference signal modeling and deep learning anomaly recognition significantly improves the accuracy and coverage of anomaly location. The adaptive model update mechanism gives the system the ability to continuously self-evolve, so that the test accuracy continues to improve with the accumulation of samples. The overall solution realizes the full-process automation and intelligence of screenless testing of LCD logic boards.

[0028] In some possible embodiments of the present invention, after powering on the liquid crystal logic board, the step of synchronously acquiring timing control signals, power rail voltage waveforms, and backlight drive pulse signals on each interface bus through a multi-channel signal acquisition unit includes: Based on the model identifier of the logic board under test, read the corresponding interface bus topology configuration, identify the physical location of the timing control signal bus, power rail node and backlight drive pulse output terminal, and automatically position and deploy the probes of the multi-channel signal acquisition unit according to the above physical locations. According to the standard power-on sequence corresponding to the model of the logic board under test, the power-on commands of the main power rail, logic power rail and backlight driver power supply are triggered in sequence to ensure that each power rail is stably established according to the specified sequence, so as to provide a stable excitation environment for subsequent signal acquisition. The moment when the main power rail voltage reaches a stable threshold is used as the global synchronization trigger reference. The multi-channel signal acquisition unit starts synchronously under the same trigger reference and acquires the signals of the timing control signal bus, each power rail node and the backlight drive pulse output terminal in parallel to ensure that the acquired data of each channel has a unified time reference. During the acquisition process, the amplitude range and waveform continuity of each channel signal are monitored in real time. Channels with undervoltage, overshoot, or signal interruption are marked as abnormal. After the acquisition is completed, the abnormal markers and the original acquisition data of the corresponding channel are output together for use in subsequent feature extraction steps.

[0029] This embodiment ensures that multi-channel signals are fully acquired under a consistent time reference by using model-adaptive probe deployment, standardized power-on timing control, and a unified synchronous triggering mechanism, thereby guaranteeing the timing accuracy and inter-channel comparability of the acquired data from the source.

[0030] In some possible embodiments of the present invention, the step of extracting the characteristic parameters of the timing control signal, power rail voltage waveform, and backlight drive pulse signal in the time domain, frequency domain, and phase domain, and combining them with the logic board model identifier and historical good product data to construct a dynamic reference signal model covering a multi-dimensional feature space includes: The timing control signals, power rail voltage waveforms, and backlight drive pulse signals acquired from multiple channels are classified and stored according to the logic board model identifier, forming a raw signal dataset indexed by model. For each signal in the original signal dataset, the amplitude, rise time, and pulse width features are extracted in the time domain, the main frequency component and harmonic energy features are extracted in the frequency domain, and the phase difference features between each signal are extracted in the phase domain, forming a multi-domain feature vector corresponding to each signal. The multi-domain feature vectors are compared with the feature distribution of the corresponding models in the historical good product data. Abnormal samples that deviate from the good product feature distribution are removed, and feature vectors with confidence levels that meet the preset threshold are retained as valid modeling samples. The multi-domain feature vectors of each signal in the effective modeling sample are fused according to the three signal dimensions of timing control, power rail and backlight drive to construct a multi-dimensional feature space covering all feature dimensions of the three signal types. Based on the multidimensional feature space, a dynamic reference signal model containing the feature mean and feature tolerance range is generated for each logic board model, and the model parameters are automatically updated as new good samples are continuously added.

[0031] In this embodiment, model-adaptive and data-driven dynamic updates of the benchmark model are realized, effectively eliminating the interference of model differences and batch fluctuations on the judgment benchmark and improving the accuracy and robustness of subsequent anomaly identification.

[0032] In some possible embodiments of the present invention, the step of establishing a virtual LCD screen model corresponding to the logic board under test in a digital twin simulation environment based on the dynamic reference signal model, mapping the acquired real-time signals to the virtual screen drive link, simulating the complete drive process of the TCON chip on the virtual screen, and thus restoring the actual drive behavior of the logic board without a physical screen, includes: Based on the model identifier of the logic board under test, the corresponding screen specification parameters, including resolution, refresh rate, LVDS / eDP interface timing specifications and backlight modulation method, are read from the dynamic reference signal model. The structure and parameter initialization of the virtual LCD screen model are completed in the digital twin simulation environment. The timing control signals, power rail voltage waveforms, and backlight drive pulse signals acquired from multiple channels are connected to the digital twin simulation environment in real time. The timing alignment and amplitude normalization preprocessing are performed according to the drive link level corresponding to each signal to form a standardized input signal stream that can drive the virtual screen model. The standardized input signal stream is injected into the virtual screen driving link to simulate the source driving, gate scanning and gamma correction of the virtual screen by the TCON chip in the digital twin simulation environment, thereby generating the simulation response signals of each node of the virtual screen. The simulation response signal was checked for completeness to confirm that the TCON drive timing, frame synchronization signal and backlight enable logic were fully responded to in the virtual screen model, thus confirming that the actual driving behavior of the logic board was fully reproduced under the condition of no physical screen.

[0033] In this embodiment, the logic board's driving behavior on the LCD screen is fully reproduced using a digital twin virtual screen, eliminating the test's dependence on the physical screen while retaining the observability of all nodes in the driving link, providing a complete simulation data foundation for subsequent signal anomaly localization.

[0034] In some possible embodiments of the present invention, the step of comparing the signal response generated during the virtual driving process with the dynamic reference signal model layer by layer, classifying and identifying the deviation features using a trained deep learning model, automatically locating the functional modules and signal link nodes corresponding to the abnormal signals, and outputting a structured diagnostic report containing the abnormality type, abnormality level, and location of associated circuits includes: The simulated response signal is compared layer by layer with the characteristic mean and tolerance range of the corresponding level in the dynamic reference signal model according to the three link levels of power rail, timing control and backlight drive, and the deviation feature vectors that exceed the tolerance range in each level are extracted. The deviation feature vector is input into a deep learning classification model trained on historical fault samples to identify the fault type of the deviation features and output the anomaly type label and classification confidence of each deviation feature. Based on the anomaly type label and classification confidence level, and combined with the preset anomaly level assessment rules, each anomaly type is assessed as fatal, severe, or minor, forming an anomaly assessment result that includes the anomaly type and the corresponding level. Based on the anomaly type and driving link level in the anomaly assessment results, the logic board circuit topology mapping table is retrieved to locate the anomaly signal to the corresponding functional module and signal link node, generating the circuit location information of the anomaly. The anomaly type label, anomaly level, and circuit location information are integrated according to a unified data structure to output a structured diagnostic report containing the above three types of information.

[0035] In this embodiment, through the synergistic effect of hierarchical comparison and deep learning classification, the complete source tracing of anomalies from signal deviation to fault type, level and circuit location is achieved, which significantly improves the accuracy and interpretability of fault diagnosis and provides a traceable structured basis for test judgment.

[0036] In some possible embodiments of the present invention, the step of automatically outputting a test pass or fail determination conclusion for the logic board based on the anomaly level in the structured diagnostic report and preset judgment rules includes: Read the abnormality level of all abnormal entries in the structured diagnostic report, and count the number of abnormalities at each level (critical, severe, and minor) to form a summary of the abnormality level distribution of the current logic board under test. The distribution of the abnormal levels is summarized and matched with the judgment rules for the corresponding logic board models in the preset judgment rule library. The judgment rules specify the upper limit of the number of abnormalities at each level and the judgment priority of different combinations of abnormalities. Based on the matching results, the judgments are executed step by step according to the priority order to obtain the judgment conclusion. Specifically, if any fatal level anomaly exists, the failure conclusion is output directly; if there is no fatal anomaly but the number of severe level anomalies exceeds the allowed limit, the failure conclusion is output; if none of the above conditions are met, the pass conclusion is output. The judgment conclusion is bound and encapsulated with the anomaly level distribution summary and associated circuit location information in the structured diagnostic report to form a complete test result record containing the judgment conclusion and its basis, and then output.

[0037] In this embodiment, by precisely matching the distribution of abnormal levels with the model-specific judgment rules, the test judgment conclusions are automatically and the rules are made transparent, eliminating the subjectivity of manual judgment, and the traceability of the judgment conclusions is ensured by binding and encapsulating complete records.

[0038] In some possible embodiments of the present invention, the step of feeding back the signal feature data and judgment results of this test to the dynamic reference signal model to drive the adaptive iterative update of the model parameters includes: Based on the judgment conclusions in the test result records, the signal feature data of this test are classified and filtered: the signal feature data of logic boards that pass the judgment conclusion are included in the feedback dataset as valid good samples; the signal feature data of logic boards that fail the judgment conclusion are archived only as fault samples and are not included in the feedback dataset for updating the benchmark model. For each valid good sample in the feedback dataset, the data credibility of each feature dimension of the sample is evaluated by combining the channel anomaly markers recorded during the collection process and the collection quality monitoring results. Feature dimension data with collection anomaly markers are removed, and feature dimension data with credibility that meets the preset threshold are retained to participate in subsequent model updates. Based on the feedback samples that have passed the quality assessment, incremental feature vectors for each feature dimension are extracted according to the multi-domain feature extraction method to form the incremental feature data package for this test cycle. The incremental feature data packet is input into the parameter update module of the dynamic benchmark signal model. The benchmark mean and tolerance range parameters of each feature dimension are iteratively updated according to the forgetting factor weighted incremental update method to complete the model adaptive iteration of this test cycle. The updated model parameters, along with the number of samples involved in the update, the update timestamp, and the model version number, are archived to ensure that the process of each iteration update is traceable. The updated model version is then marked as the current valid benchmark model for subsequent tests.

[0039] This embodiment uses a complete closed-loop mechanism of good product sample screening, quality filtering, and incremental iterative updates to ensure that only high-quality good product data drives model evolution. At the same time, version archiving ensures the traceability of the model iteration process and continuously improves the accuracy of the benchmark model in tracking production status.

[0040] In some possible embodiments of the present invention, the method for fusing the comprehensive feature scores of each signal in the multi-domain feature extraction step is as follows:

[0041] in, The comprehensive feature score of the ch-th signal; These represent the peak and trough values ​​of the time-domain amplitude, respectively. This is the baseline amplitude for good quality products; The frequency domain energy of the nth harmonic; The total energy across the entire frequency band; N is the upper limit of the harmonic order used in the calculation; Let be the phase difference between the ch-th signal and the reference signal; To allow the maximum phase deviation; These are the three domain weight coefficients, the sum of which is 1, determined by regression analysis of historical good product data; Let be the channel reliability coefficient of the ch-th signal, with a value ranging from (0,1]. It is determined based on the historical stability statistics of this channel. The worse the stability, the lower the reliability coefficient. The smaller the value, the more it suppresses the overall score; The signal-to-noise ratio of the currently acquired signal from channel ch; This is the reference signal-to-noise ratio for the good signal in this channel; This is the sensitivity coefficient for signal-to-noise ratio correction, which controls the magnitude of the correction to the score caused by the signal-to-noise ratio deviation.

[0042] In this embodiment, a channel reliability coefficient is introduced. Channels with poor acquisition quality are automatically downweighted, and the signal-to-noise ratio correction term is used to compensate for the noise level of the current acquisition environment in real time, so that the comprehensive feature score can still accurately reflect the true feature state of the signal when the acquisition environment fluctuates.

[0043] In some possible embodiments of the present invention, the adaptive tolerance range is calculated during the dynamic benchmark model generation process as follows:

[0044] in, These are the upper and lower limits of the tolerance for the dim-th feature dimension, respectively; These are the mean and standard deviation of the feature values ​​of good-quality samples in this dimension, respectively. The basic tolerance expansion factor; The number of valid modeling samples for this dimension; The baseline threshold for the number of samples; This is the slope control parameter for the Sigmoid expansion factor; Let be the coefficient of variation of the good samples in the dim dimension, defined as This reflects the degree of dispersion of good samples in this feature dimension; This is a sensitivity adjustment parameter for the coefficient of variation, controlling the extent to which the degree of dispersion affects the tolerance expansion. This is the seasonal / periodic fluctuation correction factor for the dim dimension. It is determined based on the statistical fluctuation range of this feature dimension in different production periods (such as different shifts, temperature and humidity seasons) in historical data, and the value fluctuates around 1.

[0045] In this embodiment, the coefficient of variation term automatically increases the tolerance for feature dimensions with high natural dispersion, and introduces a periodic fluctuation correction factor to compensate for the impact of periodic changes in the production environment on the baseline tolerance, so that the tolerance range takes into account the three factors of sample size, feature dispersion and periodic fluctuations in the production environment.

[0046] In some possible embodiments of the present invention, the delay estimation method for multi-channel timing alignment during real-time signal access and preprocessing is as follows:

[0047] in, The optimal alignment delay of the ch-th channel signal relative to the reference channel; The reference channel signal is sampled at time t; For the signal of channel ch at time t... The sampled value at that location; These are the start and end times of the signal segment used for time delay estimation; The signal quality weighting function at time t is determined based on the signal amplitude and the estimated local signal-to-noise ratio at that time. It assigns lower weights to sampling points in periods with poor signal quality to suppress the impact of transient interference on cross-correlation estimation. The noise variance estimate for the current acquisition segment in channel ch is obtained from statistics of the silent signal segment. The total signal variance of the currently acquired segment in channel ch; The noise suppression confidence factor reflects the proportion of effective signal energy in the total signal energy. The greater the noise, the smaller the factor, and it applies an overall confidence penalty to the time delay estimation results.

[0048] This embodiment uses a time-varying mass weighting function. The transient interference period is weighted down, and a noise suppression confidence factor is introduced to quantify the overall estimation reliability, which significantly improves the robustness of time delay estimation in scenarios with strong noise or uneven signal quality.

[0049] In some possible embodiments of the present invention, the comprehensive risk score is calculated in the anomaly level assessment as follows:

[0050] in, The comprehensive risk score for the anoth anomaly; The preset base hazard coefficient for this anomaly type; The classification confidence score output by the deep learning classification model; This represents the hierarchical depth of the signal link where the anomaly occurs. This represents the total number of levels in the driving link; This is the normalized distance between the feature vector of the abnormal deviation and the mean of the corresponding feature in the benchmark model; This is the distance sensitivity coefficient; These are the weighting coefficients for the three scoring components, and their sum is 1. This represents the frequency of occurrence of this anomaly type in recent test batches; This represents the baseline frequency of occurrence of this anomaly type in the entire historical dataset. This is the frequency trend sensitivity coefficient, which controls the amplification of risk scores by an upward frequency trend; when When the correction term is greater than 1, the score is adjusted upward to reflect the worsening trend of this type of anomaly; This is the amplification factor for anomaly co-occurrence. It is determined based on the historical correlation strength between other anomaly entries that co-occur with the anoth anomaly in the same batch on the current test board. When multiple anomalies frequently co-occur in historical data, this factor is greater than 1, reflecting that the actual risk of a single anomaly in a multi-anomaly co-occurrence scenario is higher than the risk when it appears in isolation.

[0051] This embodiment enables the scoring to maintain early warning sensitivity to the trend of increasing anomalies of a certain type; it introduces a co-occurrence correlation amplification factor to capture the synergistic risk effect under multiple anomaly combination scenarios, thereby improving the accuracy of comprehensive risk assessment for complex fault scenarios.

[0052] In some possible embodiments of the present invention, the incremental update method for the dynamic reference signal model parameters in the test conclusion decision and adaptive update steps is as follows:

[0053] in, Let be the updated mean of the dim-th feature dimension after including the (s+1)th new sample; Let be the feature value of the qth valid sample in the dim dimension; Forgetting factor, The more recent the sample, the greater its weight; The feature quality confidence score of the q-th sample in the dim dimension is jointly evaluated based on the signal-to-noise ratio and channel reliability coefficient of that sample during acquisition. The worse the acquisition quality, the lower the confidence score. The smaller the value, the less the contribution of low-quality samples to the mean update; s+1 is the total number of valid samples after the inclusion of new samples. The global historical average across all logic board models in the dim dimension serves as an anchoring reference to prevent model-specific benchmarks from deviating from a reasonable physical range. The global anchoring constraint strength coefficient controls the shrinkage of the model-specific mean towards the global mean. This is a numerical stability protection term to prevent... A division-by-zero anomaly occurs when the value approaches zero. Indicates: Model-specific average Compared with the global mean When the deviation is large, a contraction constraint is applied to the updated mean in the direction of the global mean to prevent unreasonable drift of the baseline mean due to the mixing of continuous abnormal samples or occasional batch fluctuations.

[0054] In this embodiment, based on the forgetting factor mechanism, a sample feature quality confidence level is introduced. The update contribution of low-quality samples is suppressed in two ways, and cross-model physical rationality constraints are set for the model-specific benchmark mean through a global anchoring correction term. This effectively prevents the benchmark mean from drifting uncontrollably due to abnormal sample quality or extreme batch fluctuations, and ensures the stability of the benchmark model in the long term.

[0055] Please refer to Figure 2 Another embodiment of the present invention provides an automated signal analysis system for screenless testing of liquid crystal logic boards, which is used to perform an automated signal analysis method for screenless testing of liquid crystal logic boards, including: a control processing unit and a multi-channel signal acquisition unit; The multi-channel signal acquisition unit is configured to synchronously acquire timing control signals, power rail voltage waveforms, and backlight drive pulse signals on each interface bus after the LCD logic board is powered on. The control processing unit is configured to: The characteristic parameters of timing control signals, power rail voltage waveforms and backlight drive pulse signals in the time domain, frequency domain and phase domain are extracted. Combined with logic board model identification and historical good product data, a dynamic reference signal model covering a multi-dimensional feature space is constructed. Based on the dynamic reference signal model, a virtual LCD screen model corresponding to the logic board under test is established in the digital twin simulation environment. The collected real-time signals are mapped to the virtual screen driving link to simulate the complete driving process of the TCON chip to the virtual screen, thereby restoring the actual driving behavior of the logic board without a physical screen. The signal response generated during the virtual driving process is compared layer by layer with the dynamic reference signal model. The deviation features are classified and identified using a trained deep learning model. The functional modules and signal link nodes corresponding to the abnormal signals are automatically located, and a structured diagnostic report containing the abnormality type, abnormality level and the location of the associated circuit is output. Based on the anomaly level and preset judgment rules in the structured diagnostic report, the system automatically outputs the test pass or fail judgment conclusion for the logic board. The signal feature data and judgment results of this test are fed back to the dynamic reference signal model to drive the adaptive iterative update of the model parameters.

[0056] It should be known that, Figure 2 The block diagram of the automated signal analysis system for screenless testing of liquid crystal logic boards shown is for illustrative purposes only, and the number of modules shown does not limit the scope of protection of this invention. The automated signal analysis system for screenless testing of liquid crystal logic boards provided in this embodiment can be used to execute various embodiments of the corresponding automated signal analysis method for screenless testing of liquid crystal logic boards. For specific implementation details, please refer to the descriptions of the respective method embodiments, which will not be repeated here.

[0057] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, as some steps may be performed in other orders or simultaneously according to this application. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily essential to this application.

[0058] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0059] In the several embodiments provided in this application, it should be understood that the disclosed apparatus can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of the units described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical or other forms.

[0060] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0061] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0062] If the integrated units described above are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage device (CMD). Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a memory and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned memory includes various media capable of storing program code, such as USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0063] Those skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, which may include: flash drive, read-only memory (ROM), random access memory (RAM), disk or optical disk, etc.

[0064] The embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

[0065] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can easily conceive of variations or substitutions without departing from the spirit and scope of the present invention, and various modifications and alterations can be made, including combinations of the different functions and implementation steps described above, as well as software and hardware implementation methods, all of which are within the protection scope of the present invention.

Claims

1. An automated signal analysis method for screenless testing of a liquid crystal logic board, characterized in that, include: After powering on the LCD logic board, the timing control signals, power rail voltage waveforms and backlight drive pulse signals on each interface bus are synchronously acquired through the multi-channel signal acquisition unit. The characteristic parameters of timing control signals, power rail voltage waveforms and backlight drive pulse signals in the time domain, frequency domain and phase domain are extracted. Combined with logic board model identification and historical good product data, a dynamic reference signal model covering a multi-dimensional feature space is constructed. Based on the dynamic reference signal model, a virtual LCD screen model corresponding to the logic board under test is established in the digital twin simulation environment. The collected real-time signals are mapped to the virtual screen driving link to simulate the complete driving process of the TCON chip to the virtual screen, thereby restoring the actual driving behavior of the logic board without a physical screen. The signal response generated during the virtual driving process is compared layer by layer with the dynamic reference signal model. The deviation features are classified and identified using a trained deep learning model. The functional modules and signal link nodes corresponding to the abnormal signals are automatically located, and a structured diagnostic report containing the abnormality type, abnormality level and the location of the associated circuit is output. Based on the anomaly level and preset judgment rules in the structured diagnostic report, the system automatically outputs the test pass or fail judgment conclusion for the logic board. The signal feature data and judgment results of this test are fed back to the dynamic reference signal model to drive the adaptive iterative update of the model parameters.

2. The automated signal analysis method for screenless testing of liquid crystal logic boards according to claim 1, characterized in that, The steps of extracting the characteristic parameters of the timing control signal, power rail voltage waveform, and backlight drive pulse signal in the time, frequency, and phase domains, and combining them with the logic board model identifier and historical good product data to construct a dynamic reference signal model covering a multi-dimensional feature space include: The timing control signals, power rail voltage waveforms, and backlight drive pulse signals acquired from multiple channels are classified and stored according to the logic board model identifier, forming a raw signal dataset indexed by model. For each signal in the original signal dataset, the amplitude, rise time, and pulse width features are extracted in the time domain, the main frequency component and harmonic energy features are extracted in the frequency domain, and the phase difference features between each signal are extracted in the phase domain, forming a multi-domain feature vector corresponding to each signal. The multi-domain feature vectors are compared with the feature distribution of the corresponding models in the historical good product data. Abnormal samples that deviate from the good product feature distribution are removed, and feature vectors with confidence levels that meet the preset threshold are retained as valid modeling samples. The multi-domain feature vectors of each signal in the effective modeling sample are fused according to the three signal dimensions of timing control, power rail and backlight drive to construct a multi-dimensional feature space covering all feature dimensions of the three signal types. Based on the multidimensional feature space, a dynamic reference signal model containing the feature mean and feature tolerance range is generated for each logic board model, and the model parameters are automatically updated as new good samples are continuously added.

3. The automated signal analysis method for screenless testing of liquid crystal logic boards according to claim 2, characterized in that, The steps of establishing a virtual LCD screen model corresponding to the logic board under test in a digital twin simulation environment based on the dynamic reference signal model, mapping the acquired real-time signals to the virtual screen drive link, simulating the complete drive process of the TCON chip on the virtual screen, and thus restoring the actual drive behavior of the logic board without a physical screen, include: Based on the model identifier of the logic board under test, the corresponding screen specification parameters, including resolution, refresh rate, interface timing specifications and backlight modulation method, are read from the dynamic reference signal model. The structure and parameter initialization of the virtual LCD screen model are completed in the digital twin simulation environment. The timing control signals, power rail voltage waveforms, and backlight drive pulse signals acquired from multiple channels are connected to the digital twin simulation environment in real time. The timing alignment and amplitude normalization preprocessing are performed according to the drive link level corresponding to each signal to form a standardized input signal stream that can drive the virtual screen model. The standardized input signal stream is injected into the virtual screen driving link to simulate the source driving, gate scanning and gamma correction of the virtual screen by the TCON chip in the digital twin simulation environment, thereby generating the simulation response signals of each node of the virtual screen. The simulation response signal was checked for completeness to confirm that the TCON drive timing, frame synchronization signal and backlight enable logic were fully responded to in the virtual screen model, thus confirming that the actual driving behavior of the logic board was fully reproduced under the condition of no physical screen.

4. The automated signal analysis method for screenless testing of liquid crystal logic boards according to claim 3, characterized in that, The steps of comparing the signal response generated during the virtual driving process with the dynamic reference signal model layer by layer, classifying and identifying deviation features using a trained deep learning model, automatically locating the functional modules and signal link nodes corresponding to abnormal signals, and outputting a structured diagnostic report containing the abnormality type, abnormality level, and location of associated circuits include: The simulated response signal is compared layer by layer with the characteristic mean and tolerance range of the corresponding level in the dynamic reference signal model according to the three link levels of power rail, timing control and backlight drive, and the deviation feature vectors that exceed the tolerance range in each level are extracted. The deviation feature vector is input into a deep learning classification model trained on historical fault samples to identify the fault type of the deviation features and output the anomaly type label and classification confidence of each deviation feature. Based on the anomaly type label and classification confidence level, and combined with the preset anomaly level assessment rules, each anomaly type is assessed as fatal, severe, or minor, forming an anomaly assessment result that includes the anomaly type and the corresponding level. Based on the anomaly type and driving link level in the anomaly assessment results, the logic board circuit topology mapping table is retrieved to locate the anomaly signal to the corresponding functional module and signal link node, generating the circuit location information of the anomaly. The anomaly type label, anomaly level, and circuit location information are integrated according to a unified data structure to output a structured diagnostic report containing the above three types of information.

5. The automated signal analysis method for screenless testing of liquid crystal logic boards according to claim 4, characterized in that, The step of automatically outputting the test pass or failure conclusion of the logic board based on the anomaly level in the structured diagnostic report and the preset judgment rules includes: Read the abnormality level of all abnormal entries in the structured diagnostic report, and count the number of abnormalities at each level (critical, severe, and minor) to form a summary of the abnormality level distribution of the current logic board under test. The distribution of the abnormal levels is summarized and matched with the judgment rules for the corresponding logic board models in the preset judgment rule library. The judgment rules specify the upper limit of the number of abnormalities at each level and the judgment priority of different combinations of abnormalities. Based on the matching results, the judgments are executed step by step according to the priority order to obtain the judgment conclusion. Specifically, if any fatal level anomaly exists, the failure conclusion is output directly; if there is no fatal anomaly but the number of severe level anomalies exceeds the allowed limit, the failure conclusion is output; if none of the above conditions are met, the pass conclusion is output. The judgment conclusion is bound and encapsulated with the anomaly level distribution summary and associated circuit location information in the structured diagnostic report to form a complete test result record containing the judgment conclusion and its basis, and then output.

6. The automated signal analysis method for screenless testing of liquid crystal logic boards according to claim 5, characterized in that, In the multi-domain feature extraction step, the fusion method for the comprehensive feature scores of each signal is as follows: in, The comprehensive feature score of the ch-th signal; These represent the peak and trough values ​​of the time-domain amplitude, respectively. This is the baseline amplitude for good quality products; The frequency domain energy of the nth harmonic; The total energy across the entire frequency band; N is the upper limit of the harmonic order used in the calculation; Let be the phase difference between the ch-th signal and the reference signal; To allow the maximum phase deviation; These are the three domain weight coefficients, the sum of which is 1, determined by regression analysis of historical good product data; Let be the channel reliability coefficient of the ch-th signal, with a value ranging from (0,1]. It is determined based on the historical stability statistics of this channel. The worse the stability, the lower the reliability coefficient. The smaller the value, the more it suppresses the overall score; The signal-to-noise ratio of the currently acquired signal from channel ch; This is the reference signal-to-noise ratio for the good signal in this channel; This is the sensitivity coefficient for signal-to-noise ratio correction, which controls the magnitude of the correction to the score caused by the signal-to-noise ratio deviation.

7. The automated signal analysis method for screenless testing of liquid crystal logic boards according to claim 6, characterized in that, In the process of generating the dynamic baseline model, the adaptive tolerance range is calculated as follows: in, These are the upper and lower limits of the tolerance for the dim-th feature dimension, respectively; These are the mean and standard deviation of the feature values ​​of good-quality samples in this dimension, respectively. The basic tolerance expansion factor; The number of valid modeling samples for this dimension; The baseline threshold for the number of samples; This is the slope control parameter for the Sigmoid expansion factor; Let be the coefficient of variation of the good samples in the dim dimension, defined as This reflects the degree of dispersion of good samples in this feature dimension; This is a sensitivity adjustment parameter for the coefficient of variation, controlling the extent to which the degree of dispersion affects the tolerance expansion. This is the seasonal / periodic fluctuation correction factor for the dim dimension. It is determined based on the statistical fluctuation range of this feature dimension in different production periods (such as different shifts, temperature and humidity seasons) in historical data, and the value fluctuates around 1.

8. The automated signal analysis method for screenless testing of liquid crystal logic boards according to claim 7, characterized in that, In the real-time signal access and preprocessing process, the delay estimation method for multi-channel timing alignment is as follows: in, The optimal alignment delay of the ch-th channel signal relative to the reference channel; The reference channel signal is sampled at time t; For the signal of channel ch at time t... The sampled value at that location; These are the start and end times of the signal segment used for time delay estimation; The signal quality weighting function at time t is determined based on the signal amplitude and the estimated local signal-to-noise ratio at that time. It assigns lower weights to sampling points in periods with poor signal quality to suppress the impact of transient interference on cross-correlation estimation. The noise variance estimate for the current acquisition segment in channel ch is obtained from statistics of the silent signal segment. The total signal variance of the currently acquired segment in channel ch; The noise suppression confidence factor reflects the proportion of effective signal energy in the total signal energy. The greater the noise, the smaller the factor, and it applies an overall confidence penalty to the time delay estimation results.

9. The automated signal analysis method for screenless testing of a liquid crystal logic board according to claim 8, characterized in that, In the assessment of anomaly levels, the comprehensive risk score is calculated as follows: in, The comprehensive risk score for the anoth anomaly; The preset base hazard coefficient for this anomaly type; The classification confidence score output by the deep learning classification model; This represents the hierarchical depth of the signal link where the anomaly occurs. This represents the total number of levels in the driving link; This is the normalized distance between the feature vector of the abnormal deviation and the mean of the corresponding feature in the benchmark model; This is the distance sensitivity coefficient; These are the weighting coefficients for the three scoring components, and their sum is 1. This represents the frequency of occurrence of this anomaly type in recent test batches; This represents the baseline frequency of occurrence of this anomaly type in the entire historical dataset. This is the frequency trend sensitivity coefficient, which controls the amplification of risk scores by an upward frequency trend; when When the correction term is greater than 1, the score is adjusted upward to reflect the worsening trend of this type of anomaly; This is the amplification factor for anomaly co-occurrence. It is determined based on the historical correlation strength between other anomaly entries that co-occur with the anoth anomaly in the same batch on the current test board. When multiple anomalies frequently co-occur in historical data, this factor is greater than 1, reflecting that the actual risk of a single anomaly in a multi-anomaly co-occurrence scenario is higher than the risk when it appears in isolation.

10. An automated signal analysis system for screenless testing of liquid crystal logic boards, used to execute the automated signal analysis method for screenless testing of liquid crystal logic boards as described in any one of claims 1 to 9, characterized in that, include: Control processing unit and multi-channel signal acquisition unit; The multi-channel signal acquisition unit is configured to synchronously acquire timing control signals, power rail voltage waveforms, and backlight drive pulse signals on each interface bus after the LCD logic board is powered on. The control processing unit is configured to: The characteristic parameters of timing control signals, power rail voltage waveforms and backlight drive pulse signals in the time domain, frequency domain and phase domain are extracted. Combined with logic board model identification and historical good product data, a dynamic reference signal model covering a multi-dimensional feature space is constructed. Based on the dynamic reference signal model, a virtual LCD screen model corresponding to the logic board under test is established in the digital twin simulation environment. The collected real-time signals are mapped to the virtual screen driving link to simulate the complete driving process of the TCON chip to the virtual screen, thereby restoring the actual driving behavior of the logic board without a physical screen. The signal response generated during the virtual driving process is compared layer by layer with the dynamic reference signal model. The deviation features are classified and identified using a trained deep learning model. The functional modules and signal link nodes corresponding to the abnormal signals are automatically located, and a structured diagnostic report containing the abnormality type, abnormality level and the location of the associated circuit is output. Based on the anomaly level and preset judgment rules in the structured diagnostic report, the system automatically outputs the test pass or fail judgment conclusion for the logic board. The signal feature data and judgment results of this test are fed back to the dynamic reference signal model to drive the adaptive iterative update of the model parameters.

Images