A fast matrix multiplication encryption circuit based on layer-by-layer bit accumulation

Abstract

This invention discloses a fast matrix multiplication encryption circuit based on layer-by-layer bit accumulation, comprising: a data processing module, a quantization encoding module, and a fast dot product module for quantized vectors; wherein, the data processing module is used to process the initial input of the encryption circuit; the quantization encoding module is responsible for quantizing and encoding the output data of the data processing module; and the fast dot product module for quantized vectors is responsible for the dot product circuit operation of multi-bit quantized vectors and decoding the output encryption circuit result. Compared with conventional matrix multiplication encryption circuits of the same bit width, this invention can greatly reduce overhead, reduce hardware resource consumption, achieve fast encryption calculation, and effectively adapt to resource-constrained IoT devices.

Description

Technical Field

[0001] This invention relates to the field of encryption circuit design, and in particular to a fast matrix multiplication encryption circuit based on layer-by-layer bit accumulation. Background Technology

[0002] In fields such as privacy computing, secure inference, and encrypted communication, matrix multiplication serves as a core computational module. The performance and overhead of its encrypted computation directly determine the deployment efficiency and practicality of the entire encryption system. This is especially true in resource-constrained scenarios such as IoT terminals and edge computing devices, where the demand for high-performance, low-overhead matrix multiplication encryption circuits is even more urgent. In the practical design and application of matrix multiplication encryption circuits, existing technologies have significant shortcomings: traditional matrix multiplication encryption circuits often employ full-precision encryption operation modes, failing to perform bit-level decomposition and layered optimization for the multi-bit operation characteristics of matrix multiplication. This results in high computational overhead and high hardware resource consumption during operation, making it difficult to adapt to the deployment requirements of resource-constrained devices. Furthermore, with the rapid development of privacy computing and secure inference technologies, matrix multiplication encryption circuits are widely used in scenarios such as secure inference using Transformer models. These scenarios place higher demands on the computational speed, encryption security, and hardware resource adaptability of matrix multiplication. Existing encryption schemes cannot simultaneously achieve high performance and low overhead, making them unsuitable for large-scale deployments in these scenarios.

[0003] In summary, existing matrix multiplication encryption circuits generally suffer from technical drawbacks such as high computational overhead, high hardware resource consumption, and poor multi-bit adaptability, making it difficult to meet the requirements for high efficiency and lightweight underlying circuitry in secure computing scenarios. Therefore, there is an urgent need to propose a fast matrix multiplication encryption circuit that balances low overhead with efficient multi-bit computation, addressing the efficiency and overhead challenges of multi-bit matrix multiplication encryption. Summary of the Invention

[0004] To overcome the shortcomings of existing technologies, this invention provides a fast matrix multiplication encryption circuit based on layer-by-layer bit accumulation. Compared with conventional matrix multiplication encryption circuits of the same bit width, it can greatly reduce overhead, reduce hardware resource consumption, achieve fast encryption calculation, and effectively adapt to resource-constrained IoT devices.

[0005] To achieve the above-mentioned objectives, the present invention adopts the following technical solution: The present invention provides a fast matrix multiplication encryption circuit based on layer-by-layer bit accumulation, characterized in that it includes: a data processing module, a quantization encoding module, and a fast dot product module for quantized vectors; The data processing module receives a first input matrix from external input. Second input matrix ,Will Divided into rows The first input vector , will Divided into columns The second input vector ;in, Indicates the first The first input vector, Indicates the first The second input vector, , ; The quantization and encoding module consists of a data control unit, a data quantization unit, and an encoding unit. The data control unit reads sequentially. and And send it to the data quantization unit; The data quantization unit respectively performs... and Each element in quantization of each bit yields... quantization vector and quantization vector And send it to the encoding unit, where, express The One quantized element, ,and , express The Middle Quantization feature value at bit, and , Indicates the sequence number of the quantized bit. , express The One quantized element, and , express The Middle Quantization feature value at bit, and , Another index representing the quantized bit. ; The encoding unit will and All values ​​in The quantization feature values ​​are all 0; then, for and Each quantized feature value is encoded single-bit by an encryption circuit to obtain... Encoding vector and Encoding vector ;in, express The Each encoded element express The One encoded element; The fast dot product module for quantized vectors consists of a multi-bit quantized dot product unit and a decoding unit; The multi-bit quantized dot product unit reads and And utilizes a fast dot product encryption circuit based on multi-bit quantization vectors with layer-by-layer bit accumulation to... and Calculations were performed to obtain and dot product encoding Then, it is sent to the decoding unit; The decoding unit encodes all dot product values ​​using an encryption circuit decoder. Decode to obtain dimensional output matrix .

[0006] The characteristic of the fast matrix multiplication encryption circuit based on layer-by-layer bit accumulation described in this invention is that the multi-bit quantization vector fast dot product encryption circuit based on layer-by-layer bit accumulation in the quantization vector fast dot product module is obtained according to the following steps. : Step 1, Definition A set of quantized bits ,in, Indicates the first A set of quantized bits, initialized ; Step 2, Initialization ; Step 3: Traverse the fast dot product module of the quantized vector. and The Middle On each encoded element, satisfying The Bit-level quantization feature value encoding and the Bit-level quantization feature value encoding , , and calculate Added later to the A set of quantized bits In; among them, This indicates the XOR encryption circuit operation; Step 4, Judgment Check if the condition is met. If it is, proceed to step 5; otherwise, proceed to the next step. Assign to Then, return to step 2; Step 5: Define variables and initialize ; Step 6, calculate the first... A set of hierarchical bit codes and the Hierarchical feature value encoding : ;in, This represents the encryption circuit operation of bit-by-bit accumulation. Step 7, Assign to Then, make a judgment Whether it is true or not, if true, then... Assigned to the first A set of fused bit codes Otherwise, Assign to ; Step 8, Judgment Number of elements in Is it true? If true, then calculate. Otherwise, The only element in the array is assigned to ; Step 9, Judgment Check if the condition is met. If it is met, proceed to step 10; otherwise, return to step 7. Step 10: Define variables and initialize Assign to After integrating all hierarchical feature value codes, a comprehensive feature value code is obtained. ; Step 11: Calculate the dot product code .

[0007] Furthermore, the encryption circuit that accumulates bits layer by layer is obtained according to the following steps. and : Step 6.1: The quantized vector fast dot product module reads... And assign the value to the input encoding set ; Step 6.2, Definition and Bit Encoding Set Carry bit encoding set and initialize , ; According to the number of groups ,right After grouping, the remaining number of codes is denoted as ; Step 6.3, Judgment If the condition is met, proceed to step 6.4; otherwise, proceed to step 6.9. Step 6.4, Define variables and initialize Define variables and initialize ; Step 6.5, Judgment If the condition is met, proceed to step 6.6; otherwise, proceed to step 6.7. Step 6.6: Use a dedicated 1-bit adder circuit to... The Middle Number Code , No. Number Code and the Number Code The process is performed to obtain the carry bit code. and bit encoding and will Add to In the middle, Add to In the middle, Assign to ;Will Assign to Then, return to step 6.5; Step 6.7, Judgment Whether it is true or not, if true, then... The end Add an encoding middle; Step 6.8, Assign to ,Will Assign to ,Will Assign to ,Will Assign to Then, return to step 6.3; Step 6.9, Judgment Whether it is true or false; if it is true, then it means... There is only one unique code in it, Assign to the output feature code If yes, proceed to step 6.11; otherwise, proceed to step 6.10. Step 6.10, Judgment Whether it is true or false; if it is true, then it means... There are only two codes, and a dedicated 1-bit adder circuit is used for... , and auxiliary bit encoding The process is performed to obtain the carry bit code. Hehe bit encoding and will Add to In the middle, Assign to Then, proceed to step 6.11; Step 6.11, Output of the encryption circuit with layer-by-layer bit accumulation and .

[0008] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. The layer-by-layer bit accumulation encryption circuit scheme proposed in this invention breaks through the inherent limitation of large computational overhead in traditional bit accumulation operations, and realizes fast and low-overhead matrix multiplication encryption calculation under multi-bit values, providing stable and reliable underlying privacy support for secure computing scenarios. 2. This invention designs a fast matrix multiplication encryption circuit based on layer-by-layer bit accumulation, which can dynamically adapt to the optimal quantization bit. Under the premise of ensuring data security, compared with the standard matrix multiplication encryption circuit with the same bit, it significantly reduces the computational overhead, the number of gate circuits and the consumption of hardware resources, and realizes efficient computational acceleration of encrypted matrix multiplication. It effectively solves the technical defects of overhead explosion and low efficiency in traditional multi-bit matrix operations, and has excellent performance and practicality. 3. The fast matrix multiplication encryption circuit based on layer-by-layer bit accumulation proposed in this invention, as a general-purpose low-level secure computing module, is not limited to specific upper-layer application scenarios. It can be widely applied to various scenarios such as privacy computing, secure inference, and encrypted numerical computing that require secure matrix operations. While giving full play to the low-overhead advantage of layer-by-layer bit accumulation, it also takes into account multi-bit computing capabilities and architectural versatility, which greatly improves the deployment capability and application scope of encrypted matrix multiplication in resource-constrained devices, edge computing, and large-scale secure computing systems. Attached Figure Description

[0009] Figure 1 This is a diagram of a fast matrix multiplication encryption circuit architecture based on layer-by-layer bit accumulation according to the present invention. Figure 2 This is the circuit diagram corresponding to the fast multiplication encryption operation of the quantized matrix elements in the method of this invention; Figure 3 This is a calculation diagram of the encryption circuit for layer-by-layer bit accumulation in the method of this invention; Figure 4 This is a circuit diagram of a dedicated 1-bit adder for the method of this invention; Figure 5 This is a roadmap for the fast and secure dot product of quantized vectors in this invention. Detailed Implementation

[0010] In this embodiment, a fast matrix multiplication encryption circuit based on layer-by-layer bit accumulation is described, such as... Figure 1 As shown, it includes: a data processing module, a quantization encoding module, and a fast dot product module for quantized vectors; The data processing module receives the first input matrix from external input. Second input matrix ,Will Divided into rows The first input vector , will Divided into columns The second input vector ;in, Indicates the first The first input vector, Indicates the first The second input vector, , This encryption circuit can handle any two input matrices requiring secure matrix multiplication, for example, in matrix multiplication within a Transformer inference module. and These represent the output matrix of the previous module and the weight matrix of this module, respectively.

[0011] The quantization and encoding module consists of a data control unit, a data quantization unit, and an encoding unit; The data control unit reads them sequentially. and And send it to the data quantization unit; The data quantization unit respectively... and Each element in quantization of each bit yields... quantization vector and quantization vector And send it to the encoding unit, where, express The One quantized element, ,and , express The Middle Quantization feature value at bit, and , Indicates the sequence number of the quantized bit. , express The One quantized element, and , express The Middle Quantization feature value at bit, and , Another index representing the quantized bit. ; Assumption And the two quantized vectors are , This means that each element after quantization can be represented by 3 bits. , , , , , , , , , .

[0012] The encoding unit will and All values ​​in The quantization feature values ​​are all 0; then, for and Each quantized feature value is encoded single-bit by an encryption circuit to obtain... Encoding vector and Encoding vector ;in, express The Each encoded element express The One encoded element; after replacing the quantized feature value, we get... , , , , , , , , , .

[0013] The fast dot product module for quantized vectors consists of a multi-bit quantized dot product unit and a decoding unit; Multi-bit quantized dot product unit read and And utilizes a fast dot product encryption circuit based on multi-bit quantization vectors with layer-by-layer bit accumulation to... and Calculations were performed to obtain and dot product encoding Then, it is sent to the decoding unit.

[0014] In this embodiment, the fast dot product encryption circuit based on layer-by-layer bit accumulation of multi-bit quantization vectors is obtained according to the following steps. : Step 1, Definition A set of quantized bits ,in, Indicates the first A set of quantized bits, initialized That is, initial common ownership. A set.

[0015] Step 2, Initialization ; Step 3: Traverse the fast dot product module for quantized vectors and The Middle On each encoded element, satisfying The Bit-level quantization feature value encoding and the Bit-level quantization feature value encoding , , and calculate Added later to the A set of quantized bits In; among them, This represents the XOR encryption circuit operation; with and The Middle Taking a single encoded element as an example, when At this time, it should be obtained , ; Figure 2 The circuit diagram for fast multiplication of quantized elements is shown.

[0016] Step 4, Judgment Check if the condition is met. If it is, proceed to step 5; otherwise, proceed to the next step. Assign to Then, return to step 2; from this, the following can be calculated: , , , , .

[0017] Step 5: Define variables and initialize ; Step 6, calculate the first... A set of hierarchical bit codes and the Hierarchical feature value encoding : ;in, This represents the encryption circuit operation of bit-by-bit accumulation. Figure 3 The diagram shows the calculation of the encryption circuit with bit-by-bit accumulation, thus allowing the calculation of... , .

[0018] In this embodiment, the encryption circuit that accumulates bits layer by layer is obtained according to the following steps. and : Step 6.1: Read the quantized vector fast dot product module. And assign the value to the input encoding set ;by For the input encoding example, at this time .

[0019] Step 6.2, Definition and Bit Encoding Set Carry bit encoding set and initialize , ; According to the number of groups ,right After grouping, the remaining number of codes is denoted as ;Will Grouping to get the number of groups And the remaining number of codes is .

[0020] Step 6.3, Judgment If the condition is met, proceed to step 6.4; otherwise, proceed to step 6.9. Step 6.4, Define variables and initialize Define variables and initialize .

[0021] Step 6.5, Judgment If the condition is met, proceed to step 6.6; otherwise, proceed to step 6.7. Step 6.6: Use a dedicated 1-bit adder circuit to... The Middle Number Code , No. Number Code and the Number Code The process is performed to obtain the carry bit code. and bit encoding and will Add to In the middle, Add to In the middle, Assign to ;Will Assign to Then, return to step 6.5; Figure 4 The circuit diagram of a dedicated 1-bit adder is shown. This circuit consists of 3 circuit input bits, 4 XOR gates, 1 AND gate, and 2 circuit output bits.

[0022] Step 6.7, Judgment Whether it is true or not, if true, then... The end Add an encoding middle; Step 6.8, Assign to ,Will Assign to ,Will Assign to ,Will Assign to Then, return to step 6.3.

[0023] Steps 6.3 to 6.8 apply a dedicated 1-bit adder circuit to each group and add the outputs of the two circuits to the corresponding carry bit encoding set and sum bit encoding set, then input the encoding set... Update, repeat the above process until the elements in the set are insufficient to form a group, thus obtaining , .

[0024] Step 6.9, Judgment Whether it is true or false; if it is true, then it means... There is only one unique code in it, Assign to the output feature code If yes, proceed to step 6.11; otherwise, proceed to step 6.10. Step 6.10, Judgment Whether it is true or false; if it is true, then it means... There are only two codes, and a dedicated 1-bit adder circuit is used for... , and auxiliary bit encoding The process is performed to obtain the carry bit code. Hehe bit encoding and will Add to In the middle, Assign to Then, proceed to step 6.11.

[0025] Step 6.11, Output of the encryption circuit with layer-by-layer bit accumulation and This encryption circuit outputs... and .

[0026] Step 7, Assign to Then, make a judgment Whether it is true or not, if true, then... Assigned to the first A set of fused bit codes Otherwise, Assign to .

[0027] Step 8, Judgment Number of elements in Is it true? If true, then calculate. Otherwise, The only element in the array is assigned to .

[0028] Step 9, Judgment If the condition is true, proceed to step 10; otherwise, return to step 7. From this, we can calculate... , , , , , , , , , , , , , , , , , , , ; Figure 5 The flowchart of the fast dot product encryption circuit for quantized vectors is demonstrated.

[0029] Step 10: Define variables and initialize Assign to After integrating all hierarchical feature value codes, a comprehensive feature value code is obtained. ; Step 11: Calculate the dot product code From this, we can calculate .

[0030] The decoding unit encodes all dot product values ​​through an encryption circuit decoder. Decode to obtain dimensional output matrix .

Claims

1. A fast matrix multiplication encryption circuit based on layer-by-layer bit accumulation, characterized in that, include: Data processing module, quantization encoding module, and fast dot product module for quantized vectors; The data processing module receives a first input matrix from external input. Second input matrix ,Will Divided into rows The first input vector , will Divided into columns The second input vector ;in, Indicates the first The first input vector, Indicates the first The second input vector, , ; The quantization and encoding module consists of a data control unit, a data quantization unit, and an encoding unit. The data control unit reads sequentially. and And send it to the data quantization unit; The data quantization unit respectively performs... and Each element in quantization of each bit yields... quantization vector and quantization vector And send it to the encoding unit, where, express The One quantized element, ,and , express The Middle Quantization feature value at bit, and , Indicates the sequence number of the quantized bit. , express The One quantized element, and , express The Middle Quantization feature value at bit, and , Another index representing the quantized bit. ; The encoding unit will and All values ​​in The quantization feature values ​​are all 0; then, for and Each quantized feature value is encoded single-bit by an encryption circuit to obtain... Encoding vector and Encoding vector ;in, express The Each encoded element express The One encoded element; The fast dot product module for quantized vectors consists of a multi-bit quantized dot product unit and a decoding unit; The multi-bit quantized dot product unit reads and And utilizes a fast dot product encryption circuit based on multi-bit quantization vectors with layer-by-layer bit accumulation to... and Calculations were performed to obtain and dot product encoding Then, it is sent to the decoding unit; The decoding unit encodes all dot product values ​​using an encryption circuit decoder. Decode to obtain dimensional output matrix .

2. The fast matrix multiplication encryption circuit based on layer-by-layer bit accumulation according to claim 1, characterized in that, The multi-bit quantized vector fast dot product encryption circuit based on layer-by-layer bit accumulation in the quantized vector fast dot product module is obtained according to the following steps. : Step 1, Definition A set of quantized bits ,in, Indicates the first A set of quantized bits, initialized ; Step 2, Initialization ; Step 3: Traverse the fast dot product module of the quantized vector. and The Middle On each encoded element, satisfying The Bit-level quantization feature value encoding and the Bit-level quantization feature value encoding , , and calculate Added later to the A set of quantized bits In; among them, This indicates the XOR encryption circuit operation; Step 4, Judgment Check if the condition is met. If it is, proceed to step 5; otherwise, proceed to the next step. Assign to Then, return to step 2; Step 5: Define variables and initialize ; Step 6, calculate the first... A set of hierarchical bit codes and the Hierarchical feature value encoding : ;in, This represents the encryption circuit operation of bit-by-bit accumulation. Step 7, Assign to Then, make a judgment Whether it is true or not, if true, then... Assigned to the first A set of fused bit codes Otherwise, Assign to ; Step 8, Judgment Number of elements in Is it true? If true, then calculate. Otherwise, The only element in the array is assigned to ; Step 9, Judgment Check if the condition is met. If it is met, proceed to step 10; otherwise, return to step 7. Step 10: Define variables and initialize Assign to After integrating all hierarchical feature value codes, a comprehensive feature value code is obtained. ; Step 11: Calculate the dot product code .

3. The fast dot product encryption circuit for multi-bit quantized vectors based on layer-by-layer bit accumulation according to claim 2, characterized in that, The encryption circuit that accumulates bits layer by layer is obtained according to the following steps. and : Step 6.1: The quantized vector fast dot product module reads... And assign the value to the input encoding set ; Step 6.2, Definition and Bit Encoding Set Carry bit encoding set and initialize , ; According to the number of groups ,right After grouping, the remaining number of codes is denoted as ; Step 6.3, Judgment If the condition is met, proceed to step 6.4; otherwise, proceed to step 6.

9. Step 6.4, Define variables and initialize Define variables and initialize ; Step 6.5, Judgment If the condition is met, proceed to step 6.6; otherwise, proceed to step 6.

7. Step 6.6: Use a dedicated 1-bit adder circuit to... The Middle Number Code , No. Number Code and the Number Code The process is performed to obtain the carry bit code. and bit encoding and will Add to In the middle, Add to In the middle, Assign to ;Will Assign to Then, return to step 6.5; Step 6.7, Judgment Whether it is true or not, if true, then... The end Add an encoding middle; Step 6.8, Assign to ,Will Assign to ,Will Assign to ,Will Assign to Then, return to step 6.3; Step 6.9, Judgment Whether it is true or false; if it is true, then it means... There is only one unique code in it, Assign to the output feature code If the condition is met, proceed to step 6.11; otherwise, proceed to step 6.

10. Step 6.10, Judgment Whether it is true or false; if it is true, then it means... There are only two codes, and a dedicated 1-bit adder circuit is used for... , and auxiliary bit encoding The process is performed to obtain the carry bit code. Hehe bit encoding and will Add to In the middle, Assign to Then, proceed to step 6.11; Step 6.11, Output of the encryption circuit with layer-by-layer bit accumulation and .

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