Reliability assessment methods, apparatus, equipment and storage media for power semiconductor devices

Abstract

This application discloses a method, apparatus, device, and storage medium for reliability assessment of power semiconductor devices, relating to the field of semiconductor technology. The method includes: acquiring instantaneous and stable parameter values ​​of the power semiconductor device to be assessed at various stress stages; determining parameter changes corresponding to each stress stage based on the instantaneous and stable parameter values; and assessing the reliability of the power semiconductor device based on these parameter changes. By distinguishing between total degradation and residual degradation through parameter acquisition at multiple stress stages, and defining the recoverable change as the difference between the two types of degradation, this systematically solves the technical problems of inability to assess coupled failures and confusion between degradation types, achieving effective reliability assessment of power semiconductor devices under complex stress coupling.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a method, apparatus, device and storage medium for reliability assessment of power semiconductor devices. Background Technology

[0002] Currently, power semiconductor devices are the core switching elements of power electronic systems. In practical applications, these devices are subjected to multiple physical stresses during operation, including gate bias stress, conduction current stress, and blocking voltage stress. These three stresses can respectively induce three degradation mechanisms: gate dielectric degradation, channel trap accumulation, and increased leakage current under high electric fields. To ensure safe operation, reliability assessment of power semiconductor devices is essential.

[0003] In related technologies, reliability assessment methods for power semiconductor devices typically employ single stress tests to evaluate the device's degradation behavior under gate bias, on-current, or high-voltage blocking conditions. However, these three degradation behaviors are not independent but rather involve complex coupling relationships. For example, threshold voltage drift caused by gate bias stress alters the channel carrier concentration, thereby affecting the current density and self-heating temperature rise during conduction; while the self-heating effect exacerbates leakage current and trap filling during high-voltage blocking. Therefore, a single stress test cannot expose multiple stress-coupled failure modes.

[0004] Therefore, how to effectively evaluate the reliability of power semiconductor devices under various stress coupling effects has become a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0005] This application provides a method, apparatus, device, and storage medium for evaluating the reliability of power semiconductor devices, aiming to solve the technical problems in the prior art where a single stress test cannot accurately evaluate the reliability of devices under multiple stress coupling effects, and cannot distinguish between recoverable dynamic effects and irrecoverable residual degradation.

[0006] On one hand, embodiments of this application provide a method for evaluating the reliability of power semiconductor devices, including: The instantaneous parameter values ​​and stable parameter values ​​of the power semiconductor device to be evaluated are obtained for various stress stages. The instantaneous parameter values ​​are the electrical parameter values ​​measured within a set time after the end of each stress stage, and the stable parameter values ​​are the electrical parameter values ​​corresponding to the power semiconductor device when it recovers to stability after the end of each stress stage. Based on the instantaneous parameter values ​​and the stable parameter values, the parameter change values ​​corresponding to various stress stages are determined. Among them, the parameter change values ​​include instantaneous drift, residual drift, and recoverable change. Instantaneous drift represents the total deviation of electrical parameters caused by the stress in the current stage relative to the previous stage. Residual drift represents the irreversible deviation that could not be recovered after the stress in the current stage ended. Recoverable change represents the dynamic deviation that could be recovered after the stress in the current stage ended. The reliability of power semiconductor devices is evaluated based on the changes in various parameters.

[0007] On one hand, embodiments of this application provide a power semiconductor device reliability evaluation apparatus, including: The acquisition module is used to acquire the instantaneous parameter values ​​and stable parameter values ​​of the power semiconductor device to be evaluated under various stress stages. The instantaneous parameter values ​​are the electrical parameter values ​​measured within a set time after the end of each stress stage, and the stable parameter values ​​are the electrical parameter values ​​corresponding to the power semiconductor device when it recovers to stability after the end of each stress stage. The determination module is used to determine the parameter change values ​​corresponding to various stress stages based on each instantaneous parameter value and each stable parameter value. The parameter change values ​​include instantaneous drift, residual drift, and recoverable change. Instantaneous drift represents the total deviation of electrical parameters caused by the stress in the current stage relative to the previous stage. Residual drift represents the irreversible deviation that could not be recovered after the stress in the current stage ended. Recoverable change represents the dynamic deviation that could be recovered after the stress in the current stage ended. The evaluation module is used to assess the reliability of power semiconductor devices based on the changes in various parameters.

[0008] In one embodiment, the multiple stress stages include at least two of the following: gate bias stress, conduction current stress, and blocking voltage stress; the various stress stages are executed sequentially in a preset order; the acquisition module is used to perform the following operations for each of the multiple stress stages: within a set time after the end of the stress application, acquire an instantaneous parameter value corresponding to a stress; after the power semiconductor device recovers stability, acquire a stable parameter value corresponding to a stress.

[0009] In one embodiment, the acquisition module is used to: set corresponding recovery conditions based on the evaluation purpose and application scenario of the power semiconductor device; wherein, the recovery conditions include at least one of unbiased recovery, shutdown standby recovery, light load conduction recovery, or equivalent recovery in actual application; based on the recovery conditions, determine whether the power semiconductor device has reached a stable recovery state; after the power semiconductor device has recovered to a stable state, acquire a stable parameter value corresponding to stress. In one embodiment, the acquisition module is used to: acquire multiple electrical parameter change rates of a power semiconductor device under recovery conditions; wherein the electrical parameter change rate is obtained by performing electrical parameter tests on the power semiconductor device at a set time interval and based on the test results between two adjacent tests; if N consecutive electrical parameter change rates are less than a preset threshold, it is determined that the power semiconductor device has recovered to a stable state; wherein N is an integer greater than or equal to 1.

[0010] In one embodiment, the determining module is configured to: obtain an instantaneous drift amount based on the difference between instantaneous parameter values ​​corresponding to each of two adjacent stress stages in multiple stress stages; obtain a residual drift amount based on the stable parameter values ​​corresponding to each of two adjacent stress stages; and obtain a recoverable change amount based on the difference between the residual drift amount and the instantaneous drift amount.

[0011] In one embodiment, the evaluation module is used to: obtain the cumulative residual drift based on the difference between the stable parameter value corresponding to the last applied stress and the initial parameter value in multiple stress stages; wherein the initial parameter value is obtained by testing before stress is applied to the power semiconductor device; calculate the recovery ratio corresponding to each of the multiple stress stages based on the instantaneous drift and residual drift corresponding to each of the multiple stress stages; wherein the recovery ratio characterizes the recoverability of the power semiconductor device after stress is applied; and classify the reliability of the power semiconductor device based on the cumulative residual drift, and the instantaneous drift, residual drift, and recovery stabilization time corresponding to each of the multiple stress stages.

[0012] In one implementation, the evaluation module is used to: determine a high reliability level when the instantaneous drift, residual drift, cumulative residual drift, and recovery stabilization time corresponding to each of the multiple stress stages are all less than their respective preset thresholds; determine a general reliability level when the instantaneous drift corresponding to at least one stress stage exceeds the corresponding preset threshold, but the recovered residual drift, cumulative residual drift, and recovery ratio meet preset conditions; determine a risk level when the residual drift corresponding to at least one stress stage exceeds the corresponding preset threshold, or the residual drift shows an increasing trend with the advancement of each stress stage, or the cumulative residual drift exceeds the corresponding preset threshold; and determine a non-compliant level when the key electrical parameters corresponding to any stress stage exceed the failure criteria.

[0013] On one hand, embodiments of this application provide an electronic device including a processor and a memory, wherein the memory stores program code, and when the program code is executed by the processor, the processor executes any of the above-described power semiconductor device reliability assessment methods.

[0014] On the one hand, this application provides a computer-readable storage medium including program code, which, when the storage medium is running on an electronic device, is used to cause the electronic device to perform any of the above-mentioned power semiconductor device reliability assessment methods.

[0015] The beneficial effects of this application are as follows: This application provides a method, apparatus, device, and storage medium for reliability assessment of power semiconductor devices. By acquiring electrical parameters corresponding to at least two stress application stages, isolated single-stress tests are integrated into a multi-stage associated assessment process. Furthermore, each subsequent stress stage is based on the previous one, with instantaneous and stable parameter values ​​forming a progressive relationship between different stages. This allows degradation mechanisms induced by different types of stress to be exposed sequentially during the assessment of the same device, solving the technical problem that a single stress cannot assess coupled failures. In addition, instantaneous parameter values ​​are measured within a preset time after the stress ends, reflecting the total degradation effect; stable parameter values ​​are measured after stabilization, reflecting irreversible residual degradation. Substituting both into the calculation yields instantaneous drift, residual drift, and recoverable change. This differentiation mechanism decomposes the total degradation, which is often conflated in the prior art, into two dimensions: "recoverable" and "irrecoverable," avoiding the misjudgment of recoverable dynamic effects as permanent damage and the underestimation of irrecoverable degradation. Thus, by obtaining parameters at multiple stages to distinguish between total degradation and residual degradation, and then defining the recoverable change based on the difference between the two types of degradation, the technical problems of inability to assess coupled failure and confusion of degradation types are systematically solved, and the reliability of power semiconductor devices under complex stress coupling is effectively assessed. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0017] Figure 1 This is a flowchart illustrating the implementation of a reliability assessment method for power semiconductor devices in this application.

[0018] Figure 2 This is a schematic diagram of the structure of a power semiconductor device reliability evaluation device according to an embodiment of this application.

[0019] Figure 3 This is a schematic diagram of the hardware structure of an electronic device according to an embodiment of this application. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. Unless otherwise specified, the embodiments and features in the embodiments of this application can be arbitrarily combined with each other. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than that shown here.

[0021] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate so that embodiments of the invention described herein can be implemented in sequences other than those illustrated or described herein.

[0022] The design concept of the embodiments of this application is briefly introduced below: In practical applications of power semiconductor devices, they are subjected to multiple physical stresses simultaneously during operation, including gate bias stress, on-current stress, and blocking voltage stress. These three stresses can induce three degradation mechanisms: gate dielectric degradation, channel trap accumulation, and increased leakage current under high electric fields. To ensure safe operation, reliability assessment of power semiconductor devices is essential. Existing reliability assessment methods for power semiconductor devices typically employ single-stress testing to evaluate the device's degradation behavior under gate bias, on-current, or high-voltage blocking conditions. However, these three degradation behaviors are not independent but rather involve complex coupling relationships. A single stress test cannot expose the failure modes induced by multiple stress couplings. Therefore, how to effectively assess the reliability of power semiconductor devices under multiple stress couplings has become a pressing technical problem in this field.

[0023] In view of this, embodiments of this application provide a method, apparatus, device, and storage medium for evaluating the reliability of power semiconductor devices. The method for evaluating the reliability of power semiconductor devices includes: acquiring instantaneous parameter values ​​and stable parameter values ​​of the power semiconductor device to be evaluated at various stress stages; wherein the instantaneous parameter values ​​are electrical parameter values ​​measured within a set time after the end of each stress stage, and the stable parameter values ​​are electrical parameter values ​​corresponding to the power semiconductor device when it recovers stability after each stress stage; determining parameter change values ​​corresponding to each stress stage based on the instantaneous and stable parameter values; wherein the parameter change values ​​include instantaneous drift, residual drift, and recoverable change; the instantaneous drift represents the total deviation of electrical parameters caused by the stress at the current stage relative to the previous stage, the residual drift represents the irreversible deviation that could not be recovered after the stress at the current stage ends, and the recoverable change represents the dynamic deviation that can be recovered after the stress at the current stage ends; and evaluating the reliability of the power semiconductor device based on the parameter change values. In this way, by obtaining parameters in multiple stages to distinguish between total degradation and residual degradation, and then defining the recoverable change by the difference between the two types of degradation, the technical problems of inability to assess coupled failure and confusion of degradation types are systematically solved, and the reliability of power semiconductor devices under complex stress coupling is effectively assessed.

[0024] The preferred embodiments of this application are described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are for illustration and explanation only and are not intended to limit this application. Furthermore, the embodiments and features in the embodiments of this application can be combined with each other without conflict.

[0025] refer to Figure 1 The following is a flowchart illustrating the implementation of a reliability assessment method for power semiconductor devices provided in this application. The specific implementation process of this method is as follows: S101: Obtain the instantaneous and stable parameter values ​​of the power semiconductor device to be evaluated at various stress stages.

[0026] In the embodiments of this application, power semiconductor devices include silicon-based MOSFETs, silicon-based IGBTs, silicon carbide MOSFETs, gallium nitride (HEMTs), bipolar transistors, and thyristor-type devices. Among them, gallium nitride (HEMTs) belong to gallium nitride power devices and have advantages such as high breakdown electric field, high switching speed, and low conduction loss, and have been widely used in high-frequency power supplies, fast charging, motor drives, and data center power supplies. However, because gallium nitride devices are more sensitive to gate bias, high temperature, high current conduction, and high drain electric field, their reliability degradation mechanism has stronger dynamics and coupling, and reliability evaluation cannot simply follow the single stress screening method of traditional silicon power devices.

[0027] Existing single-stress screening methods typically involve separately employing tests such as High Temperature Gate Bias (HTGB), Intermittent Operating Life (IOL), and High Temperature Reverse Bias (HTRB). HTGB is primarily used to assess gate bias stability, IOL to assess conduction and thermal stability, and HTRB to assess leakage current and withstand voltage stability under high-temperature, high-voltage turn-off conditions.

[0028] However, trapped states may exist in the gate structure, barrier layer, buffer layer, and surface passivation layer of gallium nitride power devices. Under gate bias, high drain electric field, high temperature, and high current operating conditions, trap capture and release can lead to threshold voltage drift, increased dynamic on-resistance, leakage current changes, and alterations in breakdown characteristics. Furthermore, some parameter changes can recover over time after stress relief, exhibiting recoverable dynamic effects; while changes caused by gate dielectric damage, barrier layer degradation, ohmic contact deterioration, buffer layer leakage channel formation, or edge termination degradation may exhibit unrecoverable or weakly recoverable degradation.

[0029] Therefore, for gallium nitride (GaN) power devices, relying solely on whether parameters exceed limits after a single stress test is insufficient to accurately distinguish between transient trapping effects and actual structural degradation, nor can it identify weak samples that are gradually exposed under successive stresses. Existing single-item tests or simple combination tests typically rely solely on whether parameters exceed limits before and after the test, which fails to reflect the cumulative degradation and weak sample characteristics of GaN power devices under multi-stage stress. Furthermore, GaN power devices exhibit significant trapping and release effects; after stress relief, parameters such as threshold voltage, on-resistance, and leakage current may recover over time. If testing is only performed at a fixed time point or immediately after the stress ends, recoverable dynamic effects may be misjudged as permanent degradation, or potential weak samples with slow recovery and large residual drift may be overlooked.

[0030] Based on this, in this embodiment of the application, multiple stress tests are applied to the power semiconductor device to be evaluated in a preset sequence to obtain instantaneous parameter values ​​and stable parameter values. This includes: for each stress stage of the multiple stress tests, within a set time period after the end of one stress application, obtaining an instantaneous parameter value corresponding to one stress; and after the power semiconductor device recovers stability, obtaining a stable parameter value corresponding to one stress. The instantaneous parameter values ​​are electrical parameter values ​​measured within the set time period after the end of each stress stage, and the stable parameter values ​​are the electrical parameter values ​​corresponding to the power semiconductor device when it recovers stability after each stress stage. Thus, the evaluation of the power semiconductor device is achieved.

[0031] Optionally, the multiple stress stages include at least two of the following: gate bias stress, on-current stress, and blocking voltage stress; the preset order is the sequence of gate bias stress, on-current stress, and blocking voltage stress. Then, the power semiconductor device to be evaluated is subjected to multiple stress tests in the preset order, including: applying gate bias stress and on-current stress sequentially; applying on-current stress and blocking voltage stress sequentially; and applying gate bias stress, on-current stress, and blocking voltage stress sequentially.

[0032] Thus, the embodiments of this application construct a sequential combination stress test scheme corresponding to the actual operating conditions. This scheme causes the power semiconductor device to sequentially experience three physical states: gate control, conduction current, and high voltage blocking. This exposes three types of failure mechanisms: gate dielectric degradation, channel trap accumulation, and increased leakage current due to high electric field. Furthermore, it forces the three mechanisms to gradually emerge in the actual operating sequence, thereby solving the technical problem that a single stress cannot assess coupled degradation.

[0033] It should be noted that before applying stress to the power semiconductor device for the first time, initial electrical parameter tests need to be performed to obtain initial parameter values. To illustrate this scheme in more detail, it will be described in stages below.

[0034] First: Initial Electrical Parameter Testing Phase The initial electrical parameters include at least one of the following: threshold voltage, on-resistance, gate leakage current, drain leakage current, and breakdown voltage. These initial electrical parameters serve as reference values ​​for subsequent stress testing and recovery assessment, including as reference values ​​for calculating the instantaneous and stable parameter values ​​corresponding to subsequent stress tests.

[0035] Second: Apply gate bias stress and perform recovery test. In this stress stage, high-temperature gate bias stress is applied to the power semiconductor device to expose at least one of the following problems: gate structure defects, gate dielectric or barrier layer-related defects, gate-controlled channel region trap effects, gate leakage anomalies, and threshold voltage drift. Based on this, reliability risks of the power semiconductor device under high-temperature gate bias conditions can be screened.

[0036] In this embodiment, high-temperature gate bias stress is set as the first stress stage because gate control capability directly affects the stability of electrical parameters in the subsequent on-state and off-state of the power semiconductor device. By applying high-temperature gate bias stress, defects in the gate structure, gate dielectric, or barrier layer of the power semiconductor, as well as the trap effect in the gate-controlled channel region, can be preferentially exposed. If the power semiconductor device exhibits significant gate leakage abnormalities, unrecoverable threshold voltage drift, or decreased recovery capability in this stress stage, then the power semiconductor device has a higher reliability risk under subsequent on-current stress and high-voltage off-state stress.

[0037] After the high-temperature gate deflection stress ends, electrical parameter tests are performed on the device within a set time to obtain the instantaneous parameter values ​​after the stress ends.

[0038] Furthermore, the device is placed under the set recovery conditions for recovery.

[0039] Preferably, the recovery conditions include at least one of room temperature resting, zero bias recovery, high temperature non-bias recovery, or other preset recovery conditions.

[0040] Optionally, the recovery conditions may also include at least one of the following: no-bias recovery, shutdown standby recovery, light-load conduction recovery, or practical application equivalent recovery, wherein: Unbiased recovery: After the stress phase ends, the power semiconductor device is brought to an unbiased state. At this time, the gate-source voltage VGS=0 and the drain-source voltage VDS=0, and the device recovers naturally at room temperature or a set temperature.

[0041] Shutdown Standby Recovery: After the stress phase ends, the power semiconductor device is kept in a shutdown state, and standby bias conditions are applied. For example, a gate voltage that shuts down the power semiconductor device, including 0 V or a negative gate voltage, is applied to the gate; a drain bias lower than the high-temperature reverse bias stress condition is applied to the drain; simultaneously, the temperature of the power semiconductor device is maintained at a set recovery temperature, which is determined based on the standby operating temperature or recovery test conditions of the power semiconductor device, for example, it can be 25°C to 150°C; specifically, it can be 25°C, 100°C, 125°C, or 150°C. This mode is used to simulate the recovery process of the power semiconductor device in the standby state of the power system.

[0042] Light-load conduction recovery: After the stress stage ends, a low duty cycle and low current conduction pulse is applied to the power semiconductor device to put the power semiconductor device into a light-load conduction state; wherein, the conduction pulse is used to simulate the light-load working state in actual applications, and its conduction current level is lower than the overload or overcurrent stress test level.

[0043] Practical Application Equivalent Recovery: After the stress stage, an equivalent operating waveform corresponding to the target application scenario is applied to the power semiconductor device. This equivalent operating waveform includes at least one of the gate drive waveform, drain voltage waveform, and on-current waveform. For example, partial operating segments of power factor correction (PFC), LLC, totem-pole power factor correction (PFC), or other power conversion circuits can be simulated to evaluate the parameter recovery characteristics of the power semiconductor device under practical application equivalent recovery conditions.

[0044] Furthermore, within the preset recovery window, electrical parameters of the device are tested at set time intervals. These time intervals are determined based on the parameter recovery characteristics of the power semiconductor device, the number of devices under test, the testing time for a single device, and the number of test equipment channels. For example, they can range from 10 min to 24 h; specifically, they can be 10 min, 30 min, 1 h, 2 h, 4 h, 8 h, or 24 h. If the electrical parameter measurement value at the m-th sampling time tm is denoted as P(tm), and the rate of change of electrical parameters between two adjacent samplings is denoted as Dm, then Dm can be calculated using the following formula: Dm = |P(tm)-P(tm-1)| / |P0|; or: Dm = |P(tm)-P(tm-1)| / |P(tm-1)|; Where P0 is the initial parameter value before stress is applied, and m is an integer greater than or equal to 1.

[0045] In actual testing, any of the above calculation methods can be selected based on the type of the chosen key electrical parameters and the judgment requirements. Furthermore, the evaluation purpose and application scenario for the power semiconductor device should be determined, and corresponding recovery conditions should be set. For example, for automotive electronics applications, equivalent recovery based on actual application should be prioritized; for consumer power applications, bias-free recovery can be used. Further, the power semiconductor device is placed under recovery conditions for recovery, and it is determined whether the power semiconductor device has reached a stable recovery state. The determination method includes: when the rate of change of the electrical parameters obtained according to the selected calculation method is less than a set threshold, and if the rate of change of the electrical parameters calculated N consecutively is less than the preset threshold, then the power semiconductor device is determined to have recovered to a stable state; where N is an integer greater than or equal to 1. For example, for key electrical parameters such as threshold voltage, on-resistance, transconductance, and leakage current, preset thresholds can be set according to the stability requirements of the parameters themselves. For the threshold voltage change rate, the preset threshold can be 0.1% to 5%, for example, 0.1%, 1%, 3%, or 5%; for the on-resistance change rate, the preset threshold can be 0.5% to 10%, for example, 0.5%, 1%, 5%, or 10%; and for the leakage current change rate, the preset threshold can be 0.1% to 20%, for example, 0.1%, 1%, 5%, 10%, or 20%. In this case, the corresponding sampling time is determined as the recovery end time of this stage, thereby determining the recovery stabilization time of this stage. The electrical parameter change rate and the N value can be preset according to the power semiconductor device type, test parameters, test accuracy, and application reliability requirements.

[0046] Furthermore, when the electrical parameters tend to stabilize, the stable parameter values ​​after the gate bias stress has recovered are obtained.

[0047] Third: Apply conduction current stress and perform recovery test. In this stress phase, based on the state after gate bias stress recovery, conduction current stress, such as IOL stress, is applied to the power semiconductor to simulate the reliability performance of the power semiconductor device entering the conduction state after experiencing gate bias stress. The IOL stress includes periodic conduction phases and turn-off or rest phases to simulate the current stress, power stress, self-heating effects, and thermal cycling stress experienced by the device in actual operation. This stress can further expose the reliability risks of the power semiconductor device in the conduction state caused by self-heating, thermal cycling, channel trapping, increased dynamic on-resistance, ohmic contact degradation, or localized current congestion.

[0048] Preferably, the stable parameter value or its corresponding state after the gate bias stress has recovered and stabilized is used as a benchmark to evaluate whether the residual effect after the gate bias stress has recovered is further amplified under the conduction current stress in this stage.

[0049] After completing the gate bias stress recovery test, on-current stress is applied to the power semiconductor device to screen for reliability risks in the on-state operation. This on-current stress is used to expose at least one of the following issues: increased on-resistance; current path degradation; parameter drift, packaging, interconnect, or thermal stability issues caused by self-heating; and abnormal dynamic on-resistance recovery.

[0050] After the conduction current stress ends, electrical parameter tests are performed on the power semiconductor device to obtain the instantaneous parameter values ​​after the conduction current stress ends.

[0051] Furthermore, the power semiconductor device is placed under set recovery conditions for recovery, and its electrical parameters are tested at set time intervals within a preset recovery window. The recovery conditions and the method for determining the stable recovery state can be performed in accordance with the aforementioned method for corresponding stages of gate bias stress, and will not be repeated here.

[0052] After determining that the power device has entered a stable recovery state, obtain the stable parameter values ​​after the conduction current stress has recovered and stabilized.

[0053] Fourth: Apply interruption voltage stress and perform recovery test. In this stress stage, after the power semiconductor device has successively experienced gate bias stress and conduction current stress, a blocking voltage stress is applied to evaluate the high-temperature, high-voltage blocking reliability of the power semiconductor device after experiencing gate bias stress and conduction current stress. The blocking voltage stress can further expose risks such as buffer layer traps, leakage channels, edge termination defects, surface passivation defects, and breakdown capability degradation under high drain electric field conditions in the power semiconductor device. Since the blocking voltage stress is performed after the stress and recovery stages of the previous two stages, the test results not only reflect the parameter changes caused by the blocking voltage stress itself, but also whether the latent damage caused by the preceding stress will further manifest under high-temperature, high-voltage blocking conditions.

[0054] After completing the on-current stress recovery test, high-temperature reverse bias stress is applied to the power semiconductor device to screen for reliability risks under high-temperature, high-voltage shutdown conditions. High-temperature reverse bias stress is used to expose at least one of the following issues: increased drain current; decreased withstand voltage; defects in the edge electric field region; degradation related to the buffer layer or surface passivation; and failure risk under high-temperature, high-voltage shutdown conditions.

[0055] After the high-temperature reverse bias stress ends, the power semiconductor device continues to undergo electrical parameter testing to obtain the immediate parameter values ​​after the high-temperature reverse bias stress ends. Furthermore, the power semiconductor device is placed under set recovery conditions for recovery, and electrical parameter testing is performed on the device at set time intervals within a preset recovery window. The recovery conditions and the method for determining the stable recovery state can be performed in accordance with the method described above for the corresponding stage of gate bias stress, and will not be repeated here.

[0056] Furthermore, after determining that the power semiconductor device has entered a stable recovery state, the stable parameter values ​​after the high-temperature reverse bias stress has recovered and stabilized are obtained.

[0057] In summary, the electrical parameter tests at each stress stage should prioritize uniform test conditions and measurement sequence to reduce the impact of differences in test temperature, test delay, test bias, or test pulse conditions on parameter drift judgment.

[0058] S102, based on each instantaneous parameter value and each stable parameter value, determines the parameter change values ​​corresponding to various stress stages.

[0059] In this application, the parameter change values ​​include instantaneous drift, residual drift, and recoverable change; instantaneous drift represents the total deviation of electrical parameters caused by the stress in the current stage relative to the previous stage, residual drift represents the irreversible deviation that could not be recovered after the stress in the current stage ended, and recoverable change represents the dynamic deviation that could be recovered after the stress in the current stage ended.

[0060] Optionally, the specific methods for determining the parameter change value include: obtaining the instantaneous drift based on the difference between the instantaneous parameter values ​​corresponding to each of two adjacent stress stages in multiple stress stages. For example, subtracting the instantaneous parameter value corresponding to the latter stress stage from the instantaneous parameter value corresponding to the former. The residual drift is obtained based on the difference between the stable parameter values ​​corresponding to each of two adjacent stress stages. For example, subtracting the stable parameter value corresponding to the latter stress stage from the stable parameter value corresponding to the former. Further, subtracting the instantaneous drift from the residual drift yields the recoverable change.

[0061] Specifically, based on the initial parameter values, the parameter changes corresponding to the gate bias stress are calculated. The specific calculation formula is as follows: ΔPs1 = Ps1 - P0; ΔPe1 = Pe1 - P0; Pr1 = Ps1 - Pe1; Wherein, ΔPs1 is the instantaneous drift after gate bias stress, ΔPe1 is the residual drift after gate bias stress recovery, and Pr1 is the recoverable change caused by gate bias stress.

[0062] It should be noted that during each recovery test and electrical parameter sampling process, priority should be given to keeping the test temperature, test voltage, test current, test delay time and measurement equipment conditions consistent, so as to reduce the impact of junction temperature changes, test timing differences or measurement condition changes on parameter drift judgment.

[0063] In summary, by analyzing the parameter changes corresponding to gate bias stress, it is possible to determine whether a power semiconductor device is at risk of gate-related parameter drift, leakage current abnormality, or irreversible degradation.

[0064] Furthermore, using the stable parameter values ​​after the gate bias stress has recovered and stabilized as a benchmark, the parameter changes corresponding to the on-current stress are calculated. The specific calculation formula is as follows: ΔPs2 = Ps2 - Pe1; ΔPe2 = Pe2 - Pe1; Pr2 = Ps2 - Pe2; Wherein, ΔPs2 is the instantaneous drift after conduction current stress; ΔPe2 is the residual drift that remains after recovery after conduction current stress; and Pr2 is the recoverable change caused by conduction current stress.

[0065] The above-mentioned parameter changes corresponding to the conduction current stress can be used to determine whether the power semiconductor device has increased on-resistance, slow recovery, self-heating-related degradation, or irreversible damage.

[0066] Furthermore, using the stable parameter values ​​after the conduction current stress has recovered and stabilized as a benchmark, the parameter changes corresponding to the high-temperature reverse deflection stress are calculated. The specific calculation formula is as follows: ΔPs3 = Ps3 - Pe2; ΔPe3 = Pe3 - Pe2; Pr3 = Ps3 - Pe3; Wherein, ΔPs3 is the instantaneous drift after high-temperature reverse deflection stress; ΔPe3 is the residual drift that remains after recovery after high-temperature reverse deflection stress; and Pr3 is the recoverable change caused by high-temperature reverse deflection stress.

[0067] The parameter changes corresponding to high-temperature reverse stress can be used to determine whether the device has increased leakage current, decreased withstand voltage, edge electric field-related degradation, or irreversible damage.

[0068] S103 evaluates the reliability of power semiconductor devices based on the changes in various parameters.

[0069] In this embodiment of the application, after obtaining the parameter change values ​​corresponding to the gate bias stress, conduction current stress, and blocking voltage stress, the reliability of the power semiconductor device can be further evaluated based on the parameter change values, including: The cumulative residual drift is calculated based on the difference between the stability parameter value corresponding to the last stress and the initial parameter value.

[0070] Specifically, let Pb1 be the reference before gate bias stress, Pb2 be the reference before conduction current stress, and Pb3 be the reference before blocking voltage stress. Where Pb1 = P0, Pb2 = Pe1, and Pb3 = Pe2. For the i-th stress stage, where i = 1, 2, 3, the instantaneous parameter value after stress in this stage is Psi, and the stable parameter value after recovery in this stage is Pei. Then, the instantaneous drift ΔPsi, the residual drift ΔPei, and the recoverable change Pri in this stage are related as follows: ΔPsi = Psi - Pbi; ΔPei = Pei - Pbi; Pri = Psi - Pei; Wherein, ΔPsi represents the instantaneous parameter change after the stress ends in the i-th stress stage, ΔPei represents the residual parameter change that remains after the i-th stress stage has recovered, and Pri represents the amount of recoverable change caused by stress in the i-th stress stage.

[0071] Then, the cumulative residual drift ΔPe_total can be calculated using the following formula: ΔPe_total = Pe3 - P0; ΔPe_total characterizes the unrecoverable or weakly recoverable parameter changes that the device retains relative to its initial state after sequentially experiencing gate bias stress, conduction current stress, and blocking voltage stress, and the corresponding recovery process.

[0072] Furthermore, based on the instantaneous drift and residual drift corresponding to each stress, the recovery ratio corresponding to each stress is calculated, where the recovery ratio characterizes the recoverability of the power semiconductor device after stress; specifically, the recovery ratio Krec_i for each stress stage can be calculated by the following formula: Krec_i = |Psi - Pei| / |Psi - Pbi|; When |Psi - Pbi| is zero or less than the test resolution, the recovery ratio may not be calculated, or it may be normalized using a preset minimum denominator.

[0073] When only two stress stages are used, the cumulative residual drift is calculated based on the stability parameter value corresponding to the last stress, and the recovery ratio is calculated only for the stress stages that have been performed.

[0074] Furthermore, based on the cumulative residual drift, and the instantaneous drift, residual drift, and recovery stabilization time corresponding to each stress, the reliability of power semiconductor devices is classified, including: when the instantaneous drift, residual drift, cumulative residual drift, and recovery stabilization time corresponding to each of the multiple stress stages are all less than their respective preset thresholds, it is judged as a high reliability level; when the instantaneous drift corresponding to at least one stress stage in the multiple stress stages exceeds the corresponding preset threshold, but the recovered residual drift, cumulative residual drift, and recovery ratio meet preset conditions, it is judged as a general reliability level; when the residual drift corresponding to at least one stress stage in the multiple stress stages exceeds the corresponding preset threshold, or the residual drift shows an increasing trend with the advancement of each stress stage, or the cumulative residual drift exceeds the corresponding preset threshold, it is judged as a risk level; when the key electrical parameters corresponding to any stress stage in the multiple stress stages exceed the failure criteria, it is judged as a non-compliant level.

[0075] Specifically, after obtaining the instantaneous drift, residual drift, recoverable change, recovery ratio, recovery settling time, and cumulative residual drift corresponding to various stress stages, the power semiconductor devices are further screened and graded for reliability, which may include: If the instantaneous drift of a power semiconductor device after each stress stage is less than the corresponding instantaneous drift threshold, the residual drift is less than the corresponding residual drift threshold, the cumulative residual drift is less than the cumulative drift threshold, and each recovery stabilization time is less than the preset recovery time threshold, then the power semiconductor device is determined to be of high reliability level.

[0076] If a power semiconductor device exhibits significant instantaneous drift after a certain stress stage, but the residual drift after recovery is small, the cumulative residual drift does not exceed a preset cumulative drift threshold, and the recovery ratio is higher than a preset recovery ratio threshold, then the power semiconductor device is classified as either a general reliability level or a level with significant dynamic effects. This type of semiconductor device primarily exhibits recoverable dynamic parameter changes caused by trapping and releasing.

[0077] If a power semiconductor device exhibits significant residual drift after one or more stress stages have ended and recovered, or if the residual drift continuously increases with the progression of stress stages, or if the cumulative residual drift exceeds a preset risk threshold but has not yet reached the failure criterion, then the power semiconductor device is classified as risk-level. The failure criterion refers to a critical value pre-defined according to the device datasheet or industry standards that clearly defines whether the device has failed. The specific value of the failure criterion may vary depending on the application scenario. Under the risk level, power semiconductor devices may exhibit reliability risks such as gate structure degradation, enhanced channel region traps, ohmic contact degradation, enhanced buffer layer leakage channels, or decreased high-field blocking capability.

[0078] If a power semiconductor device exhibits gate leakage, drain-source leakage, threshold voltage, on-resistance, breakdown voltage, or other critical electrical parameters exceeding the failure criteria at any stress stage, or if it fails to meet the preset electrical parameter specifications after recovery, the power semiconductor device will be deemed unqualified.

[0079] In another embodiment, weights can be set according to different key electrical parameters, and the device can be classified according to the weighted scoring results; wherein, the key electrical parameters include at least one of threshold voltage, on-resistance, gate leakage current, drain-source leakage current, breakdown voltage, dynamic on-resistance, and transconductance.

[0080] It should be noted that the aforementioned instantaneous drift threshold, residual drift threshold, cumulative drift threshold, recovery ratio threshold, and recovery time threshold can be preset according to the product specifications, process design window, target application scenario, historical reliability data, or customer reliability requirements of the power semiconductor device. For power semiconductor devices of different models, voltage levels, or application scenarios, these thresholds can be the same or different. As a non-limiting example, in the initial screening implementation, the instantaneous drift threshold is set to 5%, the residual drift threshold to 3%, the cumulative drift threshold to 10%, the recovery ratio threshold to 70%, and the recovery time threshold to 12 hours. If the instantaneous drift of the key electrical parameters of the power semiconductor device after stress ends does not exceed 5%, the residual drift after recovery and stabilization does not exceed 3%, the cumulative drift after multiple stress stages does not exceed 10%, the recovery ratio is not less than 70%, and the time to reach a stable state does not exceed 12 hours, then the power semiconductor device can be determined to meet the initial screening reliability requirements and classified as a high-reliability device.

[0081] To facilitate understanding of the technical solution of this application, a detailed explanation will be given below using gallium nitride power devices as an example.

[0082] Gallium nitride power devices from the same batch were selected as the samples to be tested, including sample A, sample B, and sample C.

[0083] First, the threshold voltage Vth, on-resistance RDS, gate leakage current Igss, drain-source leakage current Idss, and breakdown voltage BV are tested at room temperature to obtain the initial parameter value P0.

[0084] Furthermore, the gallium nitride power device under test was subjected to three stages of stress testing: HTGB, IOL, and HTRB. After each stage of stress testing, instantaneous electrical parameters were tested within a set time to obtain the instantaneous parameter value Psi. Then, the gallium nitride power device under test was placed under preset recovery conditions, and multiple sampling tests were performed at set time intervals until the recovery stability judgment condition was met to obtain the stable parameter value Pei.

[0085] The test results for the same batch of gallium nitride power devices are as follows: For sample A, the immediate drift after the three-stage stress is small, the residual drift after recovery is also small, and the cumulative residual drift is lower than the preset threshold. Therefore, it is judged to be of high reliability level.

[0086] For sample B, a significant threshold voltage drift occurred immediately after the HTGB stage, but the residual drift was small after recovery, and no continuous cumulative degradation occurred in the subsequent IOL and HTRB stages. Therefore, it was judged to be of the level with significant dynamic effects but acceptable overall reliability.

[0087] For sample C, there is a certain residual drift after the HTGB stage, the residual drift of the on-resistance further increases after the IOL stage, and the leakage source leakage current increases after the HTRB stage. The cumulative residual drift exceeds the risk threshold, so it is judged to be of risk level.

[0088] For sample D, if gate leakage or drain-source leakage exceeds the failure criterion at any stage, or if the key electrical parameters still do not meet the specifications after recovery, it is judged to be unqualified.

[0089] It should be noted that, while maintaining the above preferred order, the stress conditions such as temperature, bias voltage, current, duty cycle, duration, or number of cycles at each stress stage can be adjusted according to the device rating, target application scenario, and screening stringency. The recovery test after each stress stage can use a fixed time window, a multi-sampling-point recovery monitoring method, or a condition where parameter changes tend to stabilize as the end of recovery. The recovery condition can be at least one of the following: no-bias recovery, shutdown standby recovery, light-load conduction recovery, or practical application equivalent recovery. The recovery conditions after different stress stages can be the same or different. The key electrical parameters used for screening and grading can be selected according to the device type and application requirements, including at least one of the following: threshold voltage, on-resistance, dynamic on-resistance, gate leakage current, drain-source leakage current, breakdown voltage, or transconductance. Through the above alternative settings, the instantaneous parameters after each stress stage, post-recovery parameters, residual drift, recovery amount, and recovery ratio can still be obtained, thereby achieving reliability screening and grading of gallium nitride power devices. This alternative scheme can also be applied to other power semiconductor devices.

[0090] In summary, the power semiconductor evaluation method provided in this application has the following technical advantages: (1) To address the dynamic degradation and multi-stress coupling characteristics of power semiconductor devices, a sequential combination stress screening method is adopted. Specifically, gate bias stress, conduction current stress, and blocking voltage stress are applied sequentially to the same power semiconductor device under test. This application sequence can expose gate structure defects, conduction state degradation, and reliability risks under high temperature and high pressure blocking states in sequence according to the logic of gate control, conduction operation, and high voltage blocking.

[0091] (2) A recovery test process is set up after each stage of stress ends to obtain the instantaneous parameter values ​​after stress ends and the parameter values ​​after recovery and stabilization. By comparing the instantaneous drift and the residual drift after recovery, the recoverable dynamic effects caused by trap capture or release are distinguished from the irrecoverable degradation caused by the accumulation of structural damage or defects.

[0092] (3) The state after the previous stage is restored to stability is used as the basis for stress evaluation in the next stage. Based on the residual drift, recovery capability and final cumulative residual drift in each stage, the reliability screening and classification of power semiconductor devices can be carried out. This can identify weak samples that are difficult to find by traditional single stress test or fixed time point test, and improve the accuracy of reliability screening and classification.

[0093] Based on the same inventive concept, embodiments of this application also provide a power semiconductor device reliability evaluation apparatus. For example... Figure 2 The diagram shown is a structural schematic of a power semiconductor device reliability assessment device, which may include: The acquisition module 201 is used to acquire the instantaneous parameter values ​​and stable parameter values ​​of the power semiconductor device to be evaluated under various stress stages; wherein, the instantaneous parameter values ​​are the electrical parameter values ​​measured within a set time after the end of each stress stage, and the stable parameter values ​​are the electrical parameter values ​​corresponding to the power semiconductor device when it recovers to stability after the end of each stress stage. The determination module 202 is used to determine the parameter change values ​​corresponding to various stress stages based on each instantaneous parameter value and each stable parameter value. The parameter change values ​​include instantaneous drift, residual drift, and recoverable change. The instantaneous drift represents the total deviation of electrical parameters caused by the stress in the current stage relative to the previous stage. The residual drift represents the irreversible deviation that could not be recovered after the stress in the current stage ended. The recoverable change represents the dynamic deviation that could be recovered after the stress in the current stage ended. Evaluation module 203 is used to evaluate the reliability of power semiconductor devices based on the changes in various parameters.

[0094] In one embodiment, the multiple stress stages include at least two of the following: gate bias stress, conduction current stress, and blocking voltage stress; the various stress stages are executed sequentially in a preset order; the acquisition module 201 is used to perform the following operations for each of the multiple stress stages: within a set time after the end of the stress application, acquire an instantaneous parameter value corresponding to a stress; after the power semiconductor device recovers stability, acquire a stable parameter value corresponding to a stress.

[0095] In one embodiment, the acquisition module 201 is used to: set corresponding recovery conditions based on the evaluation purpose and application scenario of the power semiconductor device; wherein, the recovery conditions include at least one of unbiased recovery, shutdown standby recovery, light load conduction recovery, or equivalent recovery in actual application; based on the recovery conditions, determine whether the power semiconductor device has reached a stable recovery state; after the power semiconductor device has recovered to a stable state, acquire a stable parameter value corresponding to stress. In one embodiment, the acquisition module 201 is used to: acquire multiple electrical parameter change rates of a power semiconductor device under recovery conditions; wherein the electrical parameter change rate is obtained by performing electrical parameter tests on the power semiconductor device at a set time interval and based on the test results between two adjacent tests; if N consecutive electrical parameter change rates are less than a preset threshold, it is determined that the power semiconductor device has recovered to a stable state; wherein N is an integer greater than or equal to 1.

[0096] In one embodiment, the determining module 202 is used to: obtain an instantaneous drift amount based on the difference between the instantaneous parameter values ​​corresponding to each of two adjacent stress stages in multiple stress stages; obtain a residual drift amount based on the stable parameter values ​​corresponding to each of two adjacent stress stages; and obtain a recoverable change amount based on the difference between the residual drift amount and the instantaneous drift amount.

[0097] In one embodiment, the evaluation module 203 is configured to: obtain the cumulative residual drift based on the difference between the stable parameter value corresponding to the last applied stress and the initial parameter value in multiple stress stages; wherein the initial parameter value is obtained by testing before stress is applied to the power semiconductor device; calculate the recovery ratio corresponding to each of the multiple stress stages based on the instantaneous drift and residual drift corresponding to each of the multiple stress stages; wherein the recovery ratio characterizes the recoverability of the power semiconductor device after stress is applied; and classify the reliability of the power semiconductor device based on the cumulative residual drift, and the instantaneous drift, residual drift, and recovery stabilization time corresponding to each of the multiple stress stages.

[0098] In one implementation, the evaluation module 203 is used to: determine a high reliability level when the instantaneous drift, residual drift, cumulative residual drift, and recovery stabilization time corresponding to each of the multiple stress stages are all less than their respective preset thresholds; determine a general reliability level when the instantaneous drift corresponding to at least one stress stage in the multiple stress stages exceeds the corresponding preset threshold, but the recovered residual drift, cumulative residual drift, and recovery ratio meet preset conditions; determine a risk level when the residual drift corresponding to at least one stress stage in the multiple stress stages exceeds the corresponding preset threshold, or the residual drift shows an increasing trend with the advancement of each stress stage, or the cumulative residual drift exceeds the corresponding preset threshold; and determine a non-compliant level when the key electrical parameters corresponding to any stress stage in the multiple stress stages exceed the failure criteria.

[0099] The technical effects achieved by the above devices can be found in the method section, and will not be repeated here.

[0100] Based on the same inventive concept, this application also provides an electronic device that can realize the function of the aforementioned power semiconductor device reliability assessment method apparatus. (Refer to...) Figure 3 Electronic devices include: At least one processor 301 and a memory 302 connected to at least one processor 301. In this embodiment, the specific connection medium between the processor 301 and the memory 302 is not limited. Figure 3 The example shown is the connection between processor 301 and memory 302 via bus 300. Bus 300 is... Figure 3 The connections between other components are indicated by thick lines and are for illustrative purposes only, not as limiting information. Bus 300 can be divided into address bus, data bus, control bus, etc., for ease of representation. Figure 3 The term 301 is represented by a single thick line, but this does not imply that there is only one bus or one type of bus. Alternatively, the processor 301 can also be called a controller; there is no restriction on the name.

[0101] In this embodiment, memory 302 stores instructions executable by at least one processor 301. By executing the instructions stored in memory 302, at least one processor 301 can perform the power semiconductor device reliability assessment method discussed above. Processor 301 can implement... Figure 2 The functions of each module in the device shown.

[0102] The processor 301 is the control center of the device. It can connect to various parts of the control device through various interfaces and lines. By running or executing instructions stored in the memory 302 and calling data stored in the memory 302, it can realize various functions of the device and process data, thereby performing overall monitoring of the device.

[0103] In one possible design, processor 301 may include one or more processing units. Processor 301 may integrate an application processor and a modem processor, wherein the application processor mainly handles the operating system, user interface, and applications, and the modem processor mainly handles wireless communication. It is understood that the modem processor may also not be integrated into processor 301. In some embodiments, processor 301 and memory 302 may be implemented on the same chip; in some embodiments, they may also be implemented on separate chips.

[0104] Processor 301 can be a general-purpose processor, such as a central processing unit (CPU), digital signal processor, application-specific integrated circuit, field-programmable gate array or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component, capable of implementing or executing the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the power semiconductor device reliability assessment method disclosed in the embodiments of this application can be directly manifested as being executed by a hardware processor, or executed by a combination of hardware and software modules within the processor.

[0105] Memory 302, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules. Memory 302 may include at least one type of storage medium, such as flash memory, hard disk, multimedia card, card-type memory, random access memory (RAM), static random access memory (SRAM), programmable read-only memory (PROM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), magnetic storage, magnetic disk, optical disk, etc. Memory 302 can be any other medium capable of carrying or storing desired program code in the form of instructions or data structures that can be accessed by a computer, but is not limited thereto. In the embodiments of this application, memory 302 may also be a circuit or any other device capable of implementing storage functions for storing program instructions and / or data.

[0106] By designing and programming the processor 301, the code corresponding to the power semiconductor device reliability assessment method described in the foregoing embodiments can be embedded into the chip, enabling the chip to execute the code during operation. Figure 1 The steps of the power semiconductor device reliability assessment method shown in the embodiment are described. How to design and program the processor 301 is a technique well-known to those skilled in the art and will not be elaborated here.

[0107] Based on the same inventive concept, embodiments of this application also provide a storage medium storing computer instructions that, when executed on a computer, cause the computer to perform the power semiconductor device reliability assessment method described above.

[0108] In some possible implementations, various aspects of the power semiconductor device reliability assessment method provided in this application can also be implemented in the form of a program product, which includes program code that, when the program product is run on a device, causes the control device to perform the steps in the power semiconductor device reliability assessment method according to the various exemplary embodiments of this application described above.

[0109] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0110] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, as well as combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0111] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0112] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0113] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A method for reliability assessment of power semiconductor devices, characterized in that, include: The instantaneous parameter values ​​and stable parameter values ​​of the power semiconductor device to be evaluated are obtained for various stress stages. The instantaneous parameter values ​​are electrical parameter values ​​measured within a set time after the end of each stress stage, and the stable parameter values ​​are electrical parameter values ​​corresponding to the power semiconductor device when it recovers to stability after the end of each stress stage. Based on each instantaneous parameter value and each stable parameter value, the parameter change values ​​corresponding to the various stress stages are determined respectively; wherein, the parameter change values ​​include instantaneous drift, residual drift, and recoverable change; the instantaneous drift represents the total deviation of electrical parameters caused by the stress in the current stage relative to the previous stage, the residual drift represents the irreversible deviation that could not be recovered after the stress in the current stage ended, and the recoverable change represents the dynamic deviation that could be recovered after the stress in the current stage ended. The reliability of the power semiconductor device is evaluated based on the changes in each parameter.

2. The method as described in claim 1, characterized in that, The multiple stress stages include at least two of the following: gate bias stress, on-current stress, and blocking voltage stress; The various stress stages are executed sequentially according to a preset order; The acquisition of instantaneous and stable parameter values ​​of the power semiconductor device to be evaluated at various stress stages includes: For each of the aforementioned stress stages, the following operations are performed respectively: Within the set time after the stress application ends, the instantaneous parameter value corresponding to the stress is obtained; After the power semiconductor device stabilizes, the stable parameter value corresponding to the stress is obtained.

3. The method as described in claim 2, characterized in that, The step of obtaining the stability parameter value corresponding to the stress after the power semiconductor device has recovered stability includes: Based on the evaluation purpose and application scenarios of the power semiconductor device, corresponding recovery conditions are set; wherein, the recovery conditions include at least one of unbiased recovery, shutdown standby recovery, light load conduction recovery, or practical application equivalent recovery; Based on the recovery conditions, it is determined whether the power semiconductor device has reached a stable recovery state; After the power semiconductor device stabilizes, the stable parameter value corresponding to the stress is obtained.

4. The method as described in claim 3, characterized in that, The step of determining whether the power semiconductor device has reached a stable recovery state based on the recovery conditions includes: The rate of change of multiple electrical parameters of the power semiconductor device under the recovery condition is obtained; wherein the rate of change of electrical parameters is obtained by performing electrical parameter tests on the power semiconductor device at set time intervals and based on the test results between two adjacent tests; If the rate of change of N consecutive electrical parameters is less than a preset threshold, the power semiconductor device is determined to have returned to a stable state; wherein, the value of N is an integer greater than or equal to 1.

5. The method as described in claim 1, characterized in that, The determination of parameter changes corresponding to the various stress stages based on each instantaneous parameter value and each stable parameter value includes: The instantaneous drift amount is obtained based on the difference between the instantaneous parameter values ​​corresponding to each of the two adjacent stress stages in the multiple stress stages. The residual drift is obtained based on the difference between the stability parameter values ​​corresponding to each of the two adjacent stress stages. The recoverable change is obtained based on the difference between the residual drift and the instantaneous drift.

6. The method as described in claim 1, characterized in that, The method of evaluating the reliability of the power semiconductor device based on the changes in various parameters includes: The cumulative residual drift is obtained based on the difference between the stable parameter value and the initial parameter value corresponding to the last applied stress in the various stress stages; wherein the initial parameter value is obtained by testing before stress is applied to the power semiconductor device. Based on the instantaneous drift and residual drift corresponding to the various stress stages, the recovery ratio corresponding to each stress stage is calculated; wherein, the recovery ratio characterizes the recoverability of the power semiconductor device after stress is applied. Based on the cumulative residual drift, and the instantaneous drift, residual drift, and recovery stabilization time corresponding to the various stress stages, the reliability of the power semiconductor device is classified.

7. The method as described in claim 5, characterized in that, The assessment of the reliability of the power semiconductor device based on the changes in various parameters includes: When the instantaneous drift, residual drift, cumulative residual drift, and recovery stabilization time corresponding to the various stress stages are all less than their respective preset thresholds, the system is judged to be of high reliability level. If the instantaneous drift amount corresponding to at least one of the multiple stress stages exceeds the corresponding preset threshold, but the recovered residual drift amount, cumulative residual drift amount, and recovery ratio meet the preset conditions, it is determined to be of general reliability level. When the residual drift amount corresponding to at least one of the multiple stress stages exceeds the corresponding preset threshold, or the residual drift amount shows an increasing trend as each stress stage progresses, or the cumulative residual drift amount exceeds the corresponding preset threshold, it is determined to be a risk level. If the critical electrical parameter corresponding to any of the multiple stress stages exceeds the failure criterion, it is determined to be of an unqualified level.

8. A reliability evaluation device for power semiconductor devices, characterized in that, include: The acquisition module is used to acquire the instantaneous parameter values ​​and stable parameter values ​​of the power semiconductor device to be evaluated under various stress stages; wherein, the instantaneous parameter values ​​are electrical parameter values ​​measured within a set time after the end of each stress stage, and the stable parameter values ​​are electrical parameter values ​​corresponding to the power semiconductor device when it recovers to stability after the end of each stress stage. The determination module determines the parameter change values ​​corresponding to the various stress stages based on each instantaneous parameter value and each stable parameter value; wherein, the parameter change values ​​include instantaneous drift, residual drift, and recoverable change; the instantaneous drift represents the total deviation of electrical parameters caused by the stress in the current stage relative to the previous stage, the residual drift represents the irreversible deviation that could not be recovered after the stress in the current stage ended, and the recoverable change represents the dynamic deviation that could be recovered after the stress in the current stage ended; An evaluation module is used to evaluate the reliability of the power semiconductor device based on the changes in various parameters.

9. An electronic device, characterized in that, It includes a processor and a memory, wherein the memory stores program code that, when executed by the processor, causes the processor to perform the method of any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, Includes program code that, when the storage medium is run on an electronic device, causes the electronic device to perform any of the methods described in claims 1 to 7.

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