Chip design violation repair method, device and storage medium

Abstract

The application discloses a chip design violation repair method, equipment and a storage medium, relates to the technical field of integrated circuit design, and the chip design violation repair method comprises the steps of obtaining a plurality of to-be-repaired violation reports of a same driving unit, gradually screening violation reasons of a chip design violation based on preset judgment conditions and the to-be-repaired violation reports, obtaining a plurality of different violation reason combinations, determining repair commands corresponding to the violation reason combinations, aggregating the repair commands to obtain a repair script, and repairing the chip design violation based on the repair script and in allusion to the violation reason combinations. Since the repair instructions are the repair instructions corresponding to the violation reason combinations, and the violation reason combinations are obtained based on the to-be-repaired violation reports, targeted repair can be performed according to the violation reasons when repair is performed, so that the use of a fixed repair method is avoided, and the efficiency of chip design violation repair is improved.

Description

Technical Field

[0001] This application relates to the field of integrated circuit design technology, and in particular to chip design violation repair methods, devices and storage media. Background Technology

[0002] With advancements in chip manufacturing processes, the number and density of components in each submodule of high-performance chip designs have increased dramatically. The extremely high clock frequencies also place increasingly stringent requirements on clock and data path design rule violations. Therefore, design rule violations on the clock and data paths need to be corrected before the final verification and validation stages of the chip.

[0003] Currently, the commonly used method for repairing chip design rule violations is to use dedicated repair software tools to select two fixed methods—cell size adjustment and buffer insertion—based on the violation report output by static timing analysis tools. However, design violations can occur for various reasons, and choosing a fixed repair method solely based on the violation report will introduce a massive number of new physical and timing violations, resulting in low efficiency in repairing chip design rule violations. Summary of the Invention

[0004] The main objective of this application is to provide a method, device, and storage medium for repairing chip design violations, aiming to solve the technical problem of low efficiency in repairing chip design rule violations.

[0005] To achieve the above objectives, this application proposes a chip design violation repair method, the method comprising: Obtain multiple reports of unrepaired violations from the same driver unit; Based on preset judgment conditions and the violation report to be repaired, the causes of chip design violations are screened step by step to obtain multiple different combinations of violation causes; Determine the repair commands corresponding to each combination of violation causes, and aggregate the repair commands to obtain a repair script; Based on the repair script, the chip design violations are repaired for each of the aforementioned combinations of violation causes. The step of progressively filtering the causes of chip design violations based on preset judgment conditions and the violation reports to be repaired, to obtain multiple different combinations of violation causes, includes: Based on the violation report to be repaired, determine whether the driving capability of the driving unit is greater than a preset driving capability threshold. Determine whether the winding from the drive unit to the load is a long wire; If it is a long line, then determine whether the winding from the drive unit to the load is an over-wound wire; Based on the number of loads, determine whether the drive unit is a large fan-out; Based on the judgment results of whether the drive capability threshold is greater than the preset threshold, whether the winding is a long winding, whether the winding is an over-winding winding, and whether the drive unit has a large fan-out, the combination of violation reasons is determined. The step of repairing the chip design violation based on the repair script for each combination of violation causes includes: If the combination of reasons for the violation includes the fact that the driving capability of the driving unit is less than the driving capability threshold, then the driving unit is replaced based on the driving capability repair command in the repair script. If the combination of violation reasons includes the long line, then the long line in the chip design violation is repaired based on the long line repair command in the repair script; If the combination of violation reasons includes the excessive routing, then the excessive routing in the chip design violation is repaired based on the excessive routing repair command in the repair script; If the combination of reasons for the violation includes the large fan-out, then the large fan-out in the chip design violation is repaired based on the large fan-out repair command in the repair script.

[0006] In one embodiment, the step of determining whether the winding from the drive unit to the load is a long wire includes: Based on the position of the drive unit and the position of the load, determine the shortest winding distance from the drive unit to the load; Obtain the Manhattan distance of the winding from the drive unit to the load to get the winding distance, and calculate the ratio of the winding distance to the shortest winding distance to get the winding ratio. If the winding ratio is greater than a preset first long line threshold, and the winding ratio is less than a preset second long line threshold, and the shortest winding distance is greater than a preset winding distance threshold, then the winding is determined to be a long line, wherein the first long line threshold is less than the second long line threshold. The step of determining whether the winding from the drive unit to the load is over-wound includes: If the winding ratio is greater than a preset over-winding threshold, then the winding is determined to be over-winding.

[0007] In one embodiment, after the step of determining whether the winding from the drive unit to the load is a long wire, the method further includes: If the winding is not the long wire, then obtain the number of winding layers of the winding in the chip; Based on the number of winding layers, it is determined whether the length of the lower winding layer is higher than a preset lower winding layer length threshold, wherein the lower winding layer is a winding with a number of winding layers lower than the preset winding layer number threshold. If the number of winding layers is lower than the winding layer threshold, then the winding is determined to be a low-layer winding; Based on the number of loads, determine whether the drive unit is a large fan-out; Based on the judgment results of whether the drive capability threshold is greater than the preset threshold, whether the winding is a long winding, whether the winding is a low-level winding, and whether the drive unit is a large fan-out, the combination of violation reasons is determined.

[0008] In one embodiment, the step of repairing the chip design violation based on the repair script for each combination of violation causes further includes: If the combination of reasons for the violation includes the low-level winding, then the low-level winding is deleted, and the winding is redone at a higher level of the chip, wherein the higher level is a metal layer in the chip where the number of winding layers is higher than a preset winding layer threshold.

[0009] In one embodiment, the step of repairing the long lines in the chip design violation based on the long line repair command in the repair script includes: Obtain the long-line winding distance of the long line; Based on the long wire winding distance and the winding distance threshold, determine the number of long wire buffers that need to be inserted; Obtain the physical location of the long line, and based on the physical location of the long line, insert the number of buffers specified by the long line buffer in the lower layer of the long line or within a preset radius of the long line.

[0010] In one embodiment, the step of repairing the excessive routing in the chip design violation based on the excessive routing repair command in the repair script includes: Obtain the over-wound distance of the over-wound wire; Based on the over-wound distance and the over-wound distance threshold, determine the number of over-wound buffers that need to be inserted; Obtain the physical location of the over-wound wire and delete the corresponding over-wound wire in the chip; Based on the physical location of the over-wound, a number of buffers of the over-wound buffer number are inserted at the intersection of the connection line between the drive unit and the load and the high layer.

[0011] In one embodiment, the step of repairing the large fan-out in the chip design violation based on the large fan-out repair command in the repair script includes: Delete the winding from the drive unit to the load that has the large fan-out; Based on the number of loads, the loads are divided into multiple load groups, wherein the difference in the number of loads in each load group is within a preset difference threshold. Obtain the load coordinates of the loads within each load group, and determine the load center point of each load group based on the load coordinates; Insert a buffer within a preset center point range for each of the load center points; Based on the buffers corresponding to each load group, the winding from the drive unit to the load is re-performed.

[0012] In addition, to achieve the above objectives, this application also proposes a chip design violation repair device, the device comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, the computer program being configured to implement the steps of the chip design violation repair method as described above.

[0013] In addition, to achieve the above objectives, this application also proposes a storage medium, which is a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, it implements the steps of the chip design violation repair method described above.

[0014] One or more technical solutions proposed in this application have at least the following technical effects: This application obtains multiple violation reports to be repaired from the same driver unit. Based on preset judgment conditions and the violation reports to be repaired, the violation causes of chip design violations are screened step by step to obtain multiple different combinations of violation causes. The repair command corresponding to each combination of violation causes is determined, the repair commands are aggregated to obtain a repair script, and the chip design violations are repaired based on the repair script for each combination of violation causes.

[0015] Compared to current chip design violation repair methods that rely on fixed approaches like cell size adjustment and buffer insertion based on violation reports, resulting in low repair efficiency, this application addresses chip design violation repair by determining repair instructions based on different violation causes and performing targeted repairs. Specifically, this application filters violation causes to obtain different combinations of causes, selects the corresponding violation reports for each combination, determines the corresponding repair instructions, and aggregates these instructions into a repair script for violation repair. The repair instructions in this application's repair script correspond to various combinations of violation causes, and these combinations are based on the selected violation reports. Therefore, chip design violation repair can be targeted based on the violation cause, avoiding the use of fixed methods and improving the efficiency of chip design violation repair. Attached Figure Description

[0016] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0017] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a flowchart illustrating an embodiment of the chip design violation repair method of this application. Figure 2 A schematic diagram of the first scenario provided for Embodiment 1 of the chip design violation repair method of this application; Figure 3 This is a schematic diagram of the second scenario provided in Embodiment 1 of the chip design violation repair method of this application; Figure 4 A schematic diagram of Manhattan distance provided for Embodiment 1 of the chip design violation repair method of this application; Figure 5 This is a schematic diagram of over-wound wires provided for Embodiment 1 of the chip design violation repair method of this application; Figure 6 This is a flowchart illustrating Embodiment 2 of the chip design violation repair method of this application. Figure 7 A schematic diagram of a chain-like large fan-out provided for Embodiment 2 of the chip design violation repair method of this application; Figure 8 This is a schematic diagram of the chain-like large fan-out repair provided in Embodiment 2 of the chip design violation repair method of this application; Figure 9 This is a schematic diagram of a large fan-out in the form of a tree branch, provided as an example of the second embodiment of the chip design violation repair method of this application. Figure 10 This is a schematic diagram of the tree-branch-shaped large fan-out repair provided in Embodiment 2 of the chip design violation repair method of this application; Figure 11 This is a schematic diagram of the device structure of the hardware operating environment involved in the chip design violation repair method in this application embodiment.

[0019] The purpose, features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0020] It should be understood that the specific embodiments described herein are merely illustrative of the technical solutions of this application and are not intended to limit this application.

[0021] To better understand the technical solution of this application, a detailed description will be provided below in conjunction with the accompanying drawings and specific implementation methods.

[0022] It should be noted that the executing entity in this embodiment can be a computing service device with data processing, network communication, and program execution functions, such as a tablet computer, personal computer, or mobile phone, or an electronic device or chip design violation repair device capable of performing the above functions. The following description uses a chip design violation repair device as an example to illustrate this embodiment and the subsequent embodiments.

[0023] With advancements in chip manufacturing processes, especially in high-performance chip design, the number and density of devices in each submodule have increased dramatically. The extremely high clock frequencies place increasingly stringent requirements on DRV (Design Rule Violation) for both clock and data paths. The current mainstream industry process involves first fixing design rule violations on the clock and data paths when the chip enters the timing signoff stage, before addressing setup / hold timing violations.

[0024] The root cause of DRV (Driving Violation) is insufficient drive capability of the driver unit. Reasons for insufficient drive capability include: excessive distance between the driver unit and the driven unit; excessive load fan-out of the driver unit; and insufficient winding layers between the driver unit and the driven unit (high resistance). The industry standard is to use dedicated timing check-in tools or timing repair tools to fix DRV violations. However, these tools use relatively simple methods to fix DRV, typically focusing on increasing the drive capability of the driver unit and inserting drive buffers. The aforementioned design rule violations may introduce a large number of new physical and timing violations, resulting in low repair efficiency.

[0025] Based on this, embodiments of this application provide a chip design violation repair method, referring to... Figure 1 , Figure 1 This is a flowchart illustrating the first embodiment of the chip design violation repair method of this application.

[0026] In this embodiment, the chip design violation repair method includes steps S10 to S40: Step S10: Obtain multiple violation reports to be repaired for the same drive unit; It should be noted that a driver unit is a logic unit in a digital circuit used to drive other logic units (i.e., load units), such as buffers or inverters. Its driving capability is usually determined by the size or model of its standard unit.

[0027] Understandably, in this embodiment, the system first reads multiple design rule violation reports with different combinations of process corners and operating modes output by the static timing analysis tool. These reports contain specific path information of the violations. The system parses and compares these reports to identify duplicate violation paths fanned out by the same drive unit and connected to the same load unit. Next, the system deduplicates these paths that appear repeatedly in different reports, merging them into a unique list of violation reports to be repaired. This eliminates redundant information and provides clear and concise input data for the subsequent repair process.

[0028] Because static timing analysis tools generate numerous duplicate violation reports under different conditions, often involving the same physical path driven by the same driver unit, directly processing this duplicate data would waste computational resources and reduce repair efficiency. Therefore, this step identifies and merges these duplicate violation reports, retaining only a unique list of paths to be repaired, thus significantly reducing the amount of data that subsequent repair processes need to handle.

[0029] Step S20: Based on preset judgment conditions and the violation report to be repaired, the causes of chip design violations are screened step by step to obtain multiple different combinations of violation causes; It should be noted that the preset judgment conditions are pre-defined quantification thresholds or rules used to determine the root cause of violations. Violation causes are the fundamental factors leading to design rule violations in chip design, such as insufficient driving capability of the driver unit, excessively long windings between the driver and the load, the use of high-resistance lower-layer metals in the windings, excessive winding, and excessive fan-out of the driver unit. The stepwise filtering system applies different judgment conditions according to a preset order and logic to classify and filter violation reports in a multi-level, branching manner. After stepwise filtering, a violation path may be determined to be caused by one or more violation causes, representing the combined result of these causes.

[0030] It should also be noted that the process of step-by-step screening of the causes of chip design violations in this embodiment can be referred to as follows. Figure 2 and Figure 3 , Figure 2 This is a flowchart when the driving capability of the driving unit is greater than that of D4. Figure 3 This is a flowchart showing that the driving capability of the driving unit is less than D4, where D4 is the level of the driving capability of the driving unit, and the driving level can be 1, 2, 4, 6, 8, etc.

[0031] Understandably, design rule violations in chip design are often caused by a variety of complex and intertwined factors. Traditional direct repair methods cannot accurately identify the root cause, easily leading to incomplete repairs or introducing new problems. Therefore, this step introduces a multi-level, pipeline-style step-by-step screening mechanism to perform multi-dimensional analysis of the physical characteristics and topology of each violation path, accurately classifying them into different combinations of violation causes. This achieves precise location of the root cause of the violation, enabling subsequent refined repair.

[0032] In one feasible implementation, the specific implementation of progressively filtering the causes of chip design violations based on preset judgment conditions and the violation reports to be repaired, to obtain multiple different combinations of violation causes, can also be: Based on the violation report to be repaired, it is determined whether the driving capability of the drive unit is greater than a preset driving capability threshold, whether the winding from the drive unit to the load is a long line, and if it is a long line, whether the winding from the drive unit to the load is an over-winding line. Based on the number of loads, it is determined whether the drive unit has a large fan-out. Based on the results of the determination of whether the driving capability is greater than the preset driving capability threshold, the determination of whether the winding is a long line, the determination of whether the winding is an over-winding line, and the determination of whether the drive unit has a large fan-out, the combination of violation causes is determined.

[0033] It should be noted that over-routing in digital circuit layout and routing is a phenomenon where, due to limited routing resources or optimization strategies, the actual routing path deviates significantly from the theoretical shortest path (Manhattan distance), resulting in a substantial increase in path length. In this embodiment, the Manhattan distance from the drive unit to the load can be referenced... Figure 4 The transition winding from the drive unit to the load can be referenced. Figure 5 .

[0034] It is understandable that design rule violations have a variety of causes, often resulting from the combined effect of multiple factors. If the judgment order is disordered or lacks logical coherence, it may lead to inaccurate or missed cause identification. Therefore, this implementation defines a strict sequential judgment logic: first, it judges the driving capability, then sequentially judges whether it is a long line, whether it is excessive winding, and whether it is large fan-out, forming a clear causal deduction chain. This orderly judgment method can avoid misjudgment and omission of violation causes, thereby ensuring the accuracy and completeness of the final determined combination of violation causes, providing a precise basis for subsequent highly targeted remediation operations.

[0035] In one feasible implementation, the specific implementation of determining whether the winding from the drive unit to the load is a long wire can also be: Based on the position of the drive unit and the position of the load, the shortest winding distance from the drive unit to the load is determined, the Manhattan distance of the winding from the drive unit to the load is obtained, the winding distance is obtained, the ratio of the winding distance to the shortest winding distance is calculated, and the winding ratio is obtained. If the winding ratio is greater than a preset first long line threshold, and the winding ratio is less than a preset second long line threshold, and the shortest winding distance is greater than a preset winding distance threshold, then the winding is determined to be a long line, wherein the first long line threshold is less than the second long line threshold. The step of determining whether the winding from the drive unit to the load is over-wound includes: If the winding ratio is greater than a preset over-winding threshold, then the winding is determined to be over-winding.

[0036] It should be noted that the shortest routing distance refers to the theoretical shortest trace distance between the drive unit and the load on the physical layout. In this embodiment, this distance is obtained by calculating the Manhattan distance. The Manhattan distance is the sum of the horizontal and vertical distances traveled between two points in the integrated circuit layout, representing the shortest wiring path length between the two points without considering routing resources. The routing distance refers to the total actual trace length between the drive unit and the load in the layout generated by the automatic placement and routing tool, which is the sum of the lengths of each metal layer trace.

[0037] The winding ratio, obtained by dividing the winding distance by the shortest winding distance, is used to quantify the degree of detour of the actual winding path relative to the theoretical shortest path. The first long-path threshold and the second long-path threshold are two preset values ​​used to define a reasonable range for the winding ratio. A winding ratio is considered long only when it falls within this range and the shortest distance is sufficiently large. The winding distance threshold is a preset distance value used to determine whether the physical distance from the drive unit to the load is sufficiently far. The over-winding threshold is a preset value greater than the second long-path threshold, used to define a higher winding ratio. When the winding ratio exceeds this threshold, it indicates that the actual winding path has severe detours, i.e., it is considered over-winding.

[0038] It is understandable that while both long traces and excessive windings manifest as long winding paths, their causes and impacts on chip design differ, requiring different repair strategies. Relying solely on experience or simple distance judgments can easily lead to confusion between the two, resulting in incorrect repair method selection. Therefore, this implementation introduces multiple thresholds (a first and a second long trace threshold, and a winding distance threshold) to accurately define long traces, and introduces a higher excessive winding threshold to separately define excessive windings. Through these steps, this embodiment clearly distinguishes between two different physical phenomena, providing a precise classification basis for subsequent treatment of long traces and excessive windings, and avoiding the misuse of repair strategies.

[0039] In one feasible implementation, the specific implementation after determining whether the winding from the drive unit to the load is a long wire can also be: If the winding is not a long wire, the number of winding layers in the chip is obtained. Based on the number of winding layers, it is determined whether the length of the lower-layer winding is higher than a preset lower-layer winding length threshold. The lower-layer winding is a winding with a number of winding layers lower than the preset number of layers threshold. If the number of winding layers is lower than the number of winding layers threshold, the winding is determined to be a lower-layer winding. Based on the load quantity of the load, it is determined whether the drive unit is a large fan-out. Based on the determination results of whether it is greater than a preset drive capability threshold, whether the winding is a long wire, whether the winding is a lower-layer winding, and whether the drive unit is a large fan-out, the combination of violation reasons is determined.

[0040] It should be noted that the winding layer number refers to the specific layer number (e.g., M1, M2, M3, etc.) of the metal layers used for metal interconnects in a digital integrated circuit layout. Different layers have different resistance values ​​and process characteristics. Low-layer windings refer to metal layers with a winding layer number lower than a preset layer number threshold. In advanced processes, low-layer metals typically have higher resistance values, which can more easily lead to a decrease in driver capability. The low-layer winding length threshold is a preset length value used to determine whether the portion of a winding composed of low-layer metals is too long. The layer number threshold is a preset metal layer number used to distinguish low-layer metals from high-layer metals. For example, in a process with metal layers M1-M13, if the layer number threshold is set to M5, then M1 to M5 are low-layer metals.

[0041] It is understandable that design rule violations in chip design, besides insufficient drive unit capability and excessive physical distance, may also stem from the impedance characteristics of the winding itself. Even if the physical distance from the drive unit to the load is not long, if the connection path is mainly composed of low-layer metal with high resistance, a high-resistance path will still be formed, resulting in relatively insufficient drive capability. Therefore, this embodiment, by introducing quantitative analysis of the winding metal layer composition in branches that are not long, can accurately identify violations caused independently by low-layer high-resistance windings or caused in combination with other reasons. Through the above steps, this embodiment distinguishes such violations from those simply caused by long distances or large fan-outs, allowing for targeted repairs of the low-layer windings in subsequent steps.

[0042] Step S30: Determine the repair command corresponding to each combination of violation causes, and aggregate the repair commands to obtain a repair script; It should be noted that a repair command refers to a specific operational instruction that can be recognized and executed by the automatic placement and routing tool to resolve a particular violation, targeting one or more specific combinations of violation causes. This includes commands such as inserting a buffer, replacing a driver unit, and rerouting. Aggregation refers to merging and organizing multiple repair commands generated for different violation paths or combinations of violation causes into a single file according to certain rules (such as execution order, module affixation, etc.). A repair script is an executable file composed of multiple repair commands. This file can be loaded and executed sequentially by the automatic placement and routing tool at once, thereby achieving automated batch repair of all design rule violations in the entire chip design.

[0043] Understandably, since this embodiment has precisely categorized each violation path into different combinations of violation causes, the analysis results still need to be transformed into specific, executable repair actions after classification. Therefore, this step directly transforms the preliminary analysis results into actual repair operations by establishing a correspondence between violation cause combinations and repair commands.

[0044] Furthermore, this embodiment aggregates all the scattered repair commands into a unified repair script, avoiding the inefficiency and error-proneness of manually writing or executing commands one by one, thereby automatically realizing the cause analysis and repair execution of violations, significantly improving the efficiency and reliability of the entire DRV repair process.

[0045] Step S40: Based on the repair script, repair the chip design violation for each combination of violation causes.

[0046] Understandably, traditional repair tools lack the ability to accurately identify the root cause of violations. They often use a single approach—inserting buffers or increasing the size of drive units—to repair all violations, which can easily lead to incomplete repairs and the introduction of new physical or timing violations. This embodiment, however, accurately identifies the root cause combination of each violation path and generates targeted repair commands. By executing these targeted repair commands, targeted repairs of different types of violations are achieved, resulting in efficient and accurate repairs and improving the efficiency of DRV repair.

[0047] In summary, this embodiment obtains multiple violation reports to be repaired from the same driver unit. Based on preset judgment conditions and the violation reports to be repaired, the causes of chip design violations are progressively screened to obtain multiple different combinations of violation causes. The repair commands corresponding to each combination of violation causes are determined, and the repair commands are aggregated to obtain a repair script. Based on the repair script, the chip design violations are repaired for each combination of violation causes.

[0048] Compared to current chip design violation repair methods that rely on fixed approaches like cell size adjustment and buffer insertion based on violation reports, resulting in low repair efficiency, this application addresses chip design violation repair by determining repair instructions based on different violation causes and performing targeted repairs. Specifically, this embodiment filters violation causes to obtain different combinations of causes, selects the corresponding violation reports for each combination, determines the corresponding repair instructions, and aggregates these instructions into a repair script for violation repair. In this embodiment, the repair instructions in the repair script correspond to various combinations of violation causes, and these combinations are obtained based on the selected violation reports. Therefore, when repairing chip design violations, targeted repairs can be performed based on the violation causes, avoiding the use of fixed methods and improving the efficiency of chip design violation repair.

[0049] Based on the first embodiment of this application, in the second embodiment of this application, the content that is the same as or similar to that in Embodiment 1 above can be referred to the above description, and will not be repeated hereafter. Based on this, please refer to... Figure 6Step S40, the chip design violation repair method further includes steps S41~S45: Step S41: If the combination of reasons for the violation includes the fact that the driving capability of the driving unit is less than the driving capability threshold, then the driving unit is replaced based on the driving capability repair command in the repair script. It should be noted that the drive capability repair command refers to a repair command generated in response to the violation of insufficient drive capability of the drive unit. Specifically, this command replaces the drive unit with insufficient drive capability with a standard unit of the same type that has stronger drive capability. Replacing the drive unit refers to the operation in the automatic placement and routing tool of replacing the original drive unit instance with another standard unit instance with greater drive capability.

[0050] Understandably, the system had previously identified insufficient driving capability of the driver unit itself as an independent violation cause through precise judgment logic, distinguishing it from other causes. Therefore, this embodiment replaces the driver unit itself for this specific cause. Compared to the traditional approach of blindly inserting buffers for all violations, the repair method in this embodiment avoids introducing additional buffers in unnecessary locations, thereby reducing potential physical location conflicts, winding resource shortages, and new timing violation issues caused by adding new units, achieving a more efficient repair effect.

[0051] Step S42: If the combination of violation reasons includes the long line, then the long line in the chip design violation is repaired based on the long line repair command in the repair script; It should be noted that the long line repair command refers to the repair command generated in response to the violation of long lines. The specific operation of this command is to insert one or more buffers at appropriate positions between the drive unit and the load, and to optimize the insertion positions to reduce the impact on surrounding paths.

[0052] In one feasible implementation, the specific implementation of repairing the long lines in the chip design violation based on the long line repair command in the repair script can also be: Obtain the long-line winding distance of the long line, determine the number of long-line buffers to be inserted based on the long-line winding distance and the winding distance threshold, obtain the long-line physical location of the long line, and insert the number of buffers of the long-line buffer in the lower layer of the long line or within the preset radius of the long line based on the long-line physical location.

[0053] It should be noted that the long-line winding distance refers to the total actual winding length between the drive unit and the load in the violation path determined to be a long line. The long-line physical location refers to the coordinate trajectory and area traversed by the actual winding between the drive unit and the load in the chip layout in the violation path determined to be a long line. The number of long-line buffers refers to the specific number of buffers that need to be inserted on this path, calculated based on the long-line winding distance and the winding distance threshold. The preset radius range refers to a pre-defined spatial range centered on the physical location of the long line, used to limit the selectable area for newly inserted buffers to ensure the tightness of the insertion position with the original winding.

[0054] Understandably, the fundamental problem of long-wire violations lies in the excessive physical distance between the drive unit and the load, making it difficult to completely resolve the drive capability attenuation issue using only a single buffer. Insufficient buffers result in incomplete repair, while excessive buffers waste space and may introduce new timing problems. Therefore, this implementation precisely determines the required number of buffers through quantitative calculations based on the actual winding distance and a preset threshold, avoiding arbitrary quantity determination.

[0055] Furthermore, this embodiment utilizes the existing winding channels and space to the maximum extent by inserting the buffer into the layer below or within a preset radius, based on the original physical location. This reduces the negative impact caused by rewinding or large-scale movement of other standard cells. Consequently, it achieves efficient and precise repair of long-line violations, minimizing the impact of the repair operation on other parts of the chip while resolving the drive capability issue.

[0056] Step S43: If the combination of violation reasons includes the excessive routing, then the excessive routing in the chip design violation is repaired based on the excessive routing repair command in the repair script; It should be noted that the over-winding repair command refers to the repair command generated in response to the violation of over-winding. The specific operations of this command include deleting the original detour, resetting the winding attribute to prioritize the use of high-layer metal, and inserting one or more buffers in the diagonal connection direction between the drive unit and the load.

[0057] In one feasible implementation, the specific implementation of repairing the excessive routing in the chip design violation based on the excessive routing repair command in the repair script can also be: Obtain the over-wound distance of the over-wound wire, determine the number of over-wound buffers to be inserted based on the over-wound distance and the winding distance threshold, obtain the physical location of the over-wound wire, delete the corresponding over-wound wire in the chip, and insert the number of buffers required by the over-wound buffer at the intersection of the connection line between the drive unit and the load and the higher layer based on the physical location of the over-wound wire.

[0058] It should be noted that the over-wound distance refers to the total actual winding length between the drive unit and the load in the violation path determined to be over-wound. The number of over-wound buffers refers to the specific number of buffers that need to be inserted on this path, calculated based on the over-wound distance and the winding distance threshold. The over-wound physical location refers to the coordinate trajectory and area traversed by the actual winding between the drive unit and the load in the chip layout in the violation path determined to be over-wound. The direction of the connecting line refers to the straight line direction from the drive unit to the load in the chip layout, that is, the diagonal direction between the two points.

[0059] It is understandable that over-winding essentially occurs when the actual routing path deviates significantly from the theoretical straight line due to detours, leading to a surge in path length and increased resistance. Simply inserting buffers along this detour does not solve the fundamental problems of excessive path length and high impedance, and may even consume more routing resources due to the insertion of multiple buffers. Therefore, this embodiment first removes the original detour, physically eliminating the root cause of excessive path length. Furthermore, this embodiment inserts buffers along the straight line between the drive unit and the load, prioritizing reconnection with higher-layer metals. This shortens the repaired path length and utilizes the low resistance of higher-layer metals to reduce signal transmission loss, thereby achieving optimal repair of over-winding violations. With the fewest number of buffers and the optimal selection of routing layers, it completely solves the problem of insufficient drive capability and minimizes the occupation of surrounding routing resources and interference with other paths.

[0060] Step S44: If the combination of violation reasons includes the low-level winding, then delete the low-level winding and re-wound it in the high layer of the chip, wherein the high layer is a metal layer in the chip where the number of winding layers is higher than a preset winding layer threshold. It should be noted that "higher layers" refers to metal layers in the chip's metal interconnect layers that have a higher number of layers than a preset threshold. Compared to lower-layer wiring, higher-layer metals typically have lower resistance and better signal transmission characteristics.

[0061] Understandably, the insufficient driving capability caused by low-level routing is fundamentally due to the excessively high resistance of the routing itself, rather than insufficient driving unit capability or excessive physical distance. If traditional methods are used to address this situation by inserting buffers or increasing the size of the driving unit, not only will the fundamental problem of high routing impedance not be solved, but additional area overhead and timing interference may also be introduced due to the addition of units. Therefore, this implementation method eliminates the root cause of the violation—high-impedance paths—by directly deleting the original low-level routing and rerouting on a low-resistance high-level metal layer. Compared to the traditional method of inserting buffers, this repair method does not introduce any new standard units, thus avoiding physical location conflicts, routing resource shortages, and new timing violations that may arise from adding units, achieving the simplest repair effect with the fewest side effects.

[0062] Step S45: If the combination of violation reasons includes the large fan-out, then the large fan-out in the chip design violation is repaired based on the large fan-out repair command in the repair script.

[0063] It should be noted that the large fanout repair command refers to the repair command generated in response to the violation of large fanout. The specific operation of this command is to divide the load into several groups according to the distribution pattern of the load (chain or tree branch), insert a buffer at a suitable center point in each group, and delete the original fanout winding network.

[0064] It should also be noted that the large fan-out in this embodiment includes chain-like and tree-branch-like structures. The chain-like large fan-out in this embodiment can be referred to... Figure 7 The repaired winding for the chain-like large fan-out in this embodiment can be referred to... Figure 8 The large fan-shaped branch pattern in this embodiment can be referred to as... Figure 9 The winding repaired for the large, branch-shaped fan-out in this embodiment can be referred to... Figure 10 .

[0065] In one feasible implementation, the specific implementation of repairing the large fan-out in the chip design violation based on the large fan-out repair command in the repair script can also be: Delete the winding from the drive unit to the load that has the large fan-out. Based on the number of loads, divide the load into multiple load groups, wherein the difference in the number of loads in each load group is within a preset difference threshold. Obtain the load coordinates of the loads in each load group. Based on the load coordinates, determine the load center point of each load group. Insert a buffer within a preset center point range for each load center point. Based on the buffers corresponding to each load group, re-wind the drive unit to the load.

[0066] It should be noted that a load group is a subset of all loads driven by the drive unit, divided according to preset rules. Each subset's loads are driven by a newly inserted buffer. The load center point is a location determined through geometric calculations (constructing a virtual polygon and calculating its centroid) based on the physical coordinates of all loads within a load group, serving as the preferred location for inserting the buffer within that group. The center point range is a preset spatial area based on the load center point, used to define the selectable locations for the newly inserted buffer, allowing for fine-tuning within a certain radius to avoid areas with existing standard units or limited winding resources. The difference threshold is a preset value used to measure the upper limit of the difference in the number of loads between the various load groups, ensuring that the number of loads in each group is basically balanced after grouping, and avoiding new fan-out imbalance problems.

[0067] It is understandable that the fundamental reason for insufficient drive capability due to large fan-out is that a single drive unit needs to drive too many loads simultaneously, and the accumulated parasitic capacitance of each load exceeds the output capability of the drive unit. Traditional tools often tend to replace the drive unit with a unit with greater drive capability when dealing with large fan-out. However, excessively large drive units can easily cause local voltage drops in high-speed digital circuits, affecting the normal operation of surrounding standard units. Therefore, this implementation method executes a large fan-out repair command and uses a split fan-out network approach, decomposing a large fan-out network into multiple smaller fan-out networks. Each sub-network is driven by a new buffer with a smaller drive capability, thus avoiding the voltage drop risks and physical violations that may arise from using oversized drive units. Furthermore, since each buffer only needs to drive a smaller load, its insertion position can be precisely optimized according to the load distribution, improving the reliability and stability of the repair effect.

[0068] In one embodiment, after the step of repairing the chip design violation based on the repair script for each combination of violation causes, the method further includes: The static timing analysis tool is invoked to re-check the design rule violations of the repaired chip design and generate a repaired violation report. The repaired violation report is compared with the generated violation report to be repaired to identify residual violation paths that were not successfully repaired and violation paths newly added during the repair process. For the residual violation path, based on the determined combination of violation causes, it is determined whether it is caused by incomplete execution of the repair operation. If so, the path is recorded as a complex violation requiring manual intervention. For the newly added violation path, its correlation with the current repair operation is analyzed to identify secondary violations caused by the repair operation. Such paths are then added back to the list to be repaired. Based on preset judgment conditions and the violation report to be repaired, the steps of progressively screening the violation causes of chip design violations to obtain multiple different combinations of violation causes are returned, and a new round of violation cause screening and repair is carried out.

[0069] It should be noted that the post-repair violation report is a design rule violation log file output by a static timing analysis tool after a round of repair operations, used to evaluate the effectiveness of this round of repair. Residual violation paths are violation paths that still exist in the post-repair violation report and were also present in the pre-repair violation report, indicating that the previous round of repair operations failed to resolve the violation. New violation paths are violation paths that newly appear in the post-repair violation report but were not present in the pre-repair violation report, indicating that the previous round of repair operations may have introduced new design rule violations. Secondary violations refer to new design rule violations indirectly caused by the execution of repair operations, such as the maximum capacitance violation caused by adding cells resulting in excessive cell density in a local area, or the maximum transition time violation caused by rewinding and occupying other path resources.

[0070] It is understandable that in the high-performance digital chip design addressed in this embodiment, the cell density is high and winding resources are scarce. Any repair operation may have a cascading effect on surrounding paths, leading to secondary violations. Traditional tools often require repeated manual checks and multiple rounds of manual iteration to achieve violation convergence, which is inefficient and prone to omissions. Therefore, this embodiment performs violation re-verification after repair and accurately distinguishes between residual violations and new violations by comparing them with the original violation report. For residual violations, it determines whether they are caused by objective obstacles at the repair execution level by combining the identified violation cause combinations, thus avoiding invalid automatic retries.

[0071] This embodiment proactively identifies the correlation between newly added violations and the repair operation, and reintegrates them into the precise screening process for violation causes. By fully utilizing the precise cause analysis results of the previous steps, it achieves further repair of design rule violations, significantly reducing the number of manual interventions and improving the thoroughness of the repair and the quality of the final chip design.

[0072] In one embodiment, the step of determining whether the violation was caused by incomplete repair operations based on the identified combination of violation causes, and recording the path as a complex violation requiring manual intervention, includes: Obtain the repair execution log of the residual violation path when performing the repair operation. The repair execution log includes at least the content of the repair command generated for the path, the actual insertion position coordinates when the automatic placement and routing tool executes the command, the actual routing layer allocation information, and the execution status feedback. The actual execution parameters in the repair execution log are compared with the preset repair target parameters, wherein the repair target parameters include the preset buffer insertion position coordinates, the preset number of buffers, the preset winding layer priority, and the preset winding path planning. If there is a deviation between the actual execution parameters and the repair target parameters, it is further determined whether the deviation is a tolerable deviation. The tolerable deviation includes the actual insertion position offset of the buffer being within a preset offset threshold due to the physical position conflict of the surrounding standard units, or the temporary degradation of the winding layer due to the short-term shortage of high-level metal winding resources, but the path electrical performance still meets the design requirements. If the deviation exceeds the tolerable deviation range, the residual violation path is determined to be an incomplete repair execution, and the path and its corresponding deviation reason are recorded in the list of complex violations requiring manual intervention.

[0073] If the actual execution parameters are completely consistent with the repair target parameters, or the deviation is within the tolerable deviation range, but the residual violation path still exists, it is determined that the combination of violation causes of the residual violation path has been misjudged or a deeper cause has been missed, and the path is marked as a complex violation that needs to be re-analyzed.

[0074] It should be noted that the repair execution log is an operation log automatically recorded by the automatic placement and routing tool when executing the repair script. It contains specific execution details of each repair command, such as the actual coordinates of the buffer placement, the actual metal layer used for routing, and the execution status code returned by the tool. The repair target parameters are the ideal execution parameters set in the repair command generated based on the combination of violation causes. These include the number of long-line buffers and their preset insertion positions, the set routing layer attributes that prioritize the use of higher-layer metals, and the calculated coordinates of the load center point.

[0075] Tolerable deviation refers to the reasonable range of differences allowed between the actual execution result of the repair operation and the preset target parameters during the actual physical implementation of high-density chip design, due to objective limitations of standard cell layout or instantaneous fluctuations in winding resources. Permanent resource insufficiency refers to a situation where, in the current layout state of the chip design, the high-layer metal winding channels in a certain area are completely occupied by other critical paths, making it impossible to use high-layer metal for winding in that area as required by the repair command, and this situation cannot be resolved by simple local adjustments.

[0076] It is understandable that the high-performance digital chip design targeted in this embodiment is characterized by extremely high cell density and extremely limited routing resources, making the repair operation highly susceptible to the influence of the physical environment during actual execution. Specifically, the calculated load center point may be occupied by a critical standard cell, preventing the automatic placement and routing tool from inserting a buffer at that location and forcing it to place the buffer in the surrounding empty area, thus reducing the repair effect; the set priority routing of high-layer metals may be automatically downgraded to using low-layer metals for routing because the high-layer metal routing channels in that area are already completely occupied by other critical timing paths, resulting in high impedance issues still existing in the repaired path.

[0077] Traditional tools, when faced with such residual violations, often simply categorize them as invalid repair strategies and attempt the same repair operation again or mark them as unrepairable. Therefore, this embodiment compares the repair execution log with the target parameters and specifically defines execution obstacle types unique to high-density chip design scenarios, such as tolerable deviations and permanent resource shortages. This avoids the system from ineffectively repeating automatic repairs of residual violations caused by objective reasons such as physical obstruction, and provides precise failure cause localization for manual intervention, significantly improving the efficiency and accuracy of manually handling complex violations.

[0078] In summary, when the system executes the repair script in this embodiment, it matches and executes corresponding refined repair operations based on the combination of violation causes for each violation path. If the combination of violation causes includes insufficient driving capability of the drive unit, the system executes a drive capability repair command to replace the current drive unit with a standard unit of the same type with stronger driving capability. If it includes long lines, the system executes a long line repair command to insert a number of buffers calculated based on the winding distance within a preset radius below or around the original winding between the drive unit and the load. If it includes excessive winding, the system executes an excessive winding repair command, first deleting the original winding with severe detours, and then inserting a corresponding number of buffers along the diagonal line connecting the drive unit and the load, preferentially using a higher metal layer. If low-level winding is included, the system deletes the original winding that is mainly based on low-level metal and reconnects the winding on the high-level metal layer; if large fan-out is included, the system executes the large fan-out repair command, deletes the original winding network, divides the load evenly into multiple load groups, inserts buffers near the geometric center point of each load group, and rewinds based on the newly inserted buffers.

[0079] This embodiment addresses five root causes: insufficient drive capability, long traces, excessive winding, low-level winding, and large fan-out. It employs five different repair methods: replacing the drive unit, inserting a buffer along the original winding position, deleting detours and then inserting a buffer at a higher level along the straight direction, migrating to a higher-level metal and rewinding, and inserting a buffer at the geometric center after uniform grouping. These steps completely change the traditional approach of simply inserting a buffer or increasing the drive unit size for all violations. This allows for targeted repair of design rule violations, effectively resolving them while minimizing the introduction of new physical violations, timing violations, or voltage drops during the repair process. This significantly improves repair efficiency and the quality and reliability of the final chip design.

[0080] It should be noted that the above examples are only for understanding this application and do not constitute a limitation on the chip design violation repair method of this application. Any simple modifications based on this technical concept are within the protection scope of this application.

[0081] This application provides a chip design violation repair device, which includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the chip design violation repair method in the above embodiment 1.

[0082] The following is for reference. Figure 11 The diagram illustrates a structural schematic suitable for implementing a chip design violation repair device according to embodiments of this application. The chip design violation repair device in embodiments of this application may include, but is not limited to, mobile terminals such as mobile phones, tablets, laptops, digital broadcast receivers, PDAs (Personal Digital Assistants), PMPs (Portable Media Players), in-vehicle terminals (e.g., in-vehicle navigation terminals), and fixed terminals such as digital TVs and desktop computers. Figure 11 The chip design violation repair device shown is merely an example and should not impose any limitations on the functionality and scope of use of the embodiments of this application.

[0083] like Figure 11As shown, the chip design violation repair device may include a processing unit 1001 (e.g., a central processing unit, a graphics processing unit, etc.) that can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 1002 or a program loaded from a storage device 1003 into a random access memory (RAM) 1004. The RAM 1004 also stores various programs and data required for the operation of the chip design violation repair device. The processing unit 1001, ROM 1002, and RAM 1004 are interconnected via a bus 1005. An input / output (I / O) interface 1006 is also connected to the bus. Typically, the following systems can be connected to the I / O interface 1006: input devices 1007 including, for example, a touchscreen, touchpad, keyboard, mouse, image sensor, microphone, accelerometer, gyroscope, etc.; output devices 1008 including, for example, a liquid crystal display (LCD), speaker, vibrator, etc.; storage devices 1003 including, for example, magnetic tape, hard disk, etc.; and communication devices 1009. Communication device 1009 allows the chip design violation repair device to communicate wirelessly or wiredly with other devices to exchange data. While the figure shows chip design violation repair devices with various systems, it should be understood that implementation or possession of all the systems shown is not required. More or fewer systems may be implemented alternatively.

[0084] Specifically, according to the embodiments disclosed in this application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments disclosed in this application include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device, or installed from storage device 1003, or installed from ROM 1002. When the computer program is executed by processing device 1001, it performs the functions defined in the methods of the embodiments disclosed in this application.

[0085] The chip design violation repair device provided in this application, employing the chip design violation repair method in the above embodiments, can solve the technical problem of low repair efficiency for chip design rule violations. Compared with the prior art, the beneficial effects of the chip design violation repair device provided in this application are the same as those of the chip design violation repair method provided in the above embodiments, and other technical features in this chip design violation repair device are the same as those disclosed in the previous embodiment method, and will not be repeated here.

[0086] It should be understood that the various parts disclosed in this application can be implemented using hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples.

[0087] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0088] This application provides a computer-readable storage medium having computer-readable program instructions (i.e., a computer program) stored thereon, the computer-readable program instructions being used to execute the chip design violation repair method in the above embodiments.

[0089] The computer-readable storage medium provided in this application may be, for example, a USB flash drive, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to: electrical connections having one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this embodiment, the computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, system, or device. The program code contained on the computer-readable storage medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (Radio Frequency), etc., or any suitable combination thereof.

[0090] The aforementioned computer-readable storage medium may be included in a chip design violation repair device; or it may exist independently and not assembled into a chip design violation repair device.

[0091] The aforementioned computer-readable storage medium carries one or more programs, which, when executed by the chip design fault repair device, cause the chip design fault repair device to perform the aforementioned chip design fault repair method.

[0092] Computer program code for performing the operations of this application can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a Local Area Network (LAN) or a Wide Area Network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0093] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0094] The modules described in the embodiments of this application can be implemented in software or hardware. The names of the modules do not necessarily limit the functionality of the unit itself.

[0095] The readable storage medium provided in this application is a computer-readable storage medium that stores computer-readable program instructions (i.e., a computer program) for executing the above-described chip design violation repair method, thereby solving the technical problem of low repair efficiency for chip design rule violations. Compared with the prior art, the beneficial effects of the computer-readable storage medium provided in this application are the same as those of the chip design violation repair method provided in the above embodiments, and will not be repeated here.

[0096] The above description is only a part of the embodiments of this application and does not limit the scope of protection of this application. All equivalent structural transformations made under the technical concept of this application and using the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included in the patent protection scope of this application.

Claims

1. A method for repairing chip design violations, characterized in that, The method includes: Obtain multiple reports of unrepaired violations from the same driver unit; Based on preset judgment conditions and the violation report to be repaired, the causes of chip design violations are screened step by step to obtain multiple different combinations of violation causes; Determine the repair commands corresponding to each combination of violation causes, and aggregate the repair commands to obtain a repair script; Based on the repair script, the chip design violations are repaired for each of the aforementioned combinations of violation causes. The step of progressively filtering the causes of chip design violations based on preset judgment conditions and the violation reports to be repaired, to obtain multiple different combinations of violation causes, includes: Based on the violation report to be repaired, determine whether the driving capability of the driving unit is greater than a preset driving capability threshold. Determine whether the winding from the drive unit to the load is a long wire; If it is a long line, then determine whether the winding from the drive unit to the load is an over-wound wire; Based on the number of loads, determine whether the drive unit is a large fan-out; Based on the judgment results of whether the drive capability threshold is greater than the preset threshold, whether the winding is a long winding, whether the winding is an over-winding winding, and whether the drive unit has a large fan-out, the combination of violation reasons is determined. The step of repairing the chip design violation based on the repair script for each combination of violation causes includes: If the combination of reasons for the violation includes the fact that the driving capability of the driving unit is less than the driving capability threshold, then the driving unit is replaced based on the driving capability repair command in the repair script. If the combination of violation reasons includes the long line, then the long line in the chip design violation is repaired based on the long line repair command in the repair script; If the combination of violation reasons includes the excessive routing, then the excessive routing in the chip design violation is repaired based on the excessive routing repair command in the repair script; If the combination of reasons for the violation includes the large fan-out, then the large fan-out in the chip design violation is repaired based on the large fan-out repair command in the repair script.

2. The method as described in claim 1, characterized in that, The step of determining whether the winding from the drive unit to the load is a long wire includes: Based on the position of the drive unit and the position of the load, determine the shortest winding distance from the drive unit to the load; Obtain the Manhattan distance of the winding from the drive unit to the load to get the winding distance, and calculate the ratio of the winding distance to the shortest winding distance to get the winding ratio. If the winding ratio is greater than a preset first long line threshold, and the winding ratio is less than a preset second long line threshold, and the shortest winding distance is greater than a preset winding distance threshold, then the winding is determined to be a long line, wherein the first long line threshold is less than the second long line threshold. The step of determining whether the winding from the drive unit to the load is over-wound includes: If the winding ratio is greater than a preset over-winding threshold, then the winding is determined to be over-winding.

3. The method as described in claim 1, characterized in that, After the step of determining whether the winding from the drive unit to the load is a long wire, the method further includes: If the winding is not the long wire, then obtain the number of winding layers of the winding in the chip; Based on the number of winding layers, it is determined whether the length of the lower winding layer is higher than a preset lower winding layer length threshold, wherein the lower winding layer is a winding with a number of winding layers lower than the preset winding layer number threshold. If the number of winding layers is lower than the winding layer threshold, then the winding is determined to be a low-layer winding; Based on the number of loads, determine whether the drive unit is a large fan-out; Based on the judgment results of whether the drive capability threshold is greater than the preset threshold, whether the winding is a long winding, whether the winding is a low-level winding, and whether the drive unit is a large fan-out, the combination of violation reasons is determined.

4. The method as described in claim 3, characterized in that, The step of repairing the chip design violation based on the repair script for each combination of violation causes further includes: If the combination of reasons for the violation includes the low-level winding, then the low-level winding is deleted, and the winding is redone at a higher level of the chip, wherein the higher level is a metal layer in the chip where the number of winding layers is higher than a preset winding layer threshold.

5. The method as described in claim 4, characterized in that, The step of repairing the long lines in the chip design violation based on the long line repair command in the repair script includes: Obtain the long-line winding distance of the long line; Based on the long wire winding distance and the winding distance threshold, determine the number of long wire buffers that need to be inserted; Obtain the physical location of the long line, and based on the physical location of the long line, insert the number of buffers specified by the long line buffer in the lower layer of the long line or within a preset radius of the long line.

6. The method as described in claim 4, characterized in that, The step of repairing the excessive routing in the chip design violation based on the excessive routing repair command in the repair script includes: Obtain the over-wound distance of the over-wound wire; Based on the over-wound distance and the over-wound distance threshold, determine the number of over-wound buffers that need to be inserted; Obtain the physical location of the over-wound wire and delete the corresponding over-wound wire in the chip; Based on the physical location of the over-wound, a number of buffers of the over-wound buffer number are inserted at the intersection of the connection line between the drive unit and the load and the high layer.

7. The method as described in claim 4, characterized in that, The steps for repairing the large fan-out in the chip design violation based on the large fan-out repair command in the repair script include: Delete the winding from the drive unit to the load that has the large fan-out; Based on the number of loads, the loads are divided into multiple load groups, wherein the difference in the number of loads in each load group is within a preset difference threshold. Obtain the load coordinates of the loads within each load group, and determine the load center point of each load group based on the load coordinates; Insert a buffer within a preset center point range for each of the load center points; Based on the buffers corresponding to each load group, the winding from the drive unit to the load is re-performed.

8. A chip design violation repair device, characterized in that, The device includes: a memory, a processor, and a computer program stored in the memory and executable on the processor, the computer program being configured to implement the steps of the chip design violation repair method as claimed in any one of claims 1 to 7.

9. A storage medium, characterized in that, The storage medium is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by a processor, it implements the steps of the chip design violation repair method as described in any one of claims 1 to 7.

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