Artificial Intelligence-Based Integrated Circuit Design and Optimization End-to-End Management Method and System

Abstract

This invention proposes a method and system for managing the entire integrated circuit design and optimization process based on artificial intelligence. It belongs to the interdisciplinary fields of Electronic Design Automation (EDA), Artificial Intelligence, and Advanced Manufacturing. The method includes: decoupling the stages of the entire integrated circuit design process and building a multi-agent collaborative architecture to generate a multi-stage agent collaborative network; constructing a cross-stage knowledge graph based on the multi-stage agent collaborative network to form a continuous knowledge representation system; and significantly improving the efficiency and quality of integrated circuit design by constructing a multi-agent collaborative and physical information constraint system, combined with cross-stage knowledge distillation and self-evolving digital twins.

Description

Technical Field

[0001] This invention proposes a method and system for managing the entire process of integrated circuit design and optimization based on artificial intelligence, belonging to the interdisciplinary fields of electronic design automation (EDA), artificial intelligence and advanced manufacturing. Background Technology

[0002] In the field of integrated circuit design, traditional management techniques face numerous severe challenges. Currently, the architecture, RTL, and physical implementation stages of integrated circuit design are strictly separated by different toolchains, forming rigid stage barriers. Front-end designers find it difficult to predict bottlenecks in the back-end physical implementation, leading to frequent rework during the design process, a significant increase in design iterations, longer development cycles, and higher costs.

[0003] Meanwhile, PDK rules exist as discrete check items, making it impossible to integrate them into the continuous optimization process of the early design, leaving physical constraints in a black-box state. This makes it difficult for designers to fully consider physical rule limitations in the early stages, only to discover problems later, affecting design quality and efficiency.

[0004] In the manufacturing process, post-silicon issues such as yield losses suffer from significant feedback delays, often taking weeks to reach the design end. This prevents real-time guidance for current design iterations and causes missed opportunities for optimal optimization. Furthermore, the tuning experience of backend engineers is difficult to quantify and reuse in new projects, meaning each design is almost "starting from scratch," hindering the effective accumulation of knowledge.

[0005] Although published patents contain isolated functions such as "AI-assisted layout", "machine learning timing prediction" and "yield analysis", no technology has yet deeply integrated multi-agent collaboration, physical information neural networks, cross-stage knowledge distillation, real-time manufacturing feedback, and self-evolving digital twins to build a full-process intelligent management architecture with a cognitive closed loop of "design-manufacturing-verification". The field of integrated circuit design urgently needs innovative breakthroughs. Summary of the Invention

[0006] This invention provides a method and system for managing the entire process of integrated circuit design and optimization based on artificial intelligence, in order to solve the problems mentioned in the background art above: The present invention proposes an artificial intelligence-based method for the full-process management of integrated circuit design and optimization, the method comprising: S1. Decouple the entire integrated circuit design process into stages and build a multi-agent collaborative architecture to generate a multi-stage agent collaborative network; construct a cross-stage knowledge graph based on the multi-stage agent collaborative network to form a continuous knowledge representation system. S2. Based on the continuous knowledge representation system, perform physical information neural network modeling, transform PDK rules into differentiable continuous constraint functions, and generate physical constraint embedding models; use physical constraint embedding models to perform real-time physical rule checks and optimizations on early designs, and generate physical compliance optimization data; S3. Based on physical compliance optimization data, perform multi-agent collaborative optimization iteration to generate cross-stage collaborative optimization data; drive the construction of a self-evolving digital twin system through cross-stage collaborative optimization data to form a digital twin. S4. Real-time simulation of the manufacturing process is performed using a self-evolving digital twin to generate post-silicon problem prediction data; manufacturing feedback correction parameters are generated through closed-loop calibration of the post-silicon problem prediction data and actual manufacturing feedback; the digital twin is dynamically updated based on the manufacturing feedback correction parameters to form a closed-loop evolving digital twin management architecture. S5. Output design optimization guidance strategies based on the closed-loop evolution digital twin management architecture, and generate full-process optimization decision data; drive integrated circuit design iteration through full-process optimization decision data to generate final design version data; evaluate the first-version silicon success rate of the final design version data and generate first-version silicon success rate prediction indicators.

[0007] The artificial intelligence-based integrated circuit design and optimization end-to-end management system proposed in this invention includes: One or more processors; Memory, used to store one or more programs; Wherein, when the one or more programs are executed by the one or more processors, the one or more processors are made to implement the method described in any one of the above.

[0008] The beneficial effects of this invention are as follows: By constructing a multi-agent collaborative and physical information constraint system, combined with cross-stage knowledge distillation and self-evolving digital twins, this method significantly improves the efficiency and quality of integrated circuit design; it reduces the number of design iterations, eliminating the need for designers to repeatedly adjust between stages, saving significant time and manpower costs. Simultaneously, it enhances the integration of physical rules in the early stages of design, ensuring that the design meets physical requirements from the outset, reducing modifications required later due to unmet physical constraints. It reduces the delay in post-silicon issue feedback, enabling real-time guidance for design iterations and preventing missed optimal optimization opportunities due to untimely feedback. It avoids starting "from scratch" for every design, allowing for the quantification and reuse of backend engineers' optimization experience, and effective knowledge accumulation. It achieves a cognitive closed loop of design, manufacturing, and verification, improving the first-print silicon success rate, and making the design process more intelligent and collaborative, providing a new generation of full-process intelligent management core technology for advanced process integrated circuit design, significantly enhancing industry competitiveness. Attached Figure Description

[0009] Figure 1 This is a diagram illustrating the steps of the method described in this invention. Detailed Implementation

[0010] The preferred embodiments of the present invention will be described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are for illustration and explanation only and are not intended to limit the present invention.

[0011] Example 1 One embodiment of the present invention, such as Figure 1 As shown, an artificial intelligence-based integrated circuit design and optimization end-to-end management method includes: S1. Decouple the entire integrated circuit design process into stages and build a multi-agent collaborative architecture to generate a multi-stage agent collaborative network; construct a cross-stage knowledge graph based on the multi-stage agent collaborative network to form a continuous knowledge representation system, which covers stages such as architecture, RTL, and physical implementation. S2. Based on the continuous knowledge representation system, perform physical information neural network modeling, transform PDK rules into differentiable continuous constraint functions, and generate physical constraint embedding models; use physical constraint embedding models to perform real-time physical rule checks and optimizations on early designs, and generate physical compliance optimization data; S3. Based on physical compliance optimization data, perform multi-agent collaborative optimization iteration to generate cross-stage collaborative optimization data; drive the construction of a self-evolving digital twin system through cross-stage collaborative optimization data to form a digital twin, which covers the entire design, manufacturing and verification cycle; S4. Real-time simulation of the manufacturing process is performed using a self-evolving digital twin to generate post-silicon problem prediction data; manufacturing feedback correction parameters are generated through closed-loop calibration of the post-silicon problem prediction data and actual manufacturing feedback; the digital twin is dynamically updated based on the manufacturing feedback correction parameters to form a closed-loop evolving digital twin management architecture. S5. Output design optimization guidance strategies based on the closed-loop evolution digital twin management architecture, and generate full-process optimization decision data; drive integrated circuit design iteration through full-process optimization decision data to generate final design version data; evaluate the first-version silicon success rate of the final design version data and generate first-version silicon success rate prediction indicators.

[0012] The working principle and effects of the above technical solution are as follows: By decoupling the stages of the entire integrated circuit design process and building a multi-agent collaborative architecture, the efficiency of the entire process management and the synergy between each stage are improved, reducing data disconnect between stages and avoiding inefficiencies caused by design gaps. By transforming PDK rules into differentiable continuous constraint functions, the compliance of early designs is improved, the rework costs caused by non-compliant designs are reduced, and the difficulty of later adjustments is avoided. Through multi-agent collaborative optimization and digital twin simulation, the accuracy of design optimization is enhanced, the incidence of post-silicon issues is reduced, and irreparable losses during manufacturing are avoided. Through a closed-loop evolutionary digital twin management architecture, the design solution can be continuously iterated and improved, the first-print silicon success rate can be increased, and R&D investment can be reduced, making the design process more efficient and balancing performance and manufacturing feasibility.

[0013] In one embodiment of the present invention, S1 includes: S11. Decouple the entire integrated circuit design process into stages, break down the execution content and flow relationship of each design stage, and generate process stage decomposition results; S12. Based on the process phase decomposition results, build a multi-agent collaborative architecture, assign the design control responsibilities of each agent, and generate agent responsibility allocation results. S13. Construct a multi-stage intelligent agent collaborative network based on the results of intelligent agent responsibility allocation, and open up data transmission and interaction channels between each stage. S14. Relying on the multi-stage intelligent agent collaborative network, collect design data and related information at each stage to complete the collection and sorting of cross-stage knowledge elements; S15. Construct a cross-stage knowledge graph by collecting and organizing knowledge elements to form a continuous knowledge representation system, which covers stages such as architecture, RTL, and physical implementation.

[0014] The working principle and effects of the above technical solution are as follows: By decoupling the entire integrated circuit design process into stages, the execution content and flow relationships of each stage are broken down, improving the clarity of the process breakdown, reducing the overlap and confusion of responsibilities between stages, and avoiding internal friction caused by process ambiguity. By combining the process breakdown results to build a multi-agent collaborative architecture and assign control responsibilities, the pertinence of each agent's work is enhanced, reducing efficiency losses caused by unclear responsibilities and avoiding work shirking or duplication. By constructing a multi-stage agent collaborative network, data transmission and interaction channels between stages are opened up, improving the efficiency of design data flow and reducing data bottlenecks and disconnections between stages. By collecting design data from each stage, aggregating knowledge elements, and constructing a cross-stage knowledge graph, a complete and continuous knowledge representation system can be formed, improving knowledge reuse rate, avoiding redundant design exploration caused by knowledge dispersion, and making the connection between design stages smoother.

[0015] In one embodiment of the present invention, S2 includes: S21. Extract relevant physical design constraints and process parameters based on the continuous knowledge representation system to generate basic information on physical design constraints; S22. Based on the basic information of physical design constraints, conduct physical information neural network modeling and build a network computing framework that adapts to the design scenario. S23. Transform the PDK rules into differentiable continuous constraint functions to achieve deep integration of the rules and the neural network model; S24. Integrate continuous constraint functions with neural network computing frameworks to generate physical constraint embedding models that can be embedded in the design process; S25. By embedding physical constraints into the model, perform real-time physical rule checks and parameter adjustments on early design schemes to generate physical compliance optimization data.

[0016] The working principle and effects of the above technical solution are as follows: By extracting physical design constraints and process parameters based on a continuous knowledge representation system, the completeness and accuracy of physical constraint information are improved, reducing constraint omissions or parameter deviations and avoiding directional errors in subsequent modeling. By building a physical information neural network computation framework based on constraint foundation information, the adaptability of the network to the actual scenario is enhanced, reducing the probability of modeling deviating from actual needs. By transforming PDK rules into differentiable continuous constraint functions and deeply integrating them with the neural network, the fluency of rule embedding is improved, reducing conflicts between rules and model adaptation. By generating a physical constraint embedding model, early design schemes can be checked and parameters adjusted in real time. This not only quickly identifies violations but also generates compliance optimization data, reducing rework costs later and avoiding manufacturing risks caused by early non-compliant designs, making the design process more efficient and more aligned with process requirements.

[0017] In one embodiment of the present invention, step S23 includes: The PDK rules comprehensively analyze various constraints, including process limitations, geometric specifications, and electrical performance requirements. Each rule is broken down into its corresponding constraint dimensions, numerical thresholds, and execution standards, generating a PDK rule breakdown list to ensure that no constraint items are omitted or redundant. The relationships between the constraints are also marked. For each discrete constraint in the decomposition list, a nonlinear fitting and continuous transformation algorithm is adopted. Combined with the actual scenario requirements of integrated circuit physical design, the discrete rule requirements are transformed into continuously differentiable mathematical functions. At the same time, the core constraint logic of the constraint itself is retained, and the constraint deviation that occurs during the transformation process is avoided, generating a preliminary set of continuous constraint functions. The initial set of continuous constraint functions is normalized and standardized to unify the numerical range, calculation unit and precision standards of different constraint dimensions, eliminate the calculation deviation between different constraint functions, and optimize the differentiability of the functions to ensure smooth calculation transmission when fused with the neural network model, thereby generating a standardized set of continuous constraint functions. Standardized continuous constraint functions are integrated one by one into the established neural network computing framework, corresponding to the hidden layer computing nodes of the neural network. The adaptation logic between constraint functions and network nodes is optimized, the matching degree between function parameters and network weights is adjusted, adaptation conflicts are eliminated through multiple rounds of calculation and debugging, the collaborative computing effect of constraint functions and neural network models is verified, and finally the deep integration of PDK rules and neural network models is completed.

[0018] The working principle and effects of the above technical solution are as follows: By comprehensively analyzing various constraints of PDK rules, decomposing constraint dimensions, numerical thresholds, and execution standards, and generating a decomposition list, the comprehensiveness and standardization of PDK rule decomposition are improved, reducing the omission or redundancy of constraint items and avoiding deviations in subsequent transformations due to incomplete rule decomposition. By employing nonlinear fitting and continuous transformation algorithms, discrete constraints are transformed into continuously differentiable mathematical functions, retaining core constraint logic, reducing constraint deviations during the transformation process, and preventing the function transformation from becoming disconnected from the actual rules. By normalizing and standardizing the initial continuous constraint functions, the calculation standards are unified, calculation deviations are eliminated, function differentiability is enhanced, and computational stuttering is avoided during subsequent fusion with neural networks. By integrating the standardized constraint functions into the neural network and optimizing the adaptation logic, deep fusion is achieved, ensuring collaborative computation effects, reducing adaptation conflicts, lowering debugging costs, and making the combination of PDK rules and neural networks smoother, providing reliable support for subsequent design inspection and optimization.

[0019] In one embodiment of the present invention, S24 includes: Extract the continuous constraint function that has been fused in S23 and the neural network computing framework built in S22, summarize the core computing logic and parameter configuration of the two, and generate the fused basic dataset. Perform compatibility checks on the fusion base dataset, identify parameter conflicts and logical contradictions between continuous constraint functions and neural network computing frameworks, and generate compatibility check results. Based on the compatibility verification results, optimize the fusion logic, adjust the calculation parameters of the access node and network framework of the constraint function, achieve seamless connection between the two, and generate an optimized fusion system. The optimized fusion system is subjected to performance testing to verify its computational efficiency and constraint adaptation capability in physical design scenarios, and a performance test report is generated.

[0020] By fine-tuning the fusion system parameters based on the performance test report, solidifying the fusion logic, and generating a physical constraint embedding model that can be directly embedded into the entire integrated circuit design process.

[0021] The working principle and effects of the above technical solution are as follows: By extracting the core computational logic and parameter configuration of continuous constraint functions and neural network computation framework, the integrity of the data in the early stage of fusion is improved, reducing fusion deviation caused by missing key information and avoiding failure of subsequent model construction due to incomplete basic data. By conducting compatibility verification on the fusion basic dataset, parameter conflicts and logical contradictions are investigated, reducing the internal adaptation risk of the system and avoiding computational anomalies caused by parameter contradictions. By optimizing the fusion logic and access nodes based on the verification results, seamless connection between constraint functions and network framework is achieved, enhancing overall operational stability and reducing computational lag caused by poor connection. By conducting performance testing and fine-tuning parameters on the fusion system, the fusion logic is solidified, ensuring both the computational efficiency and constraint adaptability of the model in real-world scenarios, and generating a physical constraint embedding model that can be directly embedded into the process, avoiding repeated debugging and improving the overall process efficiency.

[0022] In one embodiment of the present invention, S3 includes: S31. Based on physical compliance optimization data, formulate optimization goals and execution paths for each intelligent agent, and generate a multi-agent collaborative optimization scheme; S32. Conduct cross-stage parallel iterative calculations according to the multi-agent collaborative optimization scheme to complete the collaborative optimization calculations of each design stage; S33. Summarize the optimization results of each stage after iterative calculations and generate cross-stage collaborative optimization data that is adapted to the entire process; S34. Utilize cross-stage collaborative optimization data to build a virtual design mapping environment and construct a basic operating platform for digital twins; S35. Inject design, manufacturing, and verification lifecycle data into a virtual mapping environment to form a digital twin covering the entire process.

[0023] The working principle and effects of the above technical solution are as follows: By optimizing data based on physical compliance, the optimization goals and execution paths of each intelligent agent are formulated, improving the pertinence of multi-agent collaborative optimization, reducing the blindness of intelligent agent operations, and avoiding the optimization direction from deviating from actual needs. By carrying out cross-stage parallel iterative calculations according to the collaborative optimization scheme, the optimization efficiency of each design stage is improved, the iteration cycle is shortened, and the process delays caused by single-stage serial calculations are avoided. By summarizing the iteration results of each stage to generate cross-stage collaborative optimization data, the integrity and adaptability of the data are enhanced, and the problem of data disconnect between stages is reduced. By using collaborative optimization data to build a virtual mapping environment and construct a digital twin basic carrier, the difficulty of building a virtual environment is reduced, and the disconnect between the environment and the actual process is avoided. By injecting full-cycle data into the virtual environment to form a digital twin, it is possible to realize the virtual mapping of the entire process of design, manufacturing, and verification, and to predict potential problems in the process in advance, reducing errors in actual operation and making the whole process control more efficient and accurate.

[0024] In one embodiment of the present invention, step S31 includes: Read physical compliance optimization data, extract parameter deviations and performance improvement directions, and generate intelligent agent optimization guidance data; By combining the agent optimization guidance data, the corresponding optimization tasks of each agent are allocated, and agent task allocation data is generated.

[0025] Based on the task allocation data of the intelligent agents, the operation trajectory and interaction mode of each intelligent agent are planned, and the execution path data of the intelligent agents is generated. By integrating agent task allocation data and execution path data, a complete multi-agent collaborative optimization scheme is formed.

[0026] The working principle and effects of the above technical solution are as follows: By reading physical compliance optimization data, parameter deviations and performance improvement directions are extracted to generate optimization guidance data, improving the targeting of intelligent agent optimization, reducing the blindness of optimization direction, and preventing intelligent agent operations from deviating from core requirements. By combining the optimization guidance data to allocate optimization tasks to each intelligent agent, the work focus of each intelligent agent is clarified, reducing uneven task allocation or repetitive work, and avoiding waste of manpower and time. By planning the operation trajectory and interaction mode of intelligent agents according to task allocation data, the orderliness of intelligent agent operations is enhanced, reducing problems of chaotic operation or poor interaction, and avoiding affecting optimization efficiency. By integrating task allocation and execution path data to form a collaborative optimization scheme, the integrity and feasibility of the scheme are guaranteed, and the collaboration between intelligent agents is smoother, reducing internal friction in collaboration, improving overall optimization efficiency, and avoiding optimization errors caused by imperfect schemes.

[0027] In one embodiment of the present invention, S32 includes: Load the multi-agent collaborative optimization scheme, break down the computation tasks of each stage, and generate a list of parallel computation tasks; According to the parallel computing task list, each agent's independent computing module is launched to carry out phased parameter iterative calculation and generate phased iterative calculation data. Transmit iterative computation data during the transmission phase to adjacent design phases, complete the interaction of computation results between intelligent agents, and generate cross-phase collaborative computation data; Based on the continuous updating and iterative calculation conditions of cross-stage linkage calculation data, multiple rounds of cyclic calculations are promoted to generate complete iterative calculation results; Verify the consistency and rationality of the complete iterative calculation results, and complete the collaborative optimization calculation of each design stage.

[0028] The working principle and effects of the above technical solution are as follows: By loading a multi-agent collaborative optimization scheme, the computational tasks of each stage are broken down into parallel lists, improving the clarity of task allocation, reducing the overlap and confusion of tasks at each stage, and avoiding computational delays caused by task ambiguity. By launching the independent computation modules of each agent according to the list, iterative calculations of parameters at each stage are carried out, improving computational efficiency, shortening the iteration cycle, and avoiding the process sluggishness caused by serial computation of a single agent. By transmitting stage iteration data, interaction between agents is completed, generating cross-stage linkage data, enhancing the synergy of each link, reducing data disconnect between stages, and avoiding deviations in computational results. By updating iteration conditions based on linkage data and promoting multiple rounds of cyclic computation, the completeness of iterative computation is improved, avoiding incomplete optimization caused by incomplete computation. By verifying the consistency and rationality of iteration results, the accuracy of collaborative optimization computation is ensured, which can reduce computational errors, ensure smooth connection between optimization of each design link, and further improve the overall optimization quality.

[0029] In one embodiment of the present invention, step S4 includes: S41. Utilize a self-evolving digital twin to simulate the entire integrated circuit manufacturing process and reproduce parameter changes and scenario states during process execution; S42. Analyze potential risks and performance deviations through manufacturing process simulation to generate post-silicon problem prediction data; S43. Compare the predicted data of post-silicon problems with the actual manufacturing feedback information, and extract the differences and optimization directions between the data. S44. Adjust simulation parameters and model logic according to the differences and optimization directions to generate manufacturing feedback correction parameters; S45. Update the operating rules and simulation model of the digital twin based on manufacturing feedback correction parameters to form a closed-loop evolutionary digital twin management architecture.

[0030] The working principle and effects of the above technical solution are as follows: By utilizing a self-evolving digital twin to simulate the entire integrated circuit manufacturing process, the changes in process parameters and scenario states are reproduced, improving the realism of the manufacturing process simulation, reducing the disconnect between simulation and reality, and avoiding risk prediction errors caused by simulation deviations. Through simulation analysis of potential risks and performance deviations, predictive data for post-silicon manufacturing problems is generated, allowing for early identification of manufacturing hazards, reducing the post-silicon failure rate, and avoiding resource waste caused by rework after failures occur. By comparing predicted data with actual manufacturing feedback, discrepancies and optimization directions are extracted, enhancing the targeting of optimizations, reducing blind adjustments, and preventing optimization directions from deviating from actual needs. By adjusting simulation parameters and model logic to generate correction parameters, the adaptability of the digital twin is improved, avoiding simulation failures caused by model rigidity. By updating the digital twin's operating rules and forming a closed-loop architecture with the simulation model, the continuous evolution of the digital twin is achieved, and manufacturing process control becomes more precise, further reducing manufacturing costs and improving overall manufacturing efficiency and product qualification rate.

[0031] In one embodiment of the present invention, step S5 includes: S51. Based on the closed-loop evolution digital twin management architecture, sort out the design optimization direction and adjustment measures for the entire process, and generate design optimization guidance content; S52. Integrate design optimization guidelines and plan the execution sequence to generate optimization decision data that supports the entire process; S53. By optimizing decision-making data throughout the entire process, we can guide iterative adjustments in each design stage of integrated circuits and promote the continuous improvement of design solutions. S54. After multiple rounds of iterative adjustments, the design scheme is solidified, generating the final design version data that meets the process and performance requirements; S55. Perform multi-dimensional performance and process compatibility evaluation on the final design version data, quantify the evaluation results, and generate the first version silicon success rate prediction index.

[0032] The working principle and effects of the above technical solution are as follows: By sorting out the design optimization direction and adjustment measures throughout the entire process, clear optimization guidance content is generated, improving the pertinence of design adjustments, reducing the waste of time and resources caused by blind optimization, and avoiding design iterations due to unclear optimization directions. The optimization guidance content is integrated and the execution sequence is planned to generate practical optimization decision data, enhancing the synergy of each design stage and avoiding problems with poor coordination between stages. The optimization decision data guides iterative adjustments in each design stage, promoting continuous improvement of the design scheme, reducing performance risks caused by design gaps, and preventing unqualified designs from flowing into subsequent stages. After multiple rounds of iterative adjustments, the design scheme is solidified, generating a final design version that meets process and performance requirements, reducing rework costs caused by imperfect schemes. The final design version is evaluated from multiple dimensions, quantifying the first-version silicon success rate index, which can both mitigate manufacturing risks in advance and improve design quality, making the entire design process more efficient and reliable.

[0033] In one embodiment of the present invention, S53 includes: Read the optimization decision data of the whole process, break down the specific adjustment parameters, adjustment range and optimization priority of each design stage such as integrated circuit architecture, RTL, physical implementation, etc., and generate detailed data of adaptation adjustment for each stage. By utilizing detailed data on stage adaptation adjustments, the core parameters of the integrated circuit architecture design stage are modified in a targeted manner, the architecture layout and module division logic are adjusted, the problems of mismatch between architecture design and process and performance are solved, and the iterative adjustment data of the architecture stage is generated. Based on the iterative adjustment data from the architecture phase, the RTL design phase is simultaneously adjusted to match the architecture, optimize code logic and timing constraints, correct parts of the RTL design that are inconsistent with the architecture, complete the initial iteration of the RTL phase, and generate iterative optimization data for the RTL phase. Based on the iterative optimization data of the RTL stage, the physical implementation stage is optimized synchronously, adjusting the physical layout, routing strategy and layer stack-up design, coordinating the adaptability of physical implementation with architecture and RTL stage, eliminating potential conflicts in physical design, and generating iterative data for the physical implementation stage. Summarize the iteration data from each design stage, verify the adaptability of the overall design scheme, identify new adaptability issues that arise after each iteration, fine-tune relevant parameters, ensure consistency in iteration across all stages, and continuously optimize and improve the design scheme.

[0034] The working principle and effects of the above technical solution are as follows: By reading the optimization decision data of the entire process and breaking down the adjustment details of each stage, the targeting of adjustments in each design stage is improved, reducing the waste of time and resources caused by blind optimization and avoiding repeated modifications due to deviations in adjustment direction. By specifically correcting the core parameters of the architecture, optimizing the layout and module division, the adaptability of the architecture to the process and performance is enhanced, and the adaptation conflicts at the architecture level are reduced. Based on the architecture iteration data, the RTL stage is adjusted synchronously to optimize the code logic and timing constraints, reduce the adaptation deviation between RTL and architecture, and avoid problems with poor connection. The physical implementation stage is optimized synchronously to coordinate the adaptability of each stage, eliminate potential conflicts, and improve the smoothness of the overall process. This ensures the consistency of iteration in each stage, continuously promotes the optimization and improvement of the solution, further improves the overall operational stability, and reduces subsequent rework costs.

[0035] One embodiment of the present invention provides an artificial intelligence-based integrated circuit design and optimization end-to-end management system, comprising: One or more processors; Memory, used to store one or more programs; Wherein, when the one or more programs are executed by the one or more processors, the one or more processors are made to implement the method described in any one of the above.

[0036] Example 2 In one embodiment of the present invention, based on the AI-based integrated circuit design and optimization full-process management method described in Embodiment 1, a process boundary calibration method for PDK discrete rule continuity is further provided.

[0037] Specifically, this embodiment includes the following steps: S1. Decouple the entire integrated circuit design process into stages and build a multi-agent collaborative architecture to generate a multi-stage agent collaborative network. Based on the multi-stage agent collaborative network, construct a cross-stage knowledge graph to form a continuous knowledge representation system.

[0038] Specifically, the continuous knowledge representation system includes at least the correlation information between architecture design, RTL design, physical implementation, verification feedback and manufacturing feedback, and establishes correlations between module division, timing constraints, area constraints, power consumption constraints, placement and routing constraints and process adaptation information in different design stages, so that subsequent physical constraint modeling can obtain cross-stage design context, rather than making judgments based solely on local parameters of a single design stage.

[0039] S2. Extract physical design-related constraints and process parameters based on the continuous knowledge representation system, generate basic information on physical design constraints, and carry out physical information neural network modeling based on the basic information on physical design constraints.

[0040] Specifically, the physical design constraint information includes constraints related to line width, line spacing, interlayer connectivity, via density, routing congestion, metal layer stacking, electrical reliability, timing margin, and manufacturing process window in the PDK rules. By establishing a correspondence between the above constraints and design parameters at different design stages, the physical information neural network can identify the source, scope of influence, and cross-stage transmission relationships of design variables corresponding to specific PDK rules.

[0041] S3. Transform the PDK rules into differentiable continuous constraint functions, complete the fusion of rules and neural network models, and generate the initial physical constraint embedding model.

[0042] Specifically, for each PDK discrete rule, rule type identification and boundary condition parsing are performed. Rules with discrete threshold judgment forms are transformed into continuous soft constraint functions, enabling them to participate in gradient propagation and optimization calculations in the neural network. For rules with lower bound requirements, they are transformed into continuous functions representing gradually increasing penalties when design parameters are below the rule boundary; for rules with upper bound requirements, they are transformed into continuous functions representing gradually increasing penalties when design parameters exceed the rule boundary; for rules with both upper and lower bound windows, they are transformed into continuous functions that generate penalties outside the window and maintain low constraint costs inside the window. Through the above processing, an initial physical constraint embedding model that can be embedded in the early design optimization process is formed.

[0043] S4. By embedding the initial physical constraints into the model, perform real-time physical rule checks and parameter adjustments on the early design schemes to generate initial physical compliance optimization data.

[0044] Specifically, the initial physical constraint embedding model jointly evaluates the architecture design parameters, RTL design parameters, and physical implementation prediction parameters to determine the compliance level of the design scheme under continuous constraint functions, and adjusts the design parameters based on the penalty results output by the continuous constraint functions. After multiple iterations, initial physical compliance optimization data that meets the preset compliance conditions under the meaning of continuous soft constraint functions is generated.

[0045] S5. Based on the initial physical compliance optimization data, perform subsequent physical implementation verification and feedback comparison to identify deviation samples between the continuous soft constraint function and the actual process boundary.

[0046] Specifically, initial physical compliance optimization data is input into the physical implementation or digital twin simulation stages for placement and routing, DRC checks, process window verification, or manufacturing feasibility prediction. If a design candidate is judged to meet compliance conditions in the initial physical constraint embedding model, but still shows a violation of the corresponding PDK rule in subsequent physical implementation verification, the design candidate is marked as a boundary deviation sample. Each boundary deviation sample records at least the corresponding PDK rule item, design parameter value, rule boundary value, continuous constraint function output, subsequent physical implementation check results, and the actual violation type. By aggregating these boundary deviation samples, a deviation sample library is formed for subsequent boundary calibration.

[0047] S1-S5 are the same as in Example 1.

[0048] S6. For each PDK rule item in the deviation sample library, introduce rule boundary proximity, surface compliance violation rate and gradient passivation degree to generate boundary sensitivity calibration coefficients.

[0049] The rule boundary proximity is used to characterize how close the design parameters are to the corresponding PDK true rule boundary in the continuous soft constraint function. The closer the design parameters are to the true rule boundary, the more likely the design sample is to be in the risk region where the judgment of the continuous soft constraint function and the true process boundary will differ.

[0050] The surface compliance violation rate is used to characterize the proportion of samples that are judged as compliant by the continuous soft constraint function, but still violate the rules in subsequent physical implementation verification. The higher this proportion, the more likely the continuous soft constraint function corresponding to the PDK rule item is to produce a false judgment of "surface compliance but actual violation".

[0051] The gradient passivation degree is used to characterize the extent to which the continuous constraint function is insufficient in response to changes in design parameters near the true rule boundary. If the design parameters are close to the true rule boundary, but the output of the continuous constraint function changes little, or the penalty response increases slowly, it indicates that the continuous constraint function exhibits gradient passivation near the boundary.

[0052] When generating boundary sensitivity calibration coefficients, the boundary proximity, surface compliance violation rate, and gradient passivation degree of the same PDK rule item are first statistically analyzed. Then, the three are fused according to preset weights, and the fusion result is mapped to a preset calibration interval to obtain the boundary sensitivity calibration coefficient corresponding to the PDK rule item.

[0053] In the above process, the proximity of the rule boundary and the surface compliance violation rate jointly reflect the probability of misjudgment of the rule near the real process boundary, while the gradient passivation degree reflects the responsiveness of the continuous soft constraint function itself near the boundary. If a large number of design samples corresponding to a certain rule are concentrated near the real boundary, and subsequent physical implementation violations frequently occur after the continuous function judges compliance, and the penalty change of the continuous function near the boundary is relatively slow, then the corresponding boundary sensitivity calibration coefficient increases. Therefore, in the subsequent model optimization process, the penalty strength of the rule is increased, enabling the initial physical constraint embedding model to more sensitively identify risky designs close to the real process boundary.

[0054] S7. For each PDK rule item in the deviation sample library, introduce rule boundary proximity, surface compliance violation rate and process feedback offset credibility to generate the real process boundary offset.

[0055] The process feedback offset credibility is used to characterize the credibility of the repeated occurrence of boundary deviations of the same PDK rule item under the same process level, similar design scenario, or similar process angle conditions in subsequent physical implementation verification, digital twin simulation feedback, or manufacturing feedback.

[0056] If a PDK rule term exhibits continuous function compliance only in a few samples but subsequent physical implementation violations, the deviation may originate from sporadic noise, local design anomalies, or sample randomness, and the effective boundary of this rule term should not be directly altered. If a PDK rule term repeatedly shows continuous function compliance in multiple similar design candidates, similar process corner conditions, or the same metal level but violations in actual checks, it indicates a possible systematic offset between the boundary position of the original continuous soft constraint function and the actual process boundary, requiring additional safety margins to be set for this rule term in subsequent optimizations.

[0057] When generating the actual process boundary offset, the proximity of the rule boundary and the surface compliance violation rate corresponding to the same PDK rule item are first calculated. Then, the reliability of the process feedback offset is combined to determine whether the boundary deviation has repeatability and stability. For boundary deviations with high repeatability and high reliability, they are identified as rule items that need to be corrected by boundary retention. The offset amplitude is limited according to the preset maximum boundary retention amount to generate the actual process boundary offset corresponding to the PDK rule item.

[0058] In the above process, the proximity of the rule boundary and the surface compliance violation rate are correlated with the parameters in S6, enabling boundary sensitivity calibration and real process boundary offset calibration to work synergistically for the same source of rule risk. Process feedback offset reliability is used to distinguish between occasional misjudgments and systematic boundary offsets. If a PDK rule item repeatedly exhibits a situation where the real boundary is more stringent than the continuous function boundary in subsequent physical implementation feedback, the corresponding real process boundary offset increases, requiring subsequent optimization processes to reserve a more sufficient safety margin in design parameters relative to the original rule boundary. Thus, the effective boundary of the continuous soft constraint function can be made closer to the real process boundary, rather than merely remaining at a theoretical or overly smoothed continuous constraint boundary.

[0059] S8. Based on the boundary sensitivity calibration coefficient and the actual process boundary offset, perform boundary calibration on the initial physical constraint embedding model, generate the boundary-calibrated physical constraint embedding model, and output the final physical compliance optimization result.

[0060] Specifically, the boundary sensitivity calibration coefficient obtained in S6 is used as the penalty intensity correction factor for each PDK rule item, and the actual process boundary offset obtained in S7 is used as the boundary retention correction factor for each PDK rule item. The initial continuous constraint function is reconstructed so that it maintains a low constraint cost in the safe region far from the rule boundary, increases the penalty intensity in the risk region close to the actual process boundary, and reserves additional safety margin in the rule items with systematic boundary offset.

[0061] When performing boundary calibration on the initial physical constraint embedding model, the importance weight, boundary sensitivity calibration coefficient, actual process boundary offset, and signed compliance margin of the design parameter relative to the corresponding rule item are first read for each PDK rule item. Then, it is determined whether the signed compliance margin is lower than the actual process boundary offset corresponding to the rule item. If the signed compliance margin is higher than the actual process boundary offset, it indicates that the design parameter still has sufficient safety margin from the actual violation boundary, and a low penalty response is maintained. If the signed compliance margin is lower than the actual process boundary offset, it indicates that although the design parameter may meet the compliance conditions of the original continuous soft constraint function, it is too close to the actual process boundary, and there is a risk of subsequent physical implementation violation, so the penalty response corresponding to the rule item is increased.

[0062] Meanwhile, for PDK rule terms with high boundary sensitivity calibration coefficients, their penalty intensity is increased when calculating the final physical compliance optimization results, so that the optimization process prioritizes moving away from the boundaries of such high-risk rules. For PDK rule terms with high actual process boundary offsets, their safety margin retention requirements are expanded when calculating the final physical compliance optimization results, so that the design parameters are no longer based solely on the theoretical boundaries of the original continuous soft constraint function for compliance, but rather on the actual process boundaries after subsequent physical implementation feedback calibration.

[0063] Through the above processing, the final boundary calibration optimization result value is generated. This boundary calibration optimization result value characterizes the comprehensive physical compliance risk of the current design parameter set after boundary sensitivity calibration and actual process boundary offset calibration. A lower boundary calibration optimization result value indicates that the current design parameter set is further away from the actual process violation boundary, and the risk of violation in subsequent physical implementation is lower; a higher boundary calibration optimization result value indicates that although the current design parameter set may meet the compliance conditions of the initial continuous soft constraint function, there may still be potential violation risks near the actual process boundary.

[0064] By further optimizing the design parameter set with the goal of reducing the boundary calibration optimization result value, the final physical compliance optimization result is obtained. The final physical compliance optimization result includes the boundary-calibrated design parameter set, physical compliance re-optimization data, a candidate design set that meets the actual process boundary requirements, or rule calibration parameters used to update subsequent multi-agent collaborative optimization iterations.

[0065] The physical constraint embedding model after boundary calibration continues to be integrated into the multi-agent collaborative optimization iteration process, the self-evolving digital twin construction process, and the closed-loop evolution digital twin management architecture in Example 1. This enables subsequent design optimization to be judged not only based on the original continuous soft constraint function, but also based on the physical constraint embedding model after real process boundary calibration.

[0066] The working principle and effects of the above technical solution are as follows: It further identifies the sources of deviation between the continuous soft constraint function and the actual process boundary, and performs secondary calibration on the original continuous constraint function using boundary sensitivity calibration coefficients and actual process boundary offsets. The boundary sensitivity calibration coefficients primarily address the problems of insufficient penalty and slow gradient response of continuous functions near rule boundaries, enabling the model to improve its response strength to risky samples when approaching the actual PDK boundary. The actual process boundary offsets primarily address the inconsistency between the theoretical boundary of the continuous function and the actual physical realization boundary, enabling the model to reserve reasonable safety margins for specific rule terms based on subsequent physical realization and manufacturing feedback. The boundary calibration optimization result value then applies the boundary sensitivity calibration coefficients and actual process boundary offsets together to the design parameter optimization process, ensuring that the optimization result is compliant not only in the sense of continuous soft constraint functions but also has higher compliance reliability in the sense of actual physical realization and process boundaries.

[0067] Therefore, this embodiment can effectively reduce the probability that the early optimization results appear compliant but the subsequent physical implementation is non-compliant, reduce backend rework caused by misjudgment of PDK rule boundaries, and improve the coordination and consistency between architecture design, RTL design and physical implementation.

[0068] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A method for managing the entire process of integrated circuit design and optimization based on artificial intelligence, characterized in that: The method includes: S1. Decouple the entire integrated circuit design process into stages and build a multi-agent collaborative architecture to generate a multi-stage agent collaborative network; construct a cross-stage knowledge graph based on the multi-stage agent collaborative network to form a continuous knowledge representation system. S2. Based on the continuous knowledge representation system, perform physical information neural network modeling, transform PDK rules into differentiable continuous constraint functions, and generate physical constraint embedding models; use physical constraint embedding models to perform real-time physical rule checks and optimizations on early designs, and generate physical compliance optimization data; S3. Based on physical compliance optimization data, perform multi-agent collaborative optimization iteration to generate cross-stage collaborative optimization data; drive the construction of a self-evolving digital twin system through cross-stage collaborative optimization data to form a digital twin. S4. Real-time simulation of the manufacturing process is performed using a self-evolving digital twin to generate post-silicon problem prediction data; manufacturing feedback correction parameters are generated through closed-loop calibration of the post-silicon problem prediction data and actual manufacturing feedback; the digital twin is dynamically updated based on the manufacturing feedback correction parameters to form a closed-loop evolving digital twin management architecture. S5. Output design optimization guidance strategies based on the closed-loop evolution digital twin management architecture, and generate full-process optimization decision data; drive integrated circuit design iteration through full-process optimization decision data to generate final design version data; evaluate the first-version silicon success rate of the final design version data and generate first-version silicon success rate prediction indicators.

2. The method for managing the entire process of integrated circuit design and optimization based on artificial intelligence according to claim 1, characterized in that, S1 includes: S11. Decouple the entire integrated circuit design process into stages, break down the execution content and flow relationship of each design stage, and generate process stage decomposition results; S12. Based on the process phase decomposition results, build a multi-agent collaborative architecture, assign the design control responsibilities of each agent, and generate agent responsibility allocation results. S13. Construct a multi-stage intelligent agent collaborative network based on the results of intelligent agent responsibility allocation, and open up data transmission and interaction channels between each stage. S14. Relying on the multi-stage intelligent agent collaborative network, collect design data and related information at each stage to complete the collection and sorting of cross-stage knowledge elements; S15. Construct a cross-stage knowledge graph by collecting and organizing knowledge elements to form a continuous knowledge representation system.

3. The method for full-process management of integrated circuit design and optimization based on artificial intelligence according to claim 1, characterized in that, The S2 includes: S21. Extract relevant physical design constraints and process parameters based on the continuous knowledge representation system to generate basic information on physical design constraints; S22. Based on the basic information of physical design constraints, conduct physical information neural network modeling and build a network computing framework that adapts to the design scenario. S23. Transform the PDK rules into differentiable continuous constraint functions to achieve deep integration of the rules and the neural network model; S24. Integrate continuous constraint functions with neural network computing frameworks to generate physical constraint embedding models that can be embedded in the design process; S25. By embedding physical constraints into the model, perform real-time physical rule checks and parameter adjustments on early design schemes to generate physical compliance optimization data.

4. The method for managing the entire process of integrated circuit design and optimization based on artificial intelligence according to claim 3, characterized in that, S24 includes: Extract the continuous constraint function that has been fused in S23 and the neural network computing framework built in S22, summarize the core computing logic and parameter configuration of the two, and generate the fused basic dataset. Perform compatibility checks on the fusion base dataset, identify parameter conflicts and logical contradictions between continuous constraint functions and neural network computing frameworks, and generate compatibility check results. Based on the compatibility verification results, optimize the fusion logic, adjust the calculation parameters of the access node and network framework of the constraint function, achieve seamless connection between the two, and generate an optimized fusion system. The optimized fusion system is subjected to performance testing to verify its computational efficiency and constraint adaptation capability in physical design scenarios, and a performance test report is generated. By fine-tuning the fusion system parameters based on the performance test report, solidifying the fusion logic, and generating a physical constraint embedding model that can be directly embedded into the entire integrated circuit design process.

5. The method for full-process management of integrated circuit design and optimization based on artificial intelligence according to claim 1, characterized in that, The S3 includes: S31. Based on physical compliance optimization data, formulate optimization goals and execution paths for each intelligent agent, and generate a multi-agent collaborative optimization scheme; S32. Conduct cross-stage parallel iterative calculations according to the multi-agent collaborative optimization scheme to complete the collaborative optimization calculations of each design stage; S33. Summarize the optimization results of each stage after iterative calculations and generate cross-stage collaborative optimization data that is adapted to the entire process; S34. Utilize cross-stage collaborative optimization data to build a virtual design mapping environment and construct a basic operating platform for digital twins; S35. Inject design, manufacturing, and verification lifecycle data into a virtual mapping environment to form a digital twin covering the entire process.

6. The method for managing the entire process of integrated circuit design and optimization based on artificial intelligence according to claim 5, characterized in that, S32 includes: Load the multi-agent collaborative optimization scheme, break down the computation tasks of each stage, and generate a list of parallel computation tasks; According to the parallel computing task list, each agent's independent computing module is launched to carry out phased parameter iterative calculation and generate phased iterative calculation data. Transmit iterative computation data during the transmission phase to adjacent design phases, complete the interaction of computation results between intelligent agents, and generate cross-phase collaborative computation data; Based on the continuous updating and iterative calculation conditions of cross-stage linkage calculation data, multiple rounds of cyclic calculations are promoted to generate complete iterative calculation results; Verify the consistency and rationality of the complete iterative calculation results, and complete the collaborative optimization calculation of each design stage.

7. The method for full-process management of integrated circuit design and optimization based on artificial intelligence according to claim 1, characterized in that, The S4 includes: S41. Utilize a self-evolving digital twin to simulate the entire integrated circuit manufacturing process and reproduce parameter changes and scenario states during process execution; S42. Analyze potential risks and performance deviations through manufacturing process simulation to generate post-silicon problem prediction data; S43. Compare the predicted data of post-silicon problems with the actual manufacturing feedback information, and extract the differences and optimization directions between the data. S44. Adjust simulation parameters and model logic according to the differences and optimization directions to generate manufacturing feedback correction parameters; S45. Update the operating rules and simulation model of the digital twin based on manufacturing feedback correction parameters to form a closed-loop evolutionary digital twin management architecture.

8. The method for managing the entire process of integrated circuit design and optimization based on artificial intelligence according to claim 1, characterized in that, The S5 includes: S51. Based on the closed-loop evolution digital twin management architecture, sort out the design optimization direction and adjustment measures for the entire process, and generate design optimization guidance content; S52. Integrate design optimization guidelines and plan the execution sequence to generate optimization decision data that supports the entire process; S53. By optimizing decision-making data throughout the entire process, we can guide iterative adjustments in each design stage of integrated circuits and promote the continuous improvement of design solutions. S54. After multiple rounds of iterative adjustments, the design scheme is solidified, generating the final design version data that meets the process and performance requirements; S55. Perform multi-dimensional performance and process compatibility evaluation on the final design version data, quantify the evaluation results, and generate the first version silicon success rate prediction index.

9. The method for managing the entire process of integrated circuit design and optimization based on artificial intelligence according to claim 8, characterized in that, S53 includes: Read the optimization decision data of the whole process, break down the specific adjustment parameters, adjustment range and optimization priority of each design stage, and generate detailed data of adaptation adjustment for each stage. By utilizing detailed data on stage adaptation adjustments, the core parameters of the integrated circuit architecture design stage are modified in a targeted manner, the architecture layout and module division logic are adjusted, and iterative adjustment data for the architecture stage is generated. Based on the iterative adjustment data from the architecture phase, the RTL design phase is simultaneously adjusted to match the architecture, optimize code logic and timing constraints, correct parts of the RTL design that are inconsistent with the architecture, complete the initial iteration of the RTL phase, and generate iterative optimization data for the RTL phase. Based on the iterative optimization data of the RTL stage, the physical implementation stage is optimized synchronously, adjusting the physical layout, routing strategy and layer stack-up design, coordinating the adaptability of physical implementation with architecture and RTL stage, and generating iterative data for physical implementation stage. Summarize the iteration data from each design stage, verify the adaptability of the overall design scheme, identify new adaptability issues that arise after each iteration, fine-tune relevant parameters, and continuously promote the optimization and improvement of the design scheme.

10. An AI-based integrated circuit design and optimization end-to-end management system, including: One or more processors; Memory, used to store one or more programs; Wherein, when the one or more programs are executed by the one or more processors, the one or more processors implement the method of any one of claims 1 to 9.

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