Correlation analysis methods, equipment and storage media

Abstract

Embodiments of this disclosure relate to a correlation analysis method, apparatus, and storage medium. The method includes: acquiring batch information related to multiple wafers, the batch information indicating that the multiple wafers are processed in batches at multiple processing nodes in a production process, and each of the multiple wafers having a corresponding label indicating wafer quality; determining the degree of correlation between each processing node and wafer quality based on the batch information and the corresponding labels; and providing correlation information indicating the degree of correlation between at least one of the multiple processing nodes and the quality of the sub-batch of wafers. In this manner, processing nodes with a high degree of correlation with wafer quality can be identified.

Description

Technical Field

[0001] The exemplary embodiments disclosed herein generally relate to the field of computers, and particularly to a correlation analysis method, apparatus, and computer-readable storage medium. Background Technology

[0002] Semiconductor wafer manufacturing is an extremely complex and highly precise process. During wafer manufacturing, various factors, such as process control and equipment precision, inevitably lead to defects. In cases of defects, it is usually necessary to analyze their correlation with various factors in the manufacturing process to help pinpoint the cause of the anomaly. Therefore, a more comprehensive and accurate method is needed to determine the root cause of defects. Summary of the Invention

[0003] In a first aspect of this disclosure, a correlation analysis method is provided. The method includes: acquiring batch information related to multiple wafers, the batch information indicating that the multiple wafers are processed in batches at multiple processing nodes in a production process, each of the multiple wafers having a corresponding label indicating wafer quality; determining the degree of correlation between each processing node and wafer quality based on the batch information and the corresponding labels; and providing correlation information indicating the degree of correlation between at least one of the multiple processing nodes and the quality of the sub-batch of wafers.

[0004] In a second aspect of this disclosure, an electronic device is provided. The device includes at least one processor; and at least one memory coupled to the at least one processor and storing instructions for execution by the at least one processor. When executed by the at least one processor, the instructions cause the device to perform the method of the first aspect.

[0005] In a third aspect of this disclosure, a computer-readable storage medium is provided. The computer-readable storage medium stores computer-executable instructions that can be executed by a processor to implement the method of the first aspect.

[0006] As will be understood from the following description, based on the examples in this paper, batch information related to multiple wafers is obtained. The batch information indicates that multiple wafers are processed in batches at multiple processing nodes in the production process, and each wafer has a corresponding label indicating wafer quality. Accordingly, based on the batch information and corresponding labels related to the multiple wafers, the correlation between each processing node and wafer quality is determined. Subsequently, correlation information is provided, indicating the correlation between at least one of the multiple processing nodes and the quality of the sub-batch wafers.

[0007] This approach allows for the quantitative or qualitative characterization of the correlation between each processing node and wafer quality, and in some implementations, this correlation can be represented by a correlation coefficient. This enables the automatic identification of processing nodes and corresponding sub-batch wafers with a high correlation to wafer quality. Furthermore, this scheme can identify potential influencing factors introduced by batch processing that are difficult to reflect using single-dimensional data, thereby improving the accuracy of identifying the correlation between processing nodes and wafer quality anomalies and reducing the time required for manual troubleshooting across a large number of processing nodes.

[0008] It should be understood that the content described in this content section is not intended to limit the key or essential features of the embodiments of this disclosure, nor is it intended to restrict the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0009] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. In the drawings, the same or similar reference numerals denote the same or similar elements, wherein: Figure 1 A schematic diagram is shown of an example environment in which embodiments of the present disclosure may be implemented; Figure 2 A flowchart of a process for correlation analysis according to some embodiments of the present disclosure is shown; Figure 3 Schematic diagrams illustrating analysis results according to some embodiments of the present disclosure are shown; Figures 4A to 4B A schematic diagram illustrating example sub-results according to some embodiments of the present disclosure is shown; and Figure 5 A block diagram of an electronic device in which one or more embodiments of the present disclosure can be implemented is shown. Detailed Implementation

[0010] Embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. While some embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this disclosure. It should be understood that the accompanying drawings and embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of protection of this disclosure.

[0011] It should be noted that the headings of any section / subsection provided herein are not limiting. Various embodiments are described throughout this document, and embodiments of any type may be included under any section / subsection. Furthermore, embodiments described in any section / subsection may be combined in any way with any other embodiments described in the same section / subsection and / or different sections / subsections.

[0012] In the description of embodiments of this disclosure, the term "comprising" and similar terms should be understood as open-ended inclusion, i.e., "including but not limited to". The term "based on" should be understood as "at least partially based on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The term "some embodiments" should be understood as "at least some embodiments". Other explicit and implicit definitions may also be included below. The terms "first", "second", etc., may refer to different or the same objects. Other explicit and implicit definitions may also be included below.

[0013] The embodiments of this disclosure may involve user data, data acquisition, and / or use. All of these aspects comply with applicable laws, regulations, and relevant provisions. In the embodiments of this disclosure, all data collection, acquisition, processing, manipulation, forwarding, and use are conducted with the user's knowledge and confirmation. Accordingly, in implementing the embodiments of this disclosure, the type, scope of use, and usage scenarios of any data or information that may be involved should be communicated to the user and their authorization obtained in accordance with relevant laws and regulations through appropriate means. The specific methods of notification and / or authorization may vary depending on the actual situation and application scenario, and the scope of this disclosure is not limited in this respect.

[0014] In this specification and the embodiments, any processing of personal information will be carried out only under the premise of legality (such as obtaining the consent of the personal information subject, or being necessary for the performance of a contract), and will only be carried out within the scope stipulated or agreed upon. A user's refusal to process personal information beyond what is necessary for basic functions will not affect the user's use of basic functions.

[0015] As used herein, the term "wafer" refers to a substrate used in the manufacture of semiconductor devices. A substrate can be processed through multiple process stations during semiconductor wafer fabrication to form the desired device structure. A substrate can be, for example, a sheet-like substrate, and may include, but is not limited to, silicon wafers, compound semiconductor wafers, and other suitable semiconductor substrates.

[0016] As used in this document, the term "processing node" refers to a logical or physical unit used in the manufacturing process to process or measure wafers, typically including but not limited to process steps and process stations. A processing node can correspond to a process step or to a location defined by one or more machines or chambers used to perform that process step. In the context of semiconductor wafer manufacturing, a processing node can also correspond to a process station in the semiconductor wafer manufacturing process.

[0017] As used in this article, "batch processing" refers to the process at a certain processing node where a subset of wafers belonging to the same batch are processed separately from the other wafers in that batch. For example, in the context of semiconductor wafer manufacturing, batch processing can mean that a sub-batch of wafers is processed separately from the other wafers in the batch at a corresponding process station.

[0018] As used in this document, the term "master batch wafer" refers to a batch initially organized during the production process that comprises multiple wafers. The term "sub-batch wafer" refers to a batch formed by batch processing of the master batch at a certain processing node, and includes some wafers from the master batch. In some cases, the sub-batch may be identified by appending a suffix to the master batch identifier.

[0019] The term “Yield Management System” (YMS) used in this article refers to an information system used to collect, store, query, and analyze yield-related data during the semiconductor wafer manufacturing process. It can typically include, but is not limited to, managing data such as wafer in process (WIP), wafer acceptance test (WAT), defects, and in-line measurement.

[0020] Figure 1 A schematic diagram of an example environment 100 that can be implemented in accordance with embodiments of the present disclosure is shown. This example environment 100 may include an electronic device 110.

[0021] In this example environment 100, electronic device 110 may run an application 120 that supports correlation analysis. Application 120 can be any suitable type of application for correlation analysis, including but not limited to yield management systems, data analysis software for semiconductor manufacturing, correlation analysis software, or other suitable applications. User 140 can interact with application 120 via electronic device 110 and / or its attached devices. In this document, user 140 can be an engineer, professional, manager, or any other suitable user.

[0022] exist Figure 1In environment 100, if application 120 is active, electronic device 110 can present interface 150 for supporting correlation analysis through application 120.

[0023] The terminal device can be any type of mobile terminal, fixed terminal, or portable terminal, including mobile phones, desktop computers, laptop computers, notebook computers, netbook computers, tablet computers, media computers, multimedia tablets, personal communication system (PCS) devices, personal navigation devices, personal digital assistants (PDAs), audio / video players, digital cameras / camcorders, television receivers, radio receivers, e-book devices, gaming devices, or any combination thereof, including accessories and peripherals of these devices or any combination thereof. In some embodiments, the electronic device 110 may also support any type of user-facing interface (such as "wearable" circuitry).

[0024] In some embodiments, the server-side device may be a standalone physical server, a server cluster or distributed system composed of multiple physical servers, or a cloud server providing basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, content delivery networks, and big data and artificial intelligence platforms. The server-side device may include, for example, computing systems / servers, such as mainframes, edge computing nodes, computing devices in a cloud environment, and so on.

[0025] It should be understood that the structure and function of the various elements in environment 100 are described for illustrative purposes only and do not imply any limitation on the scope of this disclosure.

[0026] As mentioned above, during wafer manufacturing, situations sometimes arise where some wafers have insufficient yield or a high number of defects. In such scenarios, users (e.g., engineers) can use yield management systems or other data analysis software to perform correlation analysis to help pinpoint the cause of the anomaly. For example, users can perform correlation analysis using numerical parameters. Users can also perform correlation analysis using non-numerical parameters. Correlation analysis of numerical parameters may include, for example, analysis of wafer acceptable test parameters, analysis of online measurement parameters, and analysis of defect counts. Correlation analysis of non-numerical parameters may include, for example, analysis of commonalities in equipment, analysis of commonalities in equipment chambers, and analysis of commonalities in process formulations.

[0027] Furthermore, within a single wafer manufacturing process, batching may occur due to various reasons during the manufacturing process. For example, at a certain process step, some wafers may need to be tested, thus separating some wafers from the rest of the batch for further processing. If, during final wafer testing, the yield of the separated wafers is found to be inconsistent with that of the other wafers, the aforementioned traditional commonality analysis methods can usually still be used to pinpoint the suspected cause.

[0028] However, in some cases, batch processing itself can be a potential cause of wafer quality fluctuations, but its impact on wafer quality cannot be directly reflected by data from a single dimension such as equipment commonality, chamber commonality, or process formulation commonality. For example, sub-batch wafers that are batched at the same processing node may exhibit different quality than other wafers in the same batch during final testing due to factors such as longer waiting times at that node, contamination caused by residual process formulation from the previous batch on the equipment or chamber, or fluctuations in the process status of the equipment or chamber at different times. Such potential influencing factors introduced by batch processing are difficult to effectively identify using existing commonality analysis methods.

[0029] Correspondingly, in actual yield management systems, each processing node is usually recorded as a site name, which does not necessarily contain sequence information. Therefore, it is difficult to directly identify which processing node is the starting point for batch processing. In addition, in actual production processes, wafer production history usually includes a large number of process steps. If the results of batch processing at each processing node are listed one by one, the information density is too high, and users will find it difficult to quickly identify the processing nodes of interest.

[0030] In view of this, a correlation analysis scheme is proposed. According to this scheme, batch information related to multiple wafers is obtained. This batch information indicates that the multiple wafers are processed in batches at multiple processing nodes in the production process, and each wafer has a corresponding label indicating wafer quality. Further, based on the batch information and corresponding labels related to the multiple wafers, the correlation between each processing node and wafer quality is determined. Then, correlation information is provided, indicating the correlation between at least one of the multiple processing nodes and the quality of the sub-batch wafers. In some examples, the correlation can be represented by a correlation coefficient.

[0031] This approach provides the correlation between each processing node and wafer quality as correlation information, which can be quantified using correlation coefficients when needed. This allows for the automatic identification of processing nodes and related sub-batch wafers with a high correlation to wafer quality. Furthermore, this scheme can identify potential influencing factors introduced by batch processing that are difficult to reflect using single-dimensional data, thereby improving the accuracy of identifying the correlation between processing nodes and wafer quality anomalies and reducing the time required for manual troubleshooting across a large number of processing nodes.

[0032] The following description will continue with reference to the accompanying drawings, which will provide some exemplary embodiments of this disclosure.

[0033] The following will be referenced Figure 2 The scheme used in this disclosure for correlation analysis is described. Figure 2 A flowchart of an example process 200 for correlation analysis according to some embodiments of the present disclosure is shown. For ease of discussion, reference will be made to... Figure 1 These embodiments are described in the context of environment 100. These embodiments can be implemented in... Figure 1 The following description will use the implementation at electronic device 110 as an example for ease of discussion.

[0034] In embodiments of this disclosure, at block 210, electronic device 110 acquires batch information relating to multiple wafers. The manufacturing process of the multiple wafers includes multiple processing nodes, and the batch information indicates that the multiple wafers are processed in batches at the multiple processing nodes. Batch processing forms at least one sub-batch of wafers. In some embodiments, the multiple wafers each have a label indicating the quality of the corresponding wafer.

[0035] In some embodiments, electronic device 110 can retrieve batch information related to the manufacturing process of multiple wafers from server 130 (e.g., a server hosting a yield management system). For example, electronic device 110 can query the entire manufacturing history of the parent batch and all sub-batches corresponding to these wafers in a batch-level data table of the yield management system based on the identifier of the parent batch wafers to be analyzed (i.e., multiple wafers). Accordingly, electronic device 110 can query the wafers corresponding to the identifiers of the parent batch and sub-batches at each processing node in a wafer-level data table based on the identifiers of the parent batch and sub-batches at each processing node in the entire manufacturing history. In some examples, the manufacturing process of multiple wafers can refer to a series of sequential processes involved in forming devices or structures on the wafer, such as, but not limited to, thin film deposition, photolithography, etching, doping, chemical mechanical polishing, cleaning, and metrology processes in semiconductor wafer manufacturing.

[0036] In some embodiments, for each of a plurality of wafers, batch information may indicate the corresponding processing time of that wafer at multiple processing nodes. Further, batch information may indicate the corresponding process recipe used for processing that wafer at multiple processing nodes. Batch information may indicate the corresponding equipment that the wafer passes through during processing at multiple processing nodes. Additionally / alternatively, batch information may indicate the corresponding chamber that the wafer passes through during processing at multiple processing nodes. In this way, batch information can characterize the actual experience of each wafer in the production process from multiple dimensions such as processing time, process recipe, equipment, and chamber, which is beneficial for more accurately characterizing the correlation between batch processing at each processing node and wafer quality in subsequent steps.

[0037] As an example, assume the master batch to be analyzed comprises 25 wafers, numbered from 01 to 25. These 25 wafers may include several wafers processed in batches. Batch information can be retrieved from the wafer production history module recorded in the yield management system. This information may include, but is not limited to, the processing time of each of the 25 wafers at each processing node, the machine / chamber it passed through, the process formulation used, and the corresponding master batch identifier, sub-batch identifier, and wafer identifier. It should be understood that the above number of wafers is given as an example only, and this solution does not limit the number of wafers included in a master batch.

[0038] In some embodiments, batch processing can refer to the process of separating a portion of wafers from the other wafers in a batch at a certain processing node for separate processing. In semiconductor wafer manufacturing scenarios, batch processing can instruct sub-batch wafers from other wafers in a batch to be processed separately at the corresponding process station, for example, splitting a full batch of wafers into several sub-batch wafers for separate processing due to experiments, equipment occupancy, or process requirements.

[0039] In some embodiments, the labels of each wafer among a plurality of wafers can be determined based on the wafer's quality metrics, including but not limited to yield, defect number, and at least one of test parameters. In some examples, the labels can indicate whether the corresponding wafer is of good or bad quality. For example, a binary label such as "Good" to represent a good wafer and "Bad" to represent a bad wafer can be used to characterize the wafer's quality, or other suitable forms can be used. In some examples, electronic device 110 can determine the wafer label based on the corresponding wafer's quality metrics.

[0040] As an example, electronic device 110 can identify the labels on wafers whose quality indicators meet a preset quality threshold as labels indicating that the corresponding wafers are good wafers (e.g., Good), and identify the labels on wafers whose quality indicators do not meet the preset quality threshold as labels indicating that the corresponding wafers are bad wafers (e.g., Bad). For example, a good wafer (i.e., a wafer with a second label) refers to a wafer that meets the quality requirements, and a bad wafer (i.e., a wafer with a first label) is a wafer that does not meet the quality requirements. As an example, the quality indicators and preset quality thresholds can be predefined by user 140 (e.g., an engineer) in conjunction with the specific case to be analyzed, and are not limited herein. For example, continuing with the above example, suppose that three wafers numbered 9, 15, and 20 out of 25 wafers numbered 1 to 25 are defined as wafers with a first label (with a label indicating bad, e.g., Bad), and the remaining 22 wafers are defined as wafers with a second label (with a label indicating good, e.g., Good). However, this is merely an example, and this disclosure does not limit it. In this way, whether a wafer is defective or not can be made explicit in the form of binary or multi-valued labels, which facilitates correlation analysis in subsequent steps.

[0041] In box 220, electronic device 110 determines the degree of correlation between each processing node and wafer quality based on batch information and corresponding tags associated with multiple wafers. In some examples, this degree of correlation can be represented by a correlation coefficient, which can indicate the degree of correlation between batch processing and wafer quality at the corresponding processing node.

[0042] In some embodiments, the electronic device 110 can traverse multiple processing nodes and determine the correlation coefficient corresponding to each processing node. In some examples, the correlation coefficient can be a numerical value used to characterize the degree of correlation between batch processing and wafer quality at a processing node, for example, the value range can be 0 to 1 or other appropriate ranges, and the larger the value, the higher the degree of correlation.

[0043] In some embodiments, the electronic device 110 can traverse multiple processing nodes and determine whether sub-batch wafers exist at each processing node. If batch information indicates that no sub-batch processing exists at a first processing node, the electronic device 110 can determine that the first processing node is unrelated to wafer quality. In some embodiments, unrelatedness can be represented by a predetermined value, which may include, but is not limited to, 0 or other values ​​indicating no correlation. As an example, if all wafers in multiple wafers at a certain processing node are processed together without sub-batch processing, the electronic device 110 can determine that there is no correlation between the processing at that processing node and wafer quality introduced by sub-batch processing. Therefore, the electronic device 110 can directly determine the correlation coefficient corresponding to that processing node as 0. In this way, by first determining whether sub-batch processing exists at each processing node, subsequent calculations for processing nodes where sub-batch processing has not occurred can be skipped, thereby reducing the computational cost required for correlation analysis.

[0044] If batch information indicates that batch processing exists at the first processing node, the electronic device 110 can determine a first degree of correlation between the first processing node and the wafer quality based on the corresponding tags of each wafer that has undergone batch processing at the first processing node. In some embodiments, the first degree of correlation can be represented by a first correlation coefficient corresponding to the first processing node.

[0045] In some embodiments, the multiple wafers processed in batches at a first processing node may include at least one sub-batch wafer. In some examples, where batch processing occurs at a single processing node, the multiple wafers may be divided into multiple sub-batches. In this case, the electronic device 110 can identify a first sub-batch wafer from at least one sub-batch wafer. The first sub-batch wafer includes wafers with a first label indicating that the quality of the corresponding wafer is less than a preset quality threshold. The electronic device 110 can then determine a first correlation between the first processing node and wafer quality based on information related to the number of first sub-batch wafers. For example, the electronic device 110 can determine a first correlation coefficient corresponding to the first processing node based on information related to the number of first sub-batch wafers.

[0046] In some embodiments, the number of wafers with the first label included in the first sub-batch wafers may be greater than the number of wafers with the first label included in at least one second sub-batch wafer, wherein the at least one second sub-batch wafer is different from the first sub-batch wafers. In other words, the first sub-batch wafers may be the sub-batch wafers with the largest number of wafers with the first label included in at least one sub-batch wafers.

[0047] As an example, the total number of wafers included in the first sub-batch can be denoted as... The number of wafers with the first tag in the first sub-batch is denoted as... The number of wafers with the first label among multiple wafers is denoted as... The first batch of wafers is identified as follows: In this way, by determining the first correlation coefficient by selecting the sub-batch wafer with the largest number of wafers bearing the first label from at least one sub-batch wafers, it is possible to focus on the sub-batch wafer with the highest degree of correlation with quality anomalies among multiple sub-batch wafers, thereby improving the accuracy of the determined correlation coefficient in characterizing the batch processing at the first processing node.

[0048] In some embodiments, the first number of wafers with a first label in the first sub-batch of wafers (i.e., ) and a second number of wafers with a first label among multiple wafers (i.e., The comparison was made based on the results of the comparison and the total number of wafers in the first sub-batch (i.e., The first degree of correlation between the first processing node and the wafer quality is determined, for example, the first correlation coefficient corresponding to the first processing node is determined.

[0049] Based on the above comparison results, different calculation methods can be used to determine the first correlation degree for the two cases where the first number and the second number are the same and different, respectively. In this way, a more suitable calculation method can be used for the two cases where the first batch of wafers has completely covered the wafers with the first label among the multiple wafers, thereby improving the accuracy of the determined correlation coefficient in representing the correlation between batch processing and wafer quality at the first processing node.

[0050] The following describes how to determine the first correlation between the first processing node and the wafer quality when the first number and the second number are the same.

[0051] In some embodiments, if the electronic device 110 determines that the first number and the second number are the same, it can determine a first correlation coefficient corresponding to the first processing node based on the first number and the total number of wafers in the first sub-batch. In some examples, where the first number and the second number are the same, the electronic device 110 can determine that the first sub-batch includes wafers with a first tag from a plurality of wafers.

[0052] As an example, in this case, the first correlation coefficient corresponding to the first processing node (which serves as an example of the first degree of correlation) can be determined by the following formula:

[0053] in Indicates the correlation coefficient corresponding to the first processing node. For example, suppose... Then the first correlation coefficient corresponding to the first processing node can be determined as: In this way, when the first and second batches of wafers are the same but the first batch also includes wafers with other tags, the correlation coefficient between batch processing and wafer quality at that processing node can be characterized by a correlation coefficient between 0 and 1. This avoids missing potentially related processing nodes when the user 140 has errors in defining wafer quality.

[0054] Alternatively / additionally, in this scenario, the second number may be less than the total number of wafers in the first sub-batch. When the second number is less than the total number, it is generally considered that when defining wafer quality, some wafers may not have been tested and therefore their quality labels may not be accurately determined, or the user may have used a relatively lenient standard for defining quality, resulting in wafers defined as good but actually close to the boundary value. Therefore, even if the first number is equal to the second number, the correlation between the first sub-batch wafers and wafer quality should not be completely excluded, but should be presented in the analysis results with an appropriate correlation coefficient so that users can re-examine their definition of quality.

[0055] The following section will continue to describe how to determine the first degree of correlation between the first processing node and the wafer quality in scenarios where the first number and the second number are different.

[0056] In some embodiments, if the electronic device 110 determines that the first number is different from the second number, it can determine a first ratio based on the first number and the second number. Accordingly, the electronic device 110 can determine a correction parameter based on the difference between the first number and the total number. Then, the electronic device 110 determines a first correlation coefficient corresponding to the first processing node based on the first ratio and the correction parameter.

[0057] As an example, the first ratio can be determined as the ratio of the first number to the second number, i.e. Accordingly, the first correlation coefficient corresponding to the first processing node can be determined by the following formula:

[0058] in To correct the parameters. For example, suppose... Then the first correlation coefficient corresponding to the first processing node can be determined as: In this way, the accuracy of the correlation coefficient can be improved.

[0059] In some embodiments, the correction parameter increases as the difference between the total number of wafers in the first sub-batch and the first number increases, and the correlation coefficient decreases as the correction parameter increases. For example, when the total number of wafers in the first sub-batch is greater than the first number, the closer the total number of wafers in the first sub-batch is to the first number, the greater the correlation between batch processing and wafer quality at the corresponding processing node can be determined. Thus, by introducing the correction parameter, it is possible to avoid the correlation coefficients calculated for multiple processing nodes being too close to be easily distinguishable, which is beneficial for highlighting processing nodes with a higher correlation to wafer quality in the analysis results (e.g., correlation information). It should be understood that the denominator in the above correction parameter is given only as an example and can be adjusted according to the needs of specific application scenarios; this solution is not limited in this respect.

[0060] Continuing in process 200, at box 230, electronic device 110 provides correlation information indicating the degree of correlation between at least one of a plurality of processing nodes and the quality of the sub-batch wafers. In some embodiments, the correlation information may be provided as an analysis result. For example, the correlation information may be presented in tabular form. The correlation information may also be presented in the form of a visualization view linked to a table.

[0061] In some embodiments, the electronic device 110 can determine the processing order of the multiple processing nodes based on the start time of processing of at least one of the multiple wafers at the multiple processing nodes. Furthermore, the electronic device 110 can provide correlation information based on the processing order and batch information.

[0062] In some embodiments, the start time can indicate the arrival time of the wafer at the corresponding processing node. In some examples, the electronic device 110 can sort multiple processing nodes according to their arrival time based on the manufacturing history of the master batch, thereby obtaining a process site sequence table (i.e., processing order) that includes the processing order of multiple processing nodes. In this way, by determining the processing order based on the start time, the logical order of the processing nodes can be decoupled from their names, providing a basis for combining and presenting the correlation coefficients of multiple processing nodes corresponding to the same sub-batch of wafers. This allows engineers to easily view the processing nodes with a high degree of correlation to wafer quality in the analysis results according to the actual process sequence, improving the efficiency of engineers in interpreting the analysis results.

[0063] For ease of understanding, the following will be combined with Figure 3 and Figures 4A to 4B This describes how to provide analysis results to user 140. Figure 3 A schematic diagram 300 is shown for displaying analysis results according to some embodiments of the present disclosure. The analysis results may be presented, for example, by an electronic device 110 via an application 120. Figures 4A to 4BA schematic diagram illustrating example sub-results according to some embodiments of the present disclosure is shown.

[0064] In some embodiments, the electronic device 110 may present multiple information items, one of which corresponds to the same sub-batch of wafers. The same sub-batch of wafers passes through one or more processing nodes among multiple processing nodes, and the corresponding information item indicates the degree of correlation between the one or more processing nodes and the quality of the same sub-batch of wafers. In some examples, the one or more processing nodes are adjacent processing nodes determined based on the processing order.

[0065] In some examples, based on the processing sequence described above, electronic device 110 can merge several adjacent processing nodes traversed by the same sub-batch of wafers into a single sub-result and present them. For example, at several adjacent processing nodes in the processing sequence, if electronic device 110 determines that these processing nodes each correspond to the same sub-batch of wafers, it can merge and present the correlation coefficients of these processing nodes. In this way, in the table, the processing nodes traversed by the same sub-batch of wafers do not need to be listed separately in multiple rows, but can be merged and presented in the same row, thereby reducing the amount of information presented repeatedly in the analysis results.

[0066] In some embodiments, the electronic device 110 may present the analysis results in a tabular format. The table indicates the identifier of at least one of the multiple processing nodes (e.g., node 5, step 5, or any other suitable identifier), its corresponding correlation coefficient, and the wafers processed in batches at at least one processing node. This allows the user to centrally obtain the correlation coefficients and related wafer information corresponding to multiple processing nodes in a single view, facilitating the user's rapid identification of processing nodes with a high degree of correlation to wafer quality.

[0067] In some embodiments, a first information item among a plurality of information items may indicate at least a second processing node among one or more processing nodes, the second processing node being the starting processing node for splitting into the same sub-batch of wafers. In other words, the second processing node may be the processing node among one or more adjacent processing nodes where batch processing occurs first in the processing order. By indicating at least the second processing node in the first information item, the user can clearly know the processing node where batch processing first occurs within the same sub-batch of wafers. In this way, while retaining the possibility of other processing nodes, the first processing node of batch processing is highlighted, which helps the user quickly identify the processing node worthy of focus among a large number of processing nodes.

[0068] As an example, such as Figure 3As shown, relevance information presented in tabular form can include multiple information items, each corresponding to a row in the table. Multiple columns in the table can be used to indicate different aspects of each information item. For example... Figure 3 As shown, as an example, the table may include columns one through seven. The first column may be used to indicate the second processing node (i.e., the processing node where the first batch occurred) in the corresponding information item. The second column may be used to indicate the wafers with the first tag in the same sub-batch of wafers in the corresponding information item (i.e., the defective wafers in the same sub-batch of wafers).

[0069] The third column can be used to indicate all wafers in the same sub-batch within the corresponding information item. The fourth column can be used to indicate the relevance indicated by the corresponding information item, such as the relevance coefficient corresponding to that relevance. The fifth column can be used to indicate one or more processing nodes traversed by the wafers in the same sub-batch within the corresponding information item. The sixth column can be used to indicate the number of wafers with the first tag in the same sub-batch within the corresponding information item. The seventh column can be used to indicate the total number of all wafers in the same sub-batch within the corresponding information item. It should be understood that the above column numbers and their order are merely illustrative, and the current solution is not limited thereto.

[0070] The analysis results are illustrated below using information item 320 as an example. Information item 320 corresponds to the case where the first batch processing node is node 50, and its corresponding sub-batch wafer (an example of the third sub-batch wafer) subsequently passes through processing node 51. The third sub-batch wafer includes 4 wafers, 3 of which are wafers with the first label (numbered 9, 15, and 20), and the remaining 1 is a wafer with the second label (numbered 21). At this time, the first number and the second number are the same (i.e., both are 3), but the first number is less than the total number, and the correlation coefficient can be determined to be 0.75 according to the aforementioned formula.

[0071] In some embodiments, if the electronic device 110 receives a trigger operation on a first information item among a plurality of information items, it can present a first view corresponding to the first information item. The first view is used to display the relevance of one or more processing nodes. In some examples, the relevance can be displayed in the first view through a second correlation coefficient or other numerical results.

[0072] In some embodiments, the triggering operation may include, but is not limited to, clicking, long-pressing, hovering, or selecting a row in the table. Upon receiving a triggering operation for a row in the table (i.e., the corresponding information item), the electronic device 110 may display a first view corresponding to that information item. For example, referring to... Figure 3 and Figures 4A to 4BIf the electronic device 110 receives a trigger operation on the information item 320, it can present views 400A and 400B.

[0073] As an example, Figure 4A View 400A is shown to illustrate the correlation between processing node 50 and the quality of sub-batch wafers. (As shown) Figure 4A As shown, view 400A can visualize the master batch wafer 411 and the sub-batch wafer 412 (which is an example of the same sub-batch wafer) formed by batch processing at processing node 50. In view 400A, the vertical axis can be used to indicate the wafer label (e.g., good or bad), and the horizontal axis can be used to indicate the corresponding batch (e.g., master batch or sub-batch).

[0074] Reference Figure 4A The electronic device 110 can display element 415 corresponding to the sub-batch wafer 412. Element 415 can indicate the total number of wafers included in the sub-batch wafer 412 (e.g., 4) and its corresponding correlation coefficient (e.g., 0.75). Accordingly, the electronic device 110 can display element 416 corresponding to the parent batch wafer 411 to which the sub-batch wafer 412 corresponds. Element 416 indicates the total number of wafers included in the parent batch wafer 411 and its corresponding correlation coefficient (e.g., 0).

[0075] In some embodiments, Figure 4B View 400B is shown to display the correlation coefficients corresponding to processing node 51. (Example) Figure 4B As shown, view 400B, in addition to showing the mother batch wafer 411 and the daughter batch wafer 412, may also show another daughter batch wafer, such as daughter batch wafer 413, corresponding to processing node 51. As an example, at processing node 50, the batch processing may include daughter batch wafer 412. At processing node 51, the batch processing may include two daughter batch wafers, daughter batch wafer 412 and daughter batch wafer 413. Daughter batch wafer 413 may, for example, include one wafer and is a wafer with a second label. In some examples, electronic device 110 may present element 425 corresponding to daughter batch wafer 413. Element 425 may indicate the total number of wafers included in daughter batch wafer 413 (e.g., 1) and its corresponding correlation coefficient (e.g., 0).

[0076] Through the linked presentation between the aforementioned triggering operation and the first view, users can quickly select the sub-results of interest from multiple sub-results presented in tabular form, and view the correlation between batch processing and wafer quality at one or more processing nodes within that sub-result in a visual format. This allows users to interpret the analysis results more intuitively.

[0077] In some embodiments, multiple information items can be arranged in descending order of their relevance, so that users can quickly identify the processing nodes with higher relevance from among the multiple information items. It should be understood that the above order is given only as an example, and the current solution does not limit the specific presentation order.

[0078] In some embodiments, at multiple processing nodes that are adjacent in the processing sequence, if each corresponds to the same sub-batch wafer, the degree of correlation between these processing nodes and the quality of the same sub-batch wafer may not be exactly the same. For example, even if the same sub-batch wafer is the same at multiple adjacent processing nodes, the specific content of at least one sub-batch wafer may differ at different processing nodes within the multiple adjacent processing nodes (e.g., some processing nodes may have other sub-batch wafers besides the same sub-batch wafer), and therefore their corresponding degrees of correlation may differ. In this case, when presented in the same information item, several adjacent processing nodes can be listed adjacent to each other in the fifth column, and the corresponding degree of correlation can be presented in an appropriate manner, such as the maximum value, average value, or correlation coefficient corresponding to the second processing node among the multiple adjacent processing nodes. The current scheme does not limit the specific merging method.

[0079] In summary, this approach can quantitatively characterize the correlation between batch processing and wafer quality at each processing node using correlation coefficients. This allows for the automatic identification of processing nodes with a high correlation to wafer quality. Furthermore, this scheme can identify potential influencing factors introduced by batch processing that are difficult to reflect using single-dimensional data, thereby improving the accuracy of identifying the correlation between processing nodes and wafer quality anomalies. Consequently, it reduces the time required for manual investigation across a large number of processing nodes. This enables automated tracing of common batch characteristics in low-yield or high-defect cases.

[0080] It should be understood that although the above examples are illustrated using semiconductor wafer manufacturing processes, the solutions disclosed herein can be used in any manufacturing process that involves a distinction between master batch wafers and daughter batch wafers and includes multiple processing nodes.

[0081] Figure 5 A block diagram of an electronic device 500 in which one or more embodiments of the present disclosure may be implemented is shown. It should be understood that... Figure 5 The electronic device 500 shown is merely exemplary and should not be construed as limiting the functionality and scope of the embodiments described herein. Figure 5 The electronic device 500 shown can be used to achieve Figure 1 Electronic devices 110.

[0082] like Figure 5As shown, electronic device 500 is in the form of a general-purpose electronic device. Components of electronic device 500 may include, but are not limited to, one or more processors 510 or processing units, memory 520, storage device 530, one or more communication units 540, one or more input devices 550, and one or more output devices 560. Processor 510 may be a physical or virtual processor and is capable of performing various processes according to programs stored in memory 520. In a multiprocessor system, multiple processors execute computer-executable instructions in parallel to improve the parallel processing capability of electronic device 500.

[0083] Electronic device 500 typically includes multiple computer storage media. Such media can be any accessible media that is accessible to electronic device 500, including but not limited to volatile and non-volatile media, removable and non-removable media. Memory 520 can be volatile memory (e.g., registers, cache, random access memory (RAM)), non-volatile memory (e.g., read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory), or some combination thereof. Storage device 530 can be removable or non-removable media and can include machine-readable media, such as flash drives, disks, or any other media that can be used to store information and / or data and can be accessed within electronic device 500.

[0084] Electronic device 500 may further include additional removable / non-removable, volatile / non-volatile storage media. Although not explicitly stated... Figure 5 As shown, disk drives for reading from or writing to removable, non-volatile disks (e.g., "floppy disks") and optical disk drives for reading from or writing to removable, non-volatile optical disks can be provided. In these cases, each drive can be connected to a bus (not shown) via one or more data media interfaces. Memory 520 may include computer program product 525 having one or more program modules configured to perform various methods or actions of various embodiments of this disclosure.

[0085] Communication unit 540 enables communication with other electronic devices via a communication medium. Additionally, the functionality of components of electronic device 500 can be implemented using a single computing cluster or multiple computing machines capable of communicating via communication connections. Therefore, electronic device 500 can operate in a networked environment using logical connections to one or more other servers, network personal computers (PCs), or another network node.

[0086] Input device 550 can be one or more input devices, such as a mouse, keyboard, trackball, etc. Output device 560 can be one or more output devices, such as a monitor, speaker, printer, etc. Electronic device 500 can also communicate with one or more external devices (not shown) via communication unit 540 as needed. These external devices include storage devices, display devices, etc., and can communicate with one or more devices that enable user interaction with electronic device 500, or with any device that enables electronic device 500 to communicate with one or more other electronic devices (e.g., network card, modem, etc.). Such communication can be performed via input / output (I / O) interface (not shown).

[0087] According to an exemplary implementation of this disclosure, a computer-readable storage medium is provided that stores computer-executable instructions thereon, wherein the computer-executable instructions are executed by a processor to implement the methods described above. According to an exemplary implementation of this disclosure, a computer program product is also provided, which is tangibly stored on a non-transitory computer-readable medium and includes computer-executable instructions, which are executed by a processor to implement the methods described above.

[0088] Various aspects of this disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatuses, devices, and computer program products implemented according to this disclosure. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0089] These computer-readable program instructions can be provided to a processing unit of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that, when executed by the processing unit of the computer or other programmable data processing apparatus, they create means for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner. Thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing aspects of the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0090] Computer-readable program instructions can be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions that execute on the computer, other programmable data processing apparatus, or other device to perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0091] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction, which contains one or more executable instructions for implementing the specified logical function. In some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0092] Various implementations of this disclosure have been described above. The foregoing description is exemplary and not exhaustive, nor is it limited to the disclosed implementations. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described implementations. The terminology used herein is chosen to best explain the principles, practical applications, or improvements to technology in the market, or to enable others skilled in the art to understand the various implementations disclosed herein.

Claims

1. A correlation analysis method, comprising: Obtain batch information related to multiple wafers, the batch information indicating that the multiple wafers are processed in batches at multiple processing nodes in the production process, and the multiple wafers each have a corresponding label indicating wafer quality; Based on the batch information and corresponding tags associated with the multiple wafers, the correlation between each processing node and wafer quality is determined; and Provide correlation information indicating the degree of correlation between at least one of the plurality of processing nodes and the quality of the sub-batch wafers.

2. The method of claim 1, wherein determining the correlation between each processing node and wafer quality comprises: In response to the batch information indicating that the batch processing does not exist at the first processing node, it is determined that the first processing node is not related to wafer quality; or In response to the batch information indicating the presence of the batch processing at the first processing node, a first correlation between the first processing node and the wafer quality is determined based on the corresponding tags of each wafer that has undergone the batch processing at the first processing node.

3. The method of claim 2, wherein each wafer processed in the batch at the first processing node comprises at least one sub-batch wafer, and determining a first correlation between the first processing node and the wafer quality based on the corresponding tags of each wafer processed in the batch at the first processing node includes: From the at least one sub-batch of wafers, a first sub-batch of wafers is determined, the first sub-batch of wafers including wafers with a first label, the first label indicating that the quality of the corresponding wafer is less than a preset quality threshold; as well as The first degree of correlation is determined based on information related to the number of wafers in the first sub-batch.

4. The method of claim 3, wherein the number of wafers having the first label included in the first sub-batch wafers is greater than the number of wafers having the first label included in at least one second sub-batch wafer in the at least one sub-batch wafers, and the at least one second sub-batch wafer is different from the first sub-batch wafer.

5. The method of claim 3, wherein determining the first degree of correlation based on information related to the number of wafers in the first sub-batch comprises: The first number of wafers with the first tag in the first sub-batch is compared with the second number of wafers with the first tag in the plurality of wafers; as well as Based on the results of the comparison and the total number of wafers in the first sub-batch, the first degree of correlation is determined.

6. The method of claim 5, wherein determining the first correlation degree based on the result of the comparison and the total number of wafers in the first sub-batch comprises: In response to the first number and the second number being the same, the first correlation degree is determined based on the first number and the total number.

7. The method of claim 5, wherein determining the first degree of correlation based on the result of the comparison and the total number of wafers in the first sub-batch comprises: In response to the difference between the first number and the second number, a first ratio is determined based on the first number and the second number; The correction parameter is determined based on the difference between the first number and the total number; as well as The first correlation degree is determined based on the first ratio and the correction parameter.

8. The method of claim 1, wherein providing the correlation information comprises: The processing order of the plurality of processing nodes is determined based on the start time of at least one of the plurality of wafers being processed at the plurality of processing nodes. as well as The correlation information is provided based on the processing order and the batch information.

9. The method of claim 8, wherein providing the correlation information comprises: Multiple information items are presented, one of which corresponds to the same sub-batch of wafers. These wafers have passed through one or more processing nodes, and the corresponding information item indicates the degree of correlation between the quality of the one or more processing nodes and the quality of the same sub-batch of wafers. The one or more processing nodes mentioned therein are adjacent processing nodes determined based on the processing order.

10. The method of claim 9, further comprising: In response to a trigger operation on a first information item among the plurality of information items, a first view corresponding to the first information item is presented, the first view being used to display the degree of relevance corresponding to the one or more processing nodes.

11. The method of claim 1, wherein the label of each of the plurality of wafers is determined based on a quality indicator of the wafer, the quality indicator including at least one of yield, number of defects, and test parameters.

12. The method of claim 1, wherein for each of the plurality of wafers, the batch information indicates at least one of the following: The corresponding processing time for the wafer at the multiple processing nodes. The corresponding process formulations used to process the wafer at the multiple processing nodes. The wafer passes through the corresponding machines at the multiple processing nodes, or The wafer passes through the corresponding chambers during processing at the multiple processing nodes.

13. An electronic device, comprising: At least one processor; as well as At least one memory coupled to the at least one processor and storing instructions for execution by the at least one processor, the instructions causing the electronic device to perform the method according to any one of claims 1 to 12 when executed by the at least one processor.

14. A computer-readable storage medium having stored thereon computer-executable instructions that can be executed by a processor to implement the method according to any one of claims 1 to 12.

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