A display panel and display device

Abstract

This application provides a display panel and a display device. The display panel includes a display area and a non-display area. The display area includes a first straight edge area and a second straight edge area, the extending directions of which intersect. The non-display area includes a first non-display area and a second non-display area, the first non-display area being located on one side of the first straight edge area and the second non-display area being located on one side of the second straight edge area. The first non-display area includes a first bending area and a first circuit setting area, the first bending area connecting the display area and the first circuit setting area, and the first circuit setting area being bent to the non-light-emitting side of the display panel through the first bending area. The second non-display area includes a second bending area, a portion of which is bent to the non-light-emitting side of the display panel. In this application, by setting a first circuit setting area in the first display area, at least a portion of the circuit structure can be set in the first circuit setting area and bent to the non-light-emitting side of the display panel, thus achieving a narrow bezel design for the display panel.

Description

Technical Field

[0001] This application relates to the field of display panel technology, and more particularly to a display panel and a display device. Background Technology

[0002] With the development of display technology, various display technologies have emerged, and various display devices have been developed, including liquid crystal display panels, organic light-emitting display panels, plasma display panels, and electrophoretic display panels.

[0003] The display panel includes a display area and a non-display area. The non-display area is located on at least one side of the display area. The non-display area may be equipped with a driving circuit to drive the light-emitting elements in the display area to emit light.

[0004] As display technology continues to develop, the driving circuits located in the non-display area become increasingly complex and occupy a larger and larger area, which makes it difficult to achieve a narrow bezel design for the display panel. Summary of the Invention

[0005] This application provides a display panel and a display device. By setting bending areas in both the adjacent first and second non-display areas and bending the bending areas to the non-light-emitting side of the display panel, a narrow bezel design of the display panel can be achieved, thereby increasing the screen-to-body ratio.

[0006] In a first aspect, embodiments of this application provide a display panel, including a display area and a non-display area; The display area includes a first straight edge area and a second straight edge area, the first straight edge area extending along a first direction and the second straight edge area extending along a second direction; the first direction and the second direction intersect. The non-display area includes a first non-display area and a second non-display area, wherein the first non-display area is located on one side of the first straight edge area and the second non-display area is located on one side of the second straight edge area; The first non-display area includes a first bending area and a first circuit setting area. The first bending area connects the display area and the first circuit setting area, and the first circuit setting area is bent to the non-light-emitting side of the display panel through the first bending area. The second non-display area includes a second bending area, a portion of which bends to the non-light-emitting side of the display panel.

[0007] Secondly, embodiments of this application provide a display panel, including a display area and a non-display area; The display area includes a first straight edge area and a second straight edge area, the first straight edge area extending along a first direction and the second straight edge area extending along a second direction; the first direction and the second direction intersect. The non-display area includes a first non-display area and a second non-display area, wherein the first non-display area is located on one side of the first straight edge area and the second non-display area is located on one side of the second straight edge area; The first non-display area includes a first bend area and a first circuit setting area, wherein the first bend area connects the display area and the first circuit setting area; The second non-display area includes the second bend area.

[0008] Thirdly, embodiments of this application provide a display device, including the display panel described in the first and second aspects.

[0009] In summary, the display panel provided in this application embodiment has bending areas set in two non-display areas that intersect in the extension direction, and both bending areas are bent to the non-light-emitting side of the display panel. This enables a narrow bezel design for the display panel and increases the display area ratio. Furthermore, the first non-display area also includes a first circuit setting area, which can house a driving circuit. The first circuit setting area is bent to the non-light-emitting side of the display panel through the first bending area. This allows the first circuit setting area and the driving circuit, originally located on the light-emitting side of the display panel, to be located on the non-light-emitting side, further achieving a narrow bezel design and increasing the display area ratio. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments of this application will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on the content of the embodiments of this application and these drawings without creative effort.

[0011] Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application; Figure 2 This is a schematic diagram of another display panel structure provided in an embodiment of this application; Figure 3 This is a schematic diagram of the structure of another display panel provided in the embodiments of this application; Figure 4 This is a schematic diagram of the structure of a first non-display area provided in an embodiment of this application; Figure 5 This is a schematic diagram of another structure of the first non-display area provided in an embodiment of this application; Figure 6 This is a schematic diagram of another structure of the first non-display area provided in the embodiments of this application; Figure 7This is a schematic diagram of another display panel structure provided in an embodiment of this application; Figure 8 yes Figure 7 Enlarged view of region a in the middle; Figure 9 yes Figure 8 A schematic diagram of the structure of the first drive transmission subunit; Figure 10 yes Figure 8 A schematic diagram of the structure of the second drive transmission subunit; Figure 11 yes Figure 8 A schematic diagram of the structure of the third drive transmission subunit; Figure 12 This is a schematic diagram of another display panel structure provided in an embodiment of this application; Figure 13 yes Figure 12 Enlarged view of region b in the middle; Figure 14 This is a schematic diagram of the structure of a first circuit setting area provided in an embodiment of this application; Figure 15 This is a schematic diagram of another structure of the first circuit setting area provided in an embodiment of this application; Figure 16 This is a schematic diagram of another structure of the first circuit setting area provided in the embodiments of this application; Figure 17 This is a schematic diagram of another structure of the first circuit setting area provided in the embodiments of this application. Figure 18 This is a schematic diagram of another display panel structure provided in an embodiment of this application; Figure 19 This is a schematic diagram of another structure of the first non-display area provided in an embodiment of this application; Figure 20 This is a schematic diagram of the structure of another display panel provided in the embodiments of this application; Figure 21 This is a schematic diagram of the structure of a first shift output signal line provided in an embodiment of this application; Figure 22 This is a schematic diagram of the circuit structure of a pixel circuit provided in an embodiment of this application; Figure 23 yes Figure 22 The driving timing diagram corresponding to the pixel circuit shown is shown. Figure 24 This is a schematic diagram of the film structure of a pixel circuit provided in an embodiment of this application; Figure 25 This is a schematic diagram of the film layer structure of a display panel provided in an embodiment of this application; Figure 26This is a schematic diagram of the structure of a display panel display area provided in an embodiment of this application; Figure 27 This is a schematic diagram of another structure of the first circuit setting area provided in an embodiment of this application; Figure 28 This is a schematic diagram of another structure of the first circuit setting area provided in the embodiments of this application; Figure 29 This is a schematic diagram of another first circuit setting area provided in an embodiment of this application; Figure 30 This is a schematic diagram of another structure of the first circuit setting area provided in an embodiment of this application; Figure 31 This is a schematic diagram of another structure of the first circuit setting area provided in the embodiments of this application; Figure 32 This is a schematic diagram of another display panel structure provided in an embodiment of this application; Figure 33 This is a schematic diagram of the structure of a first bending region provided in an embodiment of this application; Figure 34 This is a schematic diagram of another structure of the first bending region provided in an embodiment of this application; Figure 35 This is a schematic diagram of another structure of the first bending region provided in an embodiment of this application; Figure 36 This is a schematic diagram of another first bending region provided in an embodiment of this application; Figure 37 This is a schematic diagram of another structure of the first bending region provided in an embodiment of this application; Figure 38 This is a schematic diagram of another display panel structure provided in an embodiment of this application; Figure 39 This is a schematic diagram of the structure of another display panel provided in the embodiments of this application; Figure 40 This is a schematic diagram of another display panel structure provided in an embodiment of this application; Figure 41 yes Figure 1 An enlarged cross-sectional view of the provided display panel along section line A-A'; Figure 42 This is a schematic diagram of another display panel structure provided in an embodiment of this application; Figure 43 This is a schematic diagram of the structure of another display panel provided in the embodiments of this application; Figure 44 This is a schematic diagram of another display panel structure provided in an embodiment of this application; Figure 45This is a schematic diagram of another display panel structure provided in an embodiment of this application; Figure 46 This is a schematic diagram of the structure of another display panel provided in the embodiments of this application; Figure 47 This is a schematic diagram of another display panel structure provided in an embodiment of this application; Figure 48 This is a schematic diagram of another display panel structure provided in an embodiment of this application; Figure 49 This is a schematic diagram of the structure of another display panel provided in the embodiments of this application; Figure 50 This is a schematic diagram of another display panel structure provided in an embodiment of this application; Figure 51 This is a schematic diagram of another display panel structure provided in an embodiment of this application; Figure 52 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. Detailed Implementation

[0012] The present application will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the application and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present application, not the entire structure.

[0013] In the description of this application, unless otherwise expressly specified and limited, the terms "connected," "linked," and "fixed" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0014] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0015] In the description of this embodiment, the terms "upper," "lower," "right," etc., refer to the orientation or positional relationship shown in the accompanying drawings. They are used only for ease of description and simplification of operation, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. In addition, the terms "first" and "second" are used only for distinction in description and have no special meaning.

[0016] Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application, specifically a schematic diagram of the structure of the first non-display area and the second non-display area in an unfolded state; Figure 2 This is a schematic diagram of another display panel structure provided in the embodiments of this application, specifically a schematic diagram of the light-emitting surface after the first non-display area and the second non-display area are bent; Figure 3 This is a schematic diagram of another display panel structure provided in the embodiments of this application, specifically a schematic diagram of the non-light-emitting surface of the first non-display area and the second non-display area after bending. Combined with... Figures 1-3 As shown, the display panel provided in this embodiment includes a display area AA and a non-display area NAA; the display area AA includes a first straight edge area AA1 and a second straight edge area AA2, the first straight edge area AA1 extends along a first direction (the X direction shown in the figure, which will be used as an example in the following description), and the second straight edge area AA2 extends along a second direction (the Y direction shown in the figure, which will be used as an example in the following description); the first direction X and the second direction Y intersect; the non-display area NAA includes a first non-display area NAA1 and a second non-display area NAA2. The first non-display area NAA1 is located on one side of the first straight edge area AA1, and the second non-display area NAA2 is located on one side of the second straight edge area AA2. The first non-display area NAA1 includes a first bending area BA1 and a first circuit setting area CSA1. The first bending area BA1 connects the display area AA and the first circuit setting area CSA1, and the first circuit setting area CSA1 is bent to the non-light emitting side of the display panel through the first bending area BA1. The second non-display area NAA2 includes a second bending area BA2, and a portion of the second bending area BA2 is bent to the non-light emitting side of the display panel.

[0017] like Figures 1-3 As shown, the display panel includes a display area AA and a non-display area NAA, with the non-display area NAA at least partially surrounding the display area AA.

[0018] The display area AA may include multiple sub-pixels and multiple display signal lines; each sub-pixel may include electrically connected light-emitting elements and pixel circuits. Furthermore, the light-emitting elements may include light-emitting elements of different colors, such as at least one of red, green, blue, or white light-emitting elements, to achieve a color display effect on the display panel. Moreover, the light-emitting element may be an organic light-emitting diode (OLED), a micro-OLED, or a micro-LED. Taking an OLED as an example, the light-emitting element may include a first electrode, a second electrode, and an organic compound layer located between the first and second electrodes. The organic compound layer may include a hole injection layer, a hole transport layer, an electron blocking layer, a light-emitting layer, an electron transport layer, a hole blocking layer, and an electron injection layer, but is not limited thereto. Alternatively, the organic compound layer may also include a charge-generating layer, such as a P-type charge-generating layer and an N-type charge-generating layer. When a voltage is applied to the first and second electrodes of the OLED, holes passing through the hole transport layer and electrons passing through the electron transport layer move to the light-emitting layer to form excitons, causing visible light to be emitted from the light-emitting layer. The pixel circuit may include a driving transistor that supplies current to the light-emitting element, one or more switching transistors that switch the current path between the driving transistor and the light-emitting element, and a capacitor that maintains the voltage between the gate and source of the driving transistor. The pixel circuit may, for example, be a "2T1C", "7T1C", or "8T1C" structure, where "T" represents a transistor and "C" represents a capacitor. The display signal lines may include, for example, at least one of scan signal lines and data signal lines.

[0019] Display area AA includes a first straight edge area AA1 and a second straight edge area AA2. The first straight edge area AA1 and the second straight edge area AA2 can be understood as two sub-regions within display area AA whose boundaries include straight lines. Furthermore, the first straight edge area AA1 extends along a first direction X, and the second straight edge area AA2 extends along a second direction Y. That is, the first straight edge area AA1 and the second straight edge area AA2 are two straight edge areas whose extension directions intersect. For example, the first straight edge area AA1 can be the display area near the left edge of display area AA, and the second straight edge area AA2 can be the display area near the bottom edge of display area AA; or, the first straight edge area AA1 can be the display area near the right edge of display area AA, and the second straight edge area AA2 can be the display area near the bottom edge of display area AA; or, the first straight edge area AA1 can be the display area near the left edge of display area AA, and the second straight edge area AA2 can be the display area near the top edge of display area AA; or, the first straight edge area AA1 can be the display area near the right edge of display area AA, and the second straight edge area AA2 can be the display area near the top edge of display area AA. Correspondingly, the non-display area NAA includes a first non-display area NAA1 and a second non-display area NAA2. In the unbent state of the first non-display area NAA1, that is, in its unfolded state, along the second direction Y, the first non-display area NAA1 is located on the side of the first straight edge area AA1 furthest from the center of the display area AA. The second non-display area NAA2 is located on one side of the second straight edge area AA2. In the unbent state of the second non-display area NAA2, that is, in its unfolded state, along the first direction X, the second non-display area NAA2 is located on the side of the second straight edge area AA2 furthest from the center of the display area AA. Here, the center of the display area AA can be understood as the geometric center or the centroid of the display area AA. Based on this, the first non-display area NAA1 includes a first bending area BA1 and a first circuit setting area CSA1. The first bending area BA1 connects the display area AA and the first circuit setting area CSA1. The first bending area BA1 is a bendable region, and the first circuit setting area CSA1 is bent to the non-light-emitting side of the display panel through the first bending area BA1. Thus, viewed from the light-emitting side of the display panel, because a portion of the first non-display area NAA1 is bent to the non-light-emitting side of the display panel, the bezel area of ​​the display panel can be reduced, which is beneficial for achieving a narrow bezel design and increasing the area ratio of the display area AA. Similarly, the second non-display area NAA2 includes a second bending area BA2. The second bending area BA2 is a bendable region, so a portion of the second bending area BA2 can be bent to the non-light-emitting side of the display panel, which also reduces the bezel area of ​​the display panel, is beneficial for achieving a narrow bezel design and increasing the area ratio of the display area AA.

[0020] In this embodiment of the application, the setting of the first non-display area NAA1 also includes a first circuit setting area CSA1. The first circuit setting area CSA1 can be equipped with a driving circuit, such as a gate driving circuit. The first circuit setting area CSA1 is bent along the first bending area BA1 to the non-light emitting side of the display panel. Thus, the driving circuit set in the first circuit setting area CSA1 will be bent to the non-light emitting side of the display panel and will not occupy the area of ​​the light emitting side of the display panel, thereby further increasing the area ratio of the display area AA.

[0021] It should be noted that the bending area extending to the non-light-emitting side of the display panel can be divided according to the location of the bending axis. Along the orthogonal direction of the bending axis, the bending area on one side of the bending axis bends to the non-light-emitting side of the display panel, while the bending area on the other side remains on the light-emitting side. Therefore, the partial bending of the second bending area BA2 to the non-light-emitting side of the display panel can be understood as the second bending area BA2 on one side of the bending axis bending to the non-light-emitting side of the display panel, while the second bending area BA2 on the other side of the bending axis does not bend to the non-light-emitting side and remains on the light-emitting side of the display panel.

[0022] In summary, the display panel provided in this application embodiment has bending areas set in two non-display areas that intersect in the extension direction, and both bending areas are bent to the non-light-emitting side of the display panel. This enables a narrow bezel design for the display panel and increases the display area ratio. Furthermore, the first non-display area also includes a first circuit setting area, which can house a driving circuit. The first circuit setting area is bent to the non-light-emitting side of the display panel through the first bending area. This allows the first circuit setting area and the driving circuit, originally located on the light-emitting side of the display panel, to be located on the non-light-emitting side, further enabling a narrow bezel design and increasing the display area ratio.

[0023] For example, continue to refer to Figure 1 and Figure 2 As shown, along the first direction X, the extension length of the first bending region BA1 is less than or equal to the extension length of the first straight side region AA1.

[0024] like Figures 1-3 As shown, the extension length of the first bending area BA1 is less than or equal to the extension length of the first straight side area AA1. That is, after the first bending area BA1 bends to the non-light-emitting side of the display panel, it will not exceed the coverage of the display area. The setting of the first bending area BA1 will not increase the area of ​​the display panel, thus ensuring the miniaturization design of the display panel.

[0025] For example, continue to refer to Figure 1 and Figure 2As shown, along the second direction Y, the extension length of the second bending region BA2 is less than or equal to the extension length of the second straight edge region AA2.

[0026] like Figures 1-3 As shown, the extension length of the second bending area BA2 is less than or equal to the extension length of the second straight edge area AA2. That is, after the second bending area BA2 bends to the non-light-emitting side of the display panel, it will not exceed the coverage of the display area. The setting of the second bending area BA2 will not increase the area of ​​the display panel, thus ensuring the miniaturization design of the display panel.

[0027] For example, continue to refer to Figure 1 and Figure 2 As shown, the extension length of the first straight edge region AA1 in the first direction X is greater than the extension length of the second straight edge region AA2 in the second direction Y.

[0028] like Figures 1-3 As shown in the embodiment of this application, the extension length of the first straight edge area AA1 in the first direction X is greater than the extension length of the second straight edge area AA2 in the second direction Y. That is, the first straight edge area AA1 can be a long edge display area, such as the left and / or right bezel display areas of the display panel, and the second straight edge area AA2 can be a short edge display area, such as the top and / or bottom bezel display areas of the display panel. In this embodiment of the application, bending areas are provided in both the long and short edge display areas, and the bending areas of both the long and short edge display areas are bent to the non-light-emitting side of the display panel, which can further realize the narrow bezel design of the display panel and further increase the display area ratio of the display panel.

[0029] For example, Figure 4 This is a structural schematic diagram of a first non-display area provided in an embodiment of this application, specifically a structural schematic diagram of the first non-display area in its unfolded state, and a structural schematic diagram of the non-display area to the left of the display area. For example... Figure 4 As shown, the first non-display area NAA1 also includes a functional area FA and a first bonding area BAA1. The functional area FA includes a first circuit setting area CSA1, and the first bonding area BAA1 is located on the side of the functional area FA away from the first bending area BA1. The display panel also includes a plurality of first type signal bonding terminals 11 and a plurality of signal lines 12. The first type signal bonding terminals 11 are disposed in the first bonding area BAA1. The signal lines 12 are disposed in the functional area FA and are electrically connected to the first type signal bonding terminals 11.

[0030] like Figure 4As shown, the first non-display area NAA1 also includes a functional area FA. The functional area FA can be understood as the area between the first bending area BA1 and the first bonding area BAA1. The functional area FA includes the aforementioned first circuit setting area CSA1 and includes an area for setting signal lines 12. For example, the first bonding area BAA1 is provided with multiple first-type signal bonding terminals 11, which are the bonding terminals set in the first non-display area NAA1. The first-type signal bonding terminals 11 are used for electrical connection with the flexible circuit board set in the first non-display area NAA1, for receiving signals provided by the flexible circuit board, and for transmitting the signals to the signal lines 12 set in the first non-display area NAA1. Thus, through the arrangement of the first-type signal bonding terminals 11 and the signal lines 12, signal input can be achieved from the left and / or right bezels of the display panel, improving the flexibility of signal input.

[0031] Specifically, signal line 12 may include DC signal lines, and / or, signal lines may include AC signal lines. For example, DC signal lines may include at least one of power signal lines, level signal lines, and initialization signal lines; and / or, AC signal lines may include at least one of clock signal lines, start signal lines, reset signal lines, and touch signal lines.

[0032] Specifically, the signal line located in the first non-display area NAA1 can be a DC signal line, an AC signal line, or both. Since the signal line 12 is electrically connected to the first type of signal bonding terminal 11, the signal provided by the first type of signal bonding terminal 11 can include DC signals and / or AC signals, or in other words, the first type of signal bonding terminal 11 can include DC signal terminals and / or AC signal terminals.

[0033] For example, the DC signal line may include a power signal line, such as at least one of a first power signal line PVDD and a second power signal line PVEE. The first power signal line PVDD is used to provide a first power signal to the pixel circuit disposed in the display area, and the second power signal line PVEE is used to provide a second power signal to the cathode of the light-emitting element disposed in the display area. The DC signal line may also be a level signal line, such as at least one of a high-level signal line VGH and a low-level signal line VGL. Both the high-level signal line VGH and the low-level signal line VGL are used to provide a level signal to the gate driving circuit disposed in the first circuit setting area CSA1. The DC signal line may also be an initialization signal line, such as a gate initialization signal line that controls the initialization of the gate of the driving transistor in the pixel circuit in the display area AA; a reset initialization signal line that controls the reset of the anode of the light-emitting element in the display area AA; or a bias adjustment initialization signal line that controls the bias adjustment of the first terminal of the driving transistor in the pixel circuit in the display area AA.

[0034] For example, the AC signal lines may include clock signal lines, such as the CK clock signal line and / or the XCK clock signal line. The CK clock signal line and / or the XCK clock signal line are both used to provide clock signals to the gate drive circuit located in the first circuit setting area CSA1. The AC signal lines may also be start signal lines, used to provide start signals to the gate drive circuit located in the first circuit setting area CSA1. The AC signal lines may also be reset signal lines, used to provide reset signals to the gate drive circuit located in the first circuit setting area CSA1. Furthermore, the AC signal lines may also be touch signal lines, used to provide touch signals to the touch electrodes located in the display area AA.

[0035] In summary, the signal lines located in the first non-display area NAA1 can include multiple signal lines transmitting different signals. Correspondingly, the first type of signal bonding terminal 11 can include multiple signal bonding terminals outputting different signals. The specific configuration types of the first type of signal bonding terminal 11 and the signal lines 12, as well as the signals transmitted, can be flexibly configured according to actual needs.

[0036] Continue to refer to Figure 4 As shown, the display panel also includes a gate drive circuit 13 and a gate drive signal line 14 disposed in the first circuit setting area CSA1. The gate drive signal line 14 is electrically connected to the gate drive circuit 13. The signal line 12 includes the gate drive signal line 14, which includes at least one of a level signal line, a clock signal line, a start signal line, and a reset signal line.

[0037] like Figure 4As shown, the display panel also includes a gate driving circuit 13 and a gate driving signal line 14 disposed in the first circuit setting area CSA1. The gate driving signal line 14 provides a gate driving signal to the gate driving circuit 13 to drive the gate driving circuit to output a scan signal to the scan signal line disposed in the display area AA, and output a light emission control signal to the light emission control signal line disposed in the display area AA, thereby realizing the normal operation of the pixel circuit disposed in the display area AA and ensuring the normal display function of the display panel. Furthermore, in this embodiment, both the gate driving circuit 13 and the gate driving signal line 14 are disposed in the first circuit setting area CSA1, and the first circuit setting area CSA1 is further bent to the non-light emitting side of the display panel. This can reduce the area ratio of the non-display area in the light emitting side of the display panel, increase the proportion of the central display area of ​​the display panel, and improve the display effect of the display panel.

[0038] For example, signal line 12 includes gate drive signal line 14, which includes at least one of a level signal line, a clock signal line, a start signal line, and a reset signal line. Specifically, the level signal line may include a high-level signal line VGH and / or a low-level signal line VGL, both of which are used to provide a level signal to the gate drive circuit 13 disposed in the first circuit setting area CSA1. The clock signal line may include a CK clock signal line and / or an XCK clock signal line, both of which are used to provide a clock signal to the gate drive circuit 13 disposed in the first circuit setting area CSA1. The start signal line is used to provide a start signal to the gate drive circuit 13 disposed in the first circuit setting area CSA1. The reset signal line is used to provide a reset signal to the gate drive circuit 13 disposed in the first circuit setting area CSA1. By setting the gate drive signal line 14 to include at least one of a level signal line, a clock signal line, a start signal line, and a reset signal line, the signals required for normal driving of the gate drive circuit 13 are satisfied.

[0039] In one embodiment, Figure 5 This is a schematic diagram of another structure of the first non-display area provided in an embodiment of this application. Figure 5 This is a structural diagram of the first non-display area in its unfolded state, and specifically a structural diagram of the non-display area to the left of the display area. (Combined with...) Figure 4 and Figure 5 As shown, signal line 12 includes power signal line 121 and initialization signal line 122; at least one of power signal line 121 and initialization signal line 122 is at least partially disposed in functional area FA between first circuit setting area CSA1 and first bending area BA1.

[0040] like Figure 4 and Figure 5As shown, in addition to the gate drive signal line 14, signal line 12 may also include a power signal line and an initialization signal line. Power signal line 121 includes at least one of a first power signal line PVDD and a second power signal line PVEE. The first power signal line PVDD provides a first power signal to the pixel circuit disposed in the display area, and the second power signal line PVEE provides a second power signal to the cathode of the light-emitting element disposed in the display area. Initialization signal line 122 includes a gate initialization signal line, a reset initialization signal line, and a bias adjustment initialization signal line. The gate initialization signal line initializes the gate of the driving transistor in the pixel circuit of the display area AA; the reset initialization signal line resets the anode of the light-emitting element in the display area AA; and the bias adjustment initialization signal line adjusts the bias of the first terminal of the driving transistor in the pixel circuit of the display area AA. Power signal line 121 and initialization signal line 122, as non-gate drive signal lines, can be disposed in the functional area FA, excluding the first circuit setting area CSA1. Figure 4 and Figure 5 As shown, at least one of the power signal line 121 and the initialization signal line 122 is at least partially disposed in the functional area FA between the first circuit setting area CSA1 and the first bend area BA1, wherein, Figure 4 Taking the functional area FA, which is at least partially located in the power signal line 121 between the first circuit setting area CSA1 and the first bend area BA1, as an example, this will be explained. Figure 5 The following explanation uses a functional area FA located between the first circuit setting area CSA1 and the first bending area BA1 as an example. By setting at least a portion of the power signal line 121 and at least a portion of the initialization signal line 122 in the functional area FA between the first circuit setting area CSA1 and the first bending area BA1, it is convenient for at least one of the power signal line 121 and the initialization signal line 122 to be electrically connected to the corresponding structure in the display area AA, ensuring that the connection method between at least one of the power signal line 121 and the initialization signal line 122 and the corresponding structure in the display area AA is simple.

[0041] In one embodiment, Figure 6 This is a schematic diagram of another structure of the first non-display area provided in the embodiments of this application. Figure 6 This is a structural diagram of the first non-display area in its unfolded state, and specifically a structural diagram of the non-display area to the left of the display area. (Combined with...) Figure 4 and Figure 6As shown, signal line 12 includes power signal line 121 and initialization signal line 122; at least one of power signal line 121 and initialization signal line 122 is at least partially disposed in functional area FA between first circuit setting area CSA1 and first binding area BAA1.

[0042] like Figure 4 and Figure 6 As shown, in addition to the gate drive signal line 14, signal line 12 may also include a power signal line 121 and an initialization signal line 122. Power signal line 121 includes at least one of a first power signal line PVDD and a second power signal line PVEE. The first power signal line PVDD provides a first power signal to the pixel circuit disposed in the display area, and the second power signal line PVEE provides a second power signal to the cathode of the light-emitting element disposed in the display area. Initialization signal line 122 includes a gate initialization signal line, a reset initialization signal line, and a bias adjustment initialization signal line. The gate initialization signal line initializes the gate of the driving transistor in the pixel circuit of the display area AA; the reset initialization signal line resets the anode of the light-emitting element in the display area AA; and the bias adjustment initialization signal line adjusts the bias of the first terminal of the driving transistor in the pixel circuit of the display area AA. Power signal line 121 and initialization signal line 122, as non-gate drive signal lines, can be disposed in the functional area FA, excluding the first circuit setting area CSA1. Figure 4 and Figure 6 As shown, at least one of the power signal line 121 and the initialization signal line 122 is at least partially disposed in the functional area FA between the first circuit setting area CSA1 and the first binding area BAA1, wherein, Figure 4 Taking the functional area FA, which is at least partially located in the initialization signal line 122 between the first circuit setting area CSA1 and the first binding area BAA1, as an example, this will be explained. Figure 6 The following explanation uses a functional area FA located between the first circuit setting area CSA1 and the first binding area BAA1 as an example. By setting at least a portion of the power signal line 121 and at least a portion of the initialization signal line 122 in the functional area FA between the first circuit setting area CSA1 and the first binding area BAA1, it is convenient for at least one of the power signal line 121 and the initialization signal line 122 to be further electrically connected to the first type of signal binding terminal 11. This facilitates the first type of signal binding terminal 11 to input a power signal to the power signal line 121 and an initialization signal to the initialization signal line 122, ensuring a simple connection method between at least one of the power signal line 121 and the initialization signal line 122 and the first type of signal binding terminal 11.

[0043] Continue to refer to Figure 4 , Figure 5 and Figure 6 As shown, for example, signal line 12 includes power signal line 121 and initialization signal line 122; power signal line 121 includes at least two layers of signal lines stacked and electrically connected, and / or, initialization signal line 122 includes at least two layers of signal lines stacked and electrically connected.

[0044] As described above, the power signal line 121 includes at least one of a first power signal line PVDD and a second power signal line PVEE. The first power signal line PVDD is used to provide a first power signal to the pixel circuit disposed in the display area, and the second power signal line PVEE is used to provide a second power signal to the cathode of the light-emitting element disposed in the display area. The initialization signal line 122 includes a gate initialization signal line, a reset initialization signal line, and a bias adjustment initialization signal line. The gate initialization signal line is used to initialize the gate of the driving transistor in the pixel circuit in the display area AA; the reset initialization signal line is used to reset the anode of the light-emitting element in the display area AA; and the bias adjustment initialization signal line is used to adjust the bias of the first terminal of the driving transistor in the pixel circuit in the display area AA.

[0045] For example, the power signal line 121 may include at least two layers of signal lines stacked and electrically connected, with these two layers connected in parallel. This reduces power signal loss during transmission, ensuring that the power signal can be transmitted more accurately from the first non-display area to the display area AA, thus guaranteeing the display effect of the display area. Similarly, the initialization signal line 122 may include at least two layers of signal lines stacked and electrically connected, with these two layers connected in parallel. This reduces initialization signal loss during transmission, ensuring that the initialization signal can be transmitted more accurately from the first non-display area to the display area, thus guaranteeing the display effect of the display area.

[0046] Continue to refer to Figure 4 , Figure 5 and Figure 6As shown, the display panel also includes a gate drive circuit 13 and a gate drive signal line 14 disposed in the first circuit setting area CSA1, the gate drive circuit 13 and the gate drive signal line 14 being electrically connected; the first non-display area NAA1 also includes a first bonding area BAA1, the first bonding area BAA1 being located on the side of the first circuit setting area CSA1 away from the first bending area BA1; the display panel also includes a first type of signal bonding terminal 11 disposed in the first bonding area BAA1, the first type of signal bonding terminal 11 including a first type of gate drive signal terminal 111, the first type of gate drive signal terminal 111 including a plurality of first gate drive signal terminals 1111 arranged along a first direction; the display panel also includes a first type of gate drive signal transmission section 15, the first type of gate drive signal transmission section 15 including a plurality of first gate drive signal transmission sections 151, the first gate drive signal transmission sections 151 being electrically connected to the first gate drive signal terminal 1111 and the gate drive signal line 14 respectively.

[0047] Combination Figure 4 , Figure 5 and Figure 6 As shown, the display panel also includes a gate driving circuit 13 and a gate driving signal line 14 disposed in the first circuit setting area CSA1. The gate driving signal line 14 is used to provide a gate driving signal to the gate driving circuit 13, so as to drive the gate driving circuit to output a scan signal to the scan signal line disposed in the display area AA, and output a light emission control signal to the light emission control signal line disposed in the display area AA, thereby realizing the normal operation of the pixel circuit disposed in the display area AA and ensuring the normal display function of the display panel. The first bonding area BAA1 is provided with a plurality of first type signal bonding terminals 11. The first type signal bonding terminals 11 are used to electrically connect with the flexible circuit board disposed in the first non-display area NAA1, and are used to receive the signal provided by the flexible circuit board and transmit the signal to the signal line 12 disposed in the first non-display area NAA1. Specifically, the first type of signal bonding terminal 11 includes a first type of gate drive signal terminal 111. The first type of gate drive signal terminal 111 includes a plurality of first gate drive signal terminals 1111 arranged along a first direction. The first gate drive signal terminal 1111 can be understood as a terminal for transmitting gate drive signals. The gate drive signals may include at least one of clock signals, level signals, initialization signals, and reset signals. Further, the display panel also includes a first type of gate drive signal transmission unit 15. The first type of gate drive signal transmission unit 15 includes a plurality of first gate drive signal transmission units 151. The first gate drive signal transmission units 151 are electrically connected to the first gate drive signal terminal 1111 and the gate drive signal line 14, respectively. In this way, the first gate drive signal terminal 1111 transmits the gate drive signal in the first gate drive signal terminal 1111 to the gate drive signal line 14, thereby realizing the normal transmission of the gate drive signal.

[0048] It should be noted that, Figure 4 , Figure 5 and Figure 6 The illustration only shows a portion of the first type signal bonding terminals 11, a portion of the first type gate drive signal terminals 111, a portion of the first gate drive signal terminals 1111, and a portion of the first type gate drive signal transmission units 15. In the actual structure of the display panel, more first type signal bonding terminals 11, more first type gate drive signal terminals 111, more first gate drive signal terminals 1111, and more first type gate drive signal transmission units 15 can be provided as needed. The embodiments of this application do not limit the number of first type signal bonding terminals 11, first type gate drive signal terminals 111, first gate drive signal terminals 1111, and first type gate drive signal transmission units 15 provided in the first non-display area NAA.

[0049] Further reference Figure 4 , Figure 5 and Figure 6 As shown, the gate drive circuit 13 includes at least two columns of shift register circuits, each column including a multi-stage shift register circuit VSR arranged along the first direction X; the first gate drive signal transmission section 15 extends along the second direction Y, and at least a portion of the first gate drive signal transmission section 15 is located between two adjacent shift register circuits VSR arranged along the first direction X.

[0050] like Figure 4 , Figure 5 and Figure 6 As shown, the gate drive circuit 13 includes at least two columns of shift register circuits, each column including multi-stage shift register circuits (VSRs) arranged along the first direction X. The multi-stage shift register circuits (VSRs) in the same shift register circuit column can be sequentially cascaded, meaning two adjacent shift register circuits (VSRs) in the first direction X are cascaded; alternatively, the multi-stage shift register circuits (VSRs) in the same shift register circuit column can be staggered, meaning two non-adjacent shift register circuits (VSRs) in the first direction X are cascaded. This application embodiment does not limit the cascading method of multi-stage shift register circuits (VSRs) in the same shift register circuit column. Further, as... Figure 4 , Figure 5 and Figure 6As shown, in the same shift register circuit array, there is a gap between two adjacent shift register circuits VSRs arranged in the first direction X. The first gate drive signal transmission section 151 extending in the second direction Y is arranged in this gap, that is, at least part of the first gate drive signal transmission section 151 is located between two adjacent shift register circuits VSRs arranged along the first direction X. In this way, the arrangement position of at least part of the first gate drive signal transmission section 151 does not overlap with the arrangement position of the shift register circuit VSR, so as to avoid the signal transmitted in the first gate drive signal transmission section 151 from interfering with the shift register circuit VSR and ensuring the normal operation of the shift register circuit VSR.

[0051] Continue to refer to Figure 4 As shown, the first type of gate drive signal terminal 111 includes a first group of gate drive signal terminals 111a and a second group of gate drive signal terminals 111b; the first group of gate drive signal terminals 111a and the second group of gate drive signal terminals 111b are arranged along a first direction X and each includes a plurality of first gate drive signal terminals 1111 arranged along the first direction X. The first group of gate drive signal terminals 111a is located on the side closer to the second straight edge region AA2, and the second group of gate drive signal terminals 111b is located on the side away from the second straight edge region AA2; the first type of gate drive signal transmission unit 15 includes a first group of gate drive signal transmission unit 15a and a second group of gate drive signal transmission unit 15b. 5b; The first group of gate drive signal transmission units 15a and the second group of gate drive signal transmission units 15b are arranged along the first direction X and each includes multiple first gate drive signal transmission units 151 arranged along the first direction X. The first group of gate drive signal transmission units 15a is located on the side close to the second straight edge region AA2, and the second group of gate drive signal transmission units 15b is located on the side away from the second straight edge region AA2. The first group of gate drive signal transmission units 15a is electrically connected to the first group of gate drive signal terminals 111a and the gate drive signal line 14, respectively. The second group of gate drive signal transmission units 15b is electrically connected to the second group of gate drive signal terminals 111b and the gate drive signal line 14, respectively.

[0052] like Figure 4As shown, the first type of gate drive signal terminal 111 includes a first group of gate drive signal terminals 111a and a second group of gate drive signal terminals 111b. Both the first group of gate drive signal terminals 111a and the second group of gate drive signal terminals 111b include a plurality of first gate drive signal terminals 1111 arranged along the first direction X. Correspondingly, the first type of gate drive signal transmission unit 15 includes a first group of gate drive signal transmission units 15a and a second group of gate drive signal transmission units 15b. Both the first group of gate drive signal transmission units 15a and the second group of gate drive signal transmission units 15b include a plurality of first gate drive signal transmission units 151 arranged along the first direction X. At this time, the first group of gate drive signal transmission units 15a is electrically connected to the first group of gate drive signal terminals 111a and the gate drive signal line 14, respectively, serving as a transmission bridge for the gate drive signal between the first group of gate drive signal terminals 111a and the gate drive signal line 14; the second group of gate drive signal transmission units 15b is electrically connected to the second group of gate drive signal terminals 111b and the gate drive signal line 14, respectively, serving as a transmission bridge for the gate drive signal between the second group of gate drive signal terminals 111b and the gate drive signal line 14. When the first group of gate drive signal transmission units 15a and the second group of gate drive signal transmission units 15b transmit different gate drive signals, the two groups of gate drive signal transmission units cooperate to complete the transmission of all gate drive signals, and the gate drive signals transmitted in each group of gate drive signal transmission units can be flexibly set according to requirements. When the first group of gate drive signal transmission units 15a and the second group of gate drive signal transmission units 15b transmit the same gate drive signal, the arrangement of these two groups of gate drive signal transmission units can reduce the loss during the gate drive signal transmission process, ensure stable and low-loss transmission of the gate drive signal, and guarantee the accuracy of the gate drive signal. Continue to refer to Figure 4 As shown, the display panel also includes a first virtual axis of symmetry DA1, which extends along a second direction Y; a first group of gate drive signal terminals 111a and a second group of gate drive signal terminals 111b are symmetrically arranged about the first virtual axis of symmetry DA1; and a first group of gate drive signal transmission units 15a and a second group of gate drive signal transmission units 15b are symmetrically arranged about the first virtual axis of symmetry DA1.

[0053] like Figure 4As shown, the first group of gate drive signal terminals 111a is disposed on the side of the first non-display area NAA closer to the second non-display area, and the second group of gate drive signal terminals 111b is disposed on the side of the first non-display area NAA farther from the second non-display area. Furthermore, the number of first gate drive signal terminals 1111 in the first group of gate drive signal terminals 111a can be the same as the number of first gate drive signal terminals 1111 in the second group of gate drive signal terminals 111b. Further, the first group of gate drive signal terminals 111a and the second group of gate drive signal terminals 111b are symmetrically arranged about the first virtual axis of symmetry DA1. This symmetrical arrangement can be understood as the positions of the multiple first gate drive signal terminals 1111 in the first group of gate drive signal terminals 111a and the positions of the multiple first gate drive signal terminals 1111 in the second group of gate drive signal terminals 111b being symmetrically arranged about the first virtual axis of symmetry DA1. For example, in the first group of gate drive signal terminals 111a, the first gate drive signal terminal 1111 transmitting a high-level signal, and in the second group of gate drive signal terminals 111b, the first gate drive signal terminal 1111 transmitting a high-level signal are located on opposite sides of the first virtual axis of symmetry DA1 along the first direction X, and the two first gate drive signal terminals 1111 transmitting high-level signals are equidistant from the first virtual axis of symmetry DA1 in the first direction X. Alternatively, the first group of gate drive signal terminals 111a and the second group of gate drive signal terminals 111b are symmetrically arranged about the first virtual axis of symmetry DA1. This symmetrical arrangement can also be understood as the arrangement order of the multiple first gate drive signal terminals 1111 in the first group of gate drive signal terminals 111a being symmetrical about the first virtual axis of symmetry DA1 with respect to the arrangement order of the multiple first gate drive signal terminals 1111 in the second group of gate drive signal terminals 111b. For example, in the first group of gate drive signal terminals 111a, the first gate drive signal terminals 1111 transmitting high-level signals, low-level signals, and clock signals are arranged sequentially along the first direction X, and along the first direction X, the first gate drive signal terminal 1111 transmitting the clock signal is located on the side closer to the first virtual axis DA1. In the second group of gate drive signal terminals 111b, the first gate drive signal terminals 1111 transmitting high-level signals, low-level signals, and clock signals are arranged sequentially along the first direction X, and along the first direction X, the first gate drive signal terminal 1111 transmitting the clock signal is located on the side closer to the first virtual axis DA1. By setting the first group of gate drive signal terminals 111a and the second group of gate drive signal terminals 111b symmetrically about the first virtual axis DA1, the first group of gate drive signal terminals 111a and the second group of gate drive signal terminals 111b are neatly arranged, and the signal transmission accuracy is high.

[0054] Furthermore, the first group of gate drive signal transmission units 15a is disposed on the side of the first non-display area NAA closer to the second non-display area, and the second group of gate drive signal transmission units 15b is disposed on the side of the first non-display area NAA farther from the second non-display area. The number of first gate drive signal transmission units 151 included in the first group of gate drive signal transmission units 15a and the number of first gate drive signal transmission units 151 included in the second group of gate drive signal transmission units 15b can be the same. Furthermore, the first group of gate drive signal transmission units 15a and the second group of gate drive signal transmission units 15b are symmetrically arranged about the first virtual axis of symmetry DA1. This symmetrical arrangement can be understood as the arrangement positions of the plurality of first gate drive signal transmission units 151 in the first group of gate drive signal transmission units 15a and the arrangement positions of the plurality of first gate drive signal transmission units 151 in the second group of gate drive signal transmission units 15b being symmetrically arranged about the first virtual axis of symmetry DA1. For example, the first gate drive signal transmission unit 151 transmitting a high-level signal in the first group of gate drive signal transmission units 15a and the first gate drive signal transmission unit 151 transmitting a high-level signal in the second group of gate drive signal transmission units 15b are located on opposite sides of the first virtual axis of symmetry DA1 along the first direction X, and the two first gate drive signal transmission units 151 transmitting high-level signals are equidistant from the first virtual axis of symmetry DA1 in the first direction X. Alternatively, the first group of gate drive signal transmission units 15a and the second group of gate drive signal transmission units 15b are symmetrically arranged about the first virtual axis of symmetry DA1. This symmetrical arrangement can also be understood as the arrangement order of the plurality of first gate drive signal transmission units 151 in the first group of gate drive signal transmission units 15a being symmetrical about the first virtual axis of symmetry DA1 with respect to the arrangement order of the plurality of first gate drive signal transmission units 151 in the second group of gate drive signal transmission units 15b. For example, in the first group of gate drive signal transmission units 15a, the first gate drive signal transmission units 151 that transmit high-level signals, low-level signals, and clock signals are arranged sequentially along the first direction X, and along the first direction X, the first gate drive signal transmission unit 151 that transmits clock signals is located on the side closer to the first virtual axis DA1. In the second group of gate drive signal transmission units 15b, the first gate drive signal transmission units 151 that transmit high-level signals, low-level signals, and clock signals are arranged sequentially along the first direction X, and along the first direction X, the first gate drive signal transmission unit 151 that transmits clock signals is located on the side closer to the first virtual axis DA1. By setting the first group of gate drive signal transmission units 15a and the second group of gate drive signal transmission units 15b symmetrically about the first virtual axis DA1, the first group of gate drive signal transmission units 15a and the second group of gate drive signal transmission units 15b are arranged in a regular manner, and the signal transmission accuracy is high.

[0055] For example, continue to refer to Figure 4, Figure 5 and Figure 6 As shown, the first type of gate drive signal terminal 111 includes a first potential drive signal terminal 1111a and a second potential drive signal terminal 1111b. The potential difference between the first potential drive signal terminal 1111a and the second potential drive signal terminal 1111b is greater than a preset potential difference. The first type of gate drive signal terminal 111 also includes a first virtual signal terminal DUMMY 1. Along the first direction X, at least one first virtual signal terminal DUMMY 1 is provided between the potential in the first potential drive signal terminal 1111a and the second potential drive signal terminal 1111b.

[0056] like Figure 4 , Figure 5 and Figure 6 As shown, the first type of gate drive signal terminal 111 includes a first potential drive signal terminal 1111a and a second potential drive signal terminal 1111b. The first potential drive signal terminal 1111a and the second potential drive signal terminal 1111b are two first gate drive signal terminals with a large potential difference. That is, the potential difference between the first potential drive signal terminal 1111a and the second potential drive signal terminal 1111b is greater than a preset potential difference. The preset potential difference can be understood as the potential difference corresponding to the occurrence of electrochemical corrosion. Because the potential difference between the first potential driving signal terminal 1111a and the second potential driving signal terminal 1111b is large, electrochemical corrosion is easily generated between them. Therefore, in this embodiment, a first virtual signal terminal DUMMY 1 is provided between the first potential driving signal terminal 1111a and the second potential driving signal terminal 1111b. By adding the first virtual signal terminal DUMMY 1, the distance between the first potential driving signal terminal 1111a and the second potential driving signal terminal 1111b can be extended, reducing the probability of electrochemical corrosion between them and improving the stability of the structure in the display panel.

[0057] For example, the first potential drive signal terminal 1111a can be a high-level drive signal terminal, such as a VGH signal terminal; the second potential drive signal terminal 1111b can be a low-level drive signal terminal, such as a VGL signal terminal. Furthermore, since potential difference, temperature, and humidity can all affect the rate of electrochemical corrosion, the potential difference corresponding to electrochemical corrosion is different under different temperature and / or humidity environments. Therefore, this application embodiment does not limit the specific value of the preset potential difference.

[0058] For example, the potential in the first virtual signal terminal DUMMY 1 is floating, or the potential in the first virtual signal terminal DUMMY 1 is between the potential of the first potential drive signal terminal 1111a and the potential of the second potential drive signal terminal 1111b, and no electrochemical corrosion occurs between the first virtual signal terminal DUMMY 1 and the first potential drive signal terminal 1111a, nor between the first virtual signal terminal DUMMY 1 and the second potential drive signal terminal 1111b.

[0059] For example, continue to refer to Figure 4 , Figure 5 and Figure 6 As shown, the first type of gate drive signal terminal 111 includes a first clock drive signal terminal 1111c, a first fixed potential signal terminal 1111d, and a second virtual signal terminal DUMMY 2; along the first direction X, at least one second virtual signal terminal DUMMY 2 is disposed between the first clock drive signal terminal 1111c and the first fixed potential signal terminal 1111d.

[0060] like Figure 4 , Figure 5 and Figure 6 As shown, the first type of gate drive signal terminal 111 includes a first clock drive signal terminal 1111c and a first fixed potential signal terminal 1111d. The signal in the first clock drive signal terminal 1111c is a changing clock signal, and the signal in the first fixed potential signal terminal 1111d is a fixed signal. To avoid mutual interference between the clock signal and the fixed signal, in this embodiment, a second virtual signal terminal DUMMY 2 is provided between the first clock drive signal terminal 1111c and the first fixed potential signal terminal 1111d. By adding the second virtual signal terminal DUMMY 2, the distance between the first clock drive signal terminal 1111c and the first fixed potential signal terminal 1111d can be extended, reducing the probability of interference between the first clock drive signal terminal 1111c and the first fixed potential signal terminal 1111d and improving the stability of the signal in the display panel.

[0061] For example, the first clock drive signal terminal 1111c can be a CK clock signal terminal or an XCK clock signal terminal, and the first fixed potential signal terminal 1111d can be a high-level drive signal terminal, such as a VGH signal terminal; or it can be a low-level drive signal terminal, such as a VGL signal terminal.

[0062] For example, the potential in the second virtual signal terminal DUMMY 2 is either floating or fixed. The second virtual signal terminal DUMMY 2 can isolate the mutual interference between the first clock drive signal terminal 1111c and the first fixed potential signal terminal 1111d, thus ensuring the stability of the signal in the display panel.

[0063] In one embodiment, Figure 7 This is a schematic diagram of another display panel structure provided in the embodiments of this application, specifically a schematic diagram of the structure of the first non-display area and the second non-display area in an unfolded state. Figure 8 yes Figure 7 An enlarged structural diagram of region a in the middle, as shown below. Figure 7 and Figure 8 As shown, the display panel also includes a gate drive circuit 13 and a gate drive signal line 14 disposed in the first circuit setting CSA1 area, the gate drive circuit 13 and the gate drive signal line 14 being electrically connected; the second non-display area NAA2 also includes a second bonding area BAA2, the second bonding area BAA2 being located on the side of the second bent area BA2 away from the second straight edge area AA2; the display panel also includes a plurality of second type signal bonding terminals 21 disposed in the second bonding area BAA2, the second type signal bonding terminals 21 including second type gate drive signal terminals 211, the second type gate drive signal terminals 211 including a plurality of second gate drive signal terminals 2111 arranged along the second direction Y; the display panel also includes a second type gate drive signal transmission section 22, the second type gate drive signal transmission section 22 including a plurality of second gate drive signal transmission sections 221, the second gate drive signal transmission sections 221 being electrically connected to the second gate drive signal terminals 2111 and the gate drive signal line 14 respectively.

[0064] like Figure 7 and Figure 8As shown, the display panel also includes a gate driving circuit 13 and a gate driving signal line 14 disposed in the first circuit setting area CSA1. The gate driving signal line 14 is used to provide a gate driving signal to the gate driving circuit 13, so as to drive the gate driving circuit to output a scan signal to the scan signal line disposed in the display area AA, and output a light emission control signal to the light emission control signal line disposed in the display area AA, thereby realizing the normal operation of the pixel circuit disposed in the display area AA and ensuring the normal display function of the display panel. Furthermore, the second non-display area NAA2 also includes a second bonding area BAA2 and a plurality of second type signal bonding terminals 21 disposed in the second bonding area BAA2. The second type signal bonding terminals 21 include second type gate drive signal terminals 211. The second type gate drive signal terminals 211 include a plurality of second gate drive signal terminals 2111 arranged along the second direction Y. The second gate drive signal terminals 2111 are electrically connected to the gate drive signal line 14 through the second gate drive signal transmission unit 221. That is, the second gate drive signal terminals disposed in the second non-display area NAA2 can provide gate drive signals to the gate drive signal line 14 to ensure that the gate drive circuit 13 can normally receive the gate drive signal provided by the gate drive signal line 14 and ensure that the gate drive circuit 13 works normally.

[0065] Continue to refer to Figure 8 As shown, the second gate drive signal transmission unit 221 includes a first drive transmission sub-unit 2211, a second drive transmission sub-unit 2212, and a third drive transmission sub-unit 2213; the first drive transmission sub-unit 2211 is electrically connected to the second gate drive signal terminal 2111 and the second drive transmission sub-unit 2213 respectively; the third drive transmission sub-unit 2213 is electrically connected to the second drive transmission sub-unit 2213 and the gate drive signal line 14 respectively; at least a portion of the second drive transmission sub-unit 2213 is disposed in the first bending region BA1.

[0066] like Figure 8As shown, the second gate drive signal transmission unit 221 includes a first drive transmission sub-unit 2211, a second drive transmission sub-unit 2212, and a third drive transmission sub-unit 2213. At least a portion of the first drive transmission sub-unit 2211 is located in the second non-display area NAA1, at least a portion of the second drive transmission sub-unit 2212 is located in the first bending area BA1, and at least a portion of the third drive transmission sub-unit 2213 is located in the first non-display area NAA1. The first drive transmission sub-unit 2211 is electrically connected to the second gate drive signal terminal 2111 and the second drive transmission sub-unit 2212, respectively. The third drive transmission sub-unit 2213 is electrically connected to the second drive transmission sub-unit 2212 and the gate drive signal line 14, respectively. This achieves the electrical connection between the second gate drive signal terminal 2111 and the gate drive signal line 14, ensuring that the gate drive signal line 14 can normally receive the gate drive signal provided by the second gate drive signal terminal 2111 and transmit the gate drive signal to the gate drive circuit 13, ensuring the normal operation of the gate drive circuit 13.

[0067] Furthermore, the second drive transmission sub-unit 2212 is disposed on a different layer from the first drive transmission sub-unit 2211 and the third drive transmission sub-unit 2213, respectively.

[0068] like Figure 8 As shown, since at least a portion of the structure of the second drive transmission sub-section 2212 is disposed in the first bending region BA1, in order to ensure that the second drive transmission sub-section 2212 disposed in the first bending region BA1 can transmit signals normally after the first bending region BA1 bends to the non-light-emitting side of the display panel, and to prevent the circuit from being broken due to bending, the second drive transmission sub-section 2212 can be configured to have good ductility. For example, the second drive transmission sub-section 2212 can be made of a metal layer with good ductility, such as a TI-AL-TI metal layer. Furthermore, considering the wiring requirements of the area outside the first bending region BA1, that is, the wiring requirements of the area where the first drive transmission sub-section 2211 and the third drive transmission sub-section 2213 are located, the second drive transmission sub-section 2212 is disposed on a different layer from the first drive transmission sub-section 2211 and the third drive transmission sub-section 2213, respectively. This ensures that the wiring stability requirements of the area of ​​the first bending region BA1 are met, as well as the wiring distribution problem of the area outside the first bending region BA1, thus ensuring the stable setting of the second gate drive signal transmission section 221.

[0069] It should be noted that continued reference is necessary. Figure 8As shown, the second gate drive signal transmission unit 221 also includes a wiring structure located in the second bending region BA2. This wiring structure is electrically connected to the wiring structure on the side closer to the second gate drive signal terminal 2111 and the wiring structure on the side farther from the second gate drive signal terminal 2111. Furthermore, the wiring structure located in the second bending region BA2 can be disposed on a different layer from the wiring structure located outside the second bending region BA2. The wiring structure located in the second bending region BA2 can have good ductility, for example, by using a metal layer with good ductility, such as a TI-AL-TI metal layer. The wiring structure located outside the second bending region BA2 can be configured with a film layer according to the wiring requirements of the area.

[0070] Next, the specific configuration of the first drive transmission sub-unit 2211, the second drive transmission sub-unit 2212, and the third drive transmission sub-unit 2213 will be explained.

[0071] For example, the specific configuration of the first drive transmission subunit 2211 will be described first.

[0072] refer to Figure 8 and Figure 9 As shown, the first drive transmission sub-section 2211 includes at least two layers of first sub-sections 22111 arranged in different layers, and the at least two layers of first sub-sections 22111 are arranged in parallel.

[0073] like Figure 8 and Figure 9 As shown, the first driving transmission sub-section 2211 includes at least two first sub-sections 22111 disposed in different layers. The at least two first sub-sections 22111 are stacked in the thickness direction of the display panel and electrically connected through vias, that is, the at least two first sub-sections 22111 are disposed in parallel. This can reduce the impedance of the first driving transmission sub-section 2211, reduce the loss in the gate driving signal transmission process, and improve the accuracy of the gate driving signal.

[0074] Continue to refer to Figure 8 and Figure 9 As shown, the first drive transmission sub-section 2211 includes at least two layers of first sub-sections 22111 arranged in different layers; the first drive transmission sub-section 2211 includes multiple first sub-drive transmission sub-sections 2211a and multiple second sub-drive transmission sub-sections 2211b, the multiple first sub-drive transmission sub-sections 2211a are arranged in sequence, and the multiple second sub-drive transmission sub-sections 2211b are arranged in sequence; at least one layer of the first sub-section 22111 in the first sub-drive transmission sub-section 2211a and at least one layer of the first sub-section 22111 in the second sub-drive transmission sub-section 2211b are arranged in different layers.

[0075] like Figure 9As shown, the first drive transmission sub-section 2211 includes multiple first sub-drive transmission sub-sections 2211a and multiple second sub-drive transmission sub-sections 2211b. Both the first sub-drive transmission sub-sections 2211a and the multiple second sub-drive transmission sub-sections 2211b include at least two layers of first sub-sub-sections 22111 arranged in different layers. That is, the transmission impedance in the first sub-drive transmission sub-sections 2211a and the multiple second sub-drive transmission sub-sections 2211b is relatively small. Furthermore, at least one layer of the first sub-sub-segment 22111 in the first sub-drive transmission sub-section 2211a and at least one layer of the first sub-sub-segment 22111 in the second sub-drive transmission sub-section 2211b are disposed on different layers. That is, there are first sub-sub-segments 22111 in the first sub-drive transmission sub-section 2211a and the second sub-drive transmission sub-section 2211b that are not disposed on the same layer. This can ensure that the wiring of the first sub-sub-segment 22111 in the first sub-drive transmission sub-section 2211a and the second sub-drive transmission sub-section 2211b has a large degree of freedom, and can ensure that a sufficient number of first sub-drive transmission sub-sections 2211a and the second sub-drive transmission sub-section 2211b can be accommodated in a limited space, taking into account both wiring feasibility and process difficulty.

[0076] For example, the first sub-driving transmission sub-section 2211a may include two layers of first sub-sections 22111 disposed in different layers, wherein one layer of first sub-sections 22111 is disposed in a first metal layer and the other layer of first sub-sections 22111 is disposed in a second metal layer; the second sub-driving transmission sub-section 2211b may also include two layers of first sub-sections 22111 disposed in different layers, wherein one layer of first sub-sections 22111 is disposed in a first metal layer and the other layer of first sub-sections 22111 is disposed in a third metal layer. Taking a pixel circuit disposed in the display area of ​​a display panel, including a first type of transistor and a second type of transistor, as an example, the active layer of the first type of transistor includes silicon, and the active layer of the second type of transistor includes oxide. The first metal layer may be the metal layer containing the gate of the first type of transistor, the second metal layer may be the metal layer containing the bottom gate of the second type of transistor, and the third metal layer may be the metal layer containing the top gate of the second type of transistor. By rationally setting the wiring method of the first sub-drive transmission sub-unit 2211a and the second sub-drive transmission sub-unit 2211b, both the low impedance of the first sub-drive transmission sub-unit 2211a and the high wiring feasibility of the second sub-drive transmission sub-unit 2211b are taken into account.

[0077] It should be noted that the above exemplary description illustrates the wiring method of the first sub-drive transmission sub-section 2211a and the second sub-drive transmission sub-section 2211b with only one feasible implementation method and is not a limitation. The embodiments of this application do not limit the specific setting of the film layer of the first sub-section 22111 in the first sub-drive transmission sub-section 2211a and the second sub-drive transmission sub-section 2211b, and the setting method of other film layers is also within the protection scope of the embodiments of this application.

[0078] Continue to refer to Figure 9 As shown, for example, the first drive transmission sub-section 2211 includes multiple first sub-drive transmission sub-sections 2211a and multiple second sub-drive transmission sub-sections 2211b, with the multiple first sub-drive transmission sub-sections 2211a arranged sequentially and the multiple second sub-drive transmission sub-sections 2211b arranged sequentially; the first sub-drive transmission sub-sections 2211a and the second sub-drive transmission sub-sections 2211b are arranged alternately.

[0079] like Figure 9 As shown, at least one layer of the first sub-sub-segment 22111 in the first sub-drive transmission sub-section 2211a and at least one layer of the first sub-sub-segment 22111 in the second sub-drive transmission sub-section 2211b are disposed in different layers. That is, the first sub-drive transmission sub-section 2211a and the second sub-drive transmission sub-section 2211b contain first sub-sub-segments 22111 that are not disposed on the same layer. This ensures a greater degree of freedom in the wiring of the first sub-sub-segments 22111 in the first sub-drive transmission sub-section 2211a and the second sub-drive transmission sub-section 2211b. Furthermore, the first sub-drive transmission sub-sections 2211a and the second sub-drive transmission sub-section 2211b are arranged alternately. This further reduces the wiring density and wiring difficulty of the film layer of at least some of the first sub-sub-segments 22111, reduces the wiring difficulty of the first sub-drive transmission sub-sections 2211a and the second sub-drive transmission sub-section 2211b, and improves the process stability of the first sub-drive transmission sub-sections 2211a and the second sub-drive transmission sub-section 2211b. Furthermore, the fact that at least one layer of the first sub-sub-segment 22111 in the first sub-drive transmission sub-section 2211a and at least one layer of the first sub-sub-segment 22111 in the second sub-drive transmission sub-section 2211b are arranged in different layers and that the first sub-drive transmission sub-section 2211a and the second sub-drive transmission sub-section 2211b are arranged alternately can reduce the mutual interference between at least a portion of the first sub-sub-segment 22111 in the first sub-sub-segment 22111 and at least a portion of the first sub-sub-segment 22111 in the second sub-drive transmission sub-section 2211b, ensure the stability and independence of the gate drive signal transmitted in the first sub-drive transmission sub-section 2211a and the second sub-drive transmission sub-section 2211b, and ensure the accuracy of the gate drive signal transmission.

[0080] For example, the specific configuration of the second drive transmission subunit 2212 will be described.

[0081] Figure 10 yes Figure 8 A schematic diagram of the structure of the second drive transmission subunit, combined with... Figure 8 and Figure 10As shown, the second drive transmission sub-section 2212 includes a first end 2212a, a second end 2212b, and a middle section 2212c; the first end 2212a is electrically connected to the first drive transmission sub-section 2211 through a via; the second end 2212b is electrically connected to the third drive transmission sub-section 2213 through a via; the middle section 2212c connects the first end 2212a and the second end 2212b, and the middle section 2212c includes a plurality of second sub-sections 22121, which are arranged in parallel.

[0082] like Figure 8 and Figure 10 As shown, since at least a portion of the structure in the second drive transmission sub-unit 2212 is disposed in the first bending area BA1, in order for the second drive transmission sub-unit 2212 disposed in the first bending area BA1 to transmit signals normally after the first bending area BA1 bends to the non-light-emitting side of the display panel, and to prevent the circuit from being broken due to bending, the second drive transmission sub-unit 2212 can be configured to have good ductility. For example, the second drive transmission sub-unit 2212 can be made of a metal layer with good ductility, such as a TI-AL-TI metal layer. Furthermore, considering the wiring requirements of the area outside the first bending area BA1, the first drive transmission sub-unit 2211 and the second drive transmission sub-unit 2212 need to be rewired, and the third drive transmission sub-unit 2213 and the second drive transmission sub-unit 2212 also need to be rewired. Specifically, the second drive transmission sub-section 2212 includes a first end 2212a and a second end 2212b; the first end 2212a is electrically connected to the first drive transmission sub-section 2211 through a via; and the second end 2212b is electrically connected to the third drive transmission sub-section 2213 through a via. Furthermore, the second drive transmission sub-unit 2212 also includes an intermediate portion 2212c connecting the first end 2212a and the second end 2212b. The intermediate portion 2212c is entirely located in the first bending region BA1. In addition to using a metal layer with good ductility for the intermediate portion 2212c, the intermediate portion 2212c can also include multiple second sub-divisions 22121. In the unfolded state of the first bending region BA1, the multiple second sub-divisions 22121 extend along the second direction Y and are arranged along the first direction X. There is a gap between two adjacent second sub-divisions 22121 in the first direction X. In this way, the stress generated during the bending process can be further released through the gap between two adjacent second sub-divisions 22121, which makes it easier for the second drive transmission sub-unit 2212 to maintain structural and functional stability in the bending state.

[0083] For example, the signals transmitted by the second type of gate drive signal transmission unit 22 include at least one of a level signal, a clock signal, a start signal, and a reset signal. Specifically, the level signal line may include a high-level signal and / or a low-level signal; the clock signal may include a CK clock signal and / or a XCK clock signal; the start signal is used to provide a start signal to the gate drive circuit 13; and the reset signal is used to provide a reset signal to the gate drive circuit 13. Furthermore, each intermediate portion 2212c of the second type of gate drive signal transmission unit 22 transmitting different gate drive signals may include multiple second sub-portions 22121. For example, the intermediate portion 2212c of the second type of gate drive signal transmission unit 22 transmitting level signals may include multiple second sub-portions 22121; the intermediate portion 2212c of the second type of gate drive signal transmission unit 22 transmitting clock signals may include multiple second sub-portions 22121; the intermediate portion 2212c of the second type of gate drive signal transmission unit 22 transmitting start signals may include multiple second sub-portions 22121; and the intermediate portion 2212c of the second type of gate drive signal transmission unit 22 transmitting reset signals may include multiple second sub-portions 22121. Moreover, the number of second sub-portions 22121 included in the intermediate portion 2212c of the second type of gate drive signal transmission unit 22 transmitting different gate drive signals may be the same or different, and this embodiment does not limit this.

[0084] For example, the specific configuration of the third drive transmission sub-unit 2213 will be described.

[0085] Figure 11 yes Figure 8 A schematic diagram of the structure of the third drive transmission sub-unit, combined with... Figure 8 and Figure 11 As shown, the third drive transmission sub-unit 2213 includes at least two third sub-sub-units 22131 arranged in different layers, and the at least two third sub-sub-units 22131 are arranged in parallel.

[0086] like Figure 8 and Figure 11 As shown, the third driving transmission sub-section 2213 includes at least two third sub-sections 22131 disposed in different layers. The at least two third sub-sections 22131 are stacked in the thickness direction of the display panel and electrically connected through vias, that is, the at least two third sub-sections 22131 are disposed in parallel. This can reduce the impedance of the third driving transmission sub-section 2213, reduce the loss in the gate driving signal transmission process, and improve the accuracy of the gate driving signal.

[0087] Continue to refer to Figure 8 and Figure 11As shown, the third drive transmission sub-section 2213 includes at least two layers of third sub-sections 22131 arranged in different layers; the third drive transmission sub-section 2213 includes multiple third sub-drive transmission sub-sections 2213a and multiple fourth sub-drive transmission sub-sections 2213b, with the multiple third sub-drive transmission sub-sections 2213a arranged sequentially and the multiple fourth sub-drive transmission sub-sections 2213b arranged sequentially; at least one layer of the third sub-section 22131 in the third sub-drive transmission sub-section 2211a and at least one layer of the third sub-section 22131 in the fourth sub-drive transmission sub-section 2213b are arranged in different layers.

[0088] like Figure 11 As shown, the third drive transmission sub-section 2213 includes multiple third sub-drive transmission sub-sections 2213a and multiple fourth sub-drive transmission sub-sections 2213b. Both the third sub-drive transmission sub-sections 2213a and the multiple fourth sub-drive transmission sub-sections 2213b include at least two layers of third sub-sub-sections 22131 arranged in different layers. That is, the transmission impedance in the third sub-drive transmission sub-sections 2213a and the multiple fourth sub-drive transmission sub-sections 2213b is relatively small. Furthermore, at least one layer of the third sub-sub-section 22131 in the third sub-drive transmission sub-section 2213a and at least one layer of the third sub-sub-section 22131 in the fourth sub-drive transmission sub-section 2213b are arranged on different layers. That is, there are third sub-sub-sections 22131 in the third sub-drive transmission sub-section 2213a and the fourth sub-drive transmission sub-section 2213b that are not arranged on the same layer. This can ensure that the wiring of the third sub-sub-sections 22131 in the third sub-drive transmission sub-section 2213a and the fourth sub-drive transmission sub-section 2213b has a large degree of freedom, and can accommodate a sufficient number of third sub-drive transmission sub-sections 2213a and the fourth sub-drive transmission sub-section 2213b in a limited space, taking into account both wiring feasibility and process difficulty.

[0089] For example, the third sub-driving transmission sub-section 2213a may include two layers of third sub-sections 22131 disposed in different layers, wherein one layer of third sub-sections 22131 is disposed in the first metal layer and the other layer of third sub-sections 22131 is disposed in the second metal layer; the fourth sub-driving transmission sub-section 2213b may include two layers of third sub-sections 22131 disposed in different layers, wherein one layer of third sub-sections 22131 is disposed in the first metal layer and the other layer of third sub-sections 22131 is disposed in the third metal layer. Taking the pixel circuit disposed in the display area of ​​the display panel as an example, which includes a first type of transistor and a second type of transistor, the active layer of the first type of transistor includes silicon, and the active layer of the second type of transistor includes oxide. The first metal layer may be the metal layer containing the gate of the first type of transistor, the second metal layer may be the metal layer containing the bottom gate of the second type of transistor, and the third metal layer may be the metal layer containing the top gate of the second type of transistor. By rationally configuring the wiring methods of the third sub-drive transmission sub-unit 2213a and the fourth sub-drive transmission sub-unit 2213b, both the low impedance of the third sub-drive transmission sub-unit 2213a and the high wiring feasibility of the fourth sub-drive transmission sub-unit 2213b are taken into account.

[0090] It should be noted that the above exemplary description illustrates the wiring method of the third sub-drive transmission sub-section 2213a and the fourth sub-drive transmission sub-section 2213b with only one feasible implementation method and is not a limitation. The embodiments of this application do not limit the specific setting of the film layer of the third sub-section 22131 in the third sub-drive transmission sub-section 2213a and the fourth sub-drive transmission sub-section 2213b, and other film layer setting methods are also within the protection scope of the embodiments of this application.

[0091] Continue to refer to Figure 11 As shown, the third drive transmission sub-unit 2213 includes multiple third sub-drive transmission sub-units 2213a and multiple fourth sub-drive transmission sub-units 2213b. The multiple third sub-drive transmission sub-units 2213a are arranged sequentially, and the multiple fourth sub-drive transmission sub-units 2213b are arranged sequentially; the third sub-drive transmission sub-units 2213a and the fourth sub-drive transmission sub-units 2213b are arranged alternately.

[0092] like Figure 11As shown, at least one layer of the third sub-sub-section 22131 in the third sub-drive transmission sub-section 2213a and at least one layer of the third sub-sub-section 22131 in the fourth sub-drive transmission sub-section 2213b are disposed in different layers. That is, the third sub-drive transmission sub-sections 2213a and 2213b contain third sub-sub-sections 22131 that are not disposed on the same layer. This ensures greater flexibility in the wiring of the third sub-sub-sections 22131 in both sub-drive transmission sub-sections 2213a and 2213b. Furthermore, the third sub-drive transmission sub-sections 2213a and 2213b are arranged alternately, which further reduces the wiring density and difficulty of the film layers containing at least some of the third sub-sub-sections 22131, reduces the wiring difficulty of the third sub-drive transmission sub-sections 2213a and 2213b, and improves the process stability of the third sub-drive transmission sub-sections 2213a and 2213b. Furthermore, the fact that at least one layer of the third sub-sub-section 22131 in the third sub-drive transmission sub-section 2213a and at least one layer of the third sub-sub-section 22131 in the fourth sub-drive transmission sub-section 2213b are arranged in different layers and that the third sub-drive transmission sub-section 2213a and the fourth sub-drive transmission sub-section 2213b are arranged alternately can reduce the mutual interference between at least a portion of the third sub-sub-section 22131 and at least a portion of the third sub-sub-section 22131 in the fourth sub-drive transmission sub-section 2213b, ensure the stability and independence of the gate drive signal transmitted in the third sub-drive transmission sub-section 2213a and the fourth sub-drive transmission sub-section 2213b, and ensure the accuracy of the gate drive signal transmission.

[0093] Continue to refer to Figure 8 As shown, the second type of gate drive signal terminal 211 includes a third potential drive signal terminal 2111a and a fourth potential drive signal terminal 2111b. The potential difference between the third potential drive signal terminal 2111a and the fourth potential drive signal terminal 2111b is greater than a preset potential difference. The second type of gate drive signal terminal 211 also includes a third virtual signal terminal DUMMY 3. Along the second direction Y, at least one third virtual signal terminal DUMMY 3 is provided between the potential in the third potential drive signal terminal 2111a and the fourth potential drive signal terminal 2111b.

[0094] like Figure 8As shown, the second type of gate drive signal terminal 221 includes a third potential drive signal terminal 2111a and a fourth potential drive signal terminal 2111b. The third potential drive signal terminal 2111a and the fourth potential drive signal terminal 2111b are two second gate drive signal terminals with a large potential difference. That is, the potential difference between the third potential drive signal terminal 2111a and the fourth potential drive signal terminal 2111b is greater than a preset potential difference. The preset potential difference can be understood as the potential difference corresponding to the occurrence of electrochemical corrosion. Because the potential difference between the third potential drive signal terminal 2111a and the fourth potential drive signal terminal 2111b is large, electrochemical corrosion is easily generated between them. Therefore, in this embodiment, a third virtual signal terminal DUMMY 3 is provided between the third potential drive signal terminal 2111a and the fourth potential drive signal terminal 2111b. By adding the third virtual signal terminal DUMMY 3, the distance between the third potential drive signal terminal 2111a and the fourth potential drive signal terminal 2111b can be extended, reducing the probability of electrochemical corrosion between them and improving the stability of the structure in the display panel.

[0095] For example, the third potential drive signal terminal 2111a can be a high-level drive signal terminal, such as a VGH signal terminal; the fourth potential drive signal terminal 2111b can be a low-level drive signal terminal, such as a VGL signal terminal. Furthermore, since potential difference, temperature, and humidity can all affect the rate of electrochemical corrosion, the potential difference corresponding to electrochemical corrosion is different under different temperature and / or humidity environments. Therefore, this application embodiment does not limit the specific value of the preset potential difference.

[0096] For example, the potential in the third virtual signal terminal DUMMY 3 is floating, or the potential in the third virtual signal terminal DUMMY 3 is between the potential of the third potential drive signal terminal 2111a and the potential of the fourth potential drive signal terminal 2111b, and no electrochemical corrosion occurs between the third virtual signal terminal DUMMY 3 and the third potential drive signal terminal 2111a, nor between the third virtual signal terminal DUMMY 3 and the fourth potential drive signal terminal 2111b.

[0097] For example, continue to refer to Figure 8As shown, the second type of gate drive signal terminal 211 includes a second clock drive signal terminal 2111c, a second fixed potential signal terminal 2111d, and a fourth virtual signal terminal DUMMY 4; along the second direction Y, at least one fourth virtual signal terminal DUMMY 4 is disposed between the second clock drive signal terminal 2111c and the second fixed potential signal terminal 2111d.

[0098] like Figure 8 As shown, the second type of gate drive signal terminal 211 includes a second clock drive signal terminal 2111c and a second fixed potential signal terminal 2111d. The signal in the second clock drive signal terminal 2111c is a changing clock signal, and the signal in the second fixed potential signal terminal 2111d is a fixed signal. To avoid mutual interference between the clock signal and the fixed signal, in this embodiment, a fourth virtual signal terminal DUMMY 4 is provided between the second clock drive signal terminal 2111c and the second fixed potential signal terminal 2111d. By adding the fourth virtual signal terminal DUMMY 4, the distance between the second clock drive signal terminal 2111c and the second fixed potential signal terminal 2111d can be extended, reducing the probability of interference between the second clock drive signal terminal 2111c and the second fixed potential signal terminal 2111d, and improving the stability of the signal in the display panel.

[0099] For example, the second clock drive signal terminal 2111c can be a CK clock signal terminal or an XCK clock signal terminal, and the second fixed potential signal terminal 2111d can be a high-level drive signal terminal, such as a VGH signal terminal; or it can be a low-level drive signal terminal, such as a VGL signal terminal.

[0100] The potential in the fourth virtual signal terminal DUMMY 4 is either floating or fixed. The fourth virtual signal terminal DUMMY 4 can isolate the mutual interference between the second clock drive signal terminal 2111c and the second fixed potential signal terminal 2111d, thus ensuring the stability of the signal in the display panel.

[0101] In one embodiment, Figure 12 This is yet another display panel provided in the embodiments of this application. Figure 13 yes Figure 12 An enlarged diagram of region b in the middle, as shown below. Figure 12 and Figure 13As shown, the display panel also includes a gate drive circuit 13 and a gate drive signal line 14 disposed in the first circuit setting area CSA1, the gate drive circuit 13 and the gate drive signal line 14 being electrically connected; the first non-display area NAA1 also includes a first bonding area BAA1, the first bonding area BAA1 being located on the side of the first circuit setting area CSA1 away from the first bending area BA1; the second non-display area NAA2 also includes a second bonding area BAA2, the second bonding area BAA2 being located on the side of the second bending area BA2 away from the second straight edge area AA2; the display panel also includes a first type of signal bonding terminal 11 disposed in the first bonding area BAA1 and a plurality of second type of signal bonding terminals 21 disposed in the second bonding area; the first type of signal bonding terminal 11 includes a first type of gate drive signal terminal 111, the first type of gate drive signal terminal 111 including a first type of gate drive signal terminal along the first direction The display panel includes a plurality of first gate drive signal terminals 1111 arranged in the X direction; a second type of signal bonding terminal 21 includes a second type of gate drive signal terminal 211, which includes a plurality of second gate drive signal terminals 2111 arranged in the second direction Y; the display panel also includes a first type of gate drive signal transmission section 15 and a second type of gate drive signal transmission section 22; the first type of gate drive signal transmission section 15 includes a plurality of first gate drive signal transmission sections 151; the second type of gate drive signal transmission section 22 includes a plurality of second gate drive signal transmission sections 221; the first gate drive signal transmission section 151 is electrically connected to the first gate drive signal terminal 1111 and the gate drive signal line 14 respectively, and the second gate drive signal transmission section 221 is electrically connected to the second gate drive signal terminal 2111 and the gate drive signal line 14 respectively.

[0102] like Figure 12 and Figure 13 As shown, the display panel also includes a gate driving circuit 13 and a gate driving signal line 14 disposed in the first circuit setting area CSA1. The gate driving signal line 14 is used to provide a gate driving signal to the gate driving circuit 13, so as to drive the gate driving circuit to output a scan signal to the scan signal line disposed in the display area AA, and output a light emission control signal to the light emission control signal line disposed in the display area AA, thereby realizing the normal operation of the pixel circuit disposed in the display area AA and ensuring the normal display function of the display panel.

[0103] Furthermore, the first bonding area BAA1 is provided with a plurality of first type signal bonding terminals 11. The first type signal bonding terminals 11 include first type gate drive signal terminals 111. The first type gate drive signal terminals 111 include a plurality of first gate drive signal terminals 1111 arranged along the first direction. The first gate drive signal terminals 1111 are electrically connected to the gate drive signal line 14 through the first gate drive signal transmission unit 151. That is, the first gate drive signal terminals 1111 provided in the first non-display area NAA1 can provide gate drive signals to the gate drive signal line 14 to ensure that the gate drive circuit 13 can normally receive the gate drive signals provided by the gate drive signal line 14 and ensure that the gate drive circuit 13 works normally. The second non-display area NAA2 also includes a second bonding area BAA2 and a plurality of second type signal bonding terminals 21 disposed in the second bonding area BAA2. The second type signal bonding terminals 21 include second type gate drive signal terminals 211. The second type gate drive signal terminals 211 include a plurality of second gate drive signal terminals 2111 arranged along the second direction Y. The second gate drive signal terminals 2111 are electrically connected to the gate drive signal line 14 through the second gate drive signal transmission unit 221. That is, the second gate drive signal terminals 2111 disposed in the second non-display area NAA2 can provide gate drive signals to the gate drive signal line 14 to ensure that the gate drive circuit 13 can normally receive the gate drive signals provided by the gate drive signal line 14 and ensure that the gate drive circuit 13 works normally.

[0104] The gate drive signal provided by the first gate drive signal terminal 1111 in the first non-display area NAA1 to the gate drive signal line 14 and the gate drive signal provided by the second gate drive signal terminal 2111 in the second non-display area NAA2 to the gate drive signal line 14 can be the same or different. That is, the first gate drive signal terminal 1111 in the first non-display area NAA1 and the second gate drive signal terminal 2111 in the second non-display area NAA2 can be terminals that provide the same gate drive signal or terminals that provide different gate drive signals.

[0105] Specifically, when the first gate drive signal terminal 1111 and the second gate drive signal terminal 2111 are terminals that provide the same gate drive signal, the gate drive signal provided by the first gate drive signal terminal 1111 to the gate drive signal line 14 is the same as the gate drive signal provided by the second gate drive signal terminal 2111 to the gate drive signal line 14. For example, both include a clock signal, a level signal, an initialization signal, and a reset signal. That is, the gate drive signal provided by the first gate drive signal terminal 1111 to the gate drive signal line 14 can ensure the normal operation of the gate drive circuit 13, and the gate drive signal provided by the second gate drive signal terminal 2111 to the gate drive signal line 14 can also ensure the normal operation of the gate drive circuit 13. By setting the gate drive signal provided by the first gate drive signal terminal 1111 to the gate drive signal line 14 to be the same as the gate drive signal provided by the second gate drive signal terminal 2111 to the gate drive signal line 14, a dual-channel supply of the gate drive signal can be realized. While ensuring a safe and stable supply of the gate drive signal, it can also reduce the voltage drop of the gate drive signal during transmission and improve the accuracy of the gate drive signal transmission.

[0106] When the first gate drive signal terminal 1111 and the second gate drive signal terminal 2111 include terminals that provide different gate drive signals, the gate drive signal provided by the first gate drive signal terminal 1111 to the gate drive signal line 14 is different from the gate drive signal provided by the second gate drive signal terminal 2111 to the gate drive signal line 14. For example, the gate drive signal provided by the first gate drive signal terminal 1111 to the gate drive signal line 14 may include a clock signal, a level signal, and an initialization signal, while the gate drive signal provided by the second gate drive signal terminal 2111 to the gate drive signal line 14 may include a clock signal, a level signal, and a reset signal. Alternatively, the gate drive signal provided by the first gate drive signal terminal 1111 to the gate drive signal line 14 may include a clock signal and a level signal, while the gate drive signal provided by the second gate drive signal terminal 2111 to the gate drive signal line 14 may include an initialization signal and a reset signal. In other words, the combination of the gate drive signal provided by the first gate drive signal terminal 1111 to the gate drive signal line 14 and the gate drive signal provided by the second gate drive signal terminal 2111 to the gate drive signal line 14 ensures the normal operation of the gate drive circuit 13. By setting the gate drive signal provided by the first gate drive signal terminal 1111 to the gate drive signal line 14 to be different from the gate drive signal provided by the second gate drive signal terminal 2111 to the gate drive signal line 14, the first gate drive signal terminal 1111 and the second gate drive signal terminal 2111 can be flexibly configured. While ensuring a safe and stable supply of gate drive signals, the number of the first gate drive signal terminal 1111 and / or the second gate drive signal terminal 2111 can also be reduced, as can the number of the first gate drive signal transmission unit 151 and / or the second gate drive signal transmission unit 221. This facilitates the miniaturization design of the first non-display area NAA1 and / or the second non-display area NAA2.

[0107] For example, continue to refer to Figure 12 and Figure 13 As shown, the first type of gate drive signal terminal 111 includes a first group of gate drive signal terminals 111a, and the second type of gate drive signal terminal 211 includes a third group of gate drive signal terminals 211a. The first group of gate drive signal terminals 111a is located on the side of the first bonding region BAA1 near the second bonding region BAA2, and the third group of drive signal terminals 211a is located on the side of the second bonding region BAA2 near the first bonding region BAA1. The display panel also includes a second virtual axis of symmetry DA2, the extension direction of which intersects both the first direction X and the second direction Y. The first group of gate drive signal terminals 111a and the third group of gate drive signal terminals 211a are symmetrically arranged about the second virtual axis of symmetry DA2.

[0108] like Figure 13As shown, the first group of gate drive signal terminals 111a is disposed on the side of the first bonding region BAA1 near the second bonding region BAA2, and the third group of drive signal terminals 211a is disposed on the side of the second bonding region BAA2 near the first bonding region BAA1. Furthermore, the number of first gate drive signal terminals 1111 in the first group of gate drive signal terminals 111a is the same as the number of second gate drive signal terminals 2111 in the third group of gate drive signal terminals 211a. Further, the first group of gate drive signal terminals 111a and the third group of gate drive signal terminals 211a are symmetrically arranged about the second virtual axis of symmetry DA2. This symmetrical arrangement can be understood as the positions of the multiple first gate drive signal terminals 1111 in the first group of gate drive signal terminals 111a being symmetrically arranged about the second virtual axis of symmetry DA2 with respect to the positions of the multiple second gate drive signal terminals 2111 in the third group of gate drive signal terminals 211a. For example, the first gate drive signal terminal 1111 in the first group of gate drive signal terminals 111a, which transmits high-level signals, and the second gate drive signal terminal 2111 in the third group of gate drive signal terminals 211a, which transmits high-level signals, are located on opposite sides of the second virtual axis of symmetry DA2, and the distance between these two gate drive signal terminals transmitting high-level signals and the second virtual axis of symmetry is the same. Alternatively, the first group of gate drive signal terminals 111a and the third group of gate drive signal terminals 211a are symmetrically arranged about the second virtual axis of symmetry DA2. This symmetrical arrangement can also be understood as the arrangement order of the multiple first gate drive signal terminals 1111 in the first group of gate drive signal terminals 111a and the arrangement order of the multiple second gate drive signal terminals 2111 in the third group of gate drive signal terminals 211a being symmetrical about the second virtual axis of symmetry DA2. For example, in the first group of gate drive signal terminals 111a, the first gate drive signal terminals 1111 that transmit high-level signals, low-level signals, and clock signals are arranged sequentially along the first direction X, and in the first direction X, the first gate drive signal terminal 1111 that transmits high-level signals is located on the side closer to the second virtual axis DA2. In the second group of gate drive signal terminals 211a, the second gate drive signal terminals 1111 that transmit high-level signals, low-level signals, and clock signals are arranged sequentially along the second direction Y, and in the second direction Y, the second gate drive signal terminal 2111 that transmits high-level signals is located on the side closer to the second virtual axis DA2. By setting the first group of gate drive signal terminals 111a and the third group of gate drive signal terminals 211a symmetrically about the second virtual axis DA2, the first group of gate drive signal terminals 111a and the third group of gate drive signal terminals 211a are neatly arranged, and the signal transmission accuracy is high.

[0109] In one embodiment, Figure 14This is a schematic diagram of the structure of a first circuit setting area provided in an embodiment of this application, such as... Figure 14 As shown, the display panel also includes a gate driving circuit 13 disposed in the first circuit setting area CSA1; the gate driving circuit 13 includes at least two columns of shift register circuits, each column including a multi-stage shift register circuit VSR arranged along a first direction X, and the at least two columns of shift register circuits arranged along a second direction Y; the at least two columns of shift register circuits include an i-th column of shift register circuits Ci and a j-th column of shift register circuits Cj, the i-th column of shift register circuits Ci containing m-stage shift register circuit VSRs, and the j-th column of shift register circuits Cj containing n-stage shift register circuit VSRs; where i and j are different positive integers, and m and n are different positive integers; the i-th column of shift register circuits Cj... i Located in column C of the j-th shift register circuit j On the side furthest from the first bend BA1, m≤n.

[0110] like Figure 14 As shown in the embodiment of this application, the gate driving circuit 13 includes at least two columns of shift register circuits arranged along the second direction Y. The arrangement of the gate driving circuit 13 in this embodiment can reduce the size of the gate driving circuit 13 in the first direction X. Thus, the size of the first circuit setting area CSA1 in the first direction X is less than or equal to the size of the first straight side area AA1 in the first direction X, which makes it easier to bend the first circuit setting area CSA1 to the non-light-emitting side of the display panel without affecting the normal structure and normal driving function of the gate driving circuit 13.

[0111] At least two shift register circuit columns include the i-th shift register circuit column Ci and the j-th shift register circuit column Cj. Each shift register circuit column includes multiple stages of shift register circuits (VSRs). These VSRs are cascaded to achieve normal output of the gate shift signal. Furthermore, the number of stages m of the shift register circuits in the i-th shift register circuit column Ci and the number of stages n of the shift register circuits in the j-th shift register circuit column Cj satisfy m ≤ n. That is, the number of stages of the shift register circuits in the j-th shift register circuit column Cj closest to the first bending region BA1 is not less than the number of stages of the shift register circuits in the i-th shift register circuit column Ci furthest from the first bending region BA1; or, in other words, the number of stages of the shift register circuits in the j-th shift register circuit column Cj closest to the first bending region BA1 is greater. Since the j-th column of shift register circuits Cj, which is closer to the display area AA on the side near the first bending area BA1, is simpler to connect to the signal lines in the display area AA, the wiring process is simpler. Therefore, the j-th column of shift register circuits Cj contains more VSRs, which can ensure that more VSRs are connected to the signal lines in the display area AA, making the wiring process simpler, reducing the wiring difficulty of the display panel, and ensuring a simple wiring process.

[0112] Figure 15 This is a schematic diagram of another first circuit setting area provided in an embodiment of this application, combined with... Figure 14 and Figure 15 As shown, the i-th column of shift registers Ci and the j-th column of shift registers Cj are arranged adjacent to each other along the second direction Y; the i-th column of shift registers Ci includes the p-th stage shift register VSR-P and the (p+1)-th stage shift register VSR-P+1, and the j-th column of shift registers Cj includes the (p+2)-th stage shift register VSR-P+2 and the (p+3)-th stage shift register VSR-P+3; p is a positive integer; the p-th stage shift register... The circuit VSR-P, the (p+1)th stage shift register circuit VSR-P+1, the (p+2)th stage shift register circuit VSR-P+2, and the (p+3)th stage shift register circuit VSR-P+3 are cascaded in sequence; the direction in which the p-th stage shift register circuit VSR-P points to the (p+1)th stage shift register circuit VSR-P+1 is opposite to the direction in which the (p+2)th stage shift register circuit VSR-P+2 points to the (p+3)th stage shift register circuit VSR-P+3.

[0113] like Figure 14 and Figure 15As shown, the i-th column of shift register circuits Ci includes a p-th stage shift register circuit VSR-p and a p+1-th stage shift register circuit VSR-p+1 cascaded together, and the j-th column of shift register circuits Cj includes a p+2-th stage shift register circuit VSR-p+2 and a p+3-th stage shift register circuit VSR-p+3 cascaded together. The direction in which the p-th stage shift register circuit VSR-p points to the (p+1)-th stage shift register circuit VSR-p+1 is opposite to the direction in which the (p+2)-th stage shift register circuit VSR-p+2 points to the (p+3)-th stage shift register circuit VSR-p+3. Thus, when the (p+1)-th stage shift register circuit VSR-p+1 and the (p+2)-th stage shift register circuit VSR-p+2 are cascaded, the output signal of the (p+1)-th stage shift register circuit VSR-p+1 is directly used as the input signal of the (p+2)-th stage shift register circuit VSR-p+2. The cascading method between the (p+1)-th stage shift register circuit VSR-p+1 and the (p+2)-th stage shift register circuit VSR-p+2 is simple.

[0114] In one embodiment, Figure 16 This is a schematic diagram of another structure of the first circuit setting area provided in the embodiments of this application. Figure 17 This is a schematic diagram of another first circuit setting area provided in the embodiments of this application, combined with Figure 16 and Figure 17 As shown, the i-th column of shift registers Ci and the j-th column of shift registers Cj are arranged adjacent to each other along the second direction Y; the j-th column of shift registers Cj includes the q-th stage shift register VSR-q and the q+1-th stage shift register, and the i-th column of shift registers includes the q+2-th stage shift register and the q+3-th stage shift register; q is a positive integer; the q-th stage shift register, the q+1-th stage shift register, the q+2-th stage shift register, and the q+3-th stage shift register are cascaded sequentially; the direction from the q-th stage shift register to the q+1-th stage shift register is opposite to the direction from the q+2-th stage shift register to the q+3-th stage shift register.

[0115] like Figure 16 and Figure 17As shown, the j-th column of shift register circuits Cj includes a cascaded q-th stage shift register circuit VSR-q and a q+1-th stage shift register circuit VSR-q+1, and the i-th column of shift register circuits Ci includes a cascaded q+2-th stage shift register circuit VSR-q+2 and a q+3-th stage shift register circuit VSR-q+3. The direction in which the q-th stage shift register VSR-q points to the (q+1)-th stage shift register VSR-q+1 is opposite to the direction in which the (q+2)-th stage shift register VSR-q+2 points to the (q+3)-th stage shift register VSR-q+3. Thus, when the (q+1)-th stage shift register VSR-q+1 and the (q+2)-th stage shift register VSR-q+2 are cascaded, the output signal of the (q+1)-th stage shift register VSR-q+1 is directly used as the input signal of the (q+2)-th stage shift register VSR-q+2. The cascading method between the (q+1)-th stage shift register VSR-q+1 and the (q+2)-th stage shift register VSR-q+2 is simple.

[0116] Figure 18 This is a schematic diagram of another display panel structure provided in an embodiment of this application, such as... Figure 18 As shown, the i-th column of shift registers Ci and the j-th column of shift registers Cj are arranged adjacent to each other along the second direction Y; the i-th column of shift registers Ci includes the g-th level shift register VSR-g; g is a positive integer; the j-th column of shift registers Cj includes the k-th level shift register VSR-k and the (k+1)-th level shift register VSR-k+1, which are arranged adjacent to each other along the first direction X, and the k-th level shift register... There is a first gap 1 between VSR-k and the (k+1)th level shift register circuit VSR-k+1; k is a positive integer; along the second direction Y, the g-th level shift register circuit VSR-g overlaps with the first gap 1; the display panel also includes multiple shift output signal lines 16 and multiple scan signal lines 17, the shift output signal lines 16 are electrically connected to the shift register circuit 13 and the scan signal lines 17 respectively; the shift output signal lines 16 electrically connected to the g-th level shift register circuit VSR-g extend along the first gap 1.

[0117] like Figure 18As shown, the display panel also includes a shift output signal line 16 and a scan signal line 17. At least a portion of the shift output signal line 16 is located in the first non-display area NAA1. The shift output signal line 16 is electrically connected to the gate drive circuit 13 and the scan signal line 17, and is used to output the scan drive signal output by the gate drive circuit 13 to the scan signal line 17, so that the scan signal in the scan signal line 17 can control the conduction and cutoff of the transistors in the pixel circuit, thereby realizing the normal light emission display of the pixel circuit driving the light-emitting element. Specifically, the i-th column of shift register circuits Ci includes the g-th stage shift register circuit VSR-g, and the j-th column of shift register circuits Cj includes the k-th stage shift register circuit VSR-k and the (k+1)-th stage shift register circuit VSR-k+1 arranged adjacent to each other in the first direction X. There is a first gap 1 between the k-th stage shift register circuit VSR-k and the (k+1)-th stage shift register circuit VSR-k+1. At least a portion of the shift output signal line 16 electrically connected to the g-th stage shift register circuit VSR-g is located within the first gap 1 and extends along the first gap 1. That is, at least some of the shift register circuits VSR in the i-th column Ci are staggered from at least some of the shift register circuits VSR in the j-th column Cj, and at least some of the shift register circuits VSR in the i-th column Ci correspond to the gap between two adjacent shift register circuits VSR in the j-th column Cj. This ensures that the shift output signal line 16, which is electrically connected to at least a portion of the shift register circuits VSR in the i-th column of shift register circuits Ci, can be routed through the gap between two adjacent shift register circuits VSR in the j-th column of shift register circuits Cj. On the one hand, this ensures normal electrical connection between the shift output signal line 16 and the scan signal line 17, and on the other hand, it ensures that the shift output signal line 16 will not overlap with the shift register circuits VSR in the j-th column of shift register circuits Cj, thus not affecting the normal operation of the shift register circuits VSR in the j-th column of shift register circuits Cj, and ensuring the normal operation of the entire gate drive circuit 13.

[0118] Continue to refer to Figure 18 As shown, the g-th shift register circuit VSR-g, the k-th shift register circuit VSR-k, and the (k+1)-th shift register circuit VSR-k+1 can be located on the side of the first circuit setting area CSA1 close to the second straight edge area AA2, and / or, the g-th shift register circuit VSR-g, the k-th shift register circuit VSR-k, and the (k+1)-th shift register circuit VSR-k+1 can be located on the side of the first circuit setting area CSA1 away from the second straight edge area AA2. Figure 18The following example illustrates how the g-th shift register circuit VSR-g, the k-th shift register circuit VSR-k, and the (k+1)-th shift register circuit VSR-k+1 can be located on the side of the first circuit setting area CSA1 closest to the second straight edge area AA2, while the g-th shift register circuit VSR-g, the k-th shift register circuit VSR-k, and the (k+1)-th shift register circuit VSR-k+1 can be located on the side of the first circuit setting area CSA1 furthest from the second straight edge area AA2.

[0119] For example, Figure 19 This is a schematic diagram of another structure of the first non-display area provided in an embodiment of this application, as shown below. Figure 19 As shown, the display panel also includes an anti-static circuit 18 disposed in the first circuit setting area CSA1; along the first direction X, the anti-static circuit 18 is disposed on the side of the i-th column shift register circuit Ci near the second straight edge area AA2.

[0120] like Figure 19 As shown, the display panel also includes an anti-static circuit 18 disposed in the first circuit setting area CSA1, and at least a portion of the signal lines 12 disposed in the first non-display area NAA1 are electrically connected to the anti-static circuit 18. Figure 19 The following explanation uses the example of a partial gate drive signal 14 being electrically connected to an anti-static circuit 18. The anti-static circuit 18 releases static electricity from the signal line 12, ensuring that the signal in the signal line 12 is protected from static interference and that the signal in the signal line 12 can be transmitted normally.

[0121] like Figure 19 As shown, since the number of stages of the shift register circuit VSR in the i-th column Ci is less than or equal to the number of stages of the shift register circuit VSR in the j-th column Cj, that is, the size of the shift register circuit VSR in the i-th column Ci in the first direction X is less than or equal to the size of the shift register circuit VSR in the j-th column Cj in the first direction X, setting the anti-static circuit 18 on the side of the i-th column Ci closest to the second straight edge area AA2 ensures that there is sufficient space in the first non-display area NAA to set the anti-static circuit 18. The reasonable placement of the anti-static circuit 18 ensures that the circuit layout in the entire first non-display area NAA1 is simple.

[0122] In one embodiment, Figure 20 This is a schematic diagram of the structure of another display panel provided in the embodiments of this application, such as... Figure 20As shown, the display panel also includes a gate driving circuit 13 disposed in the first circuit setting area CSA1; the gate driving circuit 13 includes at least two columns of shift register circuits, each column including a multi-level shift register circuit VSR arranged along the first direction X, and the at least two columns of shift register circuits arranged along the second direction Y; the at least two columns of shift register circuits include an i-th column of shift register circuits Ci and a j-th column of shift register circuits Cj, the i-th column of shift register circuits Ci being located away from the j-th column of shift register circuits Cj from the first bending area B. On one side of A1; where i and j are different positive integers; the display panel also includes multiple shift output signal lines 16 and multiple scan signal lines 17, the shift output signal lines 16 are electrically connected to the shift register circuit VSR and the scan signal lines 17 respectively; the multiple shift output signal lines 16 include multiple first shift output signal lines 161, the first shift output signal lines 161 are electrically connected to the shift register circuit VSR in the i-th column of shift register circuit Ci; some of the signal lines in the first shift output signal lines 161 are located in the display area AA.

[0123] like Figure 20 As shown, the gate driving circuit 13 includes at least two columns of shift register circuits arranged along the second direction Y. In this embodiment, the gate driving circuit 13 can be configured in a way that reduces its size in the first direction X. Thus, the size of the first circuit setting area CSA1 in the first direction X is less than or equal to the size of the first straight side area AA1 in the first direction X, which makes it easier to bend the first circuit setting area CSA1 to the non-light-emitting side of the display panel without affecting the normal structure and normal driving function of the gate driving circuit 13.

[0124] Furthermore, at least two shift register circuit columns include the i-th shift register circuit column Ci and the j-th shift register circuit column Cj. Each shift register circuit column includes a multi-stage shift register circuit VSR, which is cascaded to achieve normal output of the gate shift signal. Figure 20 As shown, the display panel also includes a shift output signal line 16 and a scan signal line 17. The shift output signal line 16 is electrically connected to the gate drive circuit 13 and the scan signal line 17, and is used to output the scan drive signal output by the gate drive circuit 13 to the scan signal line 17, so that the scan signal in the scan signal line 17 can control the conduction and cutoff of the transistor in the pixel circuit, and realize the normal light emission display of the pixel circuit driving the light-emitting element.

[0125] The i-th column of shift register circuits Ci is located on the side of the j-th column of shift register circuits Cj away from the first bend area BA1. The first shift output signal line 161 is electrically connected to the shift register circuit VSR in the i-th column of shift register circuits Ci, that is, the first shift output signal line 161 is electrically connected to the shift register circuit VSR on the side away from the display area AA. And refer to... Figure 20 As shown, the scan signal line 17, electrically connected to the first shift output signal line 161, is located on the side closer to the second non-display area NAA2. The extension length of the first non-display area NAA1 in the first direction X is less than or equal to the length of the first straight edge area AA1, meaning the extension length of the first non-display area NAA1 in the first direction X is less than the extension length of the display area AA in the first direction X. Thus, when the first shift output signal line 161 is electrically connected to the corresponding scan signal line 17, the first shift output signal line 161 will have a portion of trace extending in the first direction X. When this portion of trace extending in the first direction X of the first shift output signal line 161 is located in the first non-display area NAA1, the bezel size of the first non-display area NAA1 will be larger, which will affect the narrow bezel design of the display panel. Therefore, in this embodiment of the application, a portion of the signal lines in the first shift output signal line 161 are distributed in the display area AA. In this way, a portion of the traces extending in the first direction X of the first shift output signal line 161 will not occupy the space in the first non-display area NAA1 that is not bent to the non-light-emitting side of the display panel, thus ensuring that the design of a narrow bezel and high screen ratio of the display panel can be achieved.

[0126] Continue to refer to Figure 20 As shown, the display area AA also includes an irregular area AAY, which is connected to the first straight edge area AA1 and the second straight edge area AA2; at least part of the first shift output signal line 16 is electrically connected to the scan signal line 17 disposed in the irregular area AAY.

[0127] refer to Figure 20 As shown, the display area AA also includes a connecting display area between the first straight edge area AA1 and the second straight edge area AA2. The connecting display area can be a non-rectangular display area, such as a rounded corner display area. In this embodiment, the non-rectangular display area can be collectively referred to as the irregular display area AAY, and the specific shape of the irregular display area AAY is not limited. The irregular display area AAY can be, for example, a rounded corner display area or a rounded arc corner display area.

[0128] Furthermore, at least some of the first shift output signal lines 16 can be electrically connected to the scan signal lines 17 located in the irregular area AAY. This ensures that the scan signal lines 17 located in the irregular area AAY can normally receive the scan drive signal output by the shift register circuit VSR, and ensures that the pixel circuit and light-emitting elements in the irregular area AAY work normally.

[0129] Furthermore, since the irregular display area AAY is closer to the second non-display area NAA1 than the first non-display area NAA1, meaning there is a distance between the first non-display area NAA1 and the irregular display area AAY in the first direction X, when at least a portion of the first shift output signal lines 16 are electrically connected to the scan signal lines 17 located in the irregular area AAY, some of the signal lines in the at least a portion of the first shift output signal lines 161 are distributed in the display area AA. In this case, the arrangement of the first shift output signal lines 161 will not occupy additional space in the first non-display area NAA1, ensuring that the narrow bezel design of the display panel can be achieved.

[0130] Continue to refer to Figure 20 As shown, the first shift output signal line 161 located in the display area AA can be located on the side closer to the second straight edge area AA2 and / or on the side farther away from the second display area AA2. Figure 20 The following is an example of the first shift output signal line 161 located in display area AA1 being located on the side closer to the second display area AA2 and on the side farther away from the second display area AA2.

[0131] Furthermore, the display area AA may also include a third straight edge area AA3, an irregular shape area AAY connecting the first straight edge area AA1 and the second straight edge area AA2, and / or, an irregular shape area AAY connecting the first straight edge area AA1 and the third straight edge area AA3. Figure 20 Let's take an irregular region AAY that connects the first straight edge region AA1 and the second straight edge region AA2, and also an irregular region AAY that connects the first straight edge region AA1 and the third straight edge region AA3, as an example. Figure 20 As shown, some signal lines in the first shift output signal line 161 are located on the side closer to the second straight edge area AA2, and / or some signal lines in the first shift output signal line 161 are located on the side closer to the third straight edge area AA3. In this case, the arrangement of the first shift output signal line 161 will not occupy additional space in the first non-display area NAA1, thus fully ensuring that the narrow bezel design of the display panel can be realized.

[0132] Figure 21 This is a schematic diagram of the structure of a first shift output signal line provided in an embodiment of this application, with reference to... Figure 20 and Figure 21As shown, the first shift output signal line 161 includes a first shift output section 1611, a second shift output section 1612, a third shift output section 1613, and a fourth shift output section 1614; the first shift output section 1611 includes a first sub-section 16111 and a second sub-section 16112 electrically connected; the third shift output section 1613 includes a third sub-section 16131 and a fourth sub-section 16132 electrically connected; the first sub-section 16111 is located in the first non-display area NAA1 and is electrically connected to the shift register circuit VSR in the i-th column of shift register circuits Ci; the second sub-section 16112 is located in the display area AA and is connected to the second shift output section... 1612 is electrically connected, and the second sub-branch 16112 extends along the second direction Y; the second shift output branch 1612 is located in the display area AA and is electrically connected to the third sub-branch 16131, and the second shift output branch 1612 extends along the first direction X; the third sub-branch 16131 is located in the display area AA and extends along the second direction Y; the fourth sub-branch 16132 is located in the first non-display area NAA1 and is electrically connected to the fourth shift output branch 1614, and the fourth sub-branch 16132 extends along the second direction Y; the fourth shift output branch 1614 is located in the first non-display area NAA1 and is electrically connected to the scan signal line 17, and the fourth shift output branch 1614 extends along the first direction X.

[0133] like Figure 20 and Figure 21 As shown, the first shift output signal line 161 includes a first shift output section 1611, a second shift output section 1612, a third shift output section 1613, and a fourth shift output section 1614. The first shift output section 1611, the second shift output section 1612, the third shift output section 1613, and the fourth shift output section 1614 are connected to realize the electrical connection between the shift register circuit VSR in the i-th column of shift register circuits Ci and the scan signal line 17, so that the shift register circuit VSR in the i-th column of shift register circuits Ci outputs a scan drive signal to the scan signal line 17. Furthermore, the first shift output section 1611 and the third shift output section 1613 generally extend along the first direction X, the second shift output section 1612 generally extends along the second direction Y, and the fourth shift output line 1614 generally extends along the second direction Y, or generally extends along the edge of the irregular display area AAY. By setting the approximate extension directions of the first shift output section 1611, the second shift output section 1612, the third shift output section 1613, and the fourth shift output section 1614, it is ensured that the extension directions of the first shift output section 1611, the second shift output section 1612, the third shift output section 1613, and the fourth shift output section 1614 are consistent with or substantially consistent with the extension directions of other signal lines located in the display area AA, thereby ensuring the overall wiring consistency of the display area AA and ensuring the optical effect of the display panel.

[0134] For example, the first shift output portion 1611 includes a second sub-portion 16112 located in the display area AA, the second sub-portion 16112 extending generally along the second direction Y; the third shift output portion 1613 includes a third sub-portion 16131 located in the display area AA, the third sub-portion 16131 extending generally along the second direction Y, the extension directions of the second sub-portion 16112 and the third sub-portion 16131 are consistent and intersect with the extension direction of the second shift output portion 1612, at this time the second sub-portion 16112 and the third sub-portion 16131 can be set on the same layer and on a different layer from the second shift output portion 1612. In other words, signal lines or signal line distributions with the same or roughly the same extension direction can be set in the same layer, while signal lines or signal line distributions with intersecting extension directions can be set in different layers. This simplifies the film layer setting method of the first shift output signal line 161 in the display area AA, avoids increasing or excessively increasing the film layer structure of the display area AA due to the setting of the first shift output signal line 161 in the display area AA, and ensures that the film layer structure of the first shift output signal line 161 and the entire display area AA is simple, which facilitates the realization of a thinner display panel design.

[0135] Figure 22 This is a schematic diagram of the circuit structure of a pixel circuit provided in an embodiment of this application. Figure 23 yes Figure 22 The driving timing diagram corresponding to the pixel circuit shown is as follows: Figure 24 This is a schematic diagram of the film structure of a pixel circuit provided in an embodiment of this application. Figure 25 This is a schematic diagram of the film layer structure of a display panel provided in an embodiment of this application, combined with... Figure 22 , Figure 23 , Figure 24 and Figure 25As shown, the display panel also includes a substrate 10 and a pixel circuit 20 located in the display area; the pixel circuit 20 includes at least one first-type transistor 201, at least one second-type transistor 202, and at least one storage capacitor Cst; the first-type transistor 201 includes a first active layer 2011 and a first gate 2012; the second-type transistor 202 includes a second active layer 2021, a second top gate 2022, and a second bottom gate 2023; the first gate 2012 is located on the side of the first active layer 2011 close to the substrate 10 or on the side of the first active layer 2011 far from the substrate 10. The second active layer 2021 is located on the side away from the substrate 10; the second top gate 2022 is located on the side of the second active layer 2021 away from the substrate 10, and the second bottom gate 2023 is located on the side of the second active layer 2021 close to the substrate 10; the storage capacitor Cst includes a first capacitor plate Cst1 and a second capacitor plate Cst2 disposed opposite to each other, with the second capacitor plate Cst2 located on the side of the first capacitor plate Cst1 away from the substrate 10; the display panel also includes a first metal layer M1, a second metal layer MC, a third metal layer MG, a first source / drain electrode layer SD1, a second source / drain electrode layer SD2, and a third source / drain electrode layer SD2. Electrode layer SD3; First gate 2012 is located in first metal layer M1, second bottom gate 2023 is located in second metal layer MC, second top gate 2022 is located in third metal layer MG, first source / drain electrode layer SD1 is located on the side of third metal layer MG away from substrate 10, second source / drain electrode layer SD2 is located on the side of first source / drain electrode layer SD1 away from substrate 10, and third source / drain electrode layer SD3 is located on the side of second source / drain electrode layer SD2 away from substrate 10; second sub-section 16112 is located in first metal layer M1, second metal layer MC, third metal layer MG, and first... The second shift output portion 1612 is located in at least one of the first metal layer M1, the second metal layer MC, the third metal layer MG, the first source-drain metal layer SD1, the second source-drain metal layer SD2, and the third source-drain metal layer SD3; the third sub-portion 16131 is located in at least one of the first metal layer M1, the second metal layer MC, the third metal layer MG, the first source-drain metal layer SD1, the second source-drain metal layer SD2, and the third source-drain metal layer SD3.

[0136] Specifically, in combination Figure 22 and Figure 24As shown, the pixel circuit provided in this embodiment includes a first type of transistor and a second type of transistor 201. The first type of transistor can be a low-temperature polysilicon (LTPS) transistor, whose active layer includes silicon. LTPS transistors have advantages such as high switching speed, high carrier mobility, and low power consumption. The second type of transistor 202 can be an indium gallium zinc oxide (IGZO) transistor, whose active layer includes oxide. Oxide transistors have advantages such as low leakage current. The pixel circuit provided in this embodiment of the invention includes both the first type of transistor and the second type of transistor, which can combine the advantages of high switching speed, high carrier mobility, low power consumption, and low leakage current, ensuring excellent pixel circuit performance. Further, referring to 22, the pixel circuit provided in this embodiment of the invention can include a pixel circuit of the form "7T1C", where "T" represents a transistor and "C" represents a capacitor. The pixel circuit includes a first light-emitting control transistor T1, a data writing transistor T2, a driving transistor T3, a threshold compensation transistor T4, an initialization reset transistor T5, a second light-emitting control transistor T6, an anode reset transistor T7, and a storage capacitor Cst. Figure 22 Taking the pixel circuit shown as an example, the first light-emitting control transistor T1, the data writing transistor T2, the driving transistor T3, the second light-emitting control transistor T6, and the anode reset transistor T7 can be a first type transistor 201, and the threshold compensation transistor T4 and the initialization reset transistor T5 can be a second type transistor 202.

[0137] Combination Figure 22 and Figure 23As shown, the operation of the pixel circuit can be roughly as follows: The scan signal line (shown as S1N in the figure) connected to the control terminal of the initialization reset transistor T5 can control the conduction and turn-off of the initialization reset transistor T5. When the initialization reset transistor T5 is on, the reset signal in the reset signal line (shown as VREF1 in the figure) connected to the input terminal of the initialization reset transistor T5 is written to the gate of the driving transistor T3 to reset the first node N1. The storage capacitor Cst can ensure the potential stability of the first node N1. The scan signal line (shown as S2N in the figure) connected to the control terminal of the threshold compensation transistor T4 can control the conduction and turn-off of the threshold compensation transistor T4. When the threshold compensation transistor T4 is on, the threshold voltage of the driving transistor T3 is compensated. The scan signal line (shown as SP* in the figure) connected to the control terminal of the data writing transistor T2 can control the conduction and turn-off of the data writing transistor T2. When the data writing transistor T2 is on, the data signal on the data signal line DATA is written to the first terminal of the driving transistor T3. Simultaneously, the scan signal line (shown as SP in the figure) connected to the control terminal of the anode reset transistor T7 can control the on and off states of the anode reset transistor T7. When the anode reset transistor T7 is on, it resets the anode RE of the light-emitting element connected to the pixel circuit, i.e., the reset signal on the reset signal line (shown as VFER2 in the figure) is written to the anode RE of the light-emitting element. The light-emitting control signal line EMIT, connected to the control terminals of the first light-emitting control transistor T1 and the second light-emitting control transistor T6, can control the on and off states of the first light-emitting control transistor T1 and the second light-emitting control transistor T6. When the first light-emitting control transistor T1 and the second light-emitting control transistor T6 are on, it writes the power signal transmitted by the first power signal line PVDD to the light-emitting element, thereby realizing the display and illumination of the light-emitting element. For details, refer to... Figure 23 As shown, in one driving cycle Y of the pixel circuit, there are three stages: a data writing stage Y1, an emission stage Y2, and an emission holding stage Y3. The data writing stage Y1 includes a disabled level stage of the emission control signal Emit; the emission stage Y2 includes an enabled level stage of the emission control signal Emit; and the emission holding stage Y3 includes multiple disabled level stages and at least one enabled level stage of the emission control signal Emit. Figure 23(Taking an enable level phase as an example for illustration). Further, during the data writing phase Y1, the signal transmitted by the scan signal line SP includes at least one low-level period, during which the anode reset transistor T7 is turned on. The anode reset signal line VREF2 can reset and adjust the anode RE of the light-emitting element through the anode reset transistor T7. And during this period, the signal transmitted by the scan signal line S1N includes at least one high-level period, during which the initialization transistor T5 is turned on. The initialization signal line VREF1 can adjust the gate of the driving transistor T3 through the initialization transistor T5. Furthermore, the signal transmitted by the scan signal line SP* includes at least one low-level period during which the data writing transistor T2 is turned on, and the signal transmitted by the scan signal line S2N includes at least one high-level period during which the threshold compensation transistor T4 is turned on. The data signal Vdata can be transmitted to the gate of the driving transistor T3 through the data writing transistor T2 and the threshold compensation transistor T4. At the same time, the signal transmitted by the light emission control signal line EMIT includes at least one low-level device, during which the light emission control transistors T1 and T6 are turned on. The driving transistor T3 is used to convert the power signal provided by the first power signal line PVDD and the data signal provided by the data signal line DATA into a driving current to drive the light emission element to emit light, thereby realizing light emission.

[0138] Combination Figure 24 and Figure 25As shown, the first type transistor 201 includes a first active layer 2011, a first gate 2012, a first source 2023 and a first drain 2024, the second type transistor 202 includes a second active layer 2021, a top gate 2022, a bottom gate 2023, a second source 2024 and a second drain 2025, and the storage capacitor Cst includes a first capacitor plate Cst1 and a second capacitor plate Cst2 disposed opposite to each other. The display panel includes a substrate 10, a first semiconductor layer POLY, a first metal layer M1, a second metal layer MC, a second semiconductor layer IGZO, a third metal layer MG, a first source / drain electrode layer SD1, a second source / drain electrode layer SD2, and a third source / drain electrode layer SD3, all stacked together. Specifically, a first active layer 2011 is located on the first semiconductor layer POLY; a first gate 2012 and a first capacitor plate Cst1 are located on the first metal layer M1; a bottom gate 2023 and a second capacitor plate Cst2 are located on the second metal layer MC; a second active layer 2021 is located on the second semiconductor layer IGZO; a top gate 2022 is located on the third metal layer MG; the first source / drain electrode layer SD1 is located on the side of the third metal layer MG away from the substrate 10; the second source / drain electrode layer SD2 is located on the side of the first source / drain electrode layer SD1 away from the substrate 10; and the third source / drain electrode layer SD3 is located on the side of the second source / drain electrode layer SD2 away from the substrate 10. Based on the film layer configuration of the display panel, the second sub-section 16112 of the first shift output signal line 161 located in the display area AA can be located in at least one of the first metal layer M1, the second metal layer MC, the third metal layer MG, the first source / drain metal layer SD1, the second source / drain metal layer SD2, and the third source / drain metal layer SD3. The second shift output sub-section 1612 of the first shift output signal line 161 located in the display area AA is located in at least one of the first metal layer M1, the second metal layer MC, the third metal layer MG, the first source / drain metal layer SD1, the second source / drain metal layer SD2, and the third source / drain metal layer SD3. The third sub-section 16131 of the first shift output signal line 161 located in the display area AA is located in at least one of the first metal layer M1, the second metal layer MC, the third metal layer MG, the first source / drain metal layer SD1, the second source / drain metal layer SD2, and the third source / drain metal layer SD3. In other words, the structure in the display area AA of the first shift output signal line 161 is located in the existing film layer in the display panel. Thus, the structure in the display area AA of the first shift output signal line 161 will not increase the film layer of the display panel. This means that while ensuring that the first shift output signal line 161 does not occupy the space in the first non-display area NAA1 that is not bent to the non-light-emitting side of the display panel, and ensuring that the display panel can achieve a narrow bezel and high screen ratio design, it can also ensure that the film layer structure of the display panel is simple, which is convenient for achieving a thinner design of the display panel.

[0139] For example, the following describes a possible configuration of the first shift output signal line 161 in the display area AA.

[0140] Figure 26 This is a schematic diagram of the structure of a display panel display area provided in an embodiment of this application, such as... Figure 26 As shown, the display panel provided in this embodiment includes multiple data signal lines DATA disposed in the display area AA. The multiple data signal lines DATA extend along a first direction X and are arranged along a second direction Y. The display panel also includes the display area AA and a non-display area NAA that at least partially surrounds the display area; the display area AA includes a first display area AA-1 and a second display area AA-2, the second display area AA-2 being located at least one side of the first display area AA-1 along the second direction Y. Figure 26 The example shows a second display area AA-2 located on either side of the first display area AA-1 along the second direction Y, but the actual implementation is not limited to this. Figure 26 As shown, the second display area AA-2 is located between the first display area AA-1 and the left and right non-display areas NAA. Along the second direction Y, the first display area AA-1 is closer to the center of the display panel, and the second display area AA-2 is closer to the edge of the display panel.

[0141] Both the first display area AA-1 and the second display area AA-2 include multiple data signal lines DATA. The display panel also includes multiple data connection traces FIAA disposed in the display area AA. The data signal lines DATA located in the second display area AA-2 are electrically connected to the fan-out traces (not shown) located in the second non-display area through the data connection traces FIAA. This saves area in the second non-display area and facilitates the design of a narrow bezel for the display panel. Specifically, the data connection traces FIAA include a first trace portion FIAA1 and a second trace portion FIAA2. The first trace portion extends along a first direction X of FIAA1, and the second trace portion extends along a second direction Y of FIAA2. The second trace portion FIAA2 is electrically connected to both the first trace portion FIAA1 and the data signal lines DATA located in the second display area AA-2, for transmitting data signals from the first trace portion FIAA1 to the data signal lines DATA in the second display area AA-2. Furthermore, the second trace portion FIAA2 and the first trace portion FIAA1 can be disposed on the same layer or on different layers; this embodiment of the invention does not limit this.

[0142] Continue to refer to Figure 26As shown, the display panel may further include virtual data connection traces L0 located in the display area AA. Virtual data connection traces L0 are insulated from data connection traces FIAA. The arrangement of virtual data connection traces L0 can balance the wiring density of the film layer containing data connection traces FIAA at different locations in the display area, ensuring that the wiring density is the same or similar in different areas of the display area, and ensuring good flatness and optical characteristics in different areas of the display area. Specifically, virtual data connection traces L0 may include a first virtual trace portion L01 and a second virtual trace portion L02. The first virtual trace portion L01 extends along a first direction X, and the second virtual trace portion L02 extends along a second direction Y. The first virtual trace portion L01 and the first trace portion FIAA1 can be on the same layer and insulated from each other, and the second virtual trace portion L02 and the second trace portion FIAA2 can be on the same layer and insulated from each other. The wiring density in the first direction X is balanced by the first virtual wiring portion L01, and the wiring density in the second direction Y is balanced by the second virtual wiring portion L02, ensuring that the film layer containing the data connection wiring FIAA has a balanced wiring density in different areas of the display area. In this embodiment, the wiring portion of the first shift output signal line 161 in the display area AA can at least partially reuse the virtual data connection wiring L0, that is, it uses the virtual data connection wiring L0 already set in the display area AA of the display panel to transmit the output signal of the gate drive circuit, ensuring that the scheme of setting the first shift output signal line 161 in the display area AA is feasible.

[0143] Specifically, both the second sub-section 16112 and the third sub-section 16131 extend along the second direction Y. Therefore, at least one of the second sub-section 16112 and the third sub-section 16131 can reuse the second virtual routing section L02 to achieve the design scheme in which the second sub-section 16112 and the third sub-section 16131 are located in the display area AA. The second shift output section 1612 extends along the first direction X. Therefore, the second shift output section 1612 can reuse the first virtual routing section L01 to achieve the design scheme in which the second shift output section 1612 is located in the display area AA.

[0144] Continue to refer to Figure 21As shown, the plurality of first shift output signal lines 161 include the r-th first shift output signal line 161r and the s-th first shift output signal line 161s, and the plurality of scan signal lines 17 include the e-th scan signal line 17e and the f-th scan signal line 17f; r and s are different positive integers, and e and f are different positive integers; the r-th first shift output signal line 161r is electrically connected to the e-th scan signal line 17e, and the s-th first shift output signal line 161s is electrically connected to the f-th scan signal line 17f; along the first direction X, the e-th scan signal line 17e is located on the side of the f-th scan signal line 17f away from the center of the display area; along the first direction X, the r-th scan signal line 17e is located on the side of the f-th scan signal line 17f away from the center of the display area; along the first direction X, the r-th scan signal line 17e is located on the side of the f-th scan signal line 17f away from the center of the display area. The second sub-section 16112 of the first shift output signal line 161r is located on the side of the second sub-section 16112 of the s-th first shift output signal line 161s away from the center of the display area; along the second direction Y, the second shift output section 1612 of the r-th first shift output signal line 161r is located on the side of the second shift output section 1612 of the s-th first shift output signal line 161s closer to the center of the display area; along the first direction X, the third sub-section 16131 of the r-th first shift output signal line 161r is located on the side of the third sub-section 16131 of the s-th first shift output signal line 161s away from the center of the display area.

[0145] like Figure 21As shown, the e-th scan signal line 17e is located on the side of the f-th scan signal line 17f away from the center of the display area. At this time, along the first direction X, the second sub-section 16112 of the r-th first shift output signal line 161r is located on the side of the second sub-section 16112 of the s-th first shift output signal line 161s away from the center of the display area; along the second direction Y, the second shift output section 1612 of the r-th first shift output signal line 161r is located on the side of the second shift output section 1612 of the s-th first shift output signal line 161s closer to the center of the display area; along the first direction X, the third sub-section 16131 of the r-th first shift output signal line 161r is located on the side of the third sub-section 16131 of the s-th first shift output signal line 161s away from the center of the display area. That is, the connection structure formed by the second sub-section 16112, the second shift output section 1612, and the third sub-section 16131 in the r-th first shift output signal line 161r semi-encloses the connection structure formed by the second sub-section 16112, the second shift output section 1612, and the third sub-section 16131 in the s-th first shift output signal line 161s. This reduces the number of crossovers between the r-th first shift output signal line 161r and the s-th first shift output signal line 161s, reduces signal interference caused by crossovers between the r-th first shift output signal line 161r and the s-th first shift output signal line 161s, and ensures that the r-th first shift output signal line 161r and the s-th first shift output signal line 161s can transmit the corresponding gate drive output signal to the corresponding scan signal line 17 with less interference, thus ensuring good transmission stability of the gate drive output signal.

[0146] In one embodiment, Figure 27 This is a schematic diagram of another first circuit setting area provided in an embodiment of this application, see reference. Figure 27As shown, the display panel also includes a gate drive circuit 13 and a gate drive signal line 14 disposed in the first circuit setting area CSA1, the gate drive circuit 13 and the gate drive signal line 14 being electrically connected; the gate drive circuit 13 includes at least two columns of shift register circuits, the shift register circuits include multi-level shift register circuits VSR arranged along the first direction X, and the at least two columns of shift register circuits are arranged along the second direction Y; the at least two columns of shift register circuits include the i-th column of shift register circuits Ci and the j-th column of shift register circuits. Column Cj; i and j are both positive integers; gate drive signal line 14 includes a first drive signal line portion 141 and a second drive signal line portion 142 that are electrically connected; both the first drive signal line portion 141 and the second drive signal line portion 142 extend along a first direction X; the first drive signal line portion 141 is electrically connected to the multi-stage shift register circuit VSR in the i-th column shift register circuit column Ci, and the second drive signal line portion 142 is electrically connected to the multi-stage shift register circuit VSR in the j-th column shift register circuit column Cj.

[0147] like Figure 27 As shown, the display panel also includes a gate driving circuit 13 and a gate driving signal line 14 disposed in the first circuit setting area CSA1. The gate driving signal line 14 is used to provide a gate driving signal to the gate driving circuit 13, so as to drive the gate driving circuit to output a scan signal to the scan signal line disposed in the display area AA, and output a light emission control signal to the light emission control signal line disposed in the display area AA, thereby realizing the normal operation of the pixel circuit disposed in the display area AA and ensuring the normal display function of the display panel.

[0148] For example, the gate driving circuit 13 includes at least two columns of shift register circuits arranged along the second direction Y. In this embodiment, the arrangement of the gate driving circuit 13 can reduce the size of the gate driving circuit 13 in the first direction X. Thus, the size of the first circuit setting area CSA1 in the first direction X is less than or equal to the size of the first straight side area AA1 in the first direction X, which makes it easier to bend the first circuit setting area CSA1 to the non-light-emitting side of the display panel without affecting the normal structure and normal driving function of the gate driving circuit 13. Specifically, at least two shift register circuit columns include the i-th shift register circuit column Ci and the j-th shift register circuit column Cj. Correspondingly, the gate drive signal line 14 includes a first drive signal line portion 141 and a second drive signal line portion 142 that are electrically connected. The first drive signal line portion 141 is electrically connected to the multi-stage shift register circuit VSR in the i-th shift register circuit column Ci, and the second drive signal line portion 142 is electrically connected to the multi-stage shift register circuit VSR in the j-th shift register circuit column Cj. This ensures that the shift register circuit VSRs in both the i-th and j-th shift register circuit columns Ci and Cj can receive the gate drive signal normally, and that both the i-th and j-th shift register circuit columns Ci and Cj can work normally and output the gate drive signal normally.

[0149] Continue to refer to Figure 7 and Figure 27 As shown, the gate drive signal line 14 further includes a third drive signal line portion 143 and / or a fourth drive signal line portion 144; the third drive signal line portion 143 is electrically connected to the first drive signal line portion 141 and the second drive signal line portion 142 respectively, and the third drive signal line portion 143 is located on the side of the first circuit setting area CSA1 close to the second non-display area NAA2; and / or, the fourth drive signal line portion 144 is electrically connected to the first drive signal line portion 141 and the second drive signal line portion 142 respectively, and the fourth drive signal line portion 144 is located on the side of the first circuit setting area CSA1 away from the second non-display area NAA2.

[0150] like Figure 7 and Figure 27As shown, the gate drive signal line 14 also includes a third drive signal line portion 143, which is electrically connected to the first drive signal line portion 141 and the second drive signal line portion 142 respectively. This realizes the electrical connection between the first drive signal line portion 141 and the second drive signal line portion 142, ensuring that the shift register circuits VSR in the i-th column shift register circuit Ci and the j-th column shift register circuit Cj can receive the gate drive signal normally, and ensuring that the shift register circuits VSR in the i-th column shift register circuit Ci and the j-th column shift register circuit Cj can work normally. For example, the third driving signal line branch 143 is located on the side of the first circuit setting area CSA1 near the second non-display area NAA2. The third driving signal line branch 143 can be electrically connected to the first type of gate driving signal terminal 111, and / or, the third driving signal line branch 143 can be electrically connected to the second type of gate driving signal terminal 211, ensuring that the third driving signal line branch 143 can stably receive the gate driving signal. When the third driving signal line branch 143 is simultaneously electrically connected to both the first type of gate driving signal terminal 111 and the second type of gate driving signal terminal 211, the transmission impedance of the gate driving signal can also be reduced, ensuring that the transmission accuracy of the gate driving signal is high.

[0151] like Figure 7 and Figure 27 As shown, the gate drive signal line 14 also includes a fourth drive signal line portion 144, which is electrically connected to the first drive signal line portion 141 and the second drive signal line portion 142, respectively. This realizes the electrical connection between the first drive signal line portion 141 and the second drive signal line portion 142, ensuring that the shift register circuits VSR in the i-th column shift register circuit Ci and the j-th column shift register circuit Cj can receive the gate drive signal normally, and ensuring that the shift register circuits VSR in the i-th column shift register circuit Ci and the j-th column shift register circuit Cj can work normally. For example, the fourth driving signal line branch 144 is located on the side of the first circuit setting area CSA1 away from the second non-display area NAA2. Compared with the side of the first circuit setting area CSA1 that is close to the second non-display area NAA2, the circuit structure and wiring structure on the side of the first circuit setting area CSA1 away from the second non-display area NAA2 are relatively simple. Therefore, the fourth driving signal line branch 144 located on the side of the first circuit setting area CSA1 away from the second non-display area NAA2 can have a more spacious wiring space, ensuring that the wiring process of the fourth driving signal line branch 144 is simple, the wiring stability is good, and the fourth driving signal line branch 144 can transmit the gate driving signal well.

[0152] Furthermore, when the gate drive signal line 14 includes both a third drive signal line portion 143 and a fourth drive signal line portion 144, the third drive signal line portion 143 is electrically connected to the first drive signal line portion 141 and the second drive signal line portion 142, respectively, and the fourth drive signal line portion 144 is electrically connected to the first drive signal line portion 141 and the second drive signal line portion 142, respectively. This ensures a good and stable electrical connection between the first drive signal line portion 141 and the second drive signal line portion 142, and also reduces the impedance in the gate drive signal line 14, thereby reducing the transmission impedance of the gate drive signal and ensuring high transmission accuracy of the gate drive signal.

[0153] Continue to refer to Figure 7 and Figure 27 As shown, the display panel includes a first gate drive signal line 14a and a second gate drive signal line 14b; the first drive signal line portion 141 of the first gate drive signal line 14a is located on the side of the first drive signal line portion 141 of the second gate drive signal line 14b away from the first bending region BA1, the second drive signal line portion 142 of the first gate drive signal line 14a is located on the side of the second drive signal line portion 142 of the second gate drive signal line 14b away from the first bending region BA1; the third drive signal line portion 143 of the first gate drive signal line 14a is located on the side of the third drive signal line portion 143 of the second gate drive signal line 14b close to the second straight edge region AA2, and / or, the fourth drive signal line portion 144 of the first gate drive signal line 14a is located on the side of the fourth drive signal line portion 144 of the second gate drive signal line 14b away from the second straight edge region AA2.

[0154] like Figure 7 and Figure 27As shown, the display panel includes a first gate drive signal line 14a and a second gate drive signal line 14b. The first gate drive signal line 14a and the second gate drive signal line 14b can be two gate drive signal lines that transmit different gate drive signals. For example, the first gate drive signal line 14a can be a gate drive signal that transmits a high-level signal, and the second gate drive signal line 14b can be a gate drive signal that transmits a low-level signal. Alternatively, the first gate drive signal line 14a can provide a gate drive signal for the first shift register circuit VSR1 in the shift register circuit VSR, and the second gate drive signal line 14b can provide a gate drive signal for the second shift register circuit VSR2 in the shift register circuit VSR. The first shift register circuit VSR1 can be, for example, a shift register circuit that outputs a light emission control signal, and the second shift register circuit VSR2 can be, for example, a shift register circuit that outputs a scan signal. This application embodiment does not limit the specific type of gate drive signal transmitted by the first gate drive signal line 14a and the second gate drive signal line 14b.

[0155] Specifically, the first drive signal line portion 141 in the first gate drive signal line 14a is located on the side of the first drive signal line portion 141 in the second gate drive signal line 14b that is away from the first bending region BA1, and the second drive signal line portion 142 in the first gate drive signal line 14a is located on the side of the second drive signal line portion 142 in the second gate drive signal line 14b that is away from the first bending region BA1, that is, the first drive signal line portion 141 in the first gate drive signal line 14a and the second gate drive signal line 14b that is away from the first bending region BA1. The relative positional relationship between the first drive signal line segments 141 in 4b is the same as the relative positional relationship between the first drive signal line segment 142 in the first gate drive signal line 14a and the second drive signal line segment 142 in the second gate drive signal line 14b. This arrangement can match the arrangement of the shift register circuit VSR in the i-th column shift register circuit column Ci and the shift register circuit VSR in the j-th column shift register circuit column Cj, ensuring that the connection between the gate drive signal line and the shift register circuit VSR is simple. Furthermore, the third driving signal line portion 143 in the first gate driving signal line 14a is located on the side of the third driving signal line portion 143 in the second gate driving signal line 14b that is closer to the second straight edge region AA2, and / or, the fourth driving signal line portion 144 in the first gate driving signal line 14a is located on the side of the fourth driving signal line portion 144 in the second gate driving signal line 14b that is farther away from the second straight edge region AA2. That is, the third driving signal line portion 143 in the first gate driving signal line 14a is located at a lower position compared to the third driving signal line portion 143 in the second gate driving signal line 14b; and the fourth driving signal line portion 144 in the first gate driving signal line 14a is located at a higher position compared to the fourth driving signal line portion 144 in the second gate driving signal line 14b. In summary, the third driving signal line portion 143 in the first gate driving signal line 14a is located closer to the periphery or edge region of the first non-display area NAA1 compared to the third driving signal line portion 143 in the second gate driving signal line 14b; and / or, the fourth driving signal line portion 144 in the first gate driving signal line 14a is located closer to the periphery or edge region of the first non-display area NAA1 compared to the fourth driving signal line portion 144 in the second gate driving signal line 14b. That is, the third driving signal line portions 143 and 144 in different gate driving signal lines 14 have the same arrangement, ensuring a regular arrangement of the gate driving signal lines and high stability of gate driving signal transmission.

[0156] In one embodiment, reference continues to... Figure 19As shown, the first non-display area NAA1 also includes a first bonding area BAA1, which is located on the side of the first circuit setting area CSA1 away from the first bending area BA1; the display panel also includes a first type of signal bonding terminal 11 disposed in the first bonding area BAA1, the first type of signal bonding terminal 11 includes a first type of gate drive signal terminal 111, the first type of gate drive signal terminal 11 includes a plurality of first gate drive signal terminals 1111 arranged along the first direction X; the display panel also includes a first type of gate drive signal transmission section 15, the first type of gate drive signal transmission section 15 includes a plurality of first gate drive signal transmission sections 151; the i-th column of shift register circuit Ci is located on the side of the j-th column of shift register circuit Cj close to the first bonding area BAA1; the first gate drive signal transmission section 151 is electrically connected to the first gate drive signal terminal 1111 and the first drive signal line section 141 respectively.

[0157] like Figure 19 As shown, the first non-display area NAA1 also includes a first bonding area BAA1 located on the side of the first circuit setting area CSA1 away from the first bonding area BA1. The first bonding area BAA1 is provided with a plurality of first type signal bonding terminals 11. The first type signal bonding terminals 11 are used to electrically connect with the flexible circuit board disposed in the first non-display area NAA1, to receive signals provided by the flexible circuit board, and to transmit the signals to the signal lines 12 disposed in the first non-display area NAA1. Specifically, the first type signal bonding terminals 11 include first type gate drive signal terminals 111. The first type gate drive signal terminals 111 include a plurality of first gate drive signal terminals 1111 arranged along a first direction. The first gate drive signal terminals 1111 can be understood as terminals for transmitting gate drive signals. The gate drive signals may include at least one of clock signals, level signals, initialization signals, and reset signals. For example, the display panel also includes a first type of gate drive signal transmission unit 15, which includes multiple first gate drive signal transmission units 151. The first gate drive signal transmission units 151 are electrically connected to the first gate drive signal terminal 1111 and the gate drive signal line 14, respectively. In this way, the first gate drive signal terminal 1111 transmits the gate drive signal in the first gate drive signal terminal 1111 to the gate drive signal line 14, thereby realizing the normal transmission of the gate drive signal.

[0158] Specifically, at least two shift register circuit columns include the i-th shift register circuit column Ci and the j-th shift register circuit column Cj. The i-th shift register circuit column Ci is located on the side of the j-th shift register circuit column closer to the first bonding area BAA1. The first drive signal line portion 141, which is electrically connected to the multi-level shift register circuit VSR in the i-th shift register circuit column Ci, is located on the side closer to the first bonding area BAA1 compared to the second drive signal line portion 142, which is electrically connected to the multi-level shift register circuit VSR in the j-th shift register circuit column Cj. The first gate drive signal transmission section 151 is electrically connected to the first gate drive signal terminal 1111 and the first drive signal line section 141, respectively. This ensures that the connection between the first gate drive signal transmission section 151 and the gate drive signal line 14 is simple, the trace length of the first gate drive signal transmission section 151 is small, and the transmission impedance of the gate drive signal on the first gate drive signal transmission section 151 is small, thus ensuring that the gate drive signal can be transmitted accurately.

[0159] In one embodiment, Figure 28 This is a schematic diagram of another structure of the first circuit setting area provided in the embodiments of this application, such as... Figure 28 As shown, the display panel also includes a gate driving circuit 13 disposed in the first circuit setting area CSA1. The gate driving circuit 13 includes at least two columns of shift register circuits. The shift register circuits include multi-level shift register circuits VSR arranged along the first direction X. The at least two columns of shift register circuits are arranged along the second direction Y. The at least two columns of shift register circuits include an i-th column of shift register circuits Ci and a j-th column of shift register circuits Cj. The shift register circuits VSR in the i-th column of shift register circuits Ci include a first shift register circuit VSR1 and a second shift register circuit VSR2 arranged along the second direction Y. The shift register circuits VSR in the j-th column of shift register circuits Cj include a first shift register circuit VSR1 and a second shift register circuit VSR2 arranged along the second direction Y.

[0160] like Figure 28As shown, the shift register circuits VSR in the i-th column Ci include a first shift register circuit VSR1 and a second shift register circuit VSR2 arranged along the second direction Y. Similarly, the shift register circuits VSR in the j-th column Cj also include a first shift register circuit VSR1 and a second shift register circuit VSR2 arranged along the second direction Y. The first shift register circuits VSR1 and VSR2 in the i-th column Ci have the same positional relationship as those in the j-th column Cj. For example, in the i-th column Ci, the first shift register circuit VSR1 is located on the side of the second shift register circuit VSR2 closest to the first binding area BAA1; similarly, in the j-th column Cj, the first shift register circuit VSR1 is located on the side of the second shift register circuit VSR2 closest to the first binding area BAA1. This configuration ensures that multiple shift register circuits located in different shift register circuit columns have the same positional relationship, which facilitates the stability between different shift register signals.

[0161] For example, the first shift register circuit VSR1 can be a light emission control shift register circuit, that is, the first shift register circuit VSR1 can output a light emission control signal, such as an Emit light emission control signal; the second shift register circuit VSR2 can be a first scan control shift register circuit, that is, the second shift register circuit VSR2 can output a first scan control signal, such as a Scan scan signal.

[0162] In one embodiment, Figure 29 This is a schematic diagram of another first circuit setting area provided in the embodiments of this application, such as... Figure 29As shown, the shift register circuits VSR in the i-th column Ci include a first shift register circuit VSR1, a third shift register circuit VSR3, and a second shift register circuit VSR2 arranged along the second direction Y. The shift register circuits VSR in the j-th column Cj also include a first shift register circuit VSR1, a third shift register circuit VSR3, and a second shift register circuit VSR2 arranged along the second direction Y. The first shift register circuits VSR1, VSR3, and VSR2 in the i-th column Ci have the same positional relationship as the first shift register circuits VSR1, VSR3, and VSR2 in the j-th column Cj. For example, in column i of shift register circuits Ci, the first shift register circuit VSR1 is located on the side of the third shift register circuit VSR3 near the first binding area BAA1, and the third shift register circuit VSR3 is located on the side of the second shift register circuit VSR2 near the first binding area BAA1; in column j of shift register circuits Cj, the first shift register circuit VSR1 is located on the side of the third shift register circuit VSR3 near the first binding area BAA1, and the third shift register circuit VSR3 is located on the side of the second shift register circuit VSR2 near the first binding area BAA1. This arrangement ensures that multiple shift register circuits located in different shift register circuit columns have the same positional relationship, facilitating the stability between different shift register signals.

[0163] For example, the first shift register circuit VSR1 can be a light emission control shift register circuit, that is, the first shift register circuit VSR1 can output a light emission control signal, such as an Emit light emission control signal; the second shift register circuit VSR2 can be a first scan control shift register circuit, that is, the second shift register circuit VSR2 can output a first scan control signal, such as a Scan scan signal; and the third shift register circuit VSR3 can be a second scan control shift register circuit, that is, the third shift register circuit VSR3 can output a second scan control signal, such as a Sn scan signal.

[0164] In one embodiment, Figure 30 This is a schematic diagram of another structure of the first circuit setting area provided in an embodiment of this application, such as... Figure 30As shown, the display panel also includes a gate driving circuit 13 disposed in the first circuit setting area CSA1. The gate driving circuit 13 includes at least two columns of shift register circuits. The shift register circuits include multi-level shift register circuits VSR arranged along the first direction X. The at least two columns of shift register circuits are arranged along the second direction Y. The at least two columns of shift register circuits include an i-th column of shift register circuits Ci and a j-th column of shift register circuits Cj. The shift register circuits VSR in the i-th column of shift register circuits Ci include a first shift register circuit VSR1 and a second shift register circuit VSR2 arranged along the second direction Y. The shift register circuits VSR in the j-th column of shift register circuits Cj include a second shift register circuit VSR2 and a first shift register circuit VSR1 arranged along the second direction Y.

[0165] like Figure 30 As shown, the shift register circuits VSR in the i-th column Ci include a first shift register circuit VSR1 and a second shift register circuit VSR2 arranged along the second direction Y. The shift register circuits VSR in the j-th column Cj include a second shift register circuit VSR2 and a first shift register circuit VSR1 arranged along the second direction Y. The first shift register circuit VSR1 and the second shift register circuit VSR2 in the i-th column Ci have different positional relationships from the first shift register circuit VSR1 and the second shift register circuit VSR2 in the j-th column Cj. For example, in the i-th column of shift registers Ci, the first shift register VSR1 is located on the side of the second shift register VSR2 closest to the first binding area BAA1; in the j-th column of shift registers Cj, the second shift register VSR2 is located on the side of the first shift register VSR1 closest to the first binding area BAA1. That is, the first and second shift registers VSR1 and VSR2 in the i-th column of shift registers Ci and the first and second shift registers VSR1 and VSR2 in the j-th column of shift registers Cj are arranged symmetrically. This arrangement ensures that shift registers of the same type are placed adjacent to each other in adjacent columns, minimizing interference between shift registers in different columns and ensuring normal operation of the shift registers in different columns.

[0166] For example, the first shift register circuit VSR1 can be a light emission control shift register circuit, that is, the first shift register circuit VSR1 can output a light emission control signal, such as an Emit light emission control signal; the second shift register circuit VSR2 can be a first scan control shift register circuit, that is, the second shift register circuit VSR2 can output a first scan control signal, such as a Scan scan signal.

[0167] In one embodiment, Figure 31 This is a schematic diagram of another structure of the first circuit setting area provided in the embodiments of this application, such as... Figure 31 As shown, the shift register circuits VSR in the i-th column Ci include a first shift register circuit VSR1, a third shift register circuit VSR3, and a second shift register circuit VSR2 arranged along the second direction Y. The shift register circuits VSR in the j-th column Cj include a second shift register circuit VSR2, a third shift register circuit VSR3, and a first shift register circuit VSR1 arranged along the second direction Y. The first shift register circuit VSR1, the third shift register circuit VSR3, and the second shift register circuit VSR2 in the i-th column Ci have different positional relationships from the first shift register circuit VSR1, the third shift register circuit VSR3, and the second shift register circuit VSR2 in the j-th column Cj. For example, in column i of shift registers Ci, the first shift register VSR1 is located on the side of the third shift register VSR3 closest to the first binding area BAA1, and the third shift register VSR3 is located on the side of the second shift register VSR2 closest to the first binding area BAA1; in column j of shift registers Cj, the second shift register VSR2 is located on the side of the third shift register VSR3 closest to the first binding area BAA1, and the third shift register VSR3 is located on the side of the first shift register VSR1 closest to the first binding area BAA1. This arrangement ensures that shift registers of the same type are placed adjacent to each other in adjacent columns, minimizing interference between shift registers in different columns and ensuring normal operation of the shift registers in different columns.

[0168] For example, the first shift register circuit VSR1 can be a light emission control shift register circuit, that is, the first shift register circuit VSR1 can output a light emission control signal, such as an Emit light emission control signal; the second shift register circuit VSR2 can be a first scan control shift register circuit, that is, the second shift register circuit VSR2 can output a first scan control signal, such as a Scan scan signal; and the third shift register circuit VSR3 can be a second scan control shift register circuit, that is, the third shift register circuit VSR3 can output a second scan control signal, such as a Sn scan signal.

[0169] Figure 32 This is a schematic diagram of another display panel structure provided in an embodiment of this application. Figure 33 This is a schematic diagram of the structure of a first bending region provided in an embodiment of this application, as shown below. Figure 32 and Figure 33As shown, the display panel also includes a gate driving circuit 13 disposed in the first circuit setting area CSA1. The gate driving circuit 13 includes a multi-level shift register circuit VSR arranged along the first direction X. The first non-display area NAA1 also includes a functional area FA. The display panel also includes multiple signal lines 12 disposed in the functional area FA. The signal lines 12 include power signal lines 121. The display panel also includes multiple shift output signal lines 16 and multiple scan signal lines 17. The shift output signal lines 16 are electrically connected to the shift register circuit VSR and the scan signal lines 17, respectively. The display panel also includes multiple jumper wires 19 disposed in the first bending area BA1. The multiple jumper wires 19 include multiple power signal jumper wires 191 and multiple shift output signal jumper wires 192. The power signal jumper wires 191 and the power signal lines 121 are disposed on different layers and electrically connected. The shift output signal jumper wires 192 and the shift output signal lines 16 are disposed on different layers and electrically connected. The power signal jumper wires 191 and the shift output signal jumper wires 192 are disposed on the same layer.

[0170] like Figure 32 As shown, the display panel also includes a gate drive circuit 13 and a gate drive signal line 14 disposed in the first circuit setting area CSA1. The gate drive signal line 14 provides a gate drive signal to the gate drive circuit 13 to drive the gate drive circuit 13 to output control signals such as scan signals and light emission control signals. The control signals such as scan signals and light emission control signals output by the gate drive circuit 13 are transmitted to the scan signal line 17 located in the display area AA via the shift output signal line 16. The scan signal line 17 transmits the scan signal, light emission control signal, and lamp control signal to the pixel circuit, thereby controlling the pixel circuit to drive the light-emitting element to emit light, realizing the normal display function of the display panel. The display panel also includes a power signal line 121 disposed in the functional area FA. The power signal line 121 receives the power signal output from the first type of bonding terminal 11 and transmits the power signal to the display area power signal line in the display area AA, so that the power signal can be normally transmitted to the pixel circuit and the light-emitting element, realizing the normal display function of the display panel. Continue to refer to Figure 32 As shown, both the shift output signal line 16 and the power signal line 121 need to pass through the first bending area BA1 when transmitting signals to the display area AA. Therefore, the display panel also includes multiple jumper wires 19 disposed in the first bending area BA1. The multiple jumper wires 19 include multiple power signal jumper wires 191 and multiple shift output signal jumper wires 192. The power signal jumper wires 191 are electrically connected to the power signal line 121, thereby realizing the transmission of power signals from the first non-display area NAA1 to the display area AA. The shift output signal jumper wires 192 are electrically connected to the shift output signal line 16, thereby realizing the transmission of control signals such as scanning signals and light emission control signals from the first non-display area NAA1 to the display area AA.

[0171] Since the jumper cable 19 is located in the first bending area BA1, to ensure that the jumper cable 19 will not break and will transmit signals normally and stably when the first non-display area NAA1 is bent, the jumper cable 19 can be designed to have good ductility. For example, the jumper cable 19 can be made of a metal layer with good ductility, such as a TI-AL-TI structure metal layer. Furthermore, considering the wiring requirements outside the first bending area BA1, the power signal jumper cable 191 and the power signal line 121 can be set on different layers and electrically connected, and the shift output signal jumper cable 192 and the shift output signal line 16 can be set on different layers and electrically connected. That is, the power signal line 121 is not set on the same layer as the power signal jumper cable 191, and the shift output signal jumper cable 192 is not set on the same layer as the shift output signal line 16, thus ensuring the wiring requirements outside the first bending area BA1 are met. Furthermore, considering the wiring requirements and simplicity of the first bending zone BA1, and to avoid affecting the bending performance of the first bending zone BA1 by laying too many film layers in the first bending zone BA1, the power signal jumper 191 and the shift output signal jumper 192 can be set on the same layer to ensure the wiring requirements and simplicity of the first bending zone BA1, while also ensuring the bending performance of the first bending zone BA1.

[0172] Continue to refer to Figure 32 As shown, the shift output signal line 16 can be located on the side closer to the second straight edge area AA2 and / or on the side farther away from the second display area AA2. Figure 32 The following explanation will be based on the example where the shift output signal line 16 is located on the side closer to the second display area AA2 and on the side farther away from the second display area AA2.

[0173] Continue to refer to Figure 33 As shown, the multiple power signal jumpers 191 include the vth power signal jumper 191v and the wth power signal jumper 191w, which are adjacent to each other along the first direction X; v and w are different positive integers; wherein, a shift output signal jumpers 192 are provided between the vth power signal jumper 191v and the wth power signal jumper 191w, where a is a positive integer.

[0174] like Figure 33 As shown, the multiple power signal jumpers 191 include a v-th power signal jumper 191v and a w-th power signal jumper 191w arranged adjacent to each other along the first direction X. At least one shift output signal jumper 192 is provided between the v-th power signal jumper 191v and the w-th power signal jumper 191w, meaning that a shift output signal jumper 192 is provided between any two adjacent power signal jumpers 191. This achieves a reasonable arrangement of the power signal jumpers 191 and the shift output signal jumpers 192 in the first bending area BA1.

[0175] Continue to refer to Figure 33 As shown, the multiple power signal jumpers 191 also include an xth power signal jumper 191x and a yth power signal jumper 191y arranged adjacent to each other along the first direction X; x and y are different positive integers; wherein, b shift output signal jumpers 192 are arranged between the xth power signal jumper 191x and the yth power signal jumper 191y; b is a positive integer and is not the same as a.

[0176] like Figure 33 As shown, the multiple power signal jumpers 191 include the xth power signal jumper 191x and the yth power signal jumper 191y arranged adjacent to each other along the first direction X, and at least one shift output signal jumper 192 is provided between the xth power signal jumper 191x and the yth power signal jumper 191y, that is, there is a shift output signal jumper 192 between two adjacent power signal jumpers 191. Furthermore, the number of shift output signal jumpers 192 set between the xth power signal jumper 191x and the yth power signal jumper 191y is different from the number of shift output signal jumpers 192 set between the vth power signal jumper 191v and the wth power signal jumper 191w. This allows for flexible and diverse settings of the power signal jumpers 191 and shift output signal jumpers 192 in the first bend area BA1. The power signal jumpers 191 and shift output signal jumpers 192 can be reasonably set according to the wiring space, ensuring that each VSR has a shift output signal jumper 192 electrically connected to it. At the same time, setting as many power signal jumpers 191 as possible reduces the transmission impedance of the power signal during transmission, reduces the power signal loss during transmission, and ensures accurate transmission of the power signal.

[0177] It should be noted that, Figure 33 This example illustrates, but is not a limitation, that there is one shift output signal jumper 192 between the v-th power signal jumper 191v and the w-th power signal jumper 191w, and two shift output signal jumpers 192 between the x-th power signal jumper 191x and the y-th power signal jumper 191y. It is understood that other numbers of shift output signal jumpers 192 may be set between the v-th power signal jumper 191v and the w-th power signal jumper 191w, and other numbers of shift output signal jumpers 192 may be set between the x-th power signal jumper 191x and the y-th power signal jumper 191y.

[0178] Continue to refer to Figure 32As shown, the gate drive circuit 13 includes at least two columns of shift register circuits, each column comprising a multi-level shift register circuit arranged along a first direction X, and at least two columns of shift register circuits arranged along a second direction Y. The first circuit setting area CSA1 includes a first setting partition CSA11 and a second setting partition CSA12 arranged along the first direction X, wherein the number of shift register circuit columns in the first setting partition CSA11 and the second setting partition CSA12 is different. The multiple shift output signal jumpers 192 include multiple first shift output signal jumpers 1921 and multiple second shift output signal jumpers 1922. The first shift output signal jumpers 1921 are electrically connected to the shift register circuit VSR in the first setting partition CSA11, and the second shift output signal jumpers 1922 are electrically connected to the shift register circuit VSR in the second setting partition CSA12. Multiple power signal jumpers 191 are provided between the first shift output signal jumpers 1921 and the second shift output signal jumpers 1922.

[0179] like Figure 32 As shown, the gate driving circuit 13 includes at least two columns of shift register circuits, which are arranged along the second direction Y. In this embodiment, the gate driving circuit 13 can be configured in a way that reduces its size in the first direction X. Thus, the size of the first circuit setting area CSA1 in the first direction X is less than or equal to the size of the first straight side area AA1 in the first direction X, which makes it easier to bend the first circuit setting area CSA1 to the non-light-emitting side of the display panel without affecting the normal structure and normal driving function of the gate driving circuit 13.

[0180] The first circuit setting area CSA1 includes a first setting partition CSA11 and a second setting partition CSA12 arranged along the first direction X. The number of shift register circuit columns in the first setting partition CSA11 and the second setting partition CSA12 is different. For example, the first setting partition CSA11 has two columns of shift register circuits, while the second setting partition CSA12 has one column and two columns of shift register circuits; or, for example, the first setting partition CSA11 has one column of shift register circuits, while the second setting partition CSA12 has two columns of shift register circuits. Because the number of shift register circuit columns in the first setting partition CSA11 and the second setting partition CSA12 is different, the number of shift register circuits (VSRs) contained in the first setting partition CSA11 and the second setting partition CSA12 along the same length in the first direction X is different. Therefore, the number of shift output signal lines 16 corresponding to the first setting partition CSA11 and the second setting partition CSA12 along the same length in the first direction X is different. Correspondingly, the number of shift output signal jumpers 192 corresponding to CSA12 in the first setting partition CSA11 and the second setting partition is different.

[0181] Specifically, the multiple shift output signal jumpers 192 include multiple first shift output signal jumpers 1921 and multiple second shift output signal jumpers 1922. The first shift output signal jumpers 1921 are electrically connected to the shift register circuit VSR in the first setting partition CSA11, and the second shift output signal jumpers 1922 are electrically connected to the shift register circuit VSR in the second setting partition CSA12. Therefore, the number of first shift output signal jumpers 1921 and second shift output signal jumpers 1922 differs. Thus, a gap can exist between the setting area of ​​the first shift output signal jumpers 1921 and the setting area of ​​the second shift output signal jumpers 1922; that is, a gap exists between the first shift output signal jumpers 1921 and the second shift output signal jumpers 1922. This gap can be used to set power signal jumpers 191, meaning that multiple power signal jumpers 191 are set between the first shift output signal jumpers 1921 and the second shift output signal jumpers 1922. This ensures that power signal jumpers 191 and shift output signal jumpers 192 can be laid simultaneously in the first bending zone BA1, and also ensures that as many power signal jumpers 191 as possible can be laid using the gaps, reducing power signal loss during transmission and ensuring the accuracy of the power signal.

[0182] For example, in combination Figure 32 and Figure 33 As shown, the gate drive circuit 13 includes at least two columns of shift register circuits, each column including a multi-level shift register circuit VSR arranged along the first direction X, and at least two columns of shift register circuits arranged along the second direction Y; the first circuit setting area CSA1 includes a first setting partition CSA11 and a second setting partition CSA12 arranged along the first direction X, the number of shift register circuit columns in the first setting partition CSA11 is less than the number of shift register circuit columns in the second setting partition CSA12; the first bending area BA1 includes a first sub-bending area BA11 and a second sub-bending area BA12, the first sub-bending area BA11 overlaps with the first setting partition CSA11 along the second direction Y, and the second sub-bending area BA12 overlaps with the second setting partition CSA12; the distribution density of power signal jumpers 191 in the first sub-bending area BA11 is greater than the distribution density of power signal jumpers 191 in the second sub-bending area BA12.

[0183] like Figure 32As shown, the first circuit setting area CSA1 includes a first setting partition CSA11 and a second setting partition CSA12 arranged along the first direction X. The number of shift register circuit columns in the first setting partition CSA11 is less than the number of shift register circuit columns in the second setting partition CSA12. For example, the first setting partition CSA11 has one column of shift register circuits, and the second setting partition CSA12 has two columns of shift register circuits. Because the number of shift register circuit columns in the first setting partition CSA11 is less than the number of shift register circuit columns in the second setting partition CSA12, the number of shift register circuit VSRs in the first setting partition CSA11 is less than the number of shift register circuit VSRs in the second setting partition CSA12 over the same length in the first direction X. Therefore, the number of shift output signal lines 16 corresponding to the first setting partition CSA11 is less than the number of shift output signal lines 16 corresponding to the second setting partition CSA12 over the same length in the first direction X. Correspondingly, the number of shift output signal jumpers 192 corresponding to the first setting partition CSA11 is less than the number of shift output signal jumpers 192 corresponding to CSA12 in the second setting partition.

[0184] Specifically, the first bending region BA1 includes a first sub-bending region BA11 and a second sub-bending region BA12. Along the second direction Y, the first sub-bending region BA11 overlaps with the first setting partition CSA11, and the second sub-bending region BA12 overlaps with the second setting partition CSA12. That is, the first sub-bending region BA11 is the setting area for the shift output signal jumper 192 corresponding to the shift register circuit VSR in the first setting partition CSA11, and the second sub-bending region BA12 is the setting area for the shift output signal jumper 192 corresponding to the shift register circuit VSR in the second setting partition CSA12. Since the number of shift output signal jumpers 192 corresponding to the first setting partition CSA11 is less than the number of shift output signal jumpers 192 corresponding to the CSA12 in the second setting partition, the number of shift output signal jumpers 192 in the first sub-bending region BA11 is less than the number of shift output signal jumpers 192 in the second sub-bending region BA12. Therefore, the distribution density of power signal jumpers 191 in the first sub-bend area BA11 can be set to be greater than that in the second sub-bend area BA12, meaning that a larger number of power signal jumpers 191 can be placed in the first sub-bend area BA11. This satisfies the wiring requirement that both power signal jumpers 191 and shift output signal jumpers 192 can be laid in the first bend area BA1 simultaneously, while also utilizing gaps to lay as many power signal jumpers 191 as possible, reducing power signal transmission losses and ensuring the accuracy of the power signal.

[0185] For example, continue to refer to Figure 32 As shown, the display area also includes a third straight edge area AA3, which extends along the second direction Y; the first bending area BA1 includes a third sub-bending area BA13 and a fourth sub-bending area BA14. Along the first direction X, the fourth sub-bending area BA14 is located on the side of the third sub-bending area BA13 near the second straight edge area AA2, and / or, the fourth sub-bending area BA14 is located on the side of the third sub-bending area BA13 near the third straight edge area AA3; all shift output signal jumpers 192 are disposed in the third sub-bending area BA13; at least a portion of the power signal jumpers 191 are disposed in the fourth sub-bending area BA14.

[0186] like Figure 32 and Figure 33 As shown, the first bending region BA1 includes a third sub-bending region BA13 and a fourth sub-bending region BA14. The fourth sub-bending region BA14 is located on the side of the third sub-bending region BA13 closest to the second straight edge region AA2, and / or, the fourth sub-bending region BA14 is located on the side of the third sub-bending region BA13 closest to the third straight edge region AA3. Figure 32 Taking the fourth sub-bend area BA14 located on the side of the third sub-bend area BA13 near the second straight edge area AA2, and the fourth sub-bend area BA14 located on the side of the third sub-bend area BA13 near the third straight edge area AA3 as examples, that is, along the first direction X, a third sub-bend area BA13 is set between the two fourth sub-bend areas BA14. For example, the shift output signal jumper wires 192 are all set in the third sub-bend area BA13, and no shift output signal jumper wires 192 are set in the fourth sub-bend area BA14. The area of ​​the fourth sub-bend area BA14 can be set with power signal jumper wires 191. In this way, on the one hand, the wiring requirement of simultaneously laying power signal jumper wires 191 and shift output signal jumper wires 192 in the first bend area BA1 is met, and on the other hand, as many power signal jumper wires 191 as possible can be laid using the gaps, reducing the loss in the power signal transmission process and ensuring the accuracy of the power signal.

[0187] For example, such as Figure 32 and Figure 33 As shown, signal line 12 also includes initialization signal line 122; multiple jumper wires 19 also include multiple initialization jumper wires 193 disposed in the first bending area BA1. The initialization jumper wires 193 are electrically connected to the initialization signal line 122 and are disposed in the same layer as the power signal jumper wire 191 and the shift output signal jumper wire 192.

[0188] Specifically, the display panel also includes an initialization signal line 122 disposed in the first non-display area NAA1. The initialization signal line 122 may include a gate initialization signal line, a reset initialization signal line, and a bias adjustment initialization signal line. The gate initialization signal line is used to initialize the gate of the driving transistor in the pixel circuit of the display area AA; the reset initialization signal line is used to reset the anode of the light-emitting element in the display area AA; and the bias adjustment initialization signal line is used to adjust the bias of the first terminal of the driving transistor in the pixel circuit of the display area AA. Therefore, the initialization signal line 122 disposed in the first non-display area NAA1 needs to be electrically connected to the display area AA to be electrically connected with the display area initialization signal line disposed in the display area AA. Therefore, the multiple jumper wires 19 also include multiple initialization jumper wires 193 disposed in the first bending area BA1. The initialization jumper wires 193 are electrically connected to the initialization signal line 122 to realize the electrical connection between the initialization signal line 122 disposed in the first non-display area NAA1 and the display initialization signal line disposed in the display area AA.

[0189] Considering the wiring requirements and simplicity of the first bending zone BA1, and to avoid affecting the bending performance of the first bending zone BA1 by laying too many film layers in the first bending zone BA1, the initialization jumper 193, the power signal jumper 191, and the shift output signal jumper 192 can all be set on the same layer. This ensures that the wiring requirements of the first bending zone BA1 are met and the wiring is simple, while also ensuring the bending performance of the first bending zone BA1.

[0190] For example, continue to refer to Figure 32 and Figure 33 As shown, along the first direction X, at least a partial initialization jumper 193 is disposed between the power jumper 191 and the shift output signal jumper 192.

[0191] like Figure 32 and Figure 33 As shown, at least a portion of the initialization jumper wire 193 is disposed between the power jumper wire 191 and the shift output signal jumper wire 192, fulfilling the wiring requirements of the power jumper wire 191, the shift output signal jumper wire 192, and the initialization jumper wire 193 in the first bend area BA1. Furthermore, at least a portion of the power jumper wire 191 and the initialization jumper wire 193 are positioned on the side of the first bend area BA1 closest to the second straight edge area AA2 and / or close to the third straight edge area AA3, meaning that the power jumper wire 191 and the initialization jumper wire 193 are kept away from the densely packed shift output signal jumper wire 192. This ensures high accuracy of signal transmission in the power jumper wire 191 and the initialization jumper wire 193, preventing the alternating scanning signal from affecting the power signal and the initialization signal.

[0192] For example, continue to refer to Figure 32and Figure 33 As shown, the display panel also includes a power signal line 121; the power signal line 121 includes a first sub-power portion 1211 and a second sub-power portion 1212; the first sub-power portion 1211 extends along the first direction X and is located on the side of the first bend area BA1 away from the display area AA; the second sub-power portion 1212 extends along the first direction X and is located on the side of the first bend area BA1 close to the display area AA; the first sub-power portion 1211 and the second sub-power portion 1212 are electrically connected by a power signal jumper 191.

[0193] like Figure 32 and Figure 33 As shown, signal line 12 also includes a power signal line 121, which includes a first sub-power section 1211 and a second sub-power section 1212. The first sub-power section 1211 is located on the side of the first bend area BA1 away from the display area AA, and the second sub-power section 1212 is located on the side of the first bend area BA1 closer to the display area AA. Power signal jumper wire 191 electrically connects the first sub-power section 1211 and the second sub-power section 1212. This arrangement of power signal line 121 can increase the area or line width of power signal line 121, reduce the impedance of power signal line 121, ensure low transmission impedance when power signal is transmitted to display area AA through power signal line 121, and ensure good transmission accuracy of power signal.

[0194] Continue to refer to Figure 32 and Figure 33 As shown, the linewidth of the first sub-power supply section 1211 in the second direction Y is greater than the linewidth of the second sub-power supply section 1212 in the second direction Y.

[0195] Specifically, the first sub-power supply section 1211 is located on the side of the first bend area BA1 away from the display area AA. This area has a large wiring space, so the line width of the first sub-power supply section 1211 can be set to be large. This can fully reduce the impedance of the power signal line 121, ensure that the transmission impedance is small when the power signal is transmitted to the display area AA through the power signal line 121, and ensure good transmission accuracy of the power signal.

[0196] Furthermore, the second sub-power supply section 1212 is located on the side of the first bending area BA1 near the display area AA. This area will not bend to the non-light-emitting side of the display panel. Therefore, in order to ensure that the light-emitting side of the display panel has the characteristic of a narrow bezel, the line width of the second sub-power supply section 1212 can be set to be smaller. This can significantly reduce the area of ​​the non-display area on the light-emitting side of the display panel, ensuring that the display panel can achieve a relatively narrow bezel design and significantly improve the screen ratio on the light-emitting side.

[0197] For example, Figure 34This is a schematic diagram of another structure of the first bending region provided in an embodiment of this application. Figure 35 This is a schematic diagram of another structure of the first bending region provided in an embodiment of this application. Figure 36 This is a schematic diagram of another structure of the first bending region provided in an embodiment of this application. Figure 37 This is a schematic diagram of another first bending region provided in an embodiment of this application, combined with... Figure 32 , Figure 33 , Figure 34 , Figure 35 , Figure 36 and Figure 37 As shown, the power signal line 121 includes a first power signal line PVDD and / or a second power signal line PVEE; the first power signal line PVDD and the second power signal line PVEE have different potentials.

[0198] Specifically, in this embodiment, the power signal line 121 may include a first power signal line PVDD and / or a second power signal line PVEE. Figure 32 and Figure 33 This explanation will take the example of power signal line 121 including only one type of power signal line. Figures 34-37 The following description uses power signal line 121, which includes two types of power signal lines, as an example. For instance, the first power signal line PVDD provides a first power signal to the pixel circuit disposed in the display area, and the second power signal line PVEE provides a second power signal to the cathode of the light-emitting element disposed in the display area. The potential of the first power signal can be greater than the potential of the second power signal. For example, the first power signal can be a positive potential signal, and the second power signal can be a negative connection signal; or, both the first and second power signals are positive power signals; or, both the first and second power signals are negative power signals. This application does not limit the potential of the first and second power signals.

[0199] Furthermore, when the power signal line 121 includes two types of power signal lines, that is, when the power signal line 121 simultaneously includes a first power signal PVDD and a second power signal PVEE, the first sub-power portion 1211 and the second sub-power portion 1212 in the first power signal PVDD and the first sub-power portion 1211 and the second sub-power portion 1212 in the second power signal PVEE can have various different configurations. Specifically, such as... Figure 34 As shown, the first sub-power portion 1211 of the first power signal PVDD is located on the side of the first sub-power portion 1211 of the second power signal PVEE away from the first bending region BA1, and the second sub-power portion 1212 of the first power signal PVDD is located on the side of the second sub-power portion 1212 of the second power signal PVEE closer to the first bending region BA1. Figure 35 As shown, the first sub-power portion 1211 of the first power signal PVDD is located on the side of the first sub-power portion 1211 of the second power signal PVEE closer to the first bending region BA1, and the second sub-power portion 1212 of the first power signal PVDD is located on the side of the second sub-power portion 1212 of the second power signal PVEE away from the first bending region BA1. Figure 36 As shown, the first sub-power portion 1211 of the first power signal PVDD is located on the side of the first sub-power portion 1211 of the second power signal PVEE away from the first bending region BA1, and the second sub-power portion 1212 of the first power signal PVDD is located on the side of the second sub-power portion 1212 of the second power signal PVEE away from the first bending region BA1. Figure 37 As shown, the first sub-power portion 1211 of the first power signal PVDD is located on the side of the first sub-power portion 1211 of the second power signal PVEE near the first bending region BA1, and the second sub-power portion 1212 of the first power signal PVDD is located on the side of the second sub-power portion 1212 of the second power signal PVEE near the first bending region BA1. By configuring the first sub-power portion 1211 and the second sub-power portion 1212 in the first power signal PVDD and the second sub-power portion 1211 and the second sub-power portion 1212 in the second power signal PVEE, various different configuration methods can be achieved. The specific positional relationship between the first power signal PVDD and the second power signal PVEE can be flexibly configured according to requirements to meet various usage needs.

[0200] Figure 38 This is a schematic diagram of another display panel structure provided in an embodiment of this application, such as... Figure 38 As shown, the display panel also includes a gate drive circuit 13 disposed in the circuit setting area CSA1; along the thickness direction of the display panel, the first sub-power supply portion 1211 covers at least a portion of the gate drive circuit 13.

[0201] like Figure 38As shown, along the thickness direction of the display panel, the first sub-power supply section 1211 covers at least a portion of the gate drive circuit 13. This ensures that the first sub-power supply section 1211 has a large size in the second direction Y, which can significantly reduce the impedance of the power signal line 121, ensuring low transmission impedance when the power signal is transmitted to the display area AA through the power signal line 121, and guaranteeing good transmission accuracy of the power signal. Furthermore, along the thickness direction of the display panel, the first sub-power supply section 1211 covers at least a portion of the gate drive circuit 13. Thus, when the circuit setting area CSA1 is bent to the non-light-emitting side of the display panel, the first sub-power supply section 1211 can act as a shielding structure to block interference from other signals to the gate drive circuit 13, ensuring that the gate drive signal 13 is not interfered with by other signals, and ensuring that the gate drive circuit 13 operates normally, accurately, and efficiently.

[0202] In one embodiment, Figure 39 This is a schematic diagram of the structure of another display panel provided in the embodiments of this application, such as... Figure 39 As shown, a portion of the second sub-power supply section 1212 is located in the second non-display area NAA2; the second non-display area NAA2 also includes a second bonding area BAA2, which is located on the side of the second bend area BA2 away from the second straight edge area AA2; the display panel also includes a plurality of second type signal bonding terminals 21 disposed in the second bonding area; the second type signal bonding terminals 21 include second power signal terminals 212; the display panel also includes a power signal connection section 23 disposed in the second bend area BA2, which is electrically connected to the second power signal terminals 212 and the second sub-power supply section 1212 located in the second non-display area NAA2.

[0203] like Figure 39 As shown, the second sub-power supply section 1212 extends from the first non-display area NAA1 along the first direction X to the second non-display area NAA2, and the second sub-power supply section 1212 located in the second non-display area NAA2 extends along the second direction Y. That is, the second sub-power supply section 1212 includes a portion located in the first non-display area NAA1 and a portion located in the second non-display area NAA2. The second sub-power supply section 1212 can be electrically connected to the power signal bonding terminals located in the first non-display area NAA1 and the power signal bonding terminals located in the second non-display area NAA2, respectively. At the same time, it receives the power signals provided by the power signal bonding terminals located in the first non-display area NAA1 and the power signal bonding terminals located in the second non-display area NAA2. On the one hand, this confirms that the second sub-power supply section 1212 can receive the power signal, and on the other hand, it can reduce the transmission impedance of the power signal and ensure the accuracy of the power signal transmission.

[0204] Specifically, the display panel also includes a power signal connection portion 23 and a second power signal terminal 212 disposed in the second bonding area BAA2. The second power signal terminal 212 is used to electrically connect to a flexible circuit board disposed in the second non-display area NAA2 to provide a power signal through the second flexible circuit board. Furthermore, the power signal connection portion 23 is electrically connected to both the second power signal terminal 212 and the second sub-power portion 1212 located in the second non-display area NAA2, realizing the design logic of the second sub-power portion 1212 receiving power signals from the second non-display area NAA2, ensuring reduced power signal transmission impedance and ensuring the accuracy of power signal transmission.

[0205] For example, continue to refer to Figure 39 As shown, the first non-display area NAA1 also includes a functional area FA and a first bonding area BAA1. The first bonding area BAA1 is located on the side of the functional area FA away from the first bending area BA1. The display panel also includes multiple signal lines 12 disposed in the functional area FA and a first type of signal bonding terminal 11 disposed in the first bonding area BAA1. The signal lines 12 include power signal lines 121, and the first type of signal bonding terminal 11 includes multiple first power signal terminals 112 arranged along the first direction X. The first power signal terminals 112 are electrically connected to the power signal lines 121.

[0206] like Figure 39 As shown, the first non-display area NAA1 also includes a functional area FA. The functional area FA can be understood as the area between the first bending area BA1 and the first bonding area BAA1. The functional area FA includes a first circuit setting area CSA1 and an area for setting signal lines 12. For example, the first bonding area BAA1 is provided with multiple first-type signal bonding terminals 11, which are the bonding terminals set in the first non-display area NAA1. The first-type signal bonding terminals 11 are used for electrical connection with the flexible circuit board set in the first non-display area NAA1, for receiving signals provided by the flexible circuit board, and for transmitting the signals to the signal lines 12 set in the first non-display area NAA1. Thus, through the arrangement of the first-type signal bonding terminals 11 and the signal lines 12, signal input can be achieved from the left and / or right bezels of the display panel, improving the flexibility of signal input.

[0207] Specifically, signal line 12 includes power signal line 121, and the first type of signal bonding terminal 11 includes a plurality of first power signal terminals 112 arranged along the first direction X. The first power signal terminals 112 are electrically connected to the power signal line 121, thereby enabling power signal input from the left and / or right bezel of the display panel. The technical solution of this application can enable power signal input from the left and / or right bezel of the display panel, which can improve the flexibility of power signal input. Furthermore, when the power signal is input from the bottom bezel of the display panel, the input impedance of the power signal can be reduced, ensuring that the power signal can be input to the display panel with low impedance and high precision.

[0208] Continue to refer to Figure 39 As shown, the display panel also includes a gate drive circuit 13 and a gate drive signal line 14 disposed in the first circuit setting area CSA1, the gate drive circuit 13 and the gate drive signal line 14 being electrically connected; the first type of signal bonding terminal 11 also includes a first type of gate drive signal terminal 111, the first type of gate drive signal terminal 111 being electrically connected to the gate drive signal line 14; the display area also includes a third straight edge area AA3, the third straight edge area AA3 extending along the second direction Y; along the first direction X, the power signal terminal 112 is located on the side of the first type of gate drive signal terminal 111 near the second straight edge area AA2, and / or, the power signal terminal 112 is located on the side of the first type of gate drive signal terminal 111 near the third straight edge area AA3.

[0209] like Figure 39As shown, the display panel also includes a gate driving circuit 13 and a gate driving signal line 14 disposed in the first circuit setting area CSA1. The gate driving signal line 14 provides a gate driving signal to the gate driving circuit 13 to drive the gate driving circuit to output a scan signal to the scan signal line disposed in the display area AA, and output a light emission control signal to the light emission control signal line disposed in the display area AA, thereby realizing the normal operation of the pixel circuit disposed in the display area AA and ensuring the normal display function of the display panel. In this embodiment, both the gate driving circuit 13 and the gate driving signal line 14 are disposed in the first circuit setting area CSA1, and the first circuit setting area CSA1 is further bent to the non-light emitting side of the display panel. This can reduce the area ratio of the non-display area in the light emitting side of the display panel, increase the proportion of the central display area of ​​the display panel, and improve the display effect of the display panel. Furthermore, the first type of signal bonding terminal 11 also includes a first type of gate drive signal terminal 111, which is electrically connected to the gate drive signal line 14. The technical solution of this application can realize gate drive signal input from the left and / or right bezels of the display panel, improving the flexibility of gate drive signal input. Moreover, when the gate drive signal and power signal are simultaneously input from the bottom bezel of the display panel, the input impedance of the gate drive signal and power signal can be reduced, ensuring that the gate drive signal and power signal can be input to the display panel with low impedance and high precision.

[0210] For example, along the first direction X, the power signal terminal 112 is located on the side of the first type gate drive signal terminal 111 near the second straight edge region AA2, and / or, the power signal terminal 112 is located on the side of the first type gate drive signal terminal 111 near the third straight edge region AA3. Figure 39 The following description takes the example of the power signal terminal 112 being located on the side of the first type of gate drive signal terminal 111 closer to the second straight edge region AA2, and the power signal terminal 112 being located on the side of the first type of gate drive signal terminal 111 closer to the third straight edge region AA3. By setting the power signal terminal 112 in the first direction X, which is closer to the edge of the first bonding region BAA1 than the first type of gate drive signal terminal 111, that is, away from the densely arranged first type of gate drive signal terminals 111, it is possible to avoid the influence of multiple types of gate drive signals on the power signal, thus ensuring high accuracy of power signal transmission.

[0211] Continue to refer to Figure 39 As shown, signal line 12 also includes initialization signal line 122, and the first type of signal bonding terminal 11 also includes initialization signal terminal 113; initialization signal terminal 113 is electrically connected to initialization signal line 122.

[0212] Specifically, signal line 12 includes an initialization signal line 122, and the first type of signal bonding terminal 11 includes an initialization signal terminal 113. The initialization signal terminal 113 is electrically connected to the initialization signal line 122, thus enabling the input of the initialization signal from the left and / or right bezel of the display panel. The technical solution of this application can realize the input of the initialization signal from the left and / or right bezel of the display panel, which can improve the flexibility of the initialization signal input. Furthermore, when the initialization signal is simultaneously input from the bottom bezel of the display panel, the input impedance of the initialization signal can also be adjusted to ensure that the initialization signal can be input to the display panel with low impedance and high precision.

[0213] Continue to refer to Figure 39 As shown, the display area AA also includes a third straight edge area AA3, which extends along the second direction Y; along the first direction X, the power signal terminal 112 is located on the side of the initialization signal terminal 113 near the second straight edge area AA2, and / or, the power signal terminal 112 is located on the side of the initialization signal terminal 113 near the third straight edge area AA3.

[0214] like Figure 39 As shown, along the first direction X, the power signal terminal 112 is located on the side of the initialization signal terminal 113 near the second straight edge region AA2, and / or, the power signal terminal 112 is located on the side of the initialization signal terminal 113 near the third straight edge region AA3. Figure 39 The following explanation uses two examples: the power signal terminal 112 is located on the side of the initialization signal terminal 113 closer to the second straight edge region AA2, and the power signal terminal 112 is located on the side of the initialization signal terminal 113 closer to the third straight edge region AA3. By setting the power signal terminal 112 in the first direction X, it is located on the side of the initialization signal terminal 113 closer to the edge of the first binding region BAA1. This ensures a high degree of freedom in setting the power signal terminal 112 and allows for more space to be reserved in the first binding region BAA1 for setting the power signal terminal 112. This reduces the connection impedance between the power signal terminal 112 and the power signal line 121, ensuring accurate transmission of the power signal.

[0215] Continue to refer to Figure 39As shown, the display panel also includes a gate drive circuit 13 and a gate drive signal line 14 disposed in the first circuit setting area CSA1, the gate drive circuit 13 and the gate drive signal line 14 being electrically connected; the first type of signal bonding terminal 11 also includes a first type of gate drive signal terminal 111, the first type of gate drive signal terminal 111 being electrically connected to the gate drive signal line 14; the display area also includes a third straight edge area AA3, the third straight edge area AA3 extending along the second direction Y; along the first direction X, the initialization signal terminal 113 is located on the side of the first type of gate drive signal terminal 111 near the second straight edge area AA2, the first power signal terminal 112 is located on the side of the initialization signal terminal 113 near the second straight edge area AA2; and / or, the initialization signal terminal 113 is located on the side of the first type of gate drive signal terminal 111 near the third straight edge area AA3, the power signal terminal 112 is located on the side of the initialization signal terminal 113 near the third straight edge area AA3.

[0216] like Figure 39 As shown, the display panel also includes a gate driving circuit 13 and a gate driving signal line 14 disposed in the first circuit setting area CSA1. The gate driving signal line 14 provides a gate driving signal to the gate driving circuit 13 to drive the gate driving circuit to output a scan signal to the scan signal line disposed in the display area AA, and output a light emission control signal to the light emission control signal line disposed in the display area AA, thereby realizing the normal operation of the pixel circuit disposed in the display area AA and ensuring the normal display function of the display panel. In this embodiment, both the gate driving circuit 13 and the gate driving signal line 14 are disposed in the first circuit setting area CSA1, and the first circuit setting area CSA1 is further bent to the non-light emitting side of the display panel. This can reduce the area ratio of the non-display area in the light emitting side of the display panel, increase the proportion of the central display area of ​​the display panel, and improve the display effect of the display panel. Furthermore, the first type of signal bonding terminal 11 also includes a first type of gate drive signal terminal 111, a power signal terminal 112, and an initialization signal terminal 113. The first type of gate drive signal terminal 111 is electrically connected to the gate drive signal line 14, the power signal terminal 112 is electrically connected to the power signal line 121, and the initialization signal terminal 113 is electrically connected to the initialization signal line 122. This allows the gate drive signal, power signal, and initialization signal to be input from the left and / or right bezels of the display panel. The technical solution of this application can improve the flexibility of gate drive signal, power signal, and initialization signal input. Furthermore, when the gate drive signal, power signal, and initialization signal are simultaneously input from the bottom bezel of the display panel, the input impedance of the gate drive signal, power signal, and initialization signal can be reduced, ensuring that the gate drive signal, power signal, and initialization signal can be input to the display panel with low impedance and high precision.

[0217] For example, along the first direction X, the initialization signal terminal 113 is located on the side of the first type gate drive signal terminal 111 near the second straight edge region AA2, and the first power signal terminal 112 is located on the side of the initialization signal terminal 113 near the second straight edge region AA2; and / or, the initialization signal terminal 113 is located on the side of the first type gate drive signal terminal 111 near the third straight edge region AA3, and the power signal terminal 112 is located on the side of the initialization signal terminal 113 near the third straight edge region AA3. Figure 39 Taking the example along the first direction X, where the initialization signal terminal 113 is located on the side of the first type gate drive signal terminal 111 near the second straight edge region AA2, and the first power signal terminal 112 is located on the side of the initialization signal terminal 113 near the second straight edge region AA2; furthermore, the initialization signal terminal 113 is located on the side of the first type gate drive signal terminal 111 near the third straight edge region AA3, and the power signal terminal 112 is located on the side of the initialization signal terminal 113 near the third straight edge region AA3, this will be explained as follows. By setting the power signal terminal 112 on the side of 111 closer to the edge of the first bonding region BAA1 in the first direction X, a high degree of freedom in setting the power signal terminal 112 can be ensured, and more space can be reserved in the first bonding region BAA1 to set the power signal terminal 112, reducing the connection impedance between the power signal terminal 112 and the power signal line 121, and ensuring accurate transmission of the power signal. Furthermore, by setting the initialization signal terminal 113 in the first direction X, and positioning it between the power signal terminal 112 and the first type of gate drive signal terminal 111, the initialization signal terminal 113 isolates the interference of the gate drive signal in the first type of gate drive signal terminal 111 on the power signal signal in the power signal terminal 112, ensuring that the power signal can be stably and accurately transmitted to the power signal line 121.

[0218] In one embodiment, Figure 40 This is a schematic diagram of another display panel structure provided in the embodiments of this application, such as... Figure 40As shown, the first non-display area NAA1 also includes a functional area FA and a first bonding area BAA1; the functional area FA includes a first circuit setting area CSA1 and a circuit setting free area CSFA, and along the first direction X, the circuit setting free area CSFA is located on at least one side of the first circuit setting area CSA1; the first bonding area BAA1 is located on the side of the functional area FA away from the first bending area BA1, and the first bonding area BA1 is provided with a plurality of first type signal bonding terminals 11, the first type signal bonding terminals 11 including fixed potential signal terminals 114; the signal line 12 includes a fixed potential signal line 123, the fixed potential signal line 123 is disposed in the functional area FA between the first circuit setting area CSA1 and the first bending area BA1; the display panel also includes a fixed signal connection part 24 disposed in the circuit setting free area CSFA, the fixed signal connection part 24 is electrically connected to the fixed potential signal terminal 114 and the fixed potential signal line 1123 respectively.

[0219] like Figure 40 As shown, the functional area FA includes a first circuit setting area CSA1 and a circuit setting spare area CSFA. The circuit setting spare area CSFA can be understood as the area remaining in the functional area FA after the first circuit setting area CSA1 has been set. Along the first direction X, the circuit setting spare area CSFA is located on at least one side of the first circuit setting area CSA1. Figure 40 Taking an example where the circuit setting free area CSFA is located along the first direction X, on the side of the first circuit setting area CSA1 closest to the second straight edge area AA2 and on the side furthest from the second straight edge area AA2, the following explanation will be provided. In order to improve the utilization efficiency of the circuit setting free area CSFA, a structure that is conducive to improving the performance of the existing structure in the first non-display area NAA1 can be set in the circuit setting free area CSFA to further improve the performance of the first non-display area NAA1.

[0220] Specifically, the first binding area BA1 is provided with a fixed potential signal terminal 114, and the signal line 12 includes a fixed potential signal line 123. A fixed signal connection part 24 is provided in the circuit configuration free area CSFA. The fixed signal connection part 24 is electrically connected to both the fixed potential signal terminal 114 and the fixed potential signal line 123. Thus, the fixed point signal terminal 114 and the fixed point signal line 123 are electrically connected through the fixed signal connection part 24. Compared to the scheme where the fixed point signal terminal 114 and the fixed point signal line 123 are directly connected by a connecting wire, the fixed signal connection part 24 has a larger surface area. Using the fixed signal connection part 24 to achieve the electrical connection between the fixed point signal terminal 114 and the fixed point signal line 123 ensures the reliability and stability of the electrical connection between them. Simultaneously, it reduces the electrical connection impedance between the fixed point signal terminal 114 and the fixed point signal line 123, ensuring the accuracy of the fixed potential signal transmission.

[0221] Continue to refer to Figure 40 As shown, the fixed signal connection portion 24 and the fixed potential signal line 123 are integrally formed, thus ensuring a simple connection relationship between them. Furthermore, the integral formation of the fixed signal connection portion 24 and the fixed potential signal line 123 can also mean that they are disposed on the same layer and fabricated using the same process, ensuring a simple film structure in the first non-display area NAA1 and a simple fabrication process for the fixed signal connection portion 24 and the fixed potential signal line 123.

[0222] For example, the fixed potential signal line 123 includes at least one of the power signal line 121 and the initialization signal line 122; the fixed potential signal terminal 114 includes at least one of the power signal terminal 112 and the initialization signal terminal 113.

[0223] like Figure 40 As shown, Figure 40 Taking a fixed-potential signal line 123 as the power signal line 121 and a fixed-potential signal terminal 114 as the power signal terminal 112 as an example, the following explanation is provided. Setting the fixed-potential signal line 123 to include at least one of the power signal line 121 and the initialization signal line 122, and the fixed-potential signal terminal 114 to include at least one of the power signal terminal 112 and the initialization signal terminal 113, can reduce the connection impedance between the power signal line 121 and the power signal terminal 112, and / or reduce the connection impedance between the initialization signal line 122 and the initialization signal terminal 113, ensuring minimal loss of the power signal and / or initialization signal during transmission, and ensuring accurate transmission of the power signal and / or initialization signal.

[0224] In one embodiment, reference continues to... Figure 39 As shown, the first non-display area NAA1 also includes a first bonding area BAA1, which is located on the side of the first circuit setting area CSA1 away from the first bending area BA1; the display panel also includes a plurality of first type signal bonding terminals 11, which include touch signal terminals 115.

[0225] Continue to refer to Figure 39 As shown, the first non-display area NAA1 also includes a first bonding area BAA1. The first bonding area BAA1 is provided with a plurality of first-type signal bonding terminals 11. The first-type signal bonding terminals 11 are the bonding terminals provided in the first non-display area NAA1. The first-type signal bonding terminals 11 are used to electrically connect with the flexible circuit board provided in the first non-display area NAA1, to receive signals provided by the flexible circuit board, and to transmit the signals to the signal lines 12 provided in the first non-display area NAA1. In this way, by setting the first-type signal bonding terminals 11, signal input can be realized from the left and / or right bezels of the display panel, which can improve the flexibility of signal input.

[0226] Specifically, the display panel in this embodiment can be a touch display panel, with touch electrodes (not shown in the figure) disposed in the display area. The touch electrodes receive touch drive signals and feed back touch sensing signals to the touch driver chip (not shown in the figure). The touch drive signals determine the touch position and / or touch pressure magnitude through the received touch sensing signals, thereby realizing the touch function of the display panel. Specifically, the touch electrodes and the touch driver chip can be electrically connected through touch traces. Part of the structure in the touch traces can be disposed in the display area, and the remaining structure can be disposed in the non-display area. In this embodiment, the first type of signal binding terminal 11 includes a touch signal terminal 115. The touch signal terminal 115 can be understood as a terminal for transmitting touch signals. The touch signal terminal 115 is electrically connected to the touch traces, transmitting touch drive signals to the touch traces and receiving touch sensing signals transmitted by the touch traces. In this embodiment, the touch signal terminals are disposed on the left and / or right bezels of the display panel, improving the flexibility of the touch signal terminal placement and reducing the difficulty of laying out traces and structures in the lower bezel.

[0227] It should be noted that, Figure 39 The example only shows that a touch signal terminal 115 is provided in the first binding area BAA1. The setting position of the touch signal terminal 115 and its relative positional relationship with other first type signal binding terminals 11 are not limited. The touch signal terminal 115 has great setting flexibility in the first binding area BAA1.

[0228] For example, continue to refer to Figure 39As shown, the first non-display area NAA1 also includes a first bonding area BAA1, which is located on the side of the first circuit setting area CSA1 away from the first bending area BA1; the display panel also includes a plurality of first type signal bonding terminals 11, which include test signal terminals 116.

[0229] It is understandable that the display panel needs to undergo performance testing before the driver chip and flexible circuit board are bonded. Only display panels that pass the test will be bonded to the driver chip and flexible circuit board in subsequent processes. Therefore, test signal terminals also need to be set in the display panel. The test signal terminals are used to receive test signals provided by external testing equipment during the testing process of the display panel and transmit the test signals to the pixel circuit and / or light-emitting elements in the display area to test the display performance of the display panel. In the embodiment of this application, the first type of signal bonding terminal 11 set in the first bonding area BAA1 includes a test signal terminal 116, that is, the test signal terminal 116 is set on the left and / or right frame of the display panel, which improves the flexibility of setting the test signal terminal and reduces the difficulty of wiring and structural layout in the lower frame.

[0230] It should be noted that, Figure 39 The example only shows that a test signal terminal 116 is provided in the first binding area BAA1. The setting position of the test signal terminal 116 and its relative positional relationship with other first type signal binding terminals 11 are not limited. The test signal terminal 116 has great setting flexibility in the first binding area BAA1.

[0231] In one embodiment, Figure 41 yes Figure 1 The provided enlarged cross-sectional diagram of the display panel along section line A-A', combined with... Figure 1 and Figure 41 As shown, the first non-display area NAA1 also includes a border area BOR along the second direction Y. The border area BOR is located on the side of the first bending area BA1 near the display area AA. The display panel also includes an encapsulation structure 30 located in the border area BOR. The encapsulation structure 30 includes at least one partition structure 31. The partition structure 31 extends along the first direction X (not shown in the figure) and includes a first partition layer 31a and a second partition layer 31b stacked together. The display panel also includes a substrate 10. The first partition layer 31a is located on the side of the second partition layer 31b near the substrate 10, and the area of ​​the first partition layer 31a is smaller than the area of ​​the second partition layer 31b. Along the thickness direction of the display panel (the Z direction shown in the figure, and the following explanation will take the thickness direction Z as an example), the second partition layer 31b covers the first partition layer 31a. a and b are both positive integers.

[0232] like Figure 1 and Figure 41 As shown, the first non-display area NAA1 also includes a border area BOR. Along the second direction Y, the border area BOR is located on the side of the first bending area BA1 closest to the display area AA. The border area BOR can be understood as an area located on the light-emitting side of the display panel that is not displayed. In this embodiment, the gate driving circuit 13 is disposed in the functional area FA, and the functional area FA is bent along the first bending area BA1 to the non-light-emitting side of the display panel. The encapsulation structure 30 is only provided in the border area BOR. In this way, on the one hand, the encapsulation structure 30 isolates moisture in the external environment, avoiding affecting the pixel circuits and light-emitting elements in the display area AA; on the other hand, it enables a narrow bezel design of the display panel, achieving a high screen-to-body ratio.

[0233] Specifically, the encapsulation structure 30 includes at least one partition structure 31. The partition structure 31 includes a first partition layer 31a and a second partition layer 31b stacked together. The first partition layer 31a is located on the side of the second partition layer 31b closest to the substrate 10, and the area of ​​the first partition layer 31a is smaller than the area of ​​the second partition layer 31b. Thus, the first partition layer 31a and the second partition layer 31b form an "undercut" structure, smaller at the bottom and larger at the top. Other structures extending to the partition structure 31 break at the locations of the first partition layer 31a and the second partition layer 31b, thereby blocking the transmission channel of moisture through other structures to the display area AA. This ensures that the partition structure 31 can effectively isolate moisture from the external environment, protecting the structures in the display area AA from moisture erosion. For example, as... Figure 41 As shown, the light-emitting element in the display panel includes a cathode 32. The cathode 32 breaks at the positions of the a-th partition layer 31a and the b-th partition layer 31b in the partition structure 31, thus blocking the transmission channel of water vapor through the cathode 32 to the display area AA, and protecting the structure in the display area AA from water vapor corrosion.

[0234] Continue to refer to Figure 41 As shown, the partition structure 31 also includes a c-th partition layer 31c, which is located on the side of the a-th partition layer 31a that is close to the substrate 10; the area of ​​the c-th partition layer 31c is larger than the area of ​​the a-th partition layer 31a, and the c-th partition layer 31c covers the a-th partition layer 31a along the thickness direction Z of the display panel; c is a positive integer.

[0235] like Figure 41As shown, the partition structure 31 also includes a c-th partition layer 31c, which is located on the side of the a-th partition layer 31a closest to the substrate 10. The area of ​​the c-th partition layer 31c is larger than the area of ​​the a-th partition layer 31a, thus forming an "I"-shaped structure. The a-th partition layer 31a, located in the middle film layer, is recessed within the b-th partition layer 31b and the c-th partition layer 31c, facilitating the breakage of other structures extending to the partition structure 31 at the position of the a-th partition layer 31a. This blocks the transmission channel of moisture to the display area AA through other structures, protecting the structures in the display area AA from moisture erosion. Furthermore, because the area of ​​the c-th partition layer 31c closer to the substrate 10 is larger than the area of ​​the a-th partition layer 31a, a larger contact area between the partition structure 31 and the film layer below it can be ensured, facilitating the stable formation of the partition structure 31 on the surface of the film layer below it and reducing the risk of the partition structure 31 detaching.

[0236] Furthermore, the isolation structure 31, comprising the a-th isolation layer 31a, the b-th isolation layer 31b, and the c-th isolation layer 31c, can be formed within the same metal layer. Utilizing the difference in etching rates between different materials within the metal layer, an "I"-shaped isolation structure 31 can be naturally formed during the etching process of the metal layer, ensuring a simple fabrication process for the isolation structure 31. For example, at least one of the first, second, and third source / drain metal layers of the display panel can employ a "titanium-aluminum-titanium" structure. Because the etching rate of aluminum is greater than that of titanium in the "titanium-aluminum-titanium" structure, an "I"-shaped isolation structure 31 can be naturally formed during the etching of the "titanium-aluminum-titanium" structure metal layer. Therefore, the isolation structure 31 can be formed in at least one of the first, second, and third source / drain metal layers of the display panel, ensuring a simple fabrication process for the isolation structure 31.

[0237] For example, continue to refer to Figure 41 As shown, the encapsulation structure 30 includes a plurality of partition structures 31, which are arranged along the second direction Y.

[0238] Specifically, the encapsulation structure 30 may include a plurality of partition structures 31 arranged along the second direction Y. The arrangement of the plurality of partition structures 31 can fully ensure that other structures extending to the partition structure 31 break at the position of the a partition layer 31a, fully blocking the transmission channel of water vapor to the display area AA, and fully protecting the structure in the display area AA from water vapor erosion.

[0239] For example, the encapsulation structure 30 may include at least two partition structures 31. Figure 41 The following explanation uses the encapsulation structure 30, which includes four partition structures 31, as an example.

[0240] For example, continue to refer to Figure 41 As shown, the border area BOR also includes a first organic clearance area BOR1, and at least one partition structure 31 is disposed in the first organic clearance area BOR1.

[0241] like Figure 41 As shown, the border area BOR also includes a first organic clearance area BOR1, which can be understood as an area where no organic material is used. Since organic materials are prone to absorbing water, at least one partition structure 31 is located within the first organic clearance area BOR1, meaning the area where at least one partition structure 31 is located does not contain organic material. This ensures that at least one partition structure 31 is protected from moisture erosion, preventing corrosion and ensuring structural and performance stability.

[0242] For example, the size of the first organic clearance area BOR1 in the second direction Y can be 10μm-100μm, such as 10μm, 15μm, 20μm, 28μm, 33μm, 40μm, 50μm, 55μm, 62μm, 70μm, 80μm, 90μm or 100μm. The specific size value of the first organic clearance area BOR1 in the second direction Y is not limited in the embodiments of this application.

[0243] For example, continue to refer to Figure 41 As shown, the encapsulation structure 30 also includes a first barrier structure 33; the display panel also includes an encapsulation layer 34, which includes at least an organic encapsulation layer 341, which terminates on the side of the first barrier structure 33 away from the first bending region BA1.

[0244] like Figure 41 As shown, the display panel also includes an encapsulation layer 34, which encapsulates and covers the pixel circuits and light-emitting elements in the display panel, ensuring that the pixel circuits and light-emitting elements are protected from water and oxygen corrosion. Furthermore, the encapsulation layer 34 may include a thin-film encapsulation layer, and may further include a stacked structure of organic and inorganic encapsulation layers to achieve a good encapsulation effect through the cooperation of the organic and inorganic encapsulation layers. Specifically, the encapsulation layer 34 may include a first inorganic encapsulation layer 342, an organic encapsulation layer 341, and a second inorganic encapsulation layer 343 stacked together. The first inorganic encapsulation layer 342 and the second inorganic encapsulation layer 343 achieve a good encapsulation protection effect, while the organic encapsulation layer 341 is used to absorb moisture and oxygen, ensuring that the pixel circuits and light-emitting elements are protected from water and oxygen corrosion.

[0245] For example, the encapsulation layer 34 covers the display area AA and extends into the first non-display area NAA1. Since the organic encapsulation layer 341 has strong fluidity, in order to avoid the organic encapsulation layer 341 extending excessively into the border area BOR, resulting in a large area of ​​the border area BOR and affecting the narrow bezel effect of the display panel, the encapsulation structure 30 can be set to include a first barrier structure 33. The barrier structure 33 is used to block the organic encapsulation layer 341 from extending into the first bending area BA1. That is, the organic encapsulation layer 341 ends at the side of the first barrier structure 33 away from the first bending area BA1, ensuring that the area of ​​the border area BOR is small and ensuring the narrow bezel effect of the display panel.

[0246] Furthermore, the first barrier structure 33 can be formed by stacking multiple layers to ensure that the first barrier structure 33 has a higher height than its adjacent structures, which can effectively block the organic encapsulation layer. For example, the first barrier structure 33 may include at least one organic material layer. Since organic material layers are relatively easy to form a thick layer, including at least one organic material layer in the first barrier structure 33 can effectively ensure the height of the first barrier structure 33.

[0247] For example, the size of the first retaining wall structure 33 in the second direction Y can be 5μm-30μm, such as 5μm, 10μm, 15μm, 20μm, 25μm or 30μm. The specific size value of the first retaining wall structure 33 in the second direction Y is not limited in this embodiment.

[0248] Continue to refer to Figure 41 As shown, the encapsulation structure 30 includes a first partition structure 31a and a second partition structure 31b; along the second direction Y, the first barrier structure 33 is located between the first partition structure 31a and the second partition structure 31b.

[0249] like Figure 41 As shown, along the second direction Y, the first barrier structure 33 is located between the first partition structure 31a and the second partition structure 31b. That is, the first barrier structure 33 is set up using the gap between the two partition structures 31. In this way, the setting of the first barrier structure 33 does not require additional space in the border area BOR. Within the limited width of the border area BOR, the metal isolation and organic layer blocking effects are achieved simultaneously, taking into account both the function of the border area BOR and the narrow border design.

[0250] Continue to refer to Figure 42 As shown, the encapsulation structure 30 also includes a second barrier structure 35, which is located on the side of the first barrier structure 33 away from the first bending area BA1; the frame area BOR also includes a second organic clearance area BOR2; along the second direction Y, the second organic clearance area BOR2 is located between the first barrier structure 33 and the second barrier structure 35.

[0251] like Figure 42 As shown, the encapsulation mechanism 30 may also include a second barrier structure 35. The second barrier structure 35 and the first barrier structure 33 work together to ensure that the organic encapsulation layer 341 is fully blocked, preventing the organic encapsulation layer 341 from continuing to extend into the first bending area BA1, thus ensuring the narrow border effect of the border area BOR.

[0252] For example, the first barrier structure 33 may include at least one layer of organic material, and the second barrier structure 35 may include at least one layer of organic material. Since organic material layers are relatively easy to form a thick layer, setting both the first barrier structure 33 and the second barrier structure 35 to include at least one layer of organic material can fully guarantee the height of the first barrier structure 33 and the second barrier 35, and ensure that a good blocking effect can be achieved on the organic encapsulation layer 241.

[0253] Furthermore, the border area BOR also includes a second organic clearance area BOR2. The second organic clearance area BOR2 can be understood as an area where no organic material is placed, or it can be understood as located between the first retaining wall structure 33 and the second retaining wall structure 35 along the second direction Y. Since the second organic clearance area BOR2 is provided between the first retaining wall structure 33 and the second retaining wall structure 35, there is a large height difference between the second organic clearance area BOR2 and the area where the first retaining wall structure 33 and the second retaining wall structure 35 are located. That is, a receiving groove can be formed in the second organic clearance area BOR2. This receiving groove can be used to fully accommodate the organic encapsulation layer 341, so as to ensure that the organic encapsulation layer 341 can stop between the first retaining wall 33 and the second retaining wall structure 35. That is, it ensures that the organic encapsulation layer 341 can stop on the side of the first retaining wall 33 away from the first bending area BA1, thus ensuring the narrow border design of the border area BOR.

[0254] For example, the dimensions of the second retaining wall structure 35 in the second direction Y can be 5μm-30μm, such as 5μm, 10μm, 15μm, 20μm, 25μm or 30μm. The specific dimensions of the second retaining wall structure 35 in the second direction Y are not limited in this embodiment.

[0255] The size of the second organic clearance area BOR2 in the second direction Y can be 3μm-20μm, for example, it can be 3μm, 5μm, 9μm, 12μm, 15μm, 18μm or 20μm. The specific size value of the second organic clearance area BOR2 in the second direction Y is not limited in the embodiments of this application.

[0256] In one embodiment, reference continues to... Figure 41As shown, the encapsulation structure 30 includes a first partition structure 311 and a first barrier structure 33, with the first barrier structure 33 located on the side of the first partition structure 311 away from the display area AA; the display panel also includes a cathode 32 and a virtual cathode 36, with the cathode 32 located within the display area AA and within the border area BOR between the display area AA and the first partition structure 311; the virtual cathode 36 is disconnected from the cathode 32 at the first partition structure 311, and the virtual cathode 36 covers the first partition structure 311 and part of the first barrier structure 33.

[0257] like Figure 41 As shown, the encapsulation structure 30 includes a first partition structure 311, which is used to partition structures extending thereto. For example, the first partition structure 311 is used to partition the cathode layer, blocking the transmission channel of moisture through the cathode layer to the display area AA, and protecting the structures in the display area AA from moisture erosion. Figure 41 As shown, the cathode layer fractures at the location of the first partition structure 311, forming a cathode 32 and a virtual cathode 36. The cathode 32 remains within the display area AA and the border area BOR between the display area AA and the first partition structure 311. The virtual cathode 36 is formed on the upper surface of the first partition structure 311 and part of the upper surface of the first baffle structure 33. An open circuit is formed between the virtual cathode 36 and the cathode 32, preventing water vapor or oxygen from being transported from the virtual cathode 36 to the cathode 32, thus ensuring the stability of the structure corresponding to the cathode 32.

[0258] For example, continue to refer to Figure 41 As shown, the bezel area BOR also includes a wire exchange hole setting area BOR3, which has multiple wire exchange holes (not shown in the figure). The signal lines set in the bezel area BOR are electrically connected to the jumper wires 19 set in the first bend area BA1 through the wire exchange holes. The encapsulation structure 30 also includes at least one organic layer 37 and at least one inorganic encapsulation layer 38 set in the wire exchange hole setting area BOR3, and the inorganic encapsulation layer 38 covers the organic layer 37 along the thickness direction Z of the display panel.

[0259] like Figure 41 As shown, the BOR (Border Area) also includes a wire-swapping hole setting area BOR3. The wire-swapping hole setting area BOR3 is the area in the BOR near the first bending area BA1. Since the jumper wire 19 set in the first bending area BA1 needs to have good bending performance, and considering the wiring requirements of the BOR, the signal lines set in the BOR need to be swapped with the jumper wire 19 set in the first bending area BA1 in the wire-swapping hole setting area BOR3, so as to realize the wiring requirements of the BOR and the first bending area BA1.

[0260] For example, continue to refer to Figure 41As shown, the encapsulation structure 30 also includes at least one organic layer 37 and at least one inorganic encapsulation layer 38 disposed in the BOR3 (replacement hole area), with the inorganic encapsulation layer 38 covering the organic layer 37 along the thickness direction Z of the display panel. The inorganic encapsulation layer 38 provides support and protection for the BOR3, ensuring the structural stability of the BOR3. The organic layer 37 can absorb moisture entering the BOR3, ensuring that the wire replacement in the BOR3 area is protected from moisture corrosion and avoiding problems such as poor wire replacement or short circuits.

[0261] It is understood that the inorganic encapsulation layer 38 can be a first inorganic encapsulation layer 342 and / or a second inorganic encapsulation layer 343.

[0262] For example, the size of the wire-changing hole setting area BOR3 in the second direction Y can be 10μm-100μm, such as 10μm, 15μm, 20μm, 28μm, 35μm, 40μm, 50μm, 58μm, 65μm, 70μm, 75μm, 80μm, 86μm, 92μm, 96μm or 100μm. In this embodiment, the size value of the wire-changing hole setting area BOR3 in the second direction Y is not limited.

[0263] For example, continue to refer to Figure 41 As shown, at least one inorganic encapsulation layer 38 includes a first inorganic encapsulation layer 342 and a second inorganic encapsulation layer 343 stacked together; the line switching hole setting area BOR3 includes a line switching area boundary on the side away from the display area, and both the first inorganic encapsulation layer 342 and the second inorganic encapsulation layer 343 terminate at the line switching area boundary.

[0264] like Figure 41 As shown, at least one inorganic encapsulation layer 38 includes a first inorganic encapsulation layer 342 and a second inorganic encapsulation layer 343 stacked together. Both the first inorganic encapsulation layer 342 and the second inorganic encapsulation layer 343 terminate at the boundary of the line switching area. That is, the position of the extension end of the first inorganic encapsulation layer 342 and the second inorganic encapsulation layer 343 in the border area BOR is the boundary of the line switching hole setting area BOR3 on the side away from the display area. In other words, the first inorganic encapsulation layer 342 and the second inorganic encapsulation layer 343 completely cover the line switching hole setting area BOR3, ensuring the encapsulation protection of the line switching hole setting area BOR3.

[0265] For example, continue to refer to Figure 41 As shown, the display panel also includes an encapsulation layer 34, which includes at least one inorganic encapsulation layer; the display panel also includes a cathode signal transmission structure 39 and at least one baffle structure disposed in the bezel area BOR; along the thickness direction Z of the display panel, the inorganic encapsulation layer covers the cathode signal transmission structure 39, the baffle structure and the partition structure 31.

[0266] like Figure 41 As shown, the display panel also includes an encapsulation layer 34, which encapsulates and covers the pixel circuits and light-emitting elements in the display panel, ensuring that the pixel circuits and light-emitting elements are protected from water and oxygen corrosion. Furthermore, the encapsulation layer 34 may include a thin-film encapsulation layer, and may further include a stacked structure of organic and inorganic encapsulation layers to achieve a good encapsulation effect through the cooperation of the organic and inorganic encapsulation layers. Specifically, the encapsulation layer 34 may include a first inorganic encapsulation layer 342, an organic encapsulation layer 341, and a second inorganic encapsulation layer 343 stacked together. The first inorganic encapsulation layer 342 and the second inorganic encapsulation layer 343 achieve a good encapsulation protection effect, while the organic encapsulation layer 341 is used to absorb moisture and oxygen, ensuring that the pixel circuits and light-emitting elements are protected from water and oxygen corrosion.

[0267] Continue to refer to Figure 41 As shown, the display panel also includes a cathode signal transmission structure disposed in the bezel area (BOR). The cathode signal transmission structure can be understood as a structure for transmitting cathode signals, which are signals transmitted to the cathode of the light-emitting element, such as the second power signal PVEE mentioned above. Furthermore, the cathode signal transmission decoupling 39 may include multiple cathode signal transmission layers that are disposed in different layers and electrically connected, such as... Figure 41 The diagram shows a first cathode signal transmission layer 391 and a second cathode signal transmission layer 392. Cathode signals can be transmitted sequentially from the first cathode signal transmission layer 391 to the second cathode signal transmission layer 392, and then from the second cathode signal transmission layer 392 to the cathode 32. Cathode signal transmission is achieved through multiple cathode signal transmission layers that are dissimilarly arranged and electrically connected. Two adjacent cathode signal transmission layers arranged in the thickness direction Z of the display panel can be electrically connected using a shallow via process. This avoids drilling deep vias during cathode signal transmission, ensuring the stability of the electrical connection between the cathode signal transmission layers and simplifying the fabrication process of the cathode signal transmission structure 39.

[0268] For example, the size of the cathode signal transmission structure 39 in the second direction Y can be between 20μm and 100μm, such as 20μm, 30μm, 40μm, 50μm, 60μm, 70μm, 80μm, 90μm or 100μm. The specific size value of the cathode signal transmission structure 39 in the second direction Y is not limited in the embodiments of this application.

[0269] Continue to refer to Figure 41 As shown, the display panel also includes a retaining wall structure disposed in the bezel area (BOR). Figure 41The following explanation uses an example where the bezel area (BOR) has a first barrier structure 33 and a second barrier structure 35. At least one barrier structure is provided in the bezel area (BOR) to prevent the organic encapsulation layer 341 from extending into the first bending area (BA1). In other words, the organic encapsulation layer 341 terminates at the side of the first barrier structure 33 away from the first bending area (BA1), ensuring a smaller area for the bezel area (BOR) and maintaining a narrow bezel effect for the display panel.

[0270] Continue to refer to Figure 41 As shown, along the thickness direction Z of the display panel, inorganic encapsulation layers, such as the first inorganic encapsulation layer 342 and / or the second inorganic encapsulation layer 343, cover the cathode signal transmission structure 39, the barrier structure, and the partition structure 31, ensuring that the inorganic encapsulation layers can encapsulate and protect the cathode signal transmission structure 39, the barrier structure, and the partition structure 31, ensuring the structural stability of the cathode signal transmission structure 39, the barrier structure, and the partition structure 31, and thus ensuring the structural and functional stability of this bezel area BOR.

[0271] For example, continue to refer to Figure 41 As shown, the display panel also includes a cathode signal transmission structure 39 located on the side of the encapsulation structure 30 near the display area, and the bezel area BOR also includes a third organic clearance area BOR4; the cathode signal transmission structure 39 and the cathode 32 are electrically connected in the third organic clearance area BOR4.

[0272] Continue to refer to Figure 41 As shown, the display panel also includes a cathode signal transmission structure 39 located on the side of the encapsulation structure 30 near the display area. The cathode signal transmission structure 39 can be understood as a structure for transmitting cathode signals, which are signals transmitted to the cathode of the light-emitting element, such as the second power signal PVEE mentioned above. Furthermore, the cathode signal transmission structure 39 may include multiple cathode signal transmission layers that are disseminated and electrically connected, such as… Figure 41 The diagram shows a first cathode signal transmission layer 391 and a second cathode signal transmission layer 392. Cathode signals can be transmitted sequentially from the first cathode signal transmission layer 391 to the second cathode signal transmission layer 392, and then from the second cathode signal transmission layer 392 to the cathode 32.

[0273] For example, the border area BOR also includes a third organic clearance area BOR4, which can be understood as an area without organic material. In this embodiment, the cathode signal transmission structure 39 and the cathode 32 are electrically connected in the third organic clearance area BOR4, meaning there is no organic material layer between the cathode signal transmission structure 39 and the cathode 32. Since the organic material layer is relatively thick, electrically connecting the cathode signal transmission structure 39 and the cathode 32 in the third organic clearance area BOR4 ensures that no holes need to be drilled in the thick organic material layer when electrically connecting them. This ensures a simple electrical connection process, stable electrical connection performance, and accurate and efficient transmission of the cathode signal from the cathode signal transmission structure 39 to the cathode 32.

[0274] Optional, continue to refer to Figure 41 As shown, the display panel also includes an organic protective layer 40 disposed in the bezel area BOR; along the thickness direction Z of the display panel, the organic protective layer 40 covers the inorganic encapsulation layer.

[0275] like Figure 41 As shown, the display panel also includes an organic protective layer 40 disposed in the bezel area (BOR). The organic protective layer 40 can be, for example, an organic OC layer; the organic protective layer 40 covers the inorganic encapsulation layer. Figure 41 The following explanation uses the example of an organic protective layer 40 covering a second inorganic encapsulation layer 343. By setting an organic protective layer 40 to cover an inorganic encapsulation layer, the organic protective layer 40 is used as the topmost film layer of the display panel. The organic protective layer 40 enables the planarization design of the light-emitting surface of the display panel, and at the same time, the organic protective layer 40 protects the film layer below it, ensuring the structural stability of the display panel.

[0276] For example, continue to refer to Figure 41 As shown, the encapsulation structure 30 also includes at least one barrier structure, the barrier structure including at least one organic barrier layer; the display panel also includes at least one organic layer located in the display area; the organic barrier layer is disposed on the same layer as the organic layer.

[0277] like Figure 41 As shown, the encapsulation structure 30 also includes at least one barrier structure. Figure 41 The following explanation uses the encapsulation structure 33, which includes a first barrier structure 33 and a second barrier structure 35, as an example. At least one barrier structure is provided in the bezel area BOR to prevent the organic encapsulation layer 341 from extending into the first bending area BA1. In other words, the organic encapsulation layer 341 is set to terminate at the side of the first barrier structure 33 away from the first bending area BA1, ensuring that the area of ​​the bezel area BOR is small and ensuring the narrow bezel effect of the display panel.

[0278] Furthermore, the first barrier structure 33 can be formed by stacking multiple layers, ensuring that the first barrier structure 33 has a higher height than adjacent structures, which can effectively block the organic encapsulation layer 341. Moreover, since the organic material layer is relatively thick, the first barrier structure 33 can include at least one organic barrier layer, thus ensuring that the first barrier structure 33 has a sufficient height.

[0279] For example, the display panel further includes at least one organic layer located in the display area AA. This at least one organic layer may include a first organic layer located between the first source / drain electrode layer and the second source / drain electrode layer, a second organic layer located between the second source / drain electrode layer and the anode film layer, and a third organic layer defining the pixel opening of the light-emitting element. The organic barrier layer is disposed on the same layer as the organic layers, meaning the organic barrier layer is located on at least one of the first, second, and third organic layers. By disposing the organic barrier layer on the same layer as the organic layers in the display area, on the one hand, the barrier structure has a large thickness; on the other hand, the placement of the organic barrier layer does not increase the existing film layers in the display panel, ensuring a simple placement method for the organic barrier layer.

[0280] In one embodiment, reference continues to... Figure 41 As shown, the display panel also includes at least two organic bending protection layers 41 located in the first bending area BA1. The organic bending protection layers 41 are used to protect the first bending area BA1 and prevent the structure disposed in the first bending area BA1 from being damaged.

[0281] For example, continue to refer to Figure 41 As shown, the display panel also includes multiple jumper wires 19 disposed in the first bending area BA1. The jumper wires 19 are disposed between two adjacent organic bending protective layers 41. The two organic bending protective layers 41 can protect the jumper wires 19 and absorb the stress generated by the jumper wires 19 when bending, so as to prevent the jumper wires 19 from breaking when bending and ensure the structural and performance stability of the jumper wires 19.

[0282] The first bending zone BA1 is provided with a multi-layer organic bending protective layer 41. The relative positional relationship between the jumper wire 19 and the multi-layer organic bending protective layer 41 can be adjusted so that the jumper wire 19 is located at or approximately located at the bending neutral plane of the first bending zone BA1. This can reduce the stress on the jumper wire 19 during bending and ensure the structural and performance stability of the jumper wire 19. This application does not limit the specific position of the jumper wire 19 in the organic bending protective layer 41.

[0283] Furthermore, the display panel also includes at least one organic layer located in the display area AA. This at least one organic layer may include a first organic layer located between the first source / drain electrode layer and the second source / drain electrode layer, a second organic layer located between the second source / drain electrode layer and the anode film layer, and a third organic layer defining the pixel opening of the light-emitting element. The organic bending protection layer 41 can be disposed on the same layer as the organic layer located in the display area; that is, the organic bending protection layer 41 includes at least one of the first, second, and third organic layers. By disposing the organic bending protection layer 41 on the same layer as the organic layer in the display area, it is ensured that the placement of the organic bending protection layer 41 does not increase the existing film layers in the display panel, thus ensuring a simple placement method for the organic bending protection layer 41.

[0284] In one embodiment, Figure 42 This is a schematic diagram of another display panel structure provided in an embodiment of this application, specifically a schematic diagram of the structure of the first non-display area and the second non-display area in an unfolded state; Figure 43 This is a schematic diagram of another display panel structure provided in the embodiments of this application, specifically a schematic diagram of the non-light-emitting surface of the first non-display area and the second non-display area after bending; Figure 44 This is a schematic diagram of another display panel structure provided in the embodiments of this application, specifically a schematic diagram of the structure of the first non-display area and the second non-display area in an unfolded state; Figure 45 This is a schematic diagram of another display panel structure provided in the embodiments of this application, specifically a schematic diagram of the non-light-emitting surface of the first non-display area and the second non-display area after bending; Combination Figure 4 , 42 , Figure 43 , Figure 44 and Figure 45 As shown, the first non-display area NAA1 also includes a first bonding area BAA1, which is located on the side of the first circuit setting area CSA1 away from the first bending area BA1; the display panel also includes a plurality of first type signal bonding terminals 11 and a first flexible circuit board FPC1; the first type signal bonding terminals 11 are disposed in the first bonding area BAA1 and are bonded and electrically connected to the first flexible circuit board FPC1.

[0285] like Figure 4 , Figure 42 , Figure 43 , Figure 44 and Figure 45As shown, the first bonding area BAA1 is provided with a plurality of first-type signal bonding terminals 11. These first-type signal bonding terminals 11 are also the bonding terminals provided in the first non-display area NAA1. The first-type signal bonding terminals 11 are used to electrically connect with the first flexible circuit board FPC1 provided in the first non-display area NAA1, to receive signals provided by the first flexible circuit board FPC1, and to transmit these signals to the signal line 12 provided in the first non-display area NAA1. Thus, through the arrangement of the first-type signal bonding terminals 11 and the first flexible circuit board FPC1, signal input can be achieved from the left and / or right bezels of the display panel, improving the flexibility of signal input.

[0286] Continue to refer to Figure 42 , Figure 43 , Figure 44 and Figure 45 As shown, the second non-display area NAA1 also includes a second bonding area BAA2, which is located on the side of the second bending area BA2 away from the display area AA. The display panel also includes a plurality of second type signal bonding terminals 22 and a second flexible circuit board FPC2. The second type signal bonding terminals 22 are disposed in the second bonding area BAA2 and are bonded and electrically connected to the second flexible circuit board FPC2. The second flexible circuit board FPC2 is electrically connected to the first flexible circuit board FPC1.

[0287] like Figure 42 , Figure 43 , Figure 44 and Figure 45 As shown, the second bonding area BAA2 is provided with multiple second-type signal bonding terminals 12, which are also the bonding terminals provided in the second non-display area NAA2. These second-type signal bonding terminals 22 are used to electrically connect with the second flexible circuit board FPC2 provided in the second non-display area NAA2, receiving signals provided by the second flexible circuit board FPC2 and transmitting these signals to the signal lines provided in the second non-display area NAA2 or to the signal lines located in the display area AA. Thus, through the provision of the second-type signal bonding terminals 22 and the second flexible circuit board FPC2, signal input from the lower and / or upper bezel of the display panel is achieved. Combined with the aforementioned scheme of signal input from the left and / or right bezel of the display panel, this ensures diverse and flexible signal input methods for the display panel. Different signal output methods can be set to input the same or different signals as needed, achieving a flexible, diverse, and efficient signal input method.

[0288] Continue to refer to Figure 43 and Figure 45As shown, the second flexible circuit board FPC2 is electrically connected to the first flexible circuit board FPC1, meaning that signal transmission can be achieved between the two flexible circuit boards. This allows the first flexible circuit board FPC1 and the second flexible circuit board FPC2 to cooperate and jointly input the signals required for normal display of the display panel. Specifically, in the first flexible circuit board FPC1 and the second flexible circuit board FPC2, the second flexible circuit board FPC2 can be used as the main circuit board and the first flexible circuit board FPC1 as the auxiliary circuit board; alternatively, the second flexible circuit board FPC2 can be used as the auxiliary circuit board and the first flexible circuit board FPC1 as the main circuit board. This embodiment of the application does not limit this approach.

[0289] For example, continue to refer to Figure 43 As shown, the first flexible circuit board FPC1 includes a first flexible portion FPC11 and a second flexible portion FPC12. The second flexible portion FPC12 is located on the side of the first flexible portion FPC11 near the second straight edge region AA2 and along the second direction Y. The second flexible portion FPC12 overlaps with the second flexible circuit board FPC2. The second flexible portion FPC12 includes a first connecting te...

Claims

1. A display panel, characterized in that, Includes display area and non-display area; The display area includes a first straight edge area and a second straight edge area, the first straight edge area extending along a first direction and the second straight edge area extending along a second direction; the first direction and the second direction intersect. The non-display area includes a first non-display area and a second non-display area, wherein the first non-display area is located on one side of the first straight edge area and the second non-display area is located on one side of the second straight edge area; The first non-display area includes a first bending area and a first circuit setting area. The first bending area connects the display area and the first circuit setting area, and the first circuit setting area is bent to the non-light-emitting side of the display panel through the first bending area. The second non-display area includes a second bending area, a portion of which bends to the non-light-emitting side of the display panel.

2. The display panel according to claim 1, characterized in that, Along the first direction, the extension length of the first bending region is less than or equal to the extension length of the first straight edge region.

3. The display panel according to claim 1, characterized in that, Along the second direction, the extension length of the second bending region is less than or equal to the extension length of the second straight edge region.

4. The display panel according to claim 1, characterized in that, The first non-display area further includes a functional area and a first binding area. The functional area includes the first circuit setting area, and the first binding area is located on the side of the functional area away from the first bending area. The display panel also includes multiple first-type signal bonding terminals and multiple signal lines; The first type of signal bonding terminal is disposed in the first bonding area; The signal line is located in the functional area and is electrically connected to the first type of signal binding terminal.

5. The display panel according to claim 4, characterized in that, The signal lines include DC signal lines, and / or, the signal lines include AC signal lines.

6. The display panel according to claim 5, characterized in that, The DC signal line includes at least one of a power signal line, a level signal line, and an initialization signal line. And / or, the AC signal lines include at least one of a clock signal line, a start signal line, a reset signal line, and a touch signal line.

7. The display panel according to claim 4, characterized in that, The display panel further includes a gate driving circuit and a gate driving signal line disposed in the first circuit setting area, wherein the gate driving signal line is electrically connected to the gate driving circuit. The signal line includes the gate drive signal line, which includes at least one of a level signal line, a clock signal line, a start signal line, and a reset signal line.

8. The display panel according to claim 4, characterized in that, The signal lines include power signal lines and initialization signal lines; At least one of the power signal line and the initialization signal line is at least partially disposed in the functional area between the first circuit setting area and the first bend area.

9. The display panel according to claim 4, characterized in that, The signal lines include power signal lines and initialization signal lines; At least one of the power signal line and the initialization signal line is at least partially disposed in the functional area between the first circuit setting area and the first binding area.

10. The display panel according to claim 4, characterized in that, The signal lines include power signal lines and initialization signal lines; The power signal line includes at least two layers of signal lines that are stacked and electrically connected, and / or the initialization signal line includes at least two layers of signal lines that are stacked and electrically connected.

11. The display panel according to claim 1, characterized in that, The display panel further includes a gate driving circuit disposed in the first circuit setting area; The gate drive circuit includes at least two columns of shift register circuits, each column of shift register circuits including a multi-stage shift register circuit arranged along the first direction, and at least two columns of the shift register circuits arranged along the second direction; The at least two columns of the shift register circuit include an i-th column of shift register circuits and a j-th column of shift register circuits. The i-th column of shift register circuits contains m-level shift register circuits, and the j-th column of shift register circuits contains n-level shift register circuits. Here, i and j are different positive integers, and m and n are different positive integers. The i-th column of shift register circuits is located on the side of the j-th column of shift register circuits away from the first bending region, where m ≤ n.

12. The display panel according to claim 11, characterized in that, The i-th column of shift register circuits and the j-th column of shift register circuits are arranged adjacent to each other along the second direction; The i-th column of shift register circuits includes a p-th level shift register circuit and a p+1-th level shift register circuit, and the j-th column of shift register circuits includes a p+2-th level shift register circuit and a p+3-th level shift register circuit; p is a positive integer; The p-th stage shift register circuit, the (p+1)-th stage shift register circuit, the (p+2)-th stage shift register circuit, and the (p+3)-th stage shift register circuit are cascaded in sequence. The direction in which the p-th stage shift register circuit points to the (p+1)-th stage shift register circuit is opposite to the direction in which the (p+2)-th stage shift register circuit points to the (p+3)-th stage shift register circuit.

13. The display panel according to claim 11, characterized in that, The i-th column of shift register circuits and the j-th column of shift register circuits are arranged adjacent to each other along the second direction; The j-th column of shift register circuits includes a q-th level shift register circuit and a q+1-th level shift register circuit, and the i-th column of shift register circuits includes a q+2-th level shift register circuit and a q+3-th level shift register circuit; q is a positive integer; The q-th stage shift register circuit, the (q+1)-th stage shift register circuit, the (q+2)-th stage shift register circuit, and the (q+3)-th stage shift register circuit are cascaded in sequence. The direction in which the q-th shift register circuit points to the (q+1)-th shift register circuit is opposite to the direction in which the (q+2)-th shift register circuit points to the (q+3)-th shift register circuit.

14. The display panel according to claim 11, characterized in that, The i-th column of shift register circuits and the j-th column of shift register circuits are arranged adjacent to each other along the second direction; The i-th column of shift register circuits includes the g-th stage of shift register circuits; g is a positive integer; The j-th column of shift register circuits includes a k-th level shift register circuit and a (k+1)-th level shift register circuit. The k-th level shift register circuit and the (k+1)-th level shift register circuit are arranged adjacent to each other along the first direction, and there is a first gap between the k-th level shift register circuit and the (k+1)-th level shift register circuit; k is a positive integer. Along the second direction, the g-th shift register circuit overlaps with the first gap; The display panel also includes multiple shift output signal lines and multiple scan signal lines, wherein the shift output signal lines are electrically connected to the shift register circuit and the scan signal lines, respectively. The shift output signal line, which is electrically connected to the g-th shift register circuit, extends along the first gap.

15. The display panel according to claim 11, characterized in that, The display panel also includes an anti-static circuit disposed in the first circuit setting area; Along the first direction, the anti-static circuit is disposed on the side of the i-th column of the shift register circuit near the second straight edge region.

16. The display panel according to claim 1, characterized in that, The display panel further includes a gate driving circuit disposed in the first circuit setting area; The gate drive circuit includes at least two columns of shift register circuits, each column of shift register circuits including a multi-stage shift register circuit arranged along the first direction, and at least two columns of the shift register circuits arranged along the second direction; The at least two columns of the shift register circuit include an i-th column of shift register circuit and a j-th column of shift register circuit, wherein the i-th column of shift register circuit is located on the side of the j-th column of shift register circuit away from the first bending region; wherein i and j are different positive integers; The display panel also includes multiple shift output signal lines and multiple scan signal lines, wherein the shift output signal lines are electrically connected to the shift register circuit and the scan signal lines, respectively. The multiple shift output signal lines include multiple first shift output signal lines, and the first shift output signal lines are electrically connected to the shift register circuits in the i-th column of shift register circuits; A portion of the signal lines in the first shift output signal line are located in the display area.

17. The display panel according to claim 16, characterized in that, The display area also includes an irregularly shaped area, which connects the first straight edge area and the second straight edge area; At least a portion of the first shift output signal line is electrically connected to the scan signal line disposed in the irregular region.

18. The display panel according to claim 16, characterized in that, The first shift output signal line includes a first shift output section, a second shift output section, a third shift output section, and a fourth shift output section; the first shift output section includes a first sub-section and a second sub-section electrically connected; the third shift output section includes a third sub-section and a fourth sub-section electrically connected. The first sub-section is located in the first non-display area and is electrically connected to the shift register circuit in the i-th column of shift register circuits; The second sub-section is located in the display area and is electrically connected to the second shift output section, and the second sub-section extends along the second direction; The second shift output portion is located in the display area and is electrically connected to the third sub-portion, and the second shift output portion extends along the first direction; The third sub-section is located in the display area and extends along the second direction; The fourth sub-section is located in the first non-display area and is electrically connected to the fourth shift output section, and the fourth sub-section extends along the second direction; The fourth shift output portion is located in the first non-display area and is electrically connected to the scanning signal line, and the fourth shift output portion extends along the first direction.

19. The display panel according to claim 18, characterized in that, The second sub-section is arranged on the same layer as the third sub-section, and on a different layer from the second shift output section.

20. The display panel according to claim 18, characterized in that, The display panel also includes a substrate and pixel circuitry located in the display area; The pixel circuit includes at least one first-type transistor, at least one second-type transistor, and at least one storage capacitor; the first-type transistor includes a first active layer and a first gate; the second-type transistor includes a second active layer, a second top gate, and a second bottom gate; The first gate is located on the side of the first active layer closer to the substrate or on the side of the first active layer farther from the substrate; the second top gate is located on the side of the second active layer farther from the substrate, and the second bottom gate is located on the side of the second active layer closer to the substrate; the storage capacitor includes a first capacitor plate and a second capacitor plate disposed opposite to each other, and the second capacitor plate is located on the side of the first capacitor plate farther from the substrate. The display panel further includes a first metal layer, a second metal layer, a third metal layer, a first source / drain electrode layer, a second source / drain electrode layer, and a third source / drain electrode layer; the first gate is located on the first metal layer, the second bottom gate is located on the second metal layer, the second top gate is located on the third metal layer, the first source / drain electrode layer is located on the side of the third metal layer away from the substrate, the second source / drain electrode layer is located on the side of the first source / drain electrode layer away from the substrate, and the third source / drain electrode layer is located on the side of the second source / drain electrode layer away from the substrate; The second sub-part is located at at least one of the first metal layer, the second metal layer, the third metal layer, the first source / drain metal layer, the second source / drain metal layer, and the third source / drain metal layer; The second shift output portion is located in at least one of the first metal layer, the second metal layer, the third metal layer, the first source / drain metal layer, the second source / drain metal layer, and the third source / drain metal layer; The third sub-part is located at at least one of the first metal layer, the second metal layer, the third metal layer, the first source / drain metal layer, the second source / drain metal layer, and the third source / drain metal layer.

21. The display panel according to claim 18, characterized in that, The plurality of first shift output signal lines include the r-th first shift output signal line and the s-th first shift output signal line, and the plurality of scan signal lines include the e-th scan signal line and the f-th scan signal line; r and s are different positive integers, and e and f are different positive integers; The r-th first shift output signal line is electrically connected to the e-th scan signal line, and the s-th first shift output signal line is electrically connected to the f-th scan signal line; Along the first direction, the e-th scan signal line is located on the side of the f-th scan signal line away from the center of the display area; Along the first direction, the second sub-section of the r-th first shift output signal line is located on the side of the second sub-section of the s-th first shift output signal line away from the center of the display area; Along the second direction, the second shift output portion of the r-th first shift output signal line is located on the side of the second shift output portion of the s-th first shift output signal line closer to the center of the display area; Along the first direction, the third sub-section of the r-th first shift output signal line is located on the side of the s-th first shift output signal line away from the center of the display area.

22. The display panel according to claim 1, characterized in that, The display panel further includes a gate driving circuit and a gate driving signal line disposed in the first circuit setting area, wherein the gate driving circuit is electrically connected to the gate driving signal line. The first non-display area also includes a first binding area, which is located on the side of the first circuit setting area away from the first bend area; The display panel further includes a first type of signal bonding terminal disposed in the first bonding area. The first type of signal bonding terminal includes a first type of gate drive signal terminal, and the first type of gate drive signal terminal includes a plurality of first gate drive signal terminals arranged along the first direction. The display panel further includes a first type of gate drive signal transmission unit, which includes multiple first gate drive signal transmission units, and the first gate drive signal transmission units are electrically connected to the first gate drive signal terminal and the gate drive signal line, respectively.

23. The display panel according to claim 22, characterized in that, The gate drive circuit includes at least two columns of shift register circuits, and the shift register circuit columns include multi-level shift register circuits arranged along the first direction; The first gate drive signal transmission section extends along the second direction, and at least a portion of the first gate drive signal transmission section is located between two adjacent shift register circuits arranged along the first direction.

24. The display panel according to claim 22, characterized in that, The first type of gate drive signal terminal includes a first group of gate drive signal terminals and a second group of gate drive signal terminals; the first group of gate drive signal terminals and the second group of gate drive signal terminals are arranged along the first direction and each includes a plurality of first gate drive signal terminals arranged along the first direction; the first group of gate drive signal terminals is located on the side closer to the second straight edge region, and the second group of gate drive signal terminals is located on the side farther away from the second straight edge region. The first type of gate drive signal transmission unit includes a first group of gate drive signal transmission units and a second group of gate drive signal transmission units; the first group of gate drive signal transmission units and the second group of gate drive signal transmission units are arranged along the first direction and each includes multiple first gate drive signal transmission units arranged along the first direction; the first group of gate drive signal transmission units is located on the side close to the second straight edge region, and the second group of gate drive signal transmission units is located on the side away from the second straight edge region. The first group of gate drive signal transmission sections are electrically connected to the first group of gate drive signal terminals and the gate drive signal line, respectively, and the second group of gate drive signal transmission sections are electrically connected to the second group of gate drive signal terminals and the gate drive signal line, respectively.

25. The display panel according to claim 24, characterized in that, The display panel further includes a first virtual axis of symmetry, which extends along the second direction; The first group of gate drive signal terminals and the second group of gate drive signal terminals are symmetrically arranged about the first virtual symmetry axis; The first group of gate drive signal transmission units and the second group of gate drive signal transmission units are symmetrically arranged about the first virtual symmetry axis.

26. The display panel according to claim 22, characterized in that, The first type of gate drive signal terminal includes a first potential drive signal terminal and a second potential drive signal terminal, wherein the potential difference between the first potential drive signal terminal and the second potential drive signal terminal is greater than a preset potential difference; The first type of gate drive signal terminal also includes a first virtual signal terminal; Along the first direction, at least one first virtual signal terminal is provided between the potential in the first potential driving signal terminal and the second potential driving signal terminal.

27. The display panel according to claim 22, characterized in that, The first type of gate drive signal terminal includes a first clock drive signal terminal, a first fixed potential signal terminal, and a second virtual signal terminal; Along the first direction, at least one second virtual signal terminal is provided between the first clock drive signal terminal and the first fixed potential signal terminal.

28. The display panel according to claim 1, characterized in that, The display panel further includes a gate driving circuit and a gate driving signal line disposed in the first circuit setting area, wherein the gate driving circuit is electrically connected to the gate driving signal line. The second non-display area also includes a second binding area, which is located on the side of the second bend area away from the second straight edge area; The display panel further includes a plurality of second type signal bonding terminals disposed in the second bonding area. The second type signal bonding terminals include second type gate drive signal terminals, and the second type gate drive signal terminals include a plurality of second gate drive signal terminals arranged along the second direction. The display panel further includes a second type of gate drive signal transmission section, which includes multiple second gate drive signal transmission sections, and the second gate drive signal transmission sections are electrically connected to the second gate drive signal terminal and the gate drive signal line, respectively.

29. The display panel according to claim 28, characterized in that, The second gate drive signal transmission section includes a first drive transmission subsection, a second drive transmission subsection, and a third drive transmission subsection; The first drive transmission sub-section is electrically connected to the second gate drive signal terminal and the second drive transmission sub-section, respectively; The third drive transmission sub-section is electrically connected to the second drive transmission sub-section and the gate drive signal line, respectively. At least a portion of the second drive transmission sub-unit is disposed in the first bending area.

30. The display panel according to claim 29, characterized in that, The first drive transmission sub-unit includes at least two first sub-units arranged in different layers, and the at least two first sub-units are arranged in parallel.

31. The display panel according to claim 29, characterized in that, The first drive transmission sub-section includes at least two first sub-sections arranged in different layers; The first drive transmission sub-unit includes multiple first sub-drive transmission sub-units and multiple second sub-drive transmission sub-units, with the multiple first sub-drive transmission sub-units arranged in sequence and the multiple second sub-drive transmission sub-units arranged in sequence; At least one layer of the first sub-sub-part in the first sub-drive transmission sub-part is disposed in a different layer from at least one layer of the first sub-sub-part in the second sub-drive transmission sub-part.

32. The display panel according to claim 29, characterized in that, The first drive transmission sub-unit includes multiple first sub-drive transmission sub-units and multiple second sub-drive transmission sub-units, with the multiple first sub-drive transmission sub-units arranged in sequence and the multiple second sub-drive transmission sub-units arranged in sequence; The first sub-drive transmission sub-section and the second sub-drive transmission sub-section are arranged alternately.

33. The display panel according to claim 29, characterized in that, The second drive transmission sub-section includes a first end portion, a second end portion, and a middle portion; The first end is electrically connected to the first drive transmission sub-part via a via; The second end is electrically connected to the third drive transmission sub-section via a via; The intermediate portion connects the first end and the second end, and the intermediate portion includes a plurality of second sub-parts, which are arranged in parallel.

34. The display panel according to claim 29, characterized in that, The third drive transmission sub-unit includes at least two third sub-sub-units arranged in different layers, and the at least two third sub-sub-units are arranged in parallel.

35. The display panel according to claim 29, characterized in that, The third drive transmission sub-section includes at least two third sub-sections arranged in different layers; The third drive transmission sub-unit includes multiple third sub-drive transmission sub-units and multiple fourth sub-drive transmission sub-units, with the multiple third sub-drive transmission sub-units arranged sequentially and the multiple fourth sub-drive transmission sub-units arranged sequentially. At least one layer of the third sub-sub-section in the third sub-drive transmission sub-section is disposed in a different layer from at least one layer of the third sub-sub-section in the fourth sub-drive transmission sub-section.

36. The display panel according to claim 29, characterized in that, The third drive transmission sub-unit includes multiple third sub-drive transmission sub-units and multiple fourth sub-drive transmission sub-units, with the multiple third sub-drive transmission sub-units arranged sequentially and the multiple fourth sub-drive transmission sub-units arranged sequentially. The third sub-drive transmission sub-unit and the fourth sub-drive transmission sub-unit are arranged alternately.

37. The display panel according to claim 29, characterized in that, The second drive transmission sub-section is disposed on a different layer from the first drive transmission sub-section and the third drive transmission sub-section, respectively.

38. The display panel according to claim 28, characterized in that, The second type of gate drive signal terminal includes a third potential drive signal terminal and a fourth potential drive signal terminal, wherein the potential difference between the third potential drive signal terminal and the fourth potential drive signal terminal is greater than a preset potential difference; The second type of gate drive signal terminal also includes a third virtual signal terminal; Along the second direction, at least one third virtual signal terminal is provided between the potential in the third potential driving signal terminal and the fourth potential driving signal terminal.

39. The display panel according to claim 28, characterized in that, The second type of gate drive signal terminal includes a second clock drive signal terminal, a second fixed potential signal terminal, and a fourth virtual signal terminal; Along the second direction, at least one of the fourth virtual signal terminals is provided between the second clock drive signal terminal and the second fixed potential signal terminal.

40. The display panel according to claim 1, characterized in that, The display panel further includes a gate driving circuit and a gate driving signal line disposed in the first circuit setting area, wherein the gate driving circuit is electrically connected to the gate driving signal line. The first non-display area further includes a first binding area, which is located on the side of the first circuit setting area away from the first bend area; the second non-display area further includes a second binding area, which is located on the side of the second bend area away from the second straight edge area. The display panel further includes a first type of signal bonding terminal disposed in the first bonding area and a plurality of second type of signal bonding terminals disposed in the second bonding area; the first type of signal bonding terminal includes a first type of gate driving signal terminal, and the first type of gate driving signal terminal includes a plurality of first gate driving signal terminals arranged along the first direction; the second type of signal bonding terminal includes a second type of gate driving signal terminal, and the second type of gate driving signal terminal includes a plurality of second gate driving signal terminals arranged along the second direction. The display panel further includes a first type of gate drive signal transmission unit and a second type of gate drive signal transmission unit; the first type of gate drive signal transmission unit includes multiple first gate drive signal transmission units; the second type of gate drive signal transmission unit includes multiple second gate drive signal transmission units; the first type of gate drive signal transmission unit is electrically connected to the first gate drive signal terminal and the gate drive signal line respectively, and the second type of gate drive signal transmission unit is electrically connected to the second gate drive signal terminal and the gate drive signal line respectively.

41. The display panel according to claim 40, characterized in that, The first type of gate drive signal terminal includes a first group of gate drive signal terminals, and the second type of gate drive signal terminal includes a third group of gate drive signal terminals; The first group of gate drive signal terminals is located on the side of the first bonding region closer to the second bonding region, and the third group of drive signal terminals is located on the side of the second bonding region closer to the first bonding region; The display panel further includes a second virtual axis of symmetry, the extension direction of which intersects both the first direction and the second direction; The first group of gate drive signal terminals and the third group of gate drive signal terminals are symmetrically arranged about the second virtual symmetry axis.

42. The display panel according to claim 1, characterized in that, The display panel further includes a gate driving circuit and a gate driving signal line disposed in the first circuit setting area, wherein the gate driving circuit is electrically connected to the gate driving signal line. The gate drive circuit includes at least two columns of shift register circuits, each column of shift register circuits including a multi-stage shift register circuit arranged along the first direction, and at least two columns of the shift register circuits arranged along the second direction; At least two columns of the shift register circuits include the i-th column and the j-th column; i and j are both positive integers; The gate drive signal line includes a first drive signal line portion and a second drive signal line portion that are electrically connected. Both the first drive signal line portion and the second drive signal line portion extend along the first direction; The first drive signal line branch is electrically connected to multiple levels of the shift register circuit in the i-th column of the shift register circuit, and the second drive signal line branch is electrically connected to multiple levels of the shift register circuit in the j-th column of the shift register circuit.

43. The display panel according to claim 42, characterized in that, The gate drive signal line further includes a third drive signal line portion and / or a fourth drive signal line portion; The third driving signal line is electrically connected to the first driving signal line and the second driving signal line respectively, and the third driving signal line is located on the side of the first circuit setting area closer to the second non-display area. And / or, the fourth driving signal line is electrically connected to the first driving signal line and the second driving signal line, respectively, and the fourth driving signal line is located on the side of the first circuit setting area away from the second non-display area.

44. The display panel according to claim 43, characterized in that, The display panel includes a first gate drive signal line and a second gate drive signal line. The first drive signal line portion of the first gate drive signal line is located on the side of the first drive signal line portion of the second gate drive signal line that is away from the first bend region, and the second drive signal line portion of the first gate drive signal line is located on the side of the second drive signal line portion of the second gate drive signal line that is away from the first bend region. The third driving signal line portion in the first gate driving signal line is located on the side of the third driving signal line portion in the second gate driving signal line that is close to the second straight edge region, and / or, the fourth driving signal line portion in the first gate driving signal line is located on the side of the fourth driving signal line portion in the second gate driving signal line that is far away from the second straight edge region.

45. The display panel according to claim 42, characterized in that, The first non-display area also includes a first binding area, which is located on the side of the first circuit setting area away from the first bend area; The display panel further includes a first type of signal bonding terminal disposed in the first bonding area. The first type of signal bonding terminal includes a first type of gate drive signal terminal, and the first type of gate drive signal terminal includes a plurality of first gate drive signal terminals arranged along the first direction. The display panel further includes a first type of gate drive signal transmission unit, which includes multiple first gate drive signal transmission units. The i-th column of shift register circuits is located on the side of the j-th column of shift register circuits closest to the first binding area; The first gate drive signal transmission section is electrically connected to the first gate drive signal terminal and the first drive signal line, respectively.

46. ​​The display panel according to claim 1, characterized in that, The display panel further includes a gate driving circuit disposed in the first circuit setting area. The gate driving circuit includes at least two columns of shift register circuits. The shift register circuit columns include multi-level shift register circuits arranged along the first direction, and at least two columns of the shift register circuits are arranged along the second direction. The at least two columns of the shift register circuits include an i-th column of shift register circuits and a j-th column of shift register circuits, wherein the shift register circuits in the i-th column of shift register circuits include a first shift register circuit and a second shift register circuit arranged along the second direction; The shift register circuit in the j-th column of shift register circuits includes a first shift register circuit and a second shift register circuit arranged along the second direction.

47. The display panel according to claim 1, characterized in that, The display panel further includes a gate driving circuit disposed in the first circuit setting area. The gate driving circuit includes at least two columns of shift register circuits. The shift register circuit columns include multi-level shift register circuits arranged along the first direction, and at least two columns of the shift register circuits are arranged along the second direction. The at least two columns of the shift register circuits include an i-th column of shift register circuits and a j-th column of shift register circuits, wherein the shift register circuits in the i-th column of shift register circuits include a first shift register circuit and a second shift register circuit arranged along the second direction; The shift register circuit in the j-th column includes a second shift register circuit and a first shift register circuit arranged along the second direction.

48. The display panel according to claim 1, characterized in that, The display panel further includes a gate driving circuit disposed in the first circuit setting area, and the gate driving circuit includes a multi-stage shift register circuit arranged along the first direction. The first non-display area also includes a functional area, and the display panel also includes multiple signal lines disposed in the functional area, the signal lines including power signal lines; The display panel also includes multiple shift output signal lines and multiple scan signal lines, wherein the shift output signal lines are electrically connected to the shift register circuit and the scan signal lines, respectively. The display panel also includes multiple jumper wires disposed in the first bending area, the multiple jumper wires including multiple power signal jumper wires and multiple shift output signal jumper wires; The power signal jumper wire is disposed on a different layer and electrically connected to the power signal line, the shift output signal jumper wire is disposed on a different layer and electrically connected to the shift output signal line, and the power signal jumper wire and the shift output signal jumper wire are disposed on the same layer.

49. The display panel according to claim 48, characterized in that, The multiple power signal jumpers include the v-th power signal jumper and the w-th power signal jumper arranged adjacent to each other along the first direction; v and w are different positive integers; Among them, a shift output signal jumpers are provided between the vth power signal jumper and the wth power signal jumper, where a is a positive integer.

50. The display panel according to claim 49, characterized in that, The multiple power signal jumpers also include an xth power signal jumper and a yth power signal jumper arranged adjacent to each other along the first direction; x and y are different positive integers; Specifically, b shift output signal jumpers are provided between the xth power signal jumper and the yth power signal jumper; b is a positive integer and is not the same as a.

51. The display panel according to claim 48, characterized in that, The gate drive circuit includes at least two columns of shift register circuits, each column of shift register circuits including a multi-stage shift register circuit arranged along the first direction, and at least two columns of the shift register circuits arranged along the second direction; The first circuit setting area includes a first setting partition and a second setting partition arranged along the first direction, and the number of shift register circuit columns in the first setting partition and the second setting partition is different; The multiple shift output signal jumpers include multiple first shift output signal jumpers and multiple second shift output signal jumpers. The first shift output signal jumpers are electrically connected to the shift register circuit in the first setting partition, and the second shift output signal jumpers are electrically connected to the shift register circuit in the second setting partition. Multiple power signal jumpers are provided between the first shift output signal jumper and the second shift output signal jumper.

52. The display panel according to claim 48, characterized in that, The gate drive circuit includes at least two columns of shift register circuits, each column of shift register circuits including a multi-stage shift register circuit arranged along the first direction, and at least two columns of the shift register circuits arranged along the second direction; The first circuit setting area includes a first setting partition and a second setting partition arranged along the first direction, wherein the number of setting columns of the shift register circuit in the first setting partition is less than the number of setting columns of the shift register circuit in the second setting partition; The first bending area includes a first sub-bending area and a second sub-bending area. Along the second direction, the first sub-bending area overlaps with the first set partition, and the second sub-bending area overlaps with the second set partition. The distribution density of the power signal jumpers in the first sub-bend area is greater than the distribution density of the power signal jumpers in the second sub-bend area.

53. The display panel according to claim 48, characterized in that, The display area further includes a third straight edge area, which extends along the second direction; The first bending area includes a third sub-bending area and a fourth sub-bending area. Along the first direction, the fourth sub-bending area is located on the side of the third sub-bending area that is close to the second straight edge area, and / or, the fourth sub-bending area is located on the side of the third sub-bending area that is close to the third straight edge area. The shift output signal jumpers are all located in the third sub-bend area; at least some of the power signal jumpers are located in the fourth sub-bend area.

54. The display panel according to claim 48, characterized in that, The signal lines also include initialization signal lines; The multiple jumper wires also include multiple initialization jumper wires disposed in the first bending area. The initialization jumper wires are electrically connected to the initialization signal line and are disposed on the same layer as the power signal jumper wire and the shift output signal jumper wire.

55. The display panel according to claim 54, characterized in that, Along the first direction, at least a portion of the initialization jumper is disposed between the power jumper and the shift output signal jumper.

56. The display panel according to claim 1, characterized in that, The display panel also includes power signal lines; The power signal line includes a first sub-power section and a second sub-power section; The first sub-power supply branch extends along the first direction and is located on the side of the first bend area away from the display area; the second sub-power supply branch extends along the first direction and is located on the side of the first bend area close to the display area. The first sub-power supply section and the second sub-power supply section are electrically connected via the power signal jumper wire.

57. The display panel according to claim 56, characterized in that, The linewidth of the first sub-power supply portion in the second direction is greater than the linewidth of the second sub-power supply portion in the second direction.

58. The display panel according to claim 56, characterized in that, The display panel further includes a gate driving circuit disposed in the circuit setting area; Along the thickness direction of the display panel, the first sub-power supply portion covers at least a portion of the gate drive circuit.

59. The display panel according to claim 56, characterized in that, A portion of the second sub-power supply is located in the second non-display area; The second non-display area also includes a second binding area, which is located on the side of the second bend area away from the second straight edge area; The display panel further includes a plurality of second-type signal bonding terminals disposed in the second bonding area; the second-type signal bonding terminals include second power signal terminals; The display panel also includes a power signal connection portion disposed in the second bending area, which is electrically connected to the second power signal terminal and the second sub-power portion located in the second non-display area.

60. The display panel according to claim 56, characterized in that, The power signal line includes a first power signal line and / or a second power signal line; The first power signal line has a different potential than the second power signal line.

61. The display panel according to claim 1, characterized in that, The first non-display area further includes a function area and a first binding area, wherein the first binding area is located on the side of the function area away from the first bend area; The display panel also includes multiple signal lines disposed in the functional area and a first type of signal bonding terminal disposed in the first bonding area. The signal lines include power signal lines, and the first type of signal bonding terminal includes multiple first power signal terminals arranged along the first direction. The first power signal terminal is electrically connected to the power signal line.

62. The display panel according to claim 61, characterized in that, The display panel further includes a gate driving circuit and a gate driving signal line disposed in the first circuit setting area, wherein the gate driving circuit is electrically connected to the gate driving signal line. The first type of signal bonding terminal also includes a first type of gate drive signal terminal, which is electrically connected to the gate drive signal line; The display area further includes a third straight edge area, which extends along the second direction; Along the first direction, the power signal terminal is located on the side of the first type of gate drive signal terminal near the second straight edge region, and / or, the power signal terminal is located on the side of the first type of gate drive signal terminal near the third straight edge region.

63. The display panel according to claim 61, characterized in that, The signal line also includes an initialization signal line, and the first type of signal bonding terminal also includes an initialization signal terminal; The initialization signal terminal is electrically connected to the initialization signal line.

64. The display panel according to claim 63, characterized in that, The display area further includes a third straight edge area, which extends along the second direction; Along the first direction, the power signal terminal is located on the side of the initialization signal terminal near the second straight edge region, and / or, the power signal terminal is located on the side of the initialization signal terminal near the third straight edge region.

65. The display panel according to claim 63, characterized in that, The display panel further includes a gate driving circuit and a gate driving signal line disposed in the first circuit setting area, wherein the gate driving circuit is electrically connected to the gate driving signal line. The first type of signal bonding terminal also includes a first type of gate drive signal terminal, which is electrically connected to the gate drive signal line; The display area further includes a third straight edge area, which extends along the second direction; Along the first direction, the initialization signal terminal is located on the side of the first type of gate drive signal terminal near the second straight edge region, and the first power supply signal terminal is located on the side of the initialization signal terminal near the second straight edge region; and / or, the initialization signal terminal is located on the side of the first type of gate drive signal terminal near the third straight edge region, and the power supply signal terminal is located on the side of the initialization signal terminal near the third straight edge region.

66. The display panel according to claim 1, characterized in that, The first non-display area also includes a function area and a first binding area; The functional area includes the first circuit setting area and the circuit setting free area. Along the first direction, the circuit setting free area is located on at least one side of the first circuit setting area. The first binding area is located on the side of the functional area away from the first bending area, and the first binding area is provided with a plurality of first type signal binding terminals, the first type signal binding terminals including fixed potential signal terminals; The signal line includes a fixed potential signal line, which is disposed in the functional area between the first circuit setting area and the first bending area; The display panel also includes a fixed signal connection part disposed in the unused area of ​​the circuit, the fixed signal connection part being electrically connected to the fixed potential signal terminal and the fixed potential signal line respectively.

67. The display panel according to claim 66, characterized in that, The fixed signal connection part is integrally formed with the fixed potential signal line.

68. The display panel according to claim 66, characterized in that, The fixed potential signal line includes at least one of a power signal line and an initialization signal line. The fixed potential signal terminal includes at least one of a power signal terminal and an initialization signal terminal.

69. The display panel according to claim 1, characterized in that, The first non-display area also includes a border area, which is located on the side of the first bend area closer to the display area along the second direction; The display panel also includes an encapsulation structure located in the bezel area, the encapsulation structure including at least one partition structure; The partition structure extends along the first direction and includes a first partition layer and a second partition layer stacked together; the display panel further includes a substrate, the first partition layer is located on the side of the second partition layer close to the substrate, and the area of ​​the first partition layer is smaller than the area of ​​the second partition layer. Along the thickness direction of the display panel, the second partition layer covers the first partition layer; a and b are both positive integers.

70. The display panel according to claim 69, characterized in that, The partition structure further includes a c-th partition layer, which is located on the side of the a-th partition layer that is closer to the substrate; The area of ​​the c-th partition layer is greater than the area of ​​the a-th partition layer, and the c-th partition layer covers the a-th partition layer along the thickness direction of the display panel; c is a positive integer.

71. The display panel according to claim 69, characterized in that, The encapsulation structure includes a plurality of the partition structures, which are arranged along the second direction.

72. The display panel according to claim 69, characterized in that, The border area also includes a first organic clearance area, and at least one of the partition structures is disposed in the first organic clearance area.

73. The display panel according to claim 69, characterized in that, The encapsulation structure also includes a first retaining wall structure; The display panel further includes an encapsulation layer, which includes at least an organic encapsulation layer, and the organic encapsulation layer terminates on the side of the first retaining wall structure away from the first bending area.

74. The display panel according to claim 73, characterized in that, The encapsulation structure includes a first partition structure and a second partition structure; Along the second direction, the first retaining wall structure is located between the first partition structure and the second partition structure.

75. The display panel according to claim 73, characterized in that, The encapsulation structure further includes a second barrier structure, which is located on the side of the first barrier structure away from the first bending area. The border area also includes a second organic clearance area; along the second direction, the second organic clearance area is located between the first retaining wall structure and the second retaining wall structure.

76. The display panel according to claim 69, characterized in that, The encapsulation structure includes a first partition structure and a first barrier structure, wherein the first barrier structure is located on the side of the first partition structure away from the display area; The display panel further includes a cathode and a virtual cathode, the cathode being located within the display area and within the border area between the display area and the first partition structure; The virtual cathode is disconnected from the cathode at the first partition structure, and the virtual cathode covers the first partition structure and part of the first retaining wall structure.

77. The display panel according to claim 69, characterized in that, The frame area also includes a cable replacement hole setting area, which has multiple cable replacement holes. The signal line set in the frame area and the jumper wire set in the first bend area are electrically connected through the cable replacement holes. The encapsulation structure further includes at least one organic layer and at least one inorganic encapsulation layer disposed in the area where the line switching hole is located, and the inorganic encapsulation layer covers the organic layer along the thickness direction of the display panel.

78. The display panel according to claim 77, characterized in that, At least one inorganic encapsulation layer includes a first inorganic encapsulation layer and a second inorganic encapsulation layer stacked together; The line-changing hole setting area includes a line-changing area boundary on the side away from the display area, and both the first inorganic encapsulation layer and the second inorganic encapsulation layer terminate at the line-changing area boundary.

79. The display panel according to claim 69, characterized in that, The display panel further includes an encapsulation layer, which includes at least one inorganic encapsulation layer. The display panel also includes a cathode signal transmission structure and at least one baffle structure disposed in the frame area; Along the thickness direction of the display panel, the inorganic encapsulation layer covers the cathode signal transmission structure, the barrier structure, and the partition structure.

80. The display panel according to claim 79, characterized in that, The display panel also includes an organic protective layer disposed in the border area; Along the thickness direction of the display panel, the organic protective layer covers the inorganic encapsulation layer.

81. The display panel according to claim 69, characterized in that, The display panel also includes a cathode signal transmission structure located on the side of the encapsulation structure near the display area, and the bezel area also includes a third organic clearance area; The cathode signal transmission structure is electrically connected to the cathode in the third organic clearance zone.

82. The display panel according to claim 69, characterized in that, The encapsulation structure further includes at least one barrier structure, the barrier structure comprising at least one organic barrier layer; The display panel further includes at least one organic layer located in the display area; The organic retaining wall layer is disposed in the same layer as the organic layer.

83. The display panel according to claim 1, characterized in that, The display panel also includes at least two organic bending protective layers located in the first bending area.

84. The display panel according to claim 83, characterized in that, The display panel also includes multiple jumper wires disposed in the first bending area, the jumper wires being disposed between two adjacent organic bending protective layers.

85. The display panel according to claim 1, characterized in that, The first non-display area also includes a first binding area, which is located on the side of the first circuit setting area away from the first bend area; The display panel also includes multiple first-type signal bonding terminals and a first flexible circuit board; The first type of signal bonding terminal is disposed in the first bonding area and is bonded and electrically connected to the first flexible circuit board.

86. The display panel according to claim 85, characterized in that, The second non-display area also includes a second binding area, which is located on the side of the second bend area away from the display area; The display panel also includes multiple second-type signal bonding terminals and a second flexible circuit board; The second type of signal bonding terminal is disposed in the second bonding area and is bonded and electrically connected to the second flexible circuit board; The second flexible circuit board is electrically connected to the first flexible circuit board.

87. The display panel according to claim 86, characterized in that, The first flexible circuit board includes a first flexible portion and a second flexible portion. The second flexible portion is located on the side of the first flexible portion near the second straight edge area and overlaps with the second flexible circuit board along the second direction. The second flexible segment includes a first connecting terminal, and the second flexible circuit board includes a second connecting terminal, wherein the first connecting terminal and the second connecting terminal are electrically connected.

88. The display panel according to claim 87, characterized in that, Along the second direction, the width of the second flexible portion is smaller than the width of the first flexible portion.

89. The display panel according to claim 85, characterized in that, The first flexible circuit board extends L1 in the first direction. The first straight edge region extends L2 in the first direction; Where 1 / 20≤L1 / L2≤1.

90. The display panel according to claim 1, characterized in that, The display area further includes a third straight edge area, which extends along the second direction; The non-display area also includes a third non-display area, which is located on one side of the third straight edge area and includes a third bending area, part of which bends to the non-light-emitting side of the display panel.

91. The display panel according to claim 1, characterized in that, The display area further includes a fourth straight edge area, which extends along the first direction; The non-display area also includes a fourth non-display area, which is located on one side of the fourth straight edge area and includes a fourth bending area and a second circuit setting area. The fourth bending area connects the display area and the second circuit setting area, and the second circuit setting area is bent to the non-light-emitting side of the display panel through the fourth bending area.

92. The display panel according to claim 91, characterized in that, The fourth non-display area also includes a third binding area, which is located on the side of the second circuit setting area away from the fourth bending area; The display panel also includes multiple third-type signal bonding terminals and a third flexible circuit board; The third type of signal bonding terminal is disposed in the third bonding area and is bonded and electrically connected to the third flexible circuit board; The second non-display area also includes a second binding area, which is located on the side of the second bend area away from the display area; The display panel also includes multiple second-type signal bonding terminals and a second flexible circuit board; The second type of signal bonding terminal is disposed in the second bonding area and is bonded and electrically connected to the second flexible circuit board; The second flexible circuit board is electrically connected to the third flexible circuit board.

93. The display panel according to claim 92, characterized in that, The third flexible circuit board includes a third flexible portion and a fourth flexible portion. The fourth flexible portion is located on the side of the third flexible portion near the second straight edge area and overlaps with the second flexible circuit board along the second direction. The fourth flexible segment includes a third connecting terminal, and the second flexible circuit board includes a fourth connecting terminal, wherein the third connecting terminal and the fourth connecting terminal are electrically connected.

94. The display panel according to claim 1, characterized in that, The first non-display area also includes a first binding area, which is located on the side of the first circuit setting area away from the first bend area; The display panel also includes a plurality of first-type signal bonding terminals, which include touch signal terminals.

95. The display panel according to claim 1, characterized in that, The first non-display area also includes a first binding area, which is located on the side of the first circuit setting area away from the first bend area; The display panel also includes a plurality of first-type signal bonding terminals, which include test signal terminals.

96. The display panel according to claim 1, characterized in that, The first straight edge region extends longer in the first direction than the second straight edge region extends longer in the second direction.

97. A display panel, characterized in that, Includes display area and non-display area; The display area includes a first straight edge area and a second straight edge area, the first straight edge area extending along a first direction and the second straight edge area extending along a second direction; the first direction and the second direction intersect. The non-display area includes a first non-display area and a second non-display area, wherein the first non-display area is located on one side of the first straight edge area and the second non-display area is located on one side of the second straight edge area; The first non-display area includes a first bend area and a first circuit setting area, wherein the first bend area connects the display area and the first circuit setting area; The second non-display area includes the second bend area.

98. The display panel according to claim 97, characterized in that, The first non-display area further includes a first binding area, and the second non-display area further includes a second binding area; The display panel also includes multiple first-type signal bonding terminals, multiple second-type signal bonding terminals, a first flexible circuit board, and a second flexible circuit board; The first type of signal bonding terminal is disposed in the first bonding area and electrically connected to the first flexible circuit board; the second type of signal bonding terminal is disposed in the second bonding area and electrically connected to the second flexible circuit board. In the unfolded state of the first non-display area and the second non-display area, there is a gap between the first flexible circuit board and the second flexible circuit board; The display area also includes a corner display area, which is connected to the first straight edge area and the second straight edge area respectively; The corner display area corresponds to the gap.

99. The display panel according to claim 98, characterized in that, In the unfolded state of the first non-display area, the first flexible circuit board extends along the first straight edge area.

100. The display panel according to claim 98, characterized in that, The display area further includes a third straight edge area, which extends along the second direction; Along the first direction, the first type of signal bonding terminal is located on the side of the first bonding area near the second straight edge area, and / or, the first type of signal bonding terminal is located on the side of the first bonding area near the third straight edge area.

101. The display panel according to claim 98, characterized in that, The first flexible circuit board extends L1 in the first direction. The first straight edge region extends L2 in the first direction; Where 1 / 20≤L1 / L2≤1.

102. A display device, characterized in that, Includes the display panel as described in any one of claims 1-101.

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