Sensing circuit and display device including the sensing circuit

Abstract

This document discloses a sensing circuit and a display device including the sensing circuit. The sensing circuit includes: a first switch connected between a first reference voltage line to which a first reference voltage is applied and each of a plurality of sensing lines; a sampling and holding unit including a first sampling and holding unit configured to sample voltages supplied through sensing lines connected to each of a plurality of first sensing channels, and a second sampling and holding unit configured to sample voltages supplied through sensing lines connected to at least one second sensing channel; an amplifier configured to receive and amplify the sampled voltages from the sampling and holding unit; and an analog-to-digital (AD) converter configured to convert the amplified voltages into digital data and generate sensing data, wherein the second sampling and holding unit is selectively activated according to a mode control signal.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2025-0018584, filed on February 13, 2025, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the present invention relate to a sensing circuit and a display device including the sensing circuit. Background Technology

[0004] With the development of the information society, the demand for display devices for displaying images has increased in various forms, and recently, various types of display devices, such as liquid crystal display (LCD) devices and organic light-emitting display (OLED) devices, have been utilized.

[0005] The display device includes a display panel, which includes multiple sub-pixels and a panel driver for driving the display panel. The panel driver includes a data driver for providing data voltages to the display panel and a gate driver for providing gate signals to the display panel.

[0006] In a display device, when drive signals such as gate signals and data signals are provided to multiple sub-pixels formed in a display panel, the selected sub-pixels can transmit light or emit light directly, thereby displaying an image.

[0007] The electrical characteristics of the driving elements in a sub-pixel should be identical. However, due to process variations, changes over time, and prolonged power outages, the electrical characteristics between sub-pixels may differ. Therefore, the data driver also includes a sensing circuit for sensing the electrical characteristics of the sub-pixels via a sensing line, and modulates the pixel data of the input image based on the results detected by the sensing circuit to compensate for the electrical characteristic deviations of the sub-pixels.

[0008] However, the number of sensing lines can vary depending on the size or resolution of the display panel. Therefore, some sensing lines may not be connected to the sensing circuitry. Consequently, when sensing lines are not connected to some sensing channels in the sensing circuitry, accurate sensing data cannot be obtained because voltage is detected when the sensing channel is floating. Summary of the Invention

[0009] The present invention relates to providing a sensing circuit that can be selectively driven and a display device including the sensing circuit.

[0010] It should be noted that the purpose of this invention is not limited to the above-described purpose, and other purposes of this invention will be apparent to those skilled in the art from the following description.

[0011] According to one aspect of the invention, a sensing circuit is provided, the sensing circuit comprising: a first switch connected between a first reference voltage line to which a first reference voltage is applied and each of a plurality of sensing lines; a sampling and holding unit including a first sampling and holding unit configured to sample voltage supplied through a sensing line connected to each of a plurality of first sensing channels, and a second sampling and holding unit configured to sample voltage supplied through a sensing line connected to at least one second sensing channel; an amplifier configured to receive the sampled voltage from the sampling and holding unit and amplify the sampled voltage; and an analog-to-digital (AD) converter configured to convert the amplified voltage into digital data and generate sensing data, wherein the second sampling and holding unit is selectively activated according to a mode control signal.

[0012] According to another aspect of the present invention, a display device is provided, the display device comprising: a display panel, wherein pixels are disposed in a region where a plurality of gate lines and a plurality of data lines intersect; a gate driver configured to output gate signals through the gate lines; a data driver configured to output data voltages through the data lines; and a timing controller configured to control the gate driver and the data driver, wherein the data driver includes a sensing circuit configured to detect electrical characteristics of the pixels and generate sensing data, and the sensing circuit includes: a first switch connected to a first reference voltage to which a first reference voltage is applied. Between a line and each of a plurality of sensing lines; a sampling and holding unit, the sampling and holding unit including a first sampling and holding unit configured to sample voltage supplied through a sensing line connected to each of a plurality of first sensing channels, and a second sampling and holding unit configured to sample voltage supplied through a sensing line connected to at least one second sensing channel; an amplifier configured to receive the sampled voltage from the sampling and holding unit and amplify the sampled voltage; and an analog-to-digital (AD) converter configured to convert the amplified voltage into digital data and generate sensing data, wherein the second sampling and holding unit is selectively activated according to a mode control signal. Attached Figure Description

[0013] The above and other objects, features, and advantages of the present invention will become more apparent to those skilled in the art from the detailed description of exemplary embodiments of the invention with reference to the accompanying drawings, wherein:

[0014] Figure 1 This is a diagram illustrating a display device according to an embodiment of the present invention;

[0015] Figure 2 This is a diagram illustrating a pixel circuit according to an embodiment of the present invention;

[0016] Figure 3 This is a diagram illustrating the configuration of a data driver according to an embodiment of the present invention;

[0017] Figure 4 and Figure 5 This is a diagram illustrating a sensing circuit according to a first embodiment of the present invention;

[0018] Figure 6A and Figure 6B It is shown Figure 4 A diagram showing the arrangement of the sampling and holding sections;

[0019] Figure 7A and 7B This is a diagram showing the activation / deactivation state of the sampling and holding section;

[0020] Figure 8 and Figure 9 This is a diagram illustrating the driving timing of a sensing circuit according to an embodiment of the present invention;

[0021] Figure 10 and Figure 11 It is used to describe Figure 8 The diagram shows the operating principle of the sensing circuit.

[0022] Figure 12 and Figure 13 This is a diagram illustrating a sensing circuit according to a second embodiment of the present invention; and

[0023] Figure 14 and Figure 15 This is a graph showing the offset values ​​of the sampling and holding sections based on the channel. Detailed Implementation

[0024] The advantages, features, and implementations of the invention will become apparent from the following detailed description of the embodiments, taken in conjunction with the accompanying drawings. The invention can be implemented in many different forms and should not be construed as limited to the embodiments set forth herein. These embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art, and the invention is defined only by the scope of the appended claims.

[0025] The shapes, dimensions, ratios, angles, quantities, etc., disclosed in the accompanying drawings to describe embodiments of the invention are illustrative, and therefore the invention is not limited to what is shown. Throughout this specification, the same reference numerals refer to substantially the same parts. Furthermore, in the following description of the invention, detailed descriptions of known related technologies will be omitted here where it is determined that such detailed descriptions would unnecessarily obscure the gist of the invention.

[0026] When the terms “have,” “comprising,” “have,” “compose of,” etc., are used as references in this invention, other parts may be added unless the term “only” is used herein. When a component is expressed in the singular, the singular may be interpreted as plural unless otherwise stated.

[0027] When analyzing components, even if not explicitly described, it is interpreted as including the error range.

[0028] When describing the positional relationship and interconnection between two components, such as "on," "above," "below," "next to," "connected or coupled," "crossing or intersecting," etc., one or more other components may be inserted between these components unless "immediately adjacent" or "directly" is mentioned.

[0029] When a temporal preceding relationship is described as "after", "following", "next", "before", etc., the situation may not be continuous on the timeline unless "immediately following" or "directly" is used.

[0030] To distinguish components, prefixes such as "first," "second," etc., can be used before the component names; however, this ordinal number or component name does not limit its function or structure. For ease of description, the ordinal numbers preceding the names of the same components may differ between embodiments.

[0031] The following embodiments may be partially or completely coupled or combined with each other, and various technologies may be interconnected and driven. The embodiments may be implemented independently of each other or may be implemented together in association.

[0032] In the following, various embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0033] Figure 1 This is a schematic diagram of a display device according to an embodiment of the present invention.

[0034] refer to Figure 1The display device 100 according to an embodiment of the present invention may include a display panel 110 and a display driving circuit for driving the display panel 110. The display driving circuit may include a gate driver 120, a data driver 130, and a timing controller 140. The display device may also include a host system 150 that provides various timing signals to the timing controller 140. In addition, the display device may also include a power supply 160.

[0035] The display panel 110 may include multiple gate lines G1 to Gn and multiple data lines D1 to Dm that are configured to intersect each other and define multiple pixel regions, as well as pixels P disposed in the multiple pixel regions.

[0036] Pixel P can be divided into a red sub-pixel (R) that emits red light, a green sub-pixel (G) that emits green light, and a blue sub-pixel (B) that emits blue light for color implementation, but the invention is not limited thereto. Each of the red, green, and blue sub-pixels (R, G, and B) may include pixel circuitry. In the following text, "pixel" may be interpreted as "sub-pixel".

[0037] As shown in the figure, the gate driver 120 can be disposed on one side of the display panel 110, for example, on the left side. However, in some cases, the gate driver 120 can be disposed on both one side and the other side of the display panel 110, for example, on both the left and right sides. The gate driver 120 may include a plurality of gate driver integrated circuits (ICs) (not shown).

[0038] The gate driver 120 may be in the form of a tape package on which the gate driver IC is mounted, but the present invention is not necessarily limited to this, and the gate driver IC may be directly mounted on the display panel 110.

[0039] The data driver 130 converts the digital image signal sent from the timing controller 140 into an analog data voltage and outputs the analog data voltage to the display panel 110. Specifically, in response to the data control signal DCS sent from the timing controller 140, the data driver 130 outputs the analog data voltage to the data lines D1 to Dm.

[0040] The data driver 130 can be disposed on one side of the display panel 110, for example, on the top side. However, in some cases, the data driver 130 can be disposed on both one side and the other side of the display panel 110, for example, on both the top and bottom sides. Furthermore, the data driver 130 can be in the form of a tape-mount package on which a source driver IC is mounted, but the invention is not necessarily limited to this.

[0041] The timing controller 140 receives various timing control signals from the host system 150, including the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, the data enable (DE) signal, and the clock signal CLK, and generates a data control signal DCS for controlling the data driver 130 and a gate control signal GCS for controlling the gate driver 120.

[0042] Additionally, the timing controller 140 can receive image data from the host system 150, convert the image data into image data in a form that can be processed by the data driver 130, and output the converted image data.

[0043] The data control signal DCS may include the source start pulse SSP, the source sampling clock SSC, and the source output enable signal SOE. The gate control signal GCS may include the gate start pulse GSP, the gate shift clock GSC, and the gate output enable signal GOE.

[0044] The host system 150 can be implemented as any of the following: a navigation system, a set-top box, a digital multifunction optical disc (DVD) player, a Blu-ray player, a personal computer (PC), a home theater system, a broadcast receiver, and a telephone system.

[0045] The host system 150 includes a system-on-chip (SoC) with an embedded scaler and can convert the digital image data (RGB) of the input image into a format suitable for display on the display panel 110. The host system 150 can send the digital image data of the input image and various timing control signals to the timing controller 140.

[0046] Power supply 160 receives the input voltage applied from host system 150 and outputs the voltage required to drive the pixels P of display panel 110 and the display driving circuitry. Power supply 160 can output a constant voltage (or DC voltage) via a DC-DC converter, such as pixel drive voltage EVDD, pixel base voltage EVSS, and reference voltage Vref. For example, the voltages of pixel drive voltage EVDD, pixel base voltage EVSS, and reference voltage Vref can be supplied to pixel P via a power line commonly connected to pixel P.

[0047] The reference voltage Vref includes a first reference voltage Vref1, a second reference voltage Vref2, and a third reference voltage Vref3. The value of the second reference voltage Vref2 can be less than or equal to the value of the first reference voltage Vref1, and the value of the third reference voltage Vref3 can be set to be less than the value of the second reference voltage Vref2.

[0048] Figure 2 This is a schematic diagram of a pixel circuit according to an embodiment of the present invention.

[0049] Reference Figure 2 According to an embodiment of the present invention, each sub-pixel P includes a pixel circuit 10, and the pixel circuit 10 may include a light-emitting element EL, a driving element DT, a first switching element ST1, a second switching element ST2, and a storage capacitor Cst.

[0050] The light-emitting element EL emits light by applying current through the channel of the driving element DT according to the gate-source voltage Vgs of the driving element DT, and the gate-source voltage Vgs varies according to the data voltage Vdata.

[0051] The driving element DT provides current to the light-emitting element EL according to the gate-source voltage Vgs to drive the light-emitting element EL.

[0052] The first switching element ST1 is turned on according to the gate turn-on voltage of the first gate signal G1, and the data voltage Vdata provided from the data driver through the data line DL is applied to the first node n1.

[0053] The second switching element ST2 is turned on according to the gate turn-on voltage of the second gate signal G2, and the reference voltage Vref provided through the sensing line SL is applied to the second node n2.

[0054] The storage capacitor Cst is connected between the first node n1 and the second node n2. The storage capacitor Cst can be charged to drive the gate-source voltage Vgs of the element DT.

[0055] In this embodiment, the electrical characteristics of the pixel circuit 10 can be detected by the sensing line SL, and therefore the detected data can be used to compensate for deviations in the electrical characteristics of the pixel circuit 10. Here, the electrical characteristics of the pixel circuit may include, for example, the threshold voltage of the driving element, the mobility of the driving element, the driving voltage (or threshold voltage) of the light-emitting element, etc.

[0056] Figure 3 This is a diagram illustrating the configuration of a data driver according to an embodiment of the present invention.

[0057] Reference Figure 3 According to an embodiment of the present invention, the data driver 130 may include a control circuit 131, an output circuit 132, and a sensing circuit 133.

[0058] The control circuit 131 can receive image data and control data from the timing controller 140, and send the image data to the output circuit 132 based on the received control data. Here, the control data may include timing control signals and channel mode information, wherein the number of channels used is set according to the size and resolution of the display panel. For example, the channel mode information may include first channel mode information using 240 sensing channels and second channel mode information using 120 sensing channels, but the invention is not limited thereto.

[0059] The control circuit 131 can generate a mode control signal for controlling the switch within the sensing circuit 133 based on the channel mode information, and apply the generated mode control signal to the sensing circuit 133. Here, the mode control signal may include a pair of first mode control signals cmb and second mode control signals cm. In addition to the mode control signal, the control circuit 131 may also provide a switch control signal for controlling the switch within the sensing circuit.

[0060] Output circuit 132 can convert digital image data into analog data voltage and provide the converted analog data voltage to the pixels in display panel 110 via data line DL. Output circuit 132 may include shift registers, latches, level shifters, digital-to-analog (DA) converters, and output buffers, but the invention is not limited thereto.

[0061] The sensing circuit 133 can detect the electrical characteristics of the pixels in the display panel 110 via the sensing line SL, generate sensing data, and provide the generated sensing data to the timing controller 140. The sensing circuit 133 may include sensing channels connected to the sensing line SL, and selectively activate or deactivate some sensing channels.

[0062] Figure 4 and Figure 5 This is a diagram illustrating a sensing circuit according to a first embodiment of the present invention. Figure 6A and Figure 6B It is shown Figure 4 The diagram shows the arrangement of the sampling and holding sections. Figure 7A and Figure 7B This is a diagram showing the activation / deactivation state of the sampling and holding section.

[0063] Reference Figure 4 and Figure 5 The sensing circuit 133 according to the first embodiment of the present invention may include a bias section BI, a first switch SW1, a sampling and holding section S / H, an amplifier AMP, and an AD converter ADC.

[0064] The bias section BI can generate and provide the bias voltage Vbias for driving the amplifier AMP and the AD converter ADC. The bias voltage Vbias can include a first bias voltage Vt as a high potential voltage and a second bias voltage Vb as a low potential voltage.

[0065] A first switch SW1 is connected between each of the multiple sensing lines SL and a first reference voltage line PL1 to which a first reference voltage Vref1 is applied. The first switch SW1 is turned on according to a switch control signal to apply the first reference voltage Vref1 to the sensing line SL.

[0066] In this configuration, the first reference voltage Vref1 can be used to compensate for errors in the sensing data generated by the ADC in the sensing circuit when driven in analog-to-digital conversion (ADC) compensation mode, and to compensate for electrical characteristic deviations of the driving elements in the pixel circuit when driven in panel compensation mode. For example, in ADC compensation mode, the first reference voltage Vref1 supplied to the sensing line is sampled. In panel compensation mode, the source node of the driving element in the pixel circuit is initialized to the first reference voltage Vref1.

[0067] The sampling and holding unit S / H is connected to the sensing line SL for each of the sensing channels SIO(1) to SIO(240), and can sample the voltage supplied through the sensing line SL. In this case, the sampling and holding unit S / H can be divided into multiple sampling and holding units. Figure 6A and 6B As shown, the sampling and holding unit S / H may include a first sampling and holding unit S / H_1 and a second sampling and holding unit S / H_2.

[0068] like Figure 6A As shown, two second sampling and holding units S / H_2 (S / H_2a and S / H_2b) are disposed on both sides of the first sampling and holding unit S / H_1, or as shown in the figure. Figure 6B As shown, the second sampling and holding unit S / H_2 is disposed on one side of the first sampling and holding unit S / H_1, but the present invention is not limited thereto. The second sampling and holding unit S / H_2 can be implemented using at least one sampling and holding circuit. Figure 6A and Figure 6B Examples are shown using all 240 sensing channels or using 120 of the 240 sensing channels, but the invention is not limited thereto.

[0069] The first sampling and holding unit S / H_1 is always activated regardless of the channel mode information. The second sampling and holding unit S / H_2 can be activated or deactivated based on the channel mode information.

[0070] For example, both the first sampling and holding unit S / H_1 and the second sampling and holding unit S / H_2 can be activated based on the first channel mode information. Based on the second channel mode information, the first sampling and holding unit S / H_1 can be activated, and the second sampling and holding unit S / H_2 can be deactivated.

[0071] A pair of first mode control signals cmb and second mode control signals cm, based on channel mode information, can be applied to each of the first sampling and holding unit S / H_1 and the second sampling and holding unit S / H_2.

[0072] The sampling and holding unit S / H may include multiple sampling and holding circuits S / H(1) to S / H(m) connected to the sensing channel. 120 sampling and holding circuits S / H(61) to S / H(180) may be provided in the first sampling and holding unit S / H_1, and 120 sampling and holding circuits S / H(1) to S / H(60) and S / H(181) to S / H(240) may be provided in the second sampling and holding unit S / H_2. Each sampling and holding circuit S / H_m may include a first mode switch SW1a, a second mode switch SW1b, first to sixth sensing switches SW2a to SW2f, a first capacitor C1, and a second capacitor C2.

[0073] The first mode switch SW1a is connected between the sensing channel SIO(m) and the first connection node N1. The second mode switch SW1b is connected between the first connection node N1 and the second reference voltage line PL2. The first mode switch SW1a and the second mode switch SW1b can be turned on or off respectively by a first mode control signal cmb and a second mode control signal cm generated according to the channel mode information. The first mode control signal cmb and the second mode control signal cm can have opposite phases.

[0074] The first mode switch SW1a is turned on by the logic high level of the first mode control signal cmb, and the second mode switch SW1b is turned on by the logic high level of the second mode control signal cm.

[0075] like Figure 7A As shown, a logic-high first mode control signal cmb and a logic-low second mode control signal cm can be applied to the sample-and-hold circuit in the sample-and-hold section activated according to the channel mode information. The first mode switch SW1a can be turned on by the logic-high first mode control signal cmb to connect the sensing channel SIO(m) and the first connection node N1, and the second mode switch SW1b can be turned off by the logic-low second mode control signal cm.

[0076] like Figure 7B As shown, a logic-low first mode control signal cmb and a logic-high second mode control signal cm can be applied to the sample-and-hold circuit in the sample-and-hold section, which is activated according to the channel mode information. The first mode switch SW1a is turned off by the logic-low first mode control signal cmb, and the second mode switch SW1b is turned on by the logic-high second mode control signal cm, so that the first connection node N1 and the second reference voltage line PL2 can be connected.

[0077] The first sensing switch SW2a is connected between the first connection node N1 and the second connection node N2. The second sensing switch SW2b is connected between the second reference voltage line PL2 and the third connection node N3. The third sensing switch SW2c is connected between the second reference voltage line PL2 and the fourth connection node N4. The fourth sensing switch SW2d is connected between the second connection node N2 and the first input terminal + of the amplifier AMP. The fifth sensing switch SW2e is connected between the third connection node N3 and the second input terminal - of the amplifier AMP. The sixth sensing switch SW2f is connected between the fourth connection node N4 and the third reference voltage line PL3, to which the third reference voltage Vref3 is applied. The first capacitor C1 is connected between the second connection node N2 and the fourth connection node N4. The second capacitor C2 is connected between the third connection node N3 and the fourth connection node N4.

[0078] When the first sensing switch SW2a and the second sensing switch SW2b in the sampling and holding circuit are turned on, and the first mode switch SW1a is turned on and the second mode switch SW1b is turned off, the voltage supplied through the sensing line SL connected to the sensing channel is sampled, and thus the sampled first voltage V1 is stored in the first capacitor C1, and the second reference voltage Vref2 supplied through the second reference voltage line PL2 is sampled, and thus the sampled second voltage V2 is stored in the second capacitor C2.

[0079] In this configuration, since a second reference voltage Vref2 is applied to the two terminals of the second capacitor C2, the second voltage V2 becomes 0V. This second voltage V2, along with the first voltage V1, is differentially input to the amplifier AMP and serves as a reference voltage for differential amplification with the first voltage V1. Therefore, to eliminate noise that may occur when generating the second reference voltage Vref2, the same voltage is applied to the two terminals of the second capacitor C2 to generate a 0V voltage in which the noise is canceled out.

[0080] When the fourth sensing switch SW2d and the fifth sensing switch SW2e are turned on, the first voltage V1 stored in the first capacitor C1 is input to the first input terminal + of the amplifier AMP, and the second voltage V2 stored in the second capacitor C2 is input to the second input terminal - of the amplifier AMP.

[0081] The amplifier AMP can amplify and output the voltage sampled from the sample-and-hold section S / H. The amplifier AMP can be implemented as a differential amplifier with two inputs and two outputs. The amplifier AMP can differentially amplify the first voltage V1 and the second voltage V2 input from the sample-and-hold section S / H, and output a first output voltage Vout1 and a second output voltage Vout2.

[0082] The amplifier AMP includes an operational amplifier OP, a first feedback capacitor C1fb and a first feedback switch SW5a connected between a first input terminal (+) and a first output terminal (-) of the operational amplifier OP, a second feedback capacitor C2fb and a second feedback switch SW5b connected between a second input terminal (-) and a second output terminal (+) of the operational amplifier OP, and a first input reset switch S connected between the first input terminal + of the operational amplifier OP and a power supply line to which a first bias voltage Vt is applied. W3a, and a second input reset switch SW3b connected between the second input terminal - of the operational amplifier OP and the power supply line to which the first bias voltage Vt is applied, an output reset switch SW4 connected between the first output terminal - and the second output terminal +, a first feedback reset switch SW6a connected between the connection node of the first feedback capacitor C1fb and the first feedback switch SW5a and the power supply line to which the first bias voltage Vt is applied, and a second feedback reset switch SW6b connected between the connection node of the second feedback capacitor C2fb and the second feedback switch SW5b and the power supply line to which the second bias voltage Vb is applied.

[0083] An analog-to-digital converter (ADC) can convert an amplified voltage from an amplifier (AMP) into digital sensing data. The ADC converts the difference between the first output voltage Vout1 and the second output voltage Vout2 from the amplifier (AMP) into digital sensing data ADC_code.

[0084] Figure 8 and Figure 9 This is a diagram illustrating the driving timing of a sensing circuit according to an embodiment of the present invention, and Figure 10 and Figure 11 It is used to describe Figure 8 The diagram shows the operating principle of the sensing circuit.

[0085] Here, the conduction of the first switch SW1 will be described based on the ADC compensation mode. In the panel compensation mode, only the first switch SW1 is turned off, and the other drive timings can be the same. In addition, the first mode control signals cmb1 and cmb2 are applied to the first mode switch SW1a, the second mode control signals cm1 and cm2 are applied to the second mode switch SW1b, the switch control signal smp is applied to the first sensing switch SW2a and the second sensing switch SW2b, the switch control signal svr2 is applied to the third sensing switch SW2c, the switch control signals ca(1) to ca(240) are applied to the fourth sensing switch SW2d and the fifth sensing switch SW2e, and the switch control signal svr1 is applied to the sixth sensing switch SW2f.

[0086] refer to Figure 8 , 10 and Figure 11 The ADC compensation mode that performs sensing through 240 sensing channels includes a first segment T1 in which sampling is performed and a second segment T2 in which amplification is performed.

[0087] like Figure 8 and Figure 10 As shown, during the first segment T1, the first mode switch SW1a, which includes all the sample and hold circuits in the first and second sample and hold sections, is turned on by the logic high level H of the first mode control signal cmb, and the second mode switch SW1b is turned off by the logic low level L of the second mode control signal cm. After the third sensing switch SW2c is turned on, the first sensing switch SW2a and the second sensing switch SW2b are turned on, and the fourth sensing switches SW2d to the sixth sensing switches SW2f are turned off.

[0088] When the first sensing switch SW2a to the third sensing switch SW2c are turned on, the voltage supplied through the sensing line SL is sampled, and thus the sampled first voltage V1 is stored in the first capacitor C1, and the second reference voltage Vref2 supplied through the second reference voltage line PL2 is sampled, and thus the sampled second voltage V2 is stored in the second capacitor C2.

[0089] In this configuration, a first reference voltage Vref1 is applied to one end of the first capacitor C1, and a second reference voltage Vref2 is applied to the other end. Therefore, the voltage difference between the first reference voltage Vref1 and the second reference voltage Vref2 is stored in the first capacitor C1. Since a momentary overvoltage may occur when the first reference voltage Vref1 and the second reference voltage Vref2 are applied simultaneously across the first capacitor C1, the first reference voltage Vref1 and the second reference voltage Vref2 are applied sequentially. That is, the switch control signal svr2 rises to a logic high level, and after a predetermined time t, the switch control signal smp rises to a logic high level. Similarly, the switch control signal svr2 falls to a logic low level, and after a predetermined time t, the switch control signal smp falls to a logic low level.

[0090] The first sensing switch SW2a and the second sensing switch SW2b are simultaneously turned on in all sensing channels.

[0091] Subsequently, the first sensing switch SW2a to the fifth sensing switch SW2e are turned off, the sixth sensing switch SW2f is turned on, the third reference voltage Vref3 is applied to the connection node of the first capacitor C1 and the second capacitor C2, and thus the level of the first voltage V1 charged in the first capacitor C1 is reduced.

[0092] For example, when Vref1=10V, Vref2=5V, and Vref3=1V, after 10V is applied to one end of the first capacitor and 5V is applied to the other end, and when the voltage at the other end of the first capacitor drops to 1V through the third reference voltage Vref3, the voltage at one end of the first capacitor also drops to 6V.

[0093] The reason is that, since the level of the sampled voltage is high, processing is performed after the voltage level is reduced. Therefore, the first switch SW1, the first mode switch SW1a and the second mode switch SW1b, and the first sensing switches SW2a to the sixth sensing switches SW2f can be implemented as high-voltage (HV) switches, and the first input reset switch SW3a and the second input reset switch SW3b, the output reset switch SW4, the first feedback switch SW5a and the second feedback switch SW5b, and the first feedback reset switch SW6a and the second feedback reset switch SW6b can be implemented as low-voltage (LV) switches.

[0094] In this case, such as Figure 10 As shown, in the amplifier AMP, the first input reset switch SW3a and the second input reset switch SW3b, the output reset switch SW4, the first feedback reset switch SW6a and the second feedback reset switch SW6b are turned on, and the first feedback switch SW5a and the second feedback switch SW5b are turned off. Therefore, the first input terminal + and the second input terminal +, the first output terminal + and the second input terminal -, the first output terminal - and the second output terminal of the operational amplifier OP are initialized by the second bias voltage Vb.

[0095] like Figure 8 and Figure 11 As shown, the first mode switch SW1a, which includes all the sampling and holding circuits in the first and second sampling and holding sections, is turned on by the logic high level H of the first mode control signal cmb, and the second mode switch SW1b is turned off by the logic low level L of the second mode control signal cm. During the second segment T2, in the sampling and holding S / H, the first sensing switches SW2a to the third sensing switches SW2c and the sixth sensing switch SW2f are turned off, and the fourth sensing switch SW2d and the fifth sensing switch SW2e can be turned on sequentially for each sensing channel.

[0096] During the second segment T2, the second a segment T2a and the second b segment T2b of each sensing channel can be repeated. The second a segment T2a can be the segment that amplifies the sampled value, and the second b segment T2b can be the segment that initializes the input and output terminals of the amplifier.

[0097] During the second segment T2a, when the first sensing switch SW2a to the third sensing switch SW2c and the sixth sensing switch SW2f are turned off and the fourth sensing switch SW2d and the fifth sensing switch SW2e are turned on in the sampling and holding S / H, the first voltage V1 stored in the first capacitor C1 is input to the first input terminal + of the amplifier AMP, and the second voltage V2 stored in the second capacitor C2 is input to the second input terminal - of the amplifier AMP.

[0098] In this case, such as Figure 11 As shown, in the amplifier AMP, the first input reset switch SW3a and the second input reset switch SW3b, the output reset switch SW4, and the first feedback reset switch SW6a and the second feedback reset switch SW6b are turned on, while the first feedback switch SW5a and the second feedback switch SW5b are turned off. Therefore, the first voltage V1 and the second voltage V2 are differentially input to the first input terminal + and the second input terminal - of the operational amplifier OP.

[0099] The first output voltage Vout1 is output from the first output terminal - of the operational amplifier OP, and the second output voltage Vout2 is output differentially from the second output terminal +, and thus the first output voltage Vout1 and the second output voltage Vout2 are input to the AD converter ADC.

[0100] During the second b-segment T2b, in the sampling and holding S / H, the first to sixth sensing switches SW2a to SW2f are turned off, the first and second input reset switches SW3a and SW3b, the output reset switch SW4, and the first and second feedback reset switches SW6a and SW6b are turned on, and the first and second feedback switches SW5a and SW5b are turned off. As a result, the first input terminal + and the second input terminal - of the operational amplifier OP are initialized by the second bias voltage Vb, the first output terminal - of the operational amplifier OP is initialized by the first bias voltage Vt, and the second output terminal + of the operational amplifier OP is initialized by the second bias voltage Vb.

[0101] The AD converter receives a first output voltage Vout1 and a second output voltage Vout2 from the differential output of the amplifier AMP, and converts the first output voltage Vout1 and the second output voltage Vout2 into digital sensing data ADC_code.

[0102] refer to Figure 9 , 10 and Figure 11 The ADC compensation mode that performs sensing through 120 sensing channels includes a first segment T1 in which sampling is performed and a second segment T2 in which holding and amplification are performed.

[0103] like Figure 9 and Figure 10 As shown, during the first segment T1, the first mode switch SW1a, which includes the sampling and holding circuit in the first sampling and holding section, is turned on by the logic high level H of the first mode control signal cmb, and the second mode switch SW1b is turned off by the logic low level L of the second mode control signal cm.

[0104] After the third sensing switch SW2c is turned on, the first sensing switch SW2a and the second sensing switch SW2b are turned on, and the fourth sensing switch SW2d to the sixth sensing switch SW2f are turned off.

[0105] When the first sensing switch SW2a to the third sensing switch SW2c are turned on, the voltage supplied through the sensing line SL is sampled, and thus the sampled first voltage V1 is stored in the first capacitor C1, and the second reference voltage Vref2 supplied through the second reference voltage line PL2 is sampled, and thus the sampled second voltage V2 is stored in the second capacitor C2.

[0106] On the other hand, the first mode switch SW1a, which includes the sampling and holding circuit in the second sampling and holding section, is turned off by the logic low level L of the first mode control signal cmb, and the second mode switch SW1b is turned on by the logic high level H of the second mode control signal cm.

[0107] The operation of the sampling and holding circuit included in the first sampling and holding section and Figure 8 and Figure 10 The same as in the first sampling and holding section. However, the only difference is that the sampling and holding operation is performed only during the first sampling and holding section, and the sampling and holding operation is not performed in the second sampling and holding section.

[0108] Subsequently, the first sensing switch SW2a to the fifth sensing switch SW2e are turned off, the sixth sensing switch SW2f is turned on, the third reference voltage Vref3 is applied to the connection node of the first capacitor C1 and the second capacitor C2, and thus the level of the first voltage V1 charged into the first capacitor C1 is reduced.

[0109] In this case, such as Figure 10 As shown, in the amplifier AMP, the first input reset switch SW3a and the second input reset switch SW3b, the output reset switch SW4, the first feedback reset switch SW6a and the second feedback reset switch SW6b are turned on, and the first feedback switch SW5a and the second feedback switch SW5b are turned off. Therefore, the first input terminal + and the second input terminal - of the operational amplifier OP, as well as the first output terminal - and the second output terminal +, are initialized by the second bias voltage Vb.

[0110] like Figure 9 and Figure 11 As shown, during the second segment T2, in the sampling and holding circuit included in the first sampling and holding section, the first sensing switch SW2a, the third sensing switch SW2c, and the sixth sensing switch SW2f are turned off, and the fourth sensing switch SW2d and the fifth sensing switch SW2e are turned on for each sensing channel.

[0111] During the second segment T2, the second a segment T2a and the second b segment T2b of each sensing channel can be repeated. The second a segment T2a can be the segment that amplifies the sampled value, and the second b segment T2b can be the segment that initializes the input and output terminals of the amplifier.

[0112] During the second segment T2a, when the fourth sensing switch SW2d and the fifth sensing switch SW2e are turned on, the first voltage V1 stored in the first capacitor C1 is input to the first input terminal + of the amplifier AMP, and the second voltage V2 stored in the second capacitor C2 is input to the second input terminal - of the amplifier AMP.

[0113] On the other hand, the first sensing switch SW2a, the second sensing switch SW2b, the fourth sensing switch SW2d, and the fifth sensing switch SW2e of the sampling and holding circuit included in the second sampling and holding section are turned off.

[0114] The operation of the sampling and holding circuit included in the first sampling and holding section and Figure 8 and Figure 11 The same as in the first sampling and holding section. However, the only difference is that the sampled voltage is only output in the first sampling and holding section, and sampling is not performed in the second sampling and holding section.

[0115] In this case, such as Figure 11 As shown, in the amplifier AMP, the first input reset switch SW3a and the second input reset switch SW3b, the output reset switch SW4, and the first feedback reset switch SW6a and the second feedback reset switch SW6b are turned on, while the first feedback switch SW5a and the second feedback switch SW5b are turned off. Therefore, the first voltage V1 and the second voltage V2 are differentially input to the first input terminal + and the second input terminal - of the operational amplifier OP.

[0116] The AD converter receives a first output voltage Vout1 and a second output voltage Vout2 from the differential output of the amplifier AMP, and converts the first output voltage Vout1 and the second output voltage Vout2 into digital sensing data ADC_code.

[0117] Figure 12 and Figure 13 This is a diagram illustrating a sensing circuit according to a second embodiment of the present invention.

[0118] Reference Figure 12 and Figure 13 According to the second embodiment of the present invention, the sensing circuit 133 may include a bias section BI, a first switch SW1, a sampling and holding section S / H, an amplifier AMP, and an AD converter ADC.

[0119] The configuration of the sensing circuit according to the second embodiment and according to Figure 4 The configuration of the sensing circuit in the first embodiment is the same, and Figure 13 The configuration of the sampling and holding section shown in the figure is different. Figure 5 Configuration.

[0120] That is, in the second embodiment, such as Figure 13 As shown, the first mode switch SW1a and the second mode switch SW1b are not set in the first sampling and holding unit S / H_1. The first sampling and holding unit S / H_1 is always activated regardless of the channel mode information, while... Figure 5 As shown, the first mode switch SW1a and the second mode switch SW1b are only set in the second sampling and holding sections S / H_2a and S / H_2b. The second sampling and holding sections S / H_2a and S / H_2b are selectively activated or deactivated according to the channel mode information.

[0121] The first sampling and holding component S / H_1 includes multiple sampling and holding circuits, which may include a first sensing switch SW2a to a sixth sensing switch SW2f, a first capacitor C1, and a second capacitor C2.

[0122] The first sensing switch SW2a is connected between the sensing channel SIO and the first connection node N1. The second sensing switch SW2b is connected between the second reference voltage line PL2 and the second connection node N2. The third sensing switch SW2c is connected between the second reference voltage line PL2 and the third connection node N3. The fourth sensing switch SW2d is connected between the first connection node N1 and the first input terminal + of the amplifier AMP. The fifth sensing switch SW2e is connected between the second connection node N2 and the second input terminal - of the amplifier AMP. The sixth sensing switch SW2f is connected between the third connection node N3 and the third reference voltage line PL3.

[0123] The first capacitor C1 is connected between the first connection node N1 and the third connection node N3. The second capacitor C2 is connected between the second connection node N2 and the third connection node N3.

[0124] The second sampling and holding section S / H_2 includes multiple sampling and holding circuits, which have the same characteristics as... Figure 5The sampling and holding circuit shown in the first embodiment has the same configuration and function.

[0125] Therefore, in the second embodiment, since it is not necessary to... Figure 12 As shown, the first mode control signal cmb and the second mode control signal cm are applied to the first sampling and holding section S / H_1. Therefore, the first mode control signal cmb and the second mode control signal cm are not applied to the first sampling and holding section S / H_1, and are only applied to the second sampling and holding sections S / H_2a and S / H_2b.

[0126] Figure 14 and Figure 15 This is a graph showing the offset values ​​of the sampling and holding sections based on the channel.

[0127] refer to Figure 14 and Figure 15 It can be confirmed that when ADC compensation and panel compensation are performed according to the embodiment, all offset values ​​of the sampling and holding unit using 240 sensing channels and the offset values ​​of the sampling and holding unit using 120 sensing channels remain constant.

[0128] Therefore, since the sampling and holding unit according to the embodiment can maintain a constant offset value, constant sensing characteristics can be obtained, and uniform compensation performance between channel modes can be ensured.

[0129] According to the present invention, the form of selectively activating or deactivating some of the sampling and holding parts in the sensing circuit can be adapted to display panels of various sizes or resolutions, depending on the number of sensing lines, and accurate sensing data can be obtained even when only some sensing lines are connected.

[0130] According to the present invention, the compensation performance of the sensing circuit can be improved by simply adding a switch while minimizing the circuit configuration, thereby minimizing the design area and manufacturing cost of the circuit configuration.

[0131] According to the present invention, uniform compensation performance can be achieved between an ADC compensation mode for compensating for errors in the sensing circuit and a panel compensation mode for compensating for deviations in the electrical characteristics of pixels.

[0132] It should be noted that the effects of the present invention are not limited to those described above, and other effects of the present invention will be apparent to those skilled in the art based on the appended claims.

[0133] Although embodiments have been described in more detail with reference to the accompanying drawings, the invention is not necessarily limited to these embodiments, and various modifications can be made without departing from the spirit of the invention. Therefore, the embodiments disclosed herein should not be considered as limiting the meaning of the technical concept of the invention, but rather as illustrative, and the scope of the technical concept of the invention is not limited to these embodiments. Thus, it should be understood that the above embodiments are not restrictive, but illustrative in all respects.

Claims

1. A sensing circuit, comprising: A first switch is connected between a first reference voltage line to which a first reference voltage is applied and each of the plurality of sensing lines. The sampling and holding unit includes a first sampling and holding unit configured to sample voltages supplied through a sensing line connected to each of a plurality of first sensing channels, and a second sampling and holding unit configured to sample voltages supplied through a sensing line connected to at least one second sensing channel. An amplifier configured to receive and amplify the sampled voltage from the sampling and holding unit; as well as An analog-to-digital (AD) converter, configured to convert amplified voltage into digital data and generate sensed data, The second sampling and holding unit is selectively activated according to the mode control signal.

2. The sensing circuit of claim 1, wherein the sampling and holding unit sends a first voltage sampled from a voltage supplied through the sensing line and a second voltage sampled from a second reference voltage applied through a second reference voltage line to the amplifier.

3. The sensing circuit according to claim 2, wherein: The sampling and holding unit includes multiple sampling and holding circuits connected to the sensing channel; and Each of the plurality of sample-and-hold circuits includes: A first mode switch is connected between the sensing channel and the first connection node; A second mode switch is connected between the first connection node and the second reference voltage line; A first sensing switch is connected between the first connection node and the second connection node; A second sensing switch is connected between the second reference voltage line and the third connection node; A third sensing switch is connected between the second reference voltage line and the fourth connection node; A fourth sensing switch is connected between the second connection node and the first input terminal of the amplifier; A fifth sensing switch is connected between the third connection node and the second input terminal of the amplifier; A first capacitor is connected between the second connection node and the fourth connection node; and The second capacitor is connected between the third connection node and the fourth connection node.

4. The sensing circuit of claim 3, further comprising a sixth sensing switch connected between the fourth connection node and the third reference voltage line, wherein the third reference voltage is applied to the third reference voltage line. The third reference voltage is set to a value less than that of the second reference voltage.

5. The sensing circuit of claim 3, wherein each of the plurality of sample and hold circuits is activated when the first mode switch is on and the second mode switch is off, and each of the plurality of sample and hold circuits is deactivated when the first mode switch is off and the second mode switch is on.

6. The sensing circuit of claim 3, wherein when the first mode switch and the first to third sensing switches are turned on and the second mode switch and the fourth to sixth sensing switches are turned off, each of the plurality of sample and hold circuits stores the first voltage in the first capacitor and stores the second voltage in the second capacitor, and when the first mode switch and the fourth and fifth sensing switches are turned on and the second mode switch and the first to third sensing switches and the sixth sensing switch are turned off, the first voltage is input to the first input terminal and the second voltage is input to the second input terminal.

7. The sensing circuit according to claim 2, wherein: The first sampling and holding unit includes a plurality of first sampling and holding circuits connected to the sensing channel; and Each of the plurality of first sample-and-hold circuits includes: A first sensing switch is connected between the sensing channel and the first connection node; A second sensing switch is connected between the second reference voltage line and the second connection node; A third sensing switch is connected between the second reference voltage line and the third connection node; A fourth sensing switch is connected between the first connection node and the first input terminal of the amplifier; A fifth sensing switch is connected between the second connection node and the second input terminal of the amplifier; A first capacitor is connected between the first connection node and the third connection node; and A second capacitor is connected between the second connection node and the third connection node.

8. The sensing circuit according to claim 2, wherein: The second sampling and holding section includes a second sampling and holding circuit connected to the sensing channel; and The second sample and hold circuit includes: A first mode switch is connected between the sensing channel and the first connection node; A second mode switch is connected between the first connection node and the second reference voltage line; A first sensing switch is connected between the first connection node and the second connection node; A second sensing switch is connected between the second reference voltage line and the third connection node; A third sensing switch is connected between the second reference voltage line and the fourth connection node; A fourth sensing switch is connected between the second connection node and the first input terminal of the amplifier; A fifth sensing switch is connected between the third connection node and the second input terminal of the amplifier; A first capacitor is connected between the second connection node and the fourth connection node; and The second capacitor is connected between the third connection node and the fourth connection node.

9. A display device, comprising: The display panel contains pixels located in areas where multiple gate lines intersect with multiple data lines; A gate driver configured to output a gate signal through the gate line; A data driver configured to output a data voltage via the data line; as well as A timing controller configured to control the gate driver and the data driver. The data driver includes a sensing circuit configured to detect the electrical characteristics of the pixel and generate sensing data. The sensing circuit includes: A first switch is connected between a first reference voltage line to which a first reference voltage is applied and each of the plurality of sensing lines. The sampling and holding unit includes a first sampling and holding unit configured to sample voltages supplied through a sensing line connected to each of a plurality of first sensing channels, and a second sampling and holding unit configured to sample voltages supplied through a sensing line connected to at least one second sensing channel. An amplifier configured to receive and amplify the sampled voltage from the sampling and holding unit; and An analog-to-digital (AD) converter, configured to convert amplified voltage into digital data and generate sensed data, The second sampling and holding unit is selectively activated according to the mode control signal.

10. The display device of claim 9, wherein the data driver further includes control circuitry configured to generate the mode control signal using control data received from the timing controller, and to apply the mode control signal to the sensing circuitry.

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