A voltage domain control circuit for an adaptive compensation curved screen
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-04-01
- Publication Date
- 2026-08-14
AI Technical Summary
但由于现有稳压电路的控制逻辑，是根据已知负载供电需求来设定参数的，而FPCB在实际生产中可能应用于不同屏幕产品与不同弯曲角度，其具体工况无法预先准确判定，因此在设计时往往需选用耐受性较高的元件，以覆盖可能出现的电气波动
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Figure CN122575249A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of voltage control technology, and more specifically, to a voltage domain control circuit for an adaptively compensated curved screen. Background Technology
[0002] In the implementation of curved screens, flexible printed circuit boards (FPCBs) are crucial components for conforming to the screen's curvature due to their "bendable" nature. However, when an FPCB is bent and fixed to the curvature of a curved screen, the characteristic impedance of its internal copper traces changes due to physical deformation. To address this effect, a voltage regulator is typically used to provide stable voltage input to the chip across different voltage domains. However, since the control logic of existing voltage regulator circuits sets parameters based on known load power requirements, and FPCBs may be used in different screen products with varying bending angles in actual production, their specific operating conditions cannot be accurately determined in advance. Therefore, components with high tolerance are often selected during the design phase to cover potential electrical fluctuations.
[0003] by Figure 1 The diagram shows a conventional series voltage regulator circuit. It uses transistor Q1 as the regulating transistor and Zener diode Z12 as the reference voltage. When the input voltage V_i or load changes cause an increase in the output voltage V_o, the emitter of Q1 is clamped at the fixed reference voltage by Zener diode Z12. This reduces the base-emitter voltage V_be of Q1, weakening its conduction and increasing its collector-emitter voltage drop, thus forcing V_o to decrease. Conversely, if V_o tends to decrease, the reverse adjustment process restores its stability, maintaining a stable output voltage V_o. This voltage regulation logic relies on the difference between the reference voltage of the Zener diode and the actual output voltage for closed-loop control. This presents a problem: under regulated conditions, when a specific impedance change caused by PCB bending is applied to the subsequent circuits and components, their own impedance plus the specific impedance change of the line will directly cause their input current to change with the characteristic impedance. This is the main reason for insufficient load capacity or even breakdown. Therefore, the configuration and selection of the subsequent circuits need to meet the requirement of being able to withstand the additional current surge range and have the ability to maintain the normal operation of the subsequent circuits under low current conditions. Summary of the Invention
[0004] In view of this, this application provides a voltage domain control circuit for an adaptive compensation curved screen, which restores the load input current to the design value through positive or reverse compensation after the characteristic impedance changes and the total load resistance changes.
[0005] In a first aspect, this application proposes a control scheme comprising resistors R1, R2, and R3, transistors Q1, Q2, and Q3, operational amplifiers U1, U2, and U3. The non-inverting input of operational amplifier U1 receives an output voltage reference signal VREF1, its inverting input is connected to one end of resistor R1, and its output terminal is connected to the base of transistor Q1. The collector of transistor Q1 is connected to VDD, and its emitter is connected to the other end of resistor R1, one end of resistor R3, and one end of the collector of transistor Q2. The base of transistor Q2 is connected to the output terminal of operational amplifier U2, and its emitter is connected to the inverting input of operational amplifier U2, one end of resistor R2, and the non-inverting input of operational amplifier U3. The inverting input of operational amplifier U3 is connected to the non-inverting input of operational amplifier U2 and receives the forward and reverse compensation signal VREF2; its output terminal is connected to the base of transistor Q3. The collector of transistor Q3 is connected to the inverting input of operational amplifier U2 and the other end of resistor R3. The other end of resistor R2, the emitter of transistor Q3, and ground are connected. In this design, VREF1 serves as the output voltage reference signal, used to adjust the regulated voltage of the load power supply; VREF2 is the forward and reverse compensation control signal; and resistor R3 represents the impedance of the load itself, such as chips and components. When using the circuit, the impedance of resistor R3 is calculated based on Ohm's law to determine the required resistance value for the design current, and then subtracted from the maximum value of the desired preset characteristic impedance range. The circuit automatically divides the forward and reverse compensation control intervals based on the preset impedance range. The larger the preset impedance range, the larger the control interval of the circuit, and the larger the adjustable step voltage corresponding to each voltage step of VREF2. Conversely, the smaller the preset impedance range, the smaller the control interval of the circuit, and the smaller the step interval corresponding to each voltage step of VREF2, resulting in higher control precision. This range can be set according to the actual target current. Assuming the current supply voltage U of resistor R3 is 3V, the design current i is 200mA, and the desired maximum characteristic impedance variation range X is 5 ohms, then after reducing resistor R3 from 15 ohms to 10 ohms, the circuit will generate a corresponding control region approaching 300mA (U / resistor R3 - transistor Q3 loss) based on the 5-ohm reduction. The 200mA control point corresponding to the design current of resistor R3 within this control region corresponds to the excess portion of the supply current minus the design current under the set resistance value of resistor R3, converted into voltage according to the current resistance value of resistor R3. When the voltage at the center point is lowered, the input current of resistor R3 will automatically increase, and vice versa. According to the design current requirement, the current VREF2 step voltage is 10mA for every 0.1V. When the characteristic impedance changes and causes the total resistance of resistor R3 to change, its input current deviates from this design value. Depending on the direction of deviation, if it is positive, the VREF2 signal is adjusted upward, and if it is negative, the VREF2 signal is adjusted downward. The circuit will make the input current of resistor R3 return to the design current. This solution can solve the problem of device breakdown or load caused by the change of characteristic impedance and reduce the requirements for component selection. The circuit operates as follows: First, VREF1 serves as the output voltage setting reference, input to the non-inverting input of operational amplifier U1, providing a reference signal for the power supply required by resistor R3. Upon receiving this signal, operational amplifier U1 outputs a drive signal from its output terminal to the base of transistor Q1, causing transistor Q1 to turn on. At this time, the power supply voltage VDD provides the operating voltage to the load resistor R3 through the collector-emitter path of transistor Q1. The output voltage is fed to the inverting input of operational amplifier U1 via a feedback network formed by resistor R1. Operational amplifier U1 continuously monitors the actual output voltage at the emitter of transistor Q1 and compares it with the reference value VREF1 to stabilize the voltage VDD finally applied to the load circuit at the VREF1 value. Subsequently, the supply voltage clamped to the VREF1 value is input to the inverting input of operational amplifier U2 and the non-inverting input of operational amplifier U3 through resistor R3. The VREF2 signal is input to the inverting input of operational amplifier U3 and the non-inverting input of operational amplifier U2. After comparison, operational amplifier U3 outputs a control signal to the base of transistor Q3 to control transistor Q3 to conduct. The series circuit formed by resistor R3 and transistor Q3 forms a current path, allowing resistor R3 to obtain the input current corresponding to its own impedance. The current loop is VDD, transistor Q1, resistor R3, transistor Q3, and ground. At the same time, operational amplifier U2 compares the voltages at both ends and outputs a control signal to the base of transistor Q2, driving transistor Q2 to conduct. After transistor Q2 turns on, the current portion in the original VDD, transistor Q1, resistor R3, transistor Q3, and ground loop is converted to a VDD, transistor Q1, transistor Q2, resistor R2, and ground loop, until the input current corresponding to the resistance value of resistor R3 is converted to the design current. When the characteristic impedance changes, causing the total impedance of resistor R3 to increase and the input current to be lower than the design value, the set voltage of VREF2 is lowered. After operational amplifier U2 detects the decrease in voltage at the non-inverting input, its output signal causes transistor Q2 to gradually turn off, reducing the current in the VDD, transistor Q1, Q2, and resistor R2 loop. At the same time, operational amplifier U3 outputs a drive signal to deepen the conduction of transistor Q3, increasing the current in the VDD, transistor Q1, resistor R3, and ground loop. Q3 and ground loop current decrease as compensation resistor R3 current decreases. When the current in resistor R3 is detected to have returned to the design value, operational amplifier U3 controls transistor Q3 to turn off, restoring the VDD, transistor Q1, transistor Q2, resistor R2, and ground loop controlled by operational amplifier U2. Conversely, if a change in characteristic impedance causes a decrease in total impedance and the load current exceeds the design value, VREF2 voltage is increased. Operational amplifier U2 increases the conduction level of transistor Q2 based on the raised reference signal, increasing the VDD, transistor Q1, transistor Q2, resistor R2, and ground loop current. The corresponding currents in the VDD, transistor Q1, resistor R3, and transistor Q3 loops will gradually decrease until they return to the design current.
[0006] Optionally, connector P1 is also included. The resistor R3, which is connected in series between the emitter of transistor Q1 and the collector of transistor Q3, is replaced by connector P1. Pin 2 of connector P1 is connected to the emitter of transistor Q1, pin 1 is connected to the collector of transistor Q3, and pins 4 and 3 are connected to the two ends of resistor R3 respectively. The resistor R3 can also be connected through connector P1, or a contact method can be used to reserve a connection position for resistor R3.
[0007] Optionally, VREF1 can be independently input by a voltage regulation circuit; in addition to being provided by the upper-level circuit, the input of VREF1 can also be adjusted by a separate voltage regulation circuit.
[0008] Optionally, a current sampling IC is also included, which is used to sample the current of resistor R3. The deviation of VREF2 can be detected and judged by the upper-level circuit. Depending on the pin occupancy of the upper-level circuit processor, the current sampling IC and the comparison circuit can be integrated into this circuit. After monitoring the current of resistor R3 by the IC, the comparison is made and then fed back to the upper-level circuit, reducing pin occupancy.
[0009] Optionally, transistors Q1, Q2, and Q3 are NPN transistors.
[0010] Secondly, based on the above-mentioned scheme, this application provides a control point control scheme that can automatically generate the corresponding control zone design current across voltage ranges. This scheme further includes an operational amplifier U4, resistors R4, R5, R6, R7, R8, R9, R10, and R11. One end of resistor R7 receives the VREF1 signal, and the other end is connected to one end of resistor R4, one end of resistor R5, and one end of resistor R6. The other end of resistor R5 is connected to the other end of resistor R6 and the non-inverting input of operational amplifier U4. The inverting input of operational amplifier U4 is connected to one end of resistor R9 and one end of resistor R8, and the output terminal is connected to the other end of resistor R9 and one end of resistor R10. The other end of resistor R10 is connected to one end of resistor R11 and the inverting input of operational amplifier U3. The other ends of resistors R4, R11, and R8 are connected to the ground terminal.
[0011] Unlike the above scheme, this scheme converts the VREF2 signal into a resistor R11 for supply and regulation. After the design current and the desired maximum range of characteristic impedance are calculated for the load resistor R3, when switching to other voltages, the circuit can synchronize the VREF2 control point of the actual current required by resistor R3 under the current voltage. This scheme can perform safe testing of the load at lower voltages. First, the input signal of VREF1 is sampled proportionally by resistors R7 and R4. The ratio is based on the ratio of the required resistance value of resistor R3 to the preset maximum range value. Assuming the final load is 5V and the test is conducted under 3V power supply, for ease of calculation, we assume that the current test current of resistor R3 is still 200mA, and its corresponding impedance is 15 ohms. The maximum impedance value of the preset range is 5 ohms. Therefore, the ratio of resistors R7 and R4 is set to 3:1. When finally applied to 5V, the actual current required is approximately 333mA, and the control area will refresh its range according to the required current of 333mA. The circuit works by sampling the signal proportionally through resistors R7 and R4, and then passing the voltage at this ratio through resistors R5 and R6. The signal is fed into the non-inverting input of operational amplifier U4. The output of operational amplifier U4 is fed back to the inverting input of operational amplifier U4 after passing through the grounding loop of resistors R9 and R8. Operational amplifier U4 superimposes the input voltages of resistors R5 and R6, and then passes through the grounding loop of resistors R10 and R11. Resistors R10 and R11 form a control point voltage divider signal based on the design current in the corresponding control zone under the current VREF1 voltage (the control point in the control zone corresponds to the 200mA test current of resistor R3). The control point voltage divider signal is input to the non-inverting input of operational amplifier U2 and the inverting input of operational amplifier U3. By adjusting resistor R11, the range of the control zone is tested through the control flow of the above scheme. The value of VREF1 is changed in real time when it is put into operation.
[0012] Optionally, resistor R11 is an adjustable resistor. Attached Figure Description
[0013] Figure 1 The schematic diagram of an existing voltage regulator circuit provided for this invention.
[0014] Figure 2 and Figure 3 The schematic diagram of the voltage domain control circuit provided by the present invention.
[0015] Figure 4 Another voltage domain control circuit schematic provided by the present invention. Detailed Implementation
[0016] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0017] The following disclosure provides numerous different embodiments or examples for implementing various structures of the invention. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the scope of the invention. Furthermore, reference numerals and / or letters may be repeated in different examples. Such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed.
[0018] like Figure 2 As shown, the purpose of this scheme is to restore the load input current to the design value through forward or reverse compensation after the change in characteristic impedance causes a change in the total load resistance. In this scheme, VREF1 serves as the output voltage reference signal, used to adjust the load power supply voltage regulation value; VREF2 is the forward and reverse compensation control signal; resistor R3 represents the impedance of the load itself, such as chips and components. When using the circuit, the impedance value of resistor R3 is calculated according to Ohm's law to obtain the required resistance value for the design current, and then subtracted from the maximum value of the desired preset characteristic impedance value change range. The circuit will automatically divide the control interval for forward and reverse compensation based on the preset impedance range. The larger the preset impedance range value, the larger the control interval range of the circuit, and the larger the adjustable step voltage corresponding to each voltage step of VREF2. Conversely, the smaller the preset impedance range value, the smaller the control interval range of the circuit, and the smaller the step interval corresponding to each voltage step of VREF2, resulting in higher control accuracy. This range can be set according to the actual target current. Assuming the current supply voltage U of resistor R3 is 3V, the design current i is 200mA, and the desired maximum characteristic impedance variation range X is 5 ohms, then after reducing resistor R3 from 15 ohms to 10 ohms, the circuit will generate a corresponding control region approaching 300mA (U / resistor R3 - transistor Q3 loss) based on the 5-ohm reduction. The 200mA control point corresponding to the design current of resistor R3 within this control region corresponds to the excess portion of the supply current minus the design current under the set resistance value of resistor R3, converted into voltage according to the current resistance value of resistor R3. When the voltage at the center point is lowered, the input current of resistor R3 will automatically increase, and vice versa. According to the design current requirement, the current VREF2 step voltage is 10mA for every 0.1V. When the characteristic impedance changes and causes the total resistance of resistor R3 to change, its input current deviates from this design value. Depending on the direction of deviation, if it is positive, the VREF2 signal is adjusted upward, and if it is negative, the VREF2 signal is adjusted downward. The circuit will make the input current of resistor R3 return to the design current. This solution can solve the problem of device breakdown or load caused by the change of characteristic impedance and reduce the requirements for component selection. The circuit operates as follows: First, VREF1 serves as the output voltage setting reference, input to the non-inverting input of operational amplifier U1, providing a reference signal for the power supply required by resistor R3. Upon receiving this signal, operational amplifier U1 outputs a drive signal from its output terminal to the base of transistor Q1, causing transistor Q1 to turn on. At this time, the power supply voltage VDD provides the operating voltage to the load resistor R3 through the collector-emitter path of transistor Q1. The output voltage is fed to the inverting input of operational amplifier U1 via a feedback network formed by resistor R1. Operational amplifier U1 continuously monitors the actual output voltage at the emitter of transistor Q1 and compares it with the reference value VREF1 to stabilize the voltage VDD finally applied to the load circuit at the VREF1 value. Subsequently, the supply voltage clamped to the VREF1 value is input to the inverting input of operational amplifier U2 and the non-inverting input of operational amplifier U3 through resistor R3. The VREF2 signal is input to the inverting input of operational amplifier U3 and the non-inverting input of operational amplifier U2. After comparison, operational amplifier U3 outputs a control signal to the base of transistor Q3 to control transistor Q3 to conduct. The series circuit formed by resistor R3 and transistor Q3 forms a current path, allowing resistor R3 to obtain the input current corresponding to its own impedance. The current loop is VDD, transistor Q1, resistor R3, transistor Q3, and ground. At the same time, operational amplifier U2 compares the voltages at both ends and outputs a control signal to the base of transistor Q2, driving transistor Q2 to conduct. After transistor Q2 turns on, the current portion in the original VDD, transistor Q1, resistor R3, transistor Q3, and ground loop is converted to a VDD, transistor Q1, transistor Q2, resistor R2, and ground loop, until the input current corresponding to the resistance value of resistor R3 is converted to the design current. When the characteristic impedance changes, causing the total impedance of resistor R3 to increase and the input current to be lower than the design value, the set voltage of VREF2 is lowered. After operational amplifier U2 detects the decrease in voltage at the non-inverting input, its output signal causes transistor Q2 to gradually turn off, reducing the current in the VDD, transistor Q1, Q2, and resistor R2 loop. At the same time, operational amplifier U3 outputs a drive signal to deepen the conduction of transistor Q3, increasing the current in the VDD, transistor Q1, resistor R3, and ground loop. Q3 and ground loop current decrease as compensation resistor R3 current decreases. When the current in resistor R3 is detected to have returned to the design value, operational amplifier U3 controls transistor Q3 to turn off, restoring the VDD, transistor Q1, transistor Q2, resistor R2, and ground loop controlled by operational amplifier U2. Conversely, if a change in characteristic impedance causes a decrease in total impedance and the load current exceeds the design value, VREF2 voltage is increased. Operational amplifier U2 increases the conduction level of transistor Q2 based on the raised reference signal, increasing the VDD, transistor Q1, transistor Q2, resistor R2, and ground loop current. The corresponding currents in the VDD, transistor Q1, resistor R3, and transistor Q3 loops will gradually decrease until they return to the design current.
[0019] See Figure 3 and Figure 4 In one embodiment, based on the above scheme, a control point control scheme that can automatically generate the corresponding control zone design current across voltages is provided. Unlike the above scheme, this scheme converts the VREF2 signal into a resistor R11 for supply and adjustment. After the design current and the desired preset maximum range of characteristic impedance are calculated for the resistor R3 load, when switching to other voltages, the circuit can synchronize the VREF2 control point of the actual required current of the resistor R3 under the current voltage. This scheme can perform safety testing on the load at lower voltages. First, the input signal of VREF1 is sampled proportionally by resistors R7 and R4. The ratio is based on the ratio of the required resistance value of resistor R3 to the preset maximum range value. Assuming the final load is 5V and the test is conducted under 3V power supply, for ease of calculation, let's assume the current test current of resistor R3 is still 200mA, corresponding to an impedance of 15 ohms. The maximum impedance in the preset range is 5 ohms. Therefore, the ratio of resistors R7 and R4 is set to 3:1. When finally applied to 5V, the actual required current is approximately 333mA, and the control area will refresh its range based on this required current. The circuit works by sampling the signal through resistors R7 and R4, and then sending the voltage at this ratio through resistors R5 and R6... The input voltage is fed into the non-inverting input of operational amplifier U4. The output of operational amplifier U4, after passing through resistors R9 and R8 and grounding, is fed back to the inverting input of operational amplifier U4. Operational amplifier U4 superimposes the input voltages of resistors R5 and R6, and then, through resistors R10 and R11 and grounding, resistors R10 and R11 form a voltage divider signal based on the design current in the corresponding control zone under the current VREF1 voltage (the control point in the control zone corresponds to the 200mA test current of resistor R3). This control point voltage divider signal is input to the non-inverting input of operational amplifier U2 and the inverting input of operational amplifier U3. By adjusting resistor R11, the range of the control zone is tested through the control flow described above. The value of VREF1 is changed continuously during operation. (Reference) Figure 4 Resistor R3 can also be connected via connector P1, or a contact connection can be reserved for resistor R3. In addition to being provided by the upper-level circuit, the input of VREF1 can also be adjusted by a separate voltage regulation circuit. The deviation of VREF2 can be detected and judged by the upper-level circuit. Depending on the pin occupancy of the upper-level circuit processor, the current sampling IC and the comparison circuit can be integrated into this circuit. After the IC monitors the current of resistor R3, it is compared and fed back to the upper-level circuit, reducing pin occupancy.
Claims
1. A voltage domain control circuit for an adaptively compensated curved screen, characterized in that, The system includes resistors R1, R2, and R3; transistors Q1, Q2, and Q3; operational amplifiers U1, U2, and U3. Operational amplifier U1 receives the output voltage reference signal VREF1 at its non-inverting input; its inverting input is connected to one end of resistor R1; and its output is connected to the base of transistor Q1. The collector of transistor Q1 is connected to VDD; its emitter is connected to the other end of resistor R1, one end of resistor R3, and one end of the collector of transistor Q2. The base of transistor Q2 is connected to the output of operational amplifier U2; its emitter is connected to the inverting input of operational amplifier U2, one end of resistor R2, and the non-inverting input of operational amplifier U3. Operational amplifier U3's inverting input is connected to the non-inverting input of operational amplifier U2 and receives the forward and reverse compensation signal VREF2; its output is connected to the base of transistor Q3; the collector of transistor Q3 is connected to the inverting input of operational amplifier U2 and the other end of resistor R3; and the other end of resistor R2, the emitter of transistor Q3, and ground.
2. The voltage domain control circuit for the adaptive compensation curved screen according to claim 1, characterized in that, It also includes operational amplifier U4, resistors R4, R5, R6, R7, R8, R9, R10, and R11. One end of resistor R7 receives the VREF1 signal, and the other end is connected to one end of resistor R4, one end of resistor R5, and one end of resistor R6. The other end of resistor R5 is connected to the other end of resistor R6 and the non-inverting input of operational amplifier U4. The inverting input of operational amplifier U4 is connected to one end of resistor R9 and one end of resistor R8, and the output terminal is connected to the other end of resistor R9 and one end of resistor R10. The other end of resistor R10 is connected to one end of resistor R11 and the inverting input of operational amplifier U3. The other ends of resistors R4, R11, and R8 are connected to ground.
3. The voltage domain control circuit for the adaptive compensation curved screen according to claim 1, characterized in that, It also includes connector P1, in which the resistor R3 connected in series between the emitter of transistor Q1 and the collector of transistor Q3 is replaced by connector P1. Pin 2 of connector P1 is connected to the emitter of transistor Q1, pin 1 is connected to the collector of transistor Q3, and pins 4 and 3 are connected to the two ends of resistor R3 respectively.
4. The voltage domain control circuit for the adaptive compensation curved screen according to claim 1, characterized in that, The transistors Q1, Q2, and Q3 are NPN type transistors.
5. The voltage domain control circuit for the adaptive compensation curved screen according to claim 2, characterized in that, The resistor R11 is an adjustable resistor.
6. The voltage domain control circuit for the adaptive compensation curved screen according to claim 1, characterized in that, VREF1 can be independently input by a voltage regulation circuit.
7. The voltage domain control circuit for the adaptive compensation curved screen according to claim 1, characterized in that, It also includes a current sampling IC, which is used to sample the current of resistor R3.