Screen testing methods and systems

Abstract

This application provides a screen testing method and system. The method includes: a master control unit issuing a delay calibration command; in response to the delay calibration command, multiple slave control units acquiring their respective channel transmission time values ​​and uploading them to the master control unit; the master control unit generating and sending, based on the channel transmission time values ​​of all slave control units, first delay configuration parameters corresponding to each slave control unit and second delay configuration parameters corresponding to each signal conversion chip; after the delay configuration is completed, the master control unit issuing a synchronization trigger signal and an image data signal to each slave control unit; in response to the synchronization trigger signal, each slave control unit converting the image data signal into an image test signal, and after delay compensation according to the corresponding first delay configuration parameters, synchronously outputting the image test signal; each signal conversion chip converting the image test signal into a screen driving signal, and after delay compensation according to the corresponding second delay configuration parameters, outputting it to the corresponding screen under test.

Description

Technical Field

[0001] This application relates to the field of screen testing technology, and in particular to a screen testing method and system. Background Technology

[0002] In mass production testing of screens, production lines typically deploy multiple testing stations, each independently testing the screen under test. During testing, the testing equipment at the testing station sends test commands to the screen, causing it to switch to test images such as solid color, grayscale, or gradient. Once the image stabilizes, the camera is triggered to capture the image, which is then analyzed to detect defects such as dead pixels, color differences, and uneven brightness.

[0003] In related technologies, in multi-screen parallel testing scenarios, a central control unit can centrally issue test commands to each test station. However, the signal link between the central control unit and each screen under test is affected by factors such as individual device differences and physical trace lengths. After the central control unit issues a unified test command, the actual start times of screen switching for each screen vary, and the completion times also differ. When camera acquisition is triggered uniformly, if the acquisition time falls within the dispersed intervals of the screen switching time windows, some screens may not have completed switching, resulting in the acquisition of transitional or abnormal images, leading to an increased false positive rate. Summary of the Invention

[0004] In view of this, the present application provides a screen testing method and system to solve at least one problem existing in the background art.

[0005] According to a first aspect of the embodiments of this application, a screen testing method is provided, applied to a screen testing system; the screen testing system includes a main control unit, a plurality of slave control units, and a signal conversion chip correspondingly connected to each slave control unit; the method includes: The main control unit issues a delay calibration command; In response to the delay calibration command, multiple slave control units acquire their respective channel transmission time values ​​and upload them to the master control unit; The master control unit generates and sends a first delay configuration parameter corresponding to each slave control unit and a second delay configuration parameter corresponding to each signal conversion chip, based on the channel transmission time values ​​of all slave control units. After the delay configuration is completed, the master control unit sends a synchronization trigger signal and an image data signal to each of the slave control units; In response to the synchronization trigger signal, each of the slave control units converts the image data signal into an image test signal, performs delay compensation according to the corresponding first delay configuration parameter, and then synchronously outputs the image test signal. When each signal conversion chip receives the image test signal, it converts the image test signal into a screen driving signal, performs delay compensation according to the corresponding second delay configuration parameters, and then outputs the screen driving signal to the corresponding screen under test.

[0006] In conjunction with the first aspect, in one embodiment, in response to the delay calibration command, multiple slave control units acquire their respective channel transmission time values, including: In response to the delay calibration command, the nth slave control unit acquires a first transmission time value from the master control unit to the nth slave control unit, and a second transmission time value from the nth slave control unit to the corresponding signal conversion chip; wherein, n is a positive integer less than or equal to the total number of slave control units; The total transmission time value is obtained based on the first transmission time value and the second transmission time value, and is used as the channel transmission time value of the nth slave control unit.

[0007] In conjunction with the first aspect, in one embodiment, the master control unit and all slave control units share the same clock source, and each slave control unit drives a local counter based on the same clock source; when the master control unit issues a delay calibration command, it synchronously outputs a calibration test frame, latches the transmission timestamp when the first valid data of the calibration test frame is output, and sends the transmission timestamp to each slave control unit through the control bus; In response to the delay calibration command, the nth slave control unit acquires a first transmission time value from the master control unit to the nth slave control unit, including: After the nth slave control unit receives the calibration test frame, it latches the receiving timestamp through the local counter when the first valid data is identified, and obtains the first transmission time value based on the difference between the receiving timestamp and the sending timestamp.

[0008] In conjunction with the first aspect, in one embodiment, the process of the nth slave control unit acquiring the second transmission time value from the nth slave control unit to the corresponding signal conversion chip includes: The transmission time from the start of sending the test signal corresponding to the calibration test frame to the signal conversion chip from the nth slave control unit to the end of receiving the trigger signal sent by the signal conversion chip via GPIO is taken as the second transmission time value; wherein, the trigger signal is issued by the signal conversion chip when it receives the first valid pixel in the test signal corresponding to the calibration test frame.

[0009] In conjunction with the first aspect, in one embodiment, the master control unit generates first delay configuration parameters for each slave control unit based on the channel transmission time values ​​of all slave control units, including: The master control unit uses the maximum duration among all channel transmission time values ​​uploaded by the slave control units as the base delay; For each slave control unit, a first delay configuration parameter corresponding to the slave control unit is generated based on the difference between the reference delay and the channel transmission time value of the slave control unit.

[0010] In conjunction with the first aspect, in one embodiment, the main control unit generates second delay configuration parameters corresponding to each of the signal conversion chips, including: For each slave control unit, the remaining delay is determined based on the difference between the reference delay and the channel transmission time of the slave control unit, and the delay amount corresponding to the first delay configuration parameter. The remaining delay amount is used to generate a second delay configuration parameter corresponding to the signal conversion chip connected to the slave control unit.

[0011] In conjunction with the first aspect, in one embodiment, in response to the synchronization trigger signal, each of the slave control units converts the image data signal into an image test signal, performs delay compensation according to the corresponding first delay configuration parameter, and synchronously outputs the image test signal, including: Upon receiving the synchronization trigger signal, the image data signal is converted into an image test signal, and the image test signal is delayed by a number of clock cycles according to the number of clock cycles indicated by the corresponding first delay configuration parameter before being output; wherein, the first clock cycle is the working clock cycle of the slave control unit.

[0012] In conjunction with the first aspect, in one embodiment, when each of the signal conversion chips receives the image test signal, it converts the image test signal into a screen driving signal, performs delay compensation according to the corresponding second delay configuration parameters, and then outputs the screen driving signal to the corresponding screen under test, including: After receiving the image test signal sent by the connected slave control unit, any of the signal conversion chips converts the image test signal into a screen drive signal, and outputs the screen drive signal to the corresponding screen under test after delaying it by a corresponding number of second clock cycles according to the number of clock cycles indicated by the corresponding second delay configuration parameter. Wherein, the second clock cycle is the working clock cycle of the signal conversion chip, and the delay compensation granularity corresponding to the signal conversion chip is smaller than the delay compensation granularity corresponding to the connected slave control unit.

[0013] In conjunction with the first aspect, in one embodiment, the screen testing system further includes a host computer, and the method further includes: The main control unit receives the configuration parameters sent by the host computer and verifies the configuration parameters. The configuration parameters include at least the synchronization configuration parameters, which are used for delay configuration. The main control unit issues a delay calibration command, including: After the configuration parameters are verified, the configuration parameters are broadcast to each slave control unit, the delay calibration command is sent to each slave control unit, and the configuration parameters are stored in the memory of the master control unit.

[0014] According to a second aspect of the embodiments of this application, a screen testing system is provided, the screen testing system including a main control unit, a plurality of slave control units, and a signal conversion chip connected to each slave control unit accordingly; The main control unit is used to issue delay calibration commands; Each of the slave control units is used to respond to the delay calibration command, obtain its own channel transmission time value, and upload it to the master control unit; The master control unit is also used to generate and send a first delay configuration parameter corresponding to each slave control unit and a second delay configuration parameter corresponding to each signal conversion chip, based on the channel transmission time value of all slave control units. The main control unit is also used to send a synchronization trigger signal and an image data signal to each of the slave control units after the delay configuration is completed; Each of the slave control units is further configured to, in response to the synchronization trigger signal, convert the image data signal into an image test signal, and after performing delay compensation according to the corresponding first delay configuration parameter, synchronously output the image test signal; Each of the signal conversion chips is used to convert the image test signal into a screen driving signal when it receives the image test signal, and output the screen driving signal to the corresponding screen under test after performing delay compensation according to the corresponding second delay configuration parameters.

[0015] This application provides a screen testing method and system. The method involves a master control unit initiating delay calibration, with each slave control unit acquiring and uploading the transmission time of its respective channel. The master control unit then generates and distributes delay configuration parameters for each slave control unit and signal conversion chip based on the differences in transmission time across channels. After delay configuration, the master control unit uniformly distributes a synchronization trigger signal and an image data signal. Each slave control unit responds to the synchronization trigger signal by converting the image data signal into an image test signal and performs delay compensation according to the corresponding first delay configuration parameter, ensuring that the output times of the image test signals from each slave control unit are nearly identical. Upon receiving the image test signal, each signal conversion chip converts it into a screen drive signal and performs delay compensation according to the corresponding second delay configuration parameter before outputting the screen drive signal to the corresponding screen under test. This further compensates for the differences in transmission time in the downstream links of each channel. As a result, each screen can receive the screen drive signal and complete the image switching at a relatively close time. At this point, the camera is triggered for acquisition, and each screen is already in a stable display state. This helps reduce the risk of misjudgment due to asynchronous test startup, thereby improving the accuracy of screen testing on the production line. Attached Figure Description

[0016] Figure 1 A schematic flowchart of a screen testing method provided in an embodiment of this application is shown; Figure 2 It shows Figure 1 A flowchart illustrating step S102; Figure 3 A schematic diagram of the structure of a screen testing system provided in an embodiment of this application is shown; Figure 4 A schematic diagram of the structure of a screen testing system provided in an embodiment of this application is shown. Detailed Implementation

[0017] To make the technical solution and beneficial effects of this application more apparent and understandable, a detailed description is provided below by listing specific embodiments. The accompanying drawings are not necessarily drawn to scale, and local features may be enlarged or reduced to more clearly show the details of the local features; unless otherwise defined, the technical and scientific terms used herein have the same meanings as those in the technical field to which this application pertains.

[0018] The embodiments in this application are not exhaustive, but merely illustrative of some embodiments, and are not intended to limit the scope of protection of this disclosure. Unless otherwise specified, each step in a particular embodiment can be implemented as an independent embodiment, and the steps can be arbitrarily combined. For example, a solution after removing some steps in a particular embodiment can also be implemented as an independent embodiment, and the order of the steps in a particular embodiment can be arbitrarily interchanged. Furthermore, the optional implementation methods in a particular embodiment can be arbitrarily combined; moreover, the embodiments can be arbitrarily combined, for example, some or all steps of different embodiments can be arbitrarily combined, and a particular embodiment can be arbitrarily combined with the optional implementation methods of other embodiments.

[0019] In each embodiment of this application, unless otherwise specified or in case of logical conflict, the terminology and / or descriptions of the embodiments are consistent and can be referenced by each other. Technical features in different embodiments can be combined to form new embodiments based on their inherent logical relationships.

[0020] In the description of the embodiments of this application, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of the embodiments of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0021] This application provides a screen testing method applied to a screen testing system. The screen testing system includes a master control unit, multiple slave control units, and signal conversion chips connected to each slave control unit.

[0022] In this embodiment, both the master control unit and each slave control unit can employ programmable logic devices, such as FPGAs (Field Programmable Gate Arrays). The signal conversion chip can be selected according to the interface type of the screen under test. For example, when the screen under test is an LCD or OLED screen with a MIPI interface (Mobile Industry Processor Interface), a MIPI driver chip such as an SSD2832 can be selected as the signal conversion chip to convert the input RGB signal into the MIPI signal required by the screen.

[0023] Taking LVDS (Low Voltage Differential Signaling) as an example, the main control unit has multiple independent LVDS output channels. Each LVDS output channel outputs an LVDS signal as image data to one of the multiple slave control units. The slave control unit then converts the LVDS signal into an RGB signal and outputs it to its connected signal conversion chip. The signal conversion chip then converts the RGB signal into the MIPI signal required by the screen. Additionally, the main control unit can... 2 The C-bus or SPI (Serial Peripheral Interface) channel sends screen parameters, power parameters, synchronization configuration parameters, etc. to multiple slave units respectively to ensure that all module parameters are consistent.

[0024] Each slave control unit is paired with a corresponding signal conversion chip. For example, the output of the slave control unit is connected to the input of the signal conversion chip via an RGB interface, and the output of the signal conversion chip is connected to the connector of the screen under test via a MIPI interface. The slave control unit generates an image test signal, and the signal conversion chip receives the image test signal, performs color correction, interface protocol conversion, and timing delay compensation on it, generating a MIPI signal suitable for the screen under test and outputting it to the screen under test.

[0025] A hardware trigger link is also provided between the master control unit and each slave control unit. This hardware trigger link is used to transmit synchronous trigger signals, providing a unified time reference for each slave control unit and the signal conversion chip. For example, the hardware trigger link can use differential traces of equal length, with the synchronous trigger pin of the master control unit connected to the synchronous trigger input pin of each slave control unit. The master control unit can synchronously output a differential hard synchronization signal at LVDS level to each slave control unit. This differential hard synchronization signal is used as the time reference for starting or stopping the screen test. For example, the rising edge of the hard synchronization start signal is used to indicate the start of test synchronization, and the falling edge of the hard synchronization start signal is used to indicate the stop of test synchronization.

[0026] In some examples, the master control unit issues delay calibration commands to each slave control unit, initiating the delay measurement process. This command can be transmitted via the system's existing I / O pins. 2 The C bus broadcasts information, and each slave unit is connected to the same I bus. 2 On the C bus, commands can be received simultaneously. For example, I... 2 The frame format of the C bus can be extended to include calibration instruction frames, delay data frames, compensation value frames, and other frame formats on top of the existing read and write operations. Calibration communication can be completed by reusing the same physical bus.

[0027] In some examples, a high-precision clock counter can be set inside the master control unit. The clock signal is generated by frequency multiplication of the same crystal oscillator through a PLL (Phase Locked Loop) and output to each slave control unit, ensuring that the clocks of each slave control unit are from the same source.

[0028] In some examples, the slave control unit can also execute a dynamic phase adjustment algorithm during decoding to eliminate jitter introduced by signal transmission. The register timing logic and the dynamic phase adjustment algorithm are functionally independent, and the timing delay does not affect the phase adjustment effect during signal decoding.

[0029] Figure 1 A flowchart illustrating the screen testing method provided in an embodiment of this application is shown. Figure 1 As shown, the screen testing method includes the following steps: S101: The main control unit issues a delay calibration command; S102: In response to the delay calibration command, multiple slave control units obtain their respective channel transmission time values ​​and upload them to the master control unit; S103: The master control unit generates and sends the first delay configuration parameter corresponding to each slave control unit and the second delay configuration parameter corresponding to each signal conversion chip, based on the channel transmission time value of all slave control units. S104: After the delay configuration is completed, the master control unit sends a synchronization trigger signal and an image data signal to each slave control unit; S105: In response to the synchronous trigger signal, each slave control unit converts the image data signal into an image test signal, performs delay compensation according to the corresponding first delay configuration parameter, and then synchronously outputs the image test signal. S106: When each signal conversion chip receives the image test signal, it converts the image test signal into a screen drive signal, and after delay compensation according to the corresponding second delay configuration parameters, it outputs the screen drive signal to the corresponding screen under test.

[0030] In actual systems, even if the physical traces between the master control unit and different slave control units are designed with equal length, the delay of different channels is usually different due to the differences in device characteristics.

[0031] In step S101, in scenarios requiring recalibration, such as changing screen specifications or replacing signal conversion chips, the main control unit can use I... 2 The C-bus or SPI channel sends a delay calibration command to each slave unit to initiate transmission time measurement. For example, this command can be transmitted via I... 2 The C bus broadcasts information, and each slave unit is connected to the same I bus. 2 The delay calibration command can be received on the C bus.

[0032] In step S102, in response to the delay calibration command, multiple slave control units acquire their respective channel transmission time values ​​and upload them to the master control unit. The channel transmission time value reflects the end-to-end transmission time of the signal from the master control unit to the final output via the signal conversion chip. The master control unit can be configured with a timeout mechanism; if a slave control unit fails to upload within a preset time, it is marked as a fault node and an alarm is issued.

[0033] In step S103, the master control unit can aggregate the time-consuming data uploaded by all slave control units and generate differentiated delay configuration parameters for each channel based on the transmission time differences between different channels. For any slave control unit, the master control unit generates a corresponding first delay configuration parameter to indicate that the slave control unit should wait for the corresponding time before outputting the test signal during subsequent synchronization triggering.

[0034] For any signal conversion chip connected to a slave control unit, the master control unit generates a corresponding second delay configuration parameter to instruct the signal conversion chip to perform corresponding delay compensation after receiving a test signal.

[0035] Because the physical link transmission time varies for each channel, the first delay configuration parameter for each channel is usually different, and the second delay configuration parameter varies depending on the channel.

[0036] Shorter-duration channels are configured with longer delays, while longer-duration channels are configured with shorter delays.

[0037] After the main control unit generates the delay configuration parameters for each channel, it uses I... 2 The master control unit sends the first delay configuration parameter to the corresponding slave unit via the C-bus or SPI channel, and sends the second delay configuration parameter to the corresponding signal conversion chip. Each slave unit and each signal conversion chip receives and stores their respective configuration parameters, completing the delay configuration. After completing the delay configuration, the master control unit uses I-channel... 2 The system uses C or SPI to read the status of each slave control unit and signal conversion chip, and obtains a configuration completion confirmation signal (such as the configuration completion flag in the status register) to confirm that the configuration of all nodes has taken effect.

[0038] After confirming the delay configuration, the master control unit can uniformly send a synchronization trigger signal and image data signal (e.g., LVDS signal) to each slave control unit. Upon receiving the synchronization trigger signal, each slave control unit converts the image data signal into an image test signal (e.g., RGB signal) and performs corresponding delay processing according to its respective first delay configuration parameters. When the delay ends, it outputs the image test signal to the corresponding signal conversion chip, thus ensuring that the timing of the image test signal output by each slave control unit is consistent.

[0039] After receiving the image test signal output from the corresponding slave control unit, each signal conversion chip performs color correction and timing optimization on the image test signal, converting it into a screen drive signal (e.g., a MIPI signal) that meets the timing requirements of the screen under test. Based on its respective second delay configuration parameters, the chip performs delay compensation before outputting the screen drive signal to the corresponding screen under test. The second delay configuration parameters are also differentiated, further compensating for the differences in transmission time between channels in the downstream link, enabling each screen under test to receive the screen drive signal at a relatively close time.

[0040] Through the aforementioned screen testing method, the transmission time differences of the physical links of each channel are measured and compensated for before testing. This ensures that each screen under test receives the screen drive signal and completes image switching at a relatively close time. At this point, the camera captures the image, and all screens are already in a stable display state. This helps reduce misjudgments caused by asynchronous test startup, thereby improving the accuracy of production line testing. Furthermore, in mass production screen testing, it is necessary to adapt to various screen specifications. Changing screen specifications usually requires replacing the signal conversion chip, and different chip models have different internal processing delays. This embodiment only requires re-executing the calibration process once. The main control unit centrally acquires the delay information of each channel, uniformly generates and distributes delay configuration parameters, achieving centralized management of parameter configuration and improving the efficiency and flexibility of production line testing.

[0041] In some embodiments, the synchronous trigger signal has a start trigger edge (e.g., rising edge) and a stop trigger edge (e.g., falling edge), the start trigger edge being used to indicate that each screen under test synchronously starts the test; the stop trigger edge being used to indicate that each screen under test synchronously stops the test.

[0042] In some examples, when the test is initiated, the master control unit sends a trigger edge to the synchronization trigger signal. Upon receiving the trigger edge, each slave control unit converts the received image data signal into an image test signal, waits for the corresponding duration according to its own first delay configuration parameter, and then outputs its image test signal, ensuring that the output timing of the test signals from each slave control unit is consistent. After receiving the image test signal, each signal conversion chip converts it into a screen drive signal, performs delay compensation according to its own second delay configuration parameter, and then outputs it to the screen under test, causing each screen to start the test synchronously. This consistent timing of screen image switching helps ensure that each screen remains in a stable display state during unified data acquisition.

[0043] In some examples, when the test stops, the master control unit sends a stop trigger edge of the synchronization trigger signal. Upon receiving this edge, each slave control unit waits for the corresponding duration according to its own first delay configuration parameter before stopping the output of the test signal. Each signal conversion chip stops outputting drive signals due to the interruption of the input signal, and each screen turns off synchronously. In this way, all workstations finish testing at the same time, facilitating unified management and simplifying the control logic.

[0044] In one embodiment, such as Figure 2 As shown, in response to the delay calibration command, step S102 above, where multiple slave control units acquire their respective channel transmission time values, may include: S201: In response to the delay calibration command, the nth slave control unit obtains the first transmission time value from the master control unit to the nth slave control unit and the second transmission time value from the nth slave control unit to the corresponding signal conversion chip; where n is a positive integer less than or equal to the total number of slave control units; S202: Obtain the total transmission time value based on the first transmission time value and the second transmission time value, and use it as the channel transmission time value of the nth slave control unit.

[0045] Here, the first transmission time value of the nth slave control unit can be used to represent the time required from when the signal is sent from the master control unit to when the nth slave control unit receives and completes signal processing. This time includes the transmission time of the physical wiring, the signal decoding time, and the time of dynamic phase adjustment performed to eliminate signal jitter. The second transmission time value of the nth slave control unit can be used to represent the time required from when the nth slave control unit outputs a signal to when the signal conversion chip connected to it receives and completes signal conversion.

[0046] In this embodiment, the channel transmission time value of the nth slave control unit can be set as the sum of its corresponding first transmission time value and second transmission time value to measure the actual time of the entire signal link from the master control unit to the channel where the nth slave control unit is located, thereby providing a basis for generating different delay configuration parameters for the slave control unit and the signal conversion chip.

[0047] In one embodiment, the master control unit and all slave control units share the same clock source, and each slave control unit drives a local counter based on the same clock source. When the master control unit issues a delay calibration command, it synchronously outputs a calibration test frame, latches the transmission timestamp when the first valid data of the output calibration test frame is displayed, and sends the transmission timestamp to each slave control unit through the control bus.

[0048] In step S201 above, in response to the delay calibration command, the nth slave control unit obtains the first transmission time value from the master control unit to the slave control unit, including: After the nth slave control unit receives the calibration test frame, it latches the receiving timestamp through a local counter when the first valid data is identified, and obtains the first transmission time value based on the difference between the sending timestamp and the receiving timestamp.

[0049] The calibration test frame can be a data frame with a pre-agreed fixed code pattern. For example, the calibration test frame can be a pure white frame, a pure black frame, or a test frame with a specific stripe pattern. Exemplarily, the nth slave control unit continuously monitors the data stream from the master control unit upon receiving a delay calibration command. When the first valid data of the calibration test frame is identified, the slave control unit latches the reception timestamp of the first valid data using a local counter. The difference between the transmission timestamp and the reception timestamp of the first valid data is the first transmission time value.

[0050] In this embodiment, since the master control unit synchronously outputs a calibration test frame when issuing a delay calibration command, latches the transmission timestamp when the first valid data of the output calibration test frame is received, and sends the transmission timestamp to each slave control unit through the control bus (I²C or SPI), and the master control unit and all slave control units share the same clock source (e.g., a synchronous clock output from a crystal oscillator of the same source), and each slave control unit drives a local counter (e.g., a local timer or timestamp counter of the slave control unit) based on the same clock source, the time base of the master control and the slave control can be completely synchronized. The slave control unit obtains the first transmission time value based on the difference between the locally recorded reception timestamp and the transmission timestamp sent by the master control. This eliminates the need to rely on external trigger signals or software command interaction, making the measurement of the first transmission time value more accurate.

[0051] In some examples, the first valid data can be the first valid pixel data in the calibration test frame. For example, when the calibration test frame is a completely white frame, the first valid pixel data is the first pixel value transmitted in the completely white frame.

[0052] In this embodiment, the slave control unit can know the code pattern of the quasi-test frame in advance and can accurately identify the first valid data of the calibration test frame, using it as the measurement endpoint, thereby reducing the additional delay introduced by relying on external signals to determine the measurement endpoint.

[0053] In one embodiment, step S201 above, where the nth slave control unit obtains the second transmission time value from the nth slave control unit to the corresponding signal conversion chip, includes: The transmission time from the start of sending the test signal corresponding to the calibration test frame to the signal conversion chip from the nth slave control unit to the end of receiving the trigger signal sent by the signal conversion chip via GPIO is used as the second transmission time value; wherein, the trigger signal is issued by the signal conversion chip when it receives the first valid pixel in the test signal corresponding to the calibration test frame.

[0054] For example, the slave control unit starts a local timer (different from the local counter in the previous embodiment) when sending the decoded calibration test frame to the signal conversion chip. After receiving the first valid pixel in the test signal, the signal conversion chip sends a trigger signal to the slave control unit via GPIO. When the slave control unit receives the trigger signal, it stops the local timer and reads the count value of the timer as the second transmission time value. Compared to sending the local timer via I / O, this is more efficient. 2 The C-type communication bus provides feedback on the measurement results, and the GPIO hardware trigger signal has a short transmission path and a fixed delay, making the measurement of the second transmission time value more accurate.

[0055] In one embodiment, in step S103 above, the master control unit generates first delay configuration parameters corresponding to each slave control unit based on the channel transmission time values ​​of all slave control units, including: The master control unit uses the maximum duration among all channel transmission time values ​​uploaded by the slave control units as the reference delay; for each slave control unit, a first delay configuration parameter corresponding to the slave control unit is generated based on the difference between the reference delay and the channel transmission time value of the slave control unit.

[0056] For example, using the maximum latency as the baseline delay, all channels are aligned with the channel with the longest latency. Channels with shorter latency are configured to wait longer, while channels with longer latency wait less or not at all. For channels whose latency value is equal to the baseline latency, the latency corresponding to their first latency configuration parameter is zero.

[0057] For example, the screen testing system includes four slave control units. The channel transmission time values ​​of the four channels are different. The master control unit takes the longest duration as the reference delay and generates the first delay configuration parameters according to the difference between the channel transmission time value of each channel and the reference delay, and sends them to the corresponding slave control units.

[0058] In this embodiment, the master control unit generates differentiated first delay configuration parameters based on the actual transmission time differences of each channel. The delay configuration obtained by each slave control unit matches the time consumption characteristics of its own channel, so that the output time of each channel can be compensated for based on its own configuration parameters during subsequent synchronous triggering, providing a reliable basis for each slave control unit to synchronously output image test signals under unified triggering.

[0059] In one embodiment, in step S103 above, the main control unit generates second delay configuration parameters corresponding to each signal conversion chip, including: For each slave control unit, the remaining delay is determined based on the difference between the reference delay and the channel transmission time of the slave control unit, as well as the delay amount corresponding to the first delay configuration parameter; and a second delay configuration parameter corresponding to the signal conversion chip connected to the slave control unit is generated based on the remaining delay.

[0060] For example, for each slave control unit, the master control unit subtracts the delay amount corresponding to the first delay configuration parameter from the total difference between the reference delay and the transmission time value of the slave control unit's channel, obtaining the remaining delay amount, and uses this to generate the second delay configuration parameter. When the total difference is large, the first delay configuration parameter can cover the entire cycle portion, and the remaining portion is handled by the second delay configuration parameter. When the total difference is small and insufficient to reach one compensation unit of the first delay configuration parameter, the delay amount corresponding to the first delay configuration parameter is zero, and the entire difference is used as the remaining delay amount to generate the second delay configuration parameter.

[0061] This embodiment uses the above two-level compensation mechanism to enable the slave control unit to perform coarse-grained delay compensation and the signal conversion chip to perform fine-grained delay compensation. This balances the compensation range and the compensation accuracy, thereby ensuring that the timing of the drive signals output by each channel to the screen under test is consistent. This helps to reduce the risk of misjudgment caused by asynchronous testing of each screen and improves the accuracy of the test.

[0062] In one embodiment, in step S105 above, in response to the synchronization trigger signal, each slave control unit converts the image data signal into an image test signal, performs delay compensation according to the corresponding first delay configuration parameter, and synchronously outputs the image test signal, including: After receiving the synchronization trigger signal, each slave control unit converts the image data signal into an image test signal, and outputs the image test signal after delaying it by the number of clock cycles indicated by the corresponding first delay configuration parameter; wherein, the first clock cycle is the working clock cycle of the slave control unit.

[0063] The first clock cycle can be the cycle of the internal logic clock of the slave control unit, such as the clock cycle used for register timing delay. The first delay configuration parameter records the number of clock cycles that the slave control unit needs to delay. Different slave control units have different first delay configuration parameters, and the corresponding number of clock cycles also varies. Channels with shorter delays are allocated more clock cycles, while channels with longer delays are allocated fewer. For channels whose delay value itself is the reference delay, the number of clock cycles corresponding to their first delay configuration parameter is zero. Upon receiving the synchronization trigger signal, the test signal is output directly, i.e., no waiting is required.

[0064] In practical implementation, the aforementioned delay can be achieved internally within the control unit using register cascading. This involves cascading flip-flops within the programmable logic device (PLD), delaying the output by one clock cycle relative to the input for each stage of the test signal's path. The number of clock cycles delayed can be controlled by adjusting the number of flip-flops at the output. For example, selecting the output from the 4th stage flip-flop delays the test signal by four first clock cycles. This register-based delay compensation eliminates the need for additional dedicated delay devices, and the delay is clock-driven, unaffected by fluctuations in temperature or other factors, thus improving the stability of the delay behavior across all channels.

[0065] In one embodiment, in step S106 above, when each signal conversion chip receives an image test signal, it converts the image test signal into a screen driving signal, performs delay compensation according to the corresponding second delay configuration parameters, and then outputs the screen driving signal to the corresponding screen under test, including: After receiving the image test signal sent by the connected slave control unit, any signal conversion chip converts the image test signal into a screen drive signal, and delays the test signal by the number of clock cycles indicated by the corresponding second delay configuration parameter, and then converts it into a screen drive signal to be output to the corresponding screen under test.

[0066] Wherein, the second clock cycle is the working clock cycle of the signal conversion chip, and the delay compensation granularity corresponding to the signal conversion chip is smaller than the delay compensation granularity corresponding to the connected slave control unit.

[0067] The second clock cycle can be the pixel clock cycle of the signal conversion chip. The pixel clock cycle is the clock inside the signal conversion chip used to drive pixel processing and drive signal output. The second clock cycle is shorter than the first clock cycle used by the slave control unit. Since the delay compensation granularity corresponding to the signal conversion chip is smaller than that corresponding to the slave control unit, the signal conversion chip can perform delay adjustment with smaller granularity to handle the remaining bits after the slave control unit uses coarse-grained compensation.

[0068] The signal conversion chip can utilize its internal native timing delay register to achieve the aforementioned delay. Taking the SSD2832 chip as an example, its internal TIMING_DELAY register is used to fine-tune the output timing of the MIPI signal. By writing different register values ​​to select the corresponding tap position, the delay amount of the signal output can be adjusted at the pixel clock cycle level. The fine compensation adjustment range can cover 0 to 1023 pixel clock cycles. On the control unit side, coarse-grained delay compensation is performed with a larger first clock cycle to cover the main transmission time differences of each channel; on the signal conversion chip side, fine-grained delay compensation is performed with a smaller second clock cycle to handle the remaining minor differences.

[0069] In this embodiment, the slave control unit performs coarse-grained delay compensation with a larger first clock cycle, covering the main transmission time differences of each channel; the signal conversion chip performs fine-grained delay compensation with a smaller second clock cycle, processing the remaining minor differences, so that the timing of the output drive signals of each channel is aligned, which helps to reduce misjudgments caused by asynchronous testing of each screen.

[0070] In one embodiment, the screen testing system further includes a host computer, and the method may further include: The main control unit receives the configuration parameters sent by the host computer and verifies the configuration parameters. The configuration parameters include at least the synchronous configuration parameters, which are used for delay configuration. In step S101 above, the main control unit issues a delay calibration command, which includes: after verifying the configuration parameters, broadcasting the configuration parameters to each slave control unit, issuing a delay calibration command to each slave control unit, and storing the configuration parameters in the main control unit's memory.

[0071] In some examples, configuration parameters may include screen basic parameters, power configuration parameters, and / or synchronization configuration parameters. Synchronization configuration parameters are used for delay configuration; for example, they may include at least one of the following: synchronization trigger mode, calibration accuracy requirements, maximum configurable delay of the signal conversion chip, and adjustable decoding delay range of the slave control unit. Screen basic parameters may include at least one of the following: resolution, refresh rate, and initialization code. Power configuration parameters may include at least one of the following: supply voltage, voltage and current thresholds, and timing requirements.

[0072] In some examples, the host computer can be a computer or a handheld device. A handheld device is a portable debugging terminal, typically equipped with a display screen and buttons or a touchscreen, communicating with the main control unit via a serial port, USB, or wireless interface. The host computer can obtain the specification information of the screen under test input or selected by the operator through the software interface, and generate configuration parameters accordingly, which are then sent to the main control unit.

[0073] The main control unit verifies the configuration parameters from the host computer. The verification may include at least one of the following: checking whether the resolution exceeds the upper limit supported by the hardware, whether the refresh rate is within the allowed range, and whether the voltage threshold is within the safe range.

[0074] After successful verification, the master control unit broadcasts the configuration parameters to each slave control unit to ensure parameter consistency across modules. Simultaneously, it sends a delay calibration command to each slave control unit to initiate the calibration process and stores the configuration parameters in non-volatile memory for retention after power failure. For example, the non-volatile memory can be an EMMC (Embedded Multi Media Card), which can store multiple sets of screen configuration parameters. Each set of configuration parameters is synchronously bound to the delay compensation value of the corresponding node, facilitating direct loading during subsequent model changes. For instance, if a delay needs to be re-performed, if the master control unit remains connected to the host computer, the configuration parameters can be re-sent from the host computer. If the master control unit is disconnected from the host computer and is offline, it can retrieve the pre-stored configuration parameters from the memory to perform the delay calibration and synchronization triggering process without the host computer's involvement.

[0075] In this way, the screen testing system supports both centralized online configuration by a host computer and autonomous delay calibration after disconnecting from the host computer. It does not need to rely on an online environment after changing screen specifications or signal conversion chips, making deployment more flexible.

[0076] In some embodiments, such as Figure 3 As shown, a screen testing system is provided. The screen testing system 100 includes a main control unit 10, a plurality of slave control units 20, and a signal conversion chip 30 connected to each slave control unit 20.

[0077] Main control unit 10 is used to issue delay calibration commands; Each slave control unit 20 is used to respond to the delay calibration command, obtain its own channel transmission time value and upload it to the master control unit 10; The main control unit 10 is also used to generate and send a first delay configuration parameter corresponding to each slave control unit 20 and a second delay configuration parameter corresponding to each signal conversion chip 30 based on the channel transmission time value of all slave control units 20. The main control unit 10 is also used to send synchronous trigger signals and image data signals to each slave control unit 20 after the delay configuration is completed; Each slave control unit 20 is also used to respond to the synchronization trigger signal, convert the image data signal into an image test signal, and after performing delay compensation according to the corresponding first delay configuration parameter, synchronously output the image test signal; Each signal conversion chip 30 is used to convert the image test signal into a screen driving signal when it receives the image test signal, and output the screen driving signal to the corresponding screen under test after delay compensation according to the corresponding second delay configuration parameters.

[0078] In some embodiments, the nth slave control unit is configured to, in response to a delay calibration command, acquire a first transmission time value from the master control unit to the nth slave control unit, and a second transmission time value from the nth slave control unit to the corresponding signal conversion chip, and obtain a total transmission time value based on the first and second transmission time values, which is used as the channel transmission time value of the nth slave control unit. Here, n is a positive integer less than or equal to the total number of slave control units.

[0079] In some embodiments, the master control unit and all slave control units share the same clock source, and each slave control unit drives a local counter based on the same clock source; when the master control unit issues a delay calibration command, it synchronously outputs a calibration test frame, latches the transmission timestamp when the first valid data of the calibration test frame is output, and sends the transmission timestamp to each slave control unit through the control bus; The nth slave control unit is used to: after receiving the calibration test frame, when the first valid data is identified, latch the receiving timestamp through the local counter, and obtain the first transmission time value based on the difference between the receiving timestamp and the sending timestamp.

[0080] In some embodiments, the nth slave control unit is configured to: use the transmission time from the moment it starts sending the test signal corresponding to the calibration test frame to the signal conversion chip until it receives the trigger signal sent by the signal conversion chip via GPIO as a second transmission time value. The trigger signal is issued by the signal conversion chip when it receives the first valid pixel in the test signal corresponding to the calibration test frame.

[0081] In some embodiments, the master control unit is used to take the maximum duration among all channel transmission time values ​​uploaded by the slave control units as the reference delay, and for each slave control unit, generate a first delay configuration parameter corresponding to the slave control unit based on the difference between the reference delay and the channel transmission time value of the slave control unit.

[0082] In some embodiments, the master control unit is configured to: for each slave control unit, determine the remaining delay amount based on the difference between the reference delay and the channel transmission time value of the slave control unit, and the delay amount corresponding to the first delay configuration parameter; and generate a second delay configuration parameter corresponding to the signal conversion chip connected to the slave control unit based on the remaining delay amount.

[0083] In some embodiments, the nth slave control unit is configured to: after receiving the synchronization trigger signal, convert the image data signal into an image test signal, and output the image test signal after delaying it by a number of clock cycles according to the number of clock cycles indicated by the corresponding first delay configuration parameter; wherein, the first clock cycle is the working clock cycle of the slave control unit.

[0084] In some embodiments, any of the signal conversion chips is configured to: after receiving an image test signal sent by the connected slave control unit, convert the image test signal into a screen drive signal, and output the screen drive to the corresponding screen under test after delaying the test signal by a number of second clock cycles according to the number of clock cycles indicated by the corresponding second delay configuration parameter; wherein, the second clock cycle is the working clock cycle of the signal conversion chip, and the delay compensation granularity corresponding to the signal conversion chip is smaller than the delay compensation granularity corresponding to the connected slave control unit.

[0085] In some embodiments, the screen testing system further includes a host computer, and the main control unit is further configured to: receive configuration parameters sent by the host computer and verify the configuration parameters, wherein the configuration parameters include at least synchronous configuration parameters, which are used for delay configuration; after the configuration parameters are verified, broadcast the configuration parameters to each slave control unit and send a delay calibration command to each slave control unit, and store the configuration parameters in the memory of the main control unit.

[0086] The screen testing system provided in this application embodiment belongs to the same application concept as the screen testing method provided in the above embodiments. It can execute the screen testing method provided in any of the above embodiments. For technical details not described in detail in this embodiment, please refer to the specific content of the screen testing method provided in the above embodiments, which will not be repeated here.

[0087] Based on one or more of the above embodiments, the technical solution provided by the embodiments of this application will be further explained below with reference to a smartphone screen testing production line and a specific scenario.

[0088] S1: The host computer sends the configuration parameters to the main FPGA through the interface.

[0089] Operators can input the specifications of the screen under test into the software interface. The host computer will then send a data packet containing basic screen parameters, power configuration parameters, and synchronization configuration parameters to the main FPGA (as the master control unit). The basic screen parameters include resolution and refresh rate; the power configuration parameters include supply voltage and voltage / current thresholds; and the synchronization configuration parameters include synchronization trigger mode, calibration accuracy requirements, the maximum configurable delay of the SSD2832 signal conversion chip, and the adjustable decoding delay range from the FPGA (as the slave control unit).

[0090] S2: After receiving the data, the main FPGA performs parameter verification.

[0091] Verification items include checking whether the resolution is within the supported range (e.g., from 480p to 8K), whether the refresh rate matches the timing, whether the voltage exceeds the safety threshold, and / or whether the synchronization configuration parameters meet the device specifications. The verification process may also include real-time threshold monitoring, such as automatically triggering protection when the current exceeds a set value.

[0092] After successful verification, the main FPGA sends an confirmation signal to the host computer and stores the parameters in the EMMC for offline use. Each screen group is configured with a synchronously bound delay compensation value for the corresponding node, facilitating direct loading during subsequent model changes.

[0093] S3: The main FPGA broadcasts parameters and initiates delay calibration.

[0094] The main FPGA is configured to output 8 channels of LVDS signals via its internal LVDS transmitter, and through I... 2 The C bus broadcasts parameters to the four slave FPGAs, including screen parameters, power parameters, and synchronization configuration parameters, to ensure that all module parameters are consistent.

[0095] The main FPGA's synchronization control submodule starts a high-precision clock counter via I 2 The C-synchronous calibration protocol sends calibration start commands to four slave FPGAs and four SSD2832 chips, initiating global delay acquisition. The high-precision clock counter generates a clock signal from a single crystal oscillator via PLL frequency multiplication and outputs it to all slave FPGAs. The high-precision clock counter has a counting frequency of, for example, 1 GHz and a counting accuracy of 1 nanosecond.

[0096] S4: Delayed data acquisition and transmission at each node.

[0097] Each FPGA and its corresponding connected SSD2832 form an independent test node.

[0098] While sending the calibration command, the master FPGA outputs a calibration test frame with a known code pattern, such as a completely white frame. When the master control unit outputs the first valid data of the calibration test frame, it latches a high-precision transmission timestamp based on a high-precision clock counter and sends the transmission timestamp to each slave control unit via the control bus.

[0099] When the first valid data of the calibration test frame is received from the FPGA's LVDS receiver, a local counter is triggered to latch the received timestamp. The first transmission time value T1 is obtained based on the difference between the transmitted and received timestamps. T1 includes the physical trace delay, LVDS decoding delay, and the processing time of the dynamic phase adjustment algorithm.

[0100] The decoded RGB calibration frame is sent from the FPGA to the SSD2832. When the SSD2832 receives the first valid RGB pixel, it sends a trigger signal to its slave FPGA via GPIO. The FPGA records this time to obtain the second transmission time value T2. T2 includes the processing time for color correction, timing optimization, and MIPI encoding.

[0101] From the total delay of the FPGA computing node T = T1 + T2, through I 2 The C-bus transmits the delay value back to the synchronization control submodule of the main FPGA. Each node completes the transmission sequentially. The main FPGA is configured with a timeout mechanism. If a slave control unit fails to transmit the value after a preset time, it is marked as a faulty node and an alarm is issued.

[0102] S5: Calculation and distribution of delay compensation for the main FPGA.

[0103] After the main FPGA collects the total delay data from all nodes, it takes the maximum duration as the baseline delay Tmax, and then calculates the delay compensation value ΔT for each node. The main FPGA decomposes ΔT into a coarse compensation part and a fine compensation part, through I... 2 The C bus sends the coarse compensation value to the corresponding slave FPGA and the fine compensation value to the corresponding SSD2832. After each node loads the configuration, the total delay of all nodes is unified to Tmax.

[0104] S6: From FPGA decoding to SSD2832 conversion.

[0105] The FPGA configures the LVDS receiver based on the broadcast parameters for decoding, converting the LVDS signal into a 24-bit RGB signal for output. During decoding, the sampling phase is dynamically adjusted to eliminate signal jitter, and a coarse compensation value is applied. Delay coarse compensation is performed through register timing logic to ensure that the decoded output delay meets the global benchmark. The FPGA can also dynamically optimize the sampling phase based on the broadcast refresh rate parameters to adapt to the testing requirements of screens with different refresh rates.

[0106] The SSD2832 receives RGB signals and control signals from the FPGA, internally performs color space conversion and timing optimization, loads fine compensation values, performs delay fine compensation through the TIMING_DELAY register, and converts the RGB signal into a 4-channel MIPI signal, which drives the screen under test through a connector. The conversion process supports resolution adaptation; for example, a 2340×1080 input can automatically match the corresponding MIPI configuration.

[0107] S7: Global synchronous start / stop to enable multi-screen parallel testing.

[0108] After all nodes have completed the delay compensation configuration, they send a compensation ready confirmation signal back to the master FPGA. Once the master FPGA confirms that all nodes are ready, it sends a synchronization trigger signal to all slave FPGAs via equal-length differential LVDS traces.

[0109] When the test starts, each node receives the rising edge of the synchronization trigger signal. After a delay according to its own coarse compensation value, the FPGA synchronously outputs the actual test frame. The SSD2832, after a delay according to its own fine compensation value, converts the RGB signals into MIPI signals and sends them to the screen. Each screen synchronously receives the valid drive signal. When the test stops, the main FPGA sends the falling edge of the synchronization trigger signal, and each node synchronously stops outputting drive signals, and each screen synchronously stops displaying.

[0110] When used offline, the main FPGA detects the power status through GPIO. Once the power is ready, it automatically loads the pre-stored configuration parameters and corresponding delay compensation values ​​from the EMMC to complete the calibration configuration and synchronization trigger process without the need for the host computer to participate.

[0111] It should be understood that, for the sake of simplicity of the illustrations, steps S1 to S7 are not shown in the accompanying drawings, but their specific implementation has been described in detail in the specification, and will not affect the understanding and implementation of this application by those skilled in the art.

[0112] In some embodiments, steps S1 to S7 may be implemented individually to constitute an independent embodiment, or, without contradiction, at least one of steps S1 to S7 may be implemented in conjunction with... Figure 1 One or more of the steps S101 to S106 shown are combined to form an independent embodiment.

[0113] In some embodiments, such as Figure 4 The screen testing system shown can simultaneously drive four screens under test. The main FPGA outputs eight channels of LVDS to four slave FPGAs, each slave FPGA processing two channels of LVDS. Each slave FPGA is connected to an independent SSD2832 chip. The electrical connections between the devices are as follows: the host computer is connected to the main FPGA; the LVDS output pins of the main FPGA are connected to the LVDS receivers of each slave FPGA; the RGB output pins of each slave FPGA are connected to the parallel interface of the corresponding SSD2832; the MIPI outputs of each SSD2832 chip are connected to the connector of the corresponding screen under test; and the synchronization trigger pins of the main FPGA are connected to the synchronization trigger input pins of each slave FPGA via differential traces of equal length. The connector of the screen under test can be an FPC (Flexible Printed Circuit) connector.

[0114] In summary, the technical solutions provided by the embodiments of this application have at least the following beneficial effects: 1. By automatically acquiring the link transmission time information of each channel through delay calibration, and generating differentiated delay configuration parameters, the delay deviation caused by the physical link difference of each channel is compensated, and each screen receives the drive signal at a relatively close time, which helps to reduce the risk of misjudgment caused by asynchronous switching.

[0115] 2. The main control unit centrally acquires delay information from each channel, uniformly generates and distributes delay configuration parameters, achieving centralized management and control of parameter configuration. When the production line replaces the signal conversion chip or the delay conditions of each channel change, it only needs to re-execute the calibration process to automatically adapt, eliminating the need for manual channel-by-channel debugging and improving changeover efficiency.

[0116] 3. Delay compensation employs a two-stage approach combining coarse and fine compensation. Coarse compensation covers a wide range of transmission time differences, while fine compensation addresses remaining minor differences. This two-stage compensation works synergistically, balancing compensation range and accuracy. Furthermore, this scheme can reuse existing I / O methods. 2 The C-bus transmits calibration data, and delay compensation is achieved by using the register stamping logic of the slave control unit and the native timing delay register of the signal conversion chip, without the need for additional dedicated hardware.

[0117] The various embodiments or implementation methods described in this specification are presented in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.

[0118] It is worth noting that, without contradiction, the foregoing method embodiments can be combined arbitrarily. For example, some or all of the steps of different embodiments can be combined arbitrarily, and one embodiment can be combined arbitrarily with the optional implementations of other embodiments.

[0119] This application also provides a computer-readable storage medium having an executable program stored thereon, which, when executed by a processor, implements the steps of the screen testing method provided in any of the foregoing embodiments.

[0120] For ease of understanding, the following focuses on explaining the terminology used in this embodiment: In this application embodiment, a processor is a circuit with signal processing capabilities. In one implementation, the processor can be a circuit with instruction read and execute capabilities, such as a Central Processing Unit (CPU), a microprocessor, a graphics processing unit (GPU) (which can be understood as a type of microprocessor), or a digital signal processor (DSP). In another implementation, the processor can implement certain functions through the logical relationships of hardware circuits. The logical relationships of the aforementioned hardware circuits are fixed or reconfigurable. For example, the processor is a hardware circuit implemented using an application-specific integrated circuit (ASIC) or a programmable logic device (PLD), such as an FPGA. In a reconfigurable hardware circuit, the process of the processor loading a configuration document and configuring the hardware circuit can be understood as the process of the processor loading instructions to implement the functions of some or all of the above units or modules. In addition, it can also be a hardware circuit designed for artificial intelligence, which can be understood as an ASIC, such as a Neural Network Processing Unit (NPU), a Tensor Processing Unit (TPU), a Deep Learning Processing Unit (DPU), etc.

[0121] The computer-readable storage medium provided in this embodiment can execute the screen testing method of the above embodiment. Its implementation principle and technical effect are similar to those of the above embodiment, and will not be repeated here.

[0122] The aforementioned computer-readable storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk. The readable storage medium can be any available medium accessible to a general-purpose or special-purpose computer.

[0123] An exemplary readable storage medium is coupled to a processor, enabling the processor to read information from and write information to the readable storage medium. Of course, the readable storage medium can also be a component of the processor. The processor and the readable storage medium can reside in an Application Specific Integrated Circuit (ASIC). Alternatively, the processor and the readable storage medium can exist as discrete components in an electronic device or a host device.

[0124] Those skilled in the art will understand that all or part of the steps of the above-described method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments; and the aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.

[0125] The various embodiments or implementation methods described in this specification are presented in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.

[0126] In the description of this specification, references to "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with an embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0127] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A screen testing method, characterized in that, The method is applied to a screen testing system; the screen testing system includes a master control unit, multiple slave control units, and signal conversion chips connected to each slave unit; the method includes: The main control unit issues a delay calibration command; In response to the delay calibration command, multiple slave control units acquire their respective channel transmission time values ​​and upload them to the master control unit; The master control unit generates and sends a first delay configuration parameter corresponding to each slave control unit and a second delay configuration parameter corresponding to each signal conversion chip, based on the channel transmission time values ​​of all slave control units. After the delay configuration is completed, the master control unit sends a synchronization trigger signal and an image data signal to each of the slave control units; In response to the synchronization trigger signal, each of the slave control units converts the image data signal into an image test signal, performs delay compensation according to the corresponding first delay configuration parameter, and then synchronously outputs the image test signal. When each signal conversion chip receives the image test signal, it converts the image test signal into a screen driving signal, performs delay compensation according to the corresponding second delay configuration parameters, and then outputs the screen driving signal to the corresponding screen under test.

2. The screen testing method according to claim 1, characterized in that, In response to the delay calibration command, multiple slave control units acquire their respective channel transmission time values, including: In response to the delay calibration command, the nth slave control unit acquires a first transmission time value from the master control unit to the nth slave control unit, and a second transmission time value from the nth slave control unit to the corresponding signal conversion chip; wherein, n is a positive integer less than or equal to the total number of slave control units; The total transmission time value is obtained based on the first transmission time value and the second transmission time value, and is used as the channel transmission time value of the nth slave control unit.

3. The screen testing method according to claim 2, characterized in that, The master control unit and all slave control units share the same clock source, and each slave control unit drives a local counter based on the same clock source; when the master control unit issues a delay calibration command, it synchronously outputs a calibration test frame, latches the transmission timestamp when the first valid data of the calibration test frame is output, and sends the transmission timestamp to each slave control unit through the control bus; In response to the delay calibration command, the nth slave control unit acquires a first transmission time value from the master control unit to the nth slave control unit, including: After the nth slave control unit receives the calibration test frame, it latches the receiving timestamp through the local counter when the first valid data is identified, and obtains the first transmission time value based on the difference between the receiving timestamp and the sending timestamp.

4. The screen testing method according to claim 3, characterized in that, The nth slave control unit obtains the second transmission time value from the nth slave control unit to the corresponding signal conversion chip, including: The transmission time from the start of sending the test signal corresponding to the calibration test frame to the signal conversion chip from the nth slave control unit to the end of receiving the trigger signal sent by the signal conversion chip via GPIO is taken as the second transmission time value; wherein, the trigger signal is issued by the signal conversion chip when it receives the first valid pixel in the test signal corresponding to the calibration test frame.

5. The screen testing method according to claim 1, characterized in that, The master control unit generates first delay configuration parameters for each slave control unit based on the channel transmission time values ​​of all slave control units, including: The master control unit uses the maximum duration of the channel transmission time values ​​uploaded by all slave control units as the reference delay; For each slave control unit, a first delay configuration parameter corresponding to the slave control unit is generated based on the difference between the reference delay and the channel transmission time value of the slave control unit.

6. The screen testing method according to claim 5, characterized in that, The main control unit generates second delay configuration parameters corresponding to each of the signal conversion chips, including: For each slave control unit, the remaining delay is determined based on the difference between the reference delay and the channel transmission time of the slave control unit, and the delay amount corresponding to the first delay configuration parameter. The remaining delay amount is used to generate a second delay configuration parameter corresponding to the signal conversion chip connected to the slave control unit.

7. The screen testing method according to claim 1, characterized in that, In response to the synchronization trigger signal, each of the slave control units converts the image data signal into an image test signal, performs delay compensation according to the corresponding first delay configuration parameter, and synchronously outputs the image test signal, including: Upon receiving the synchronization trigger signal, the image data signal is converted into an image test signal, and the image test signal is delayed by a number of clock cycles according to the number of clock cycles indicated by the corresponding first delay configuration parameter before being output; wherein, the first clock cycle is the working clock cycle of the slave control unit.

8. The screen testing method according to claim 7, characterized in that, Upon receiving the image test signal, each of the signal conversion chips converts the image test signal into a screen drive signal, performs delay compensation according to the corresponding second delay configuration parameters, and then outputs the screen drive signal to the corresponding screen under test, including: After receiving the image test signal sent by the connected slave control unit, any of the signal conversion chips converts the image test signal into a screen drive signal, and outputs the screen drive signal to the corresponding screen under test after delaying it by a corresponding number of second clock cycles according to the number of clock cycles indicated by the corresponding second delay configuration parameter. Wherein, the second clock cycle is the working clock cycle of the signal conversion chip, and the delay compensation granularity corresponding to the signal conversion chip is smaller than the delay compensation granularity corresponding to the connected slave control unit.

9. The screen testing method according to any one of claims 1 to 8, characterized in that, The screen testing system also includes a host computer, and the method further includes: The main control unit receives the configuration parameters sent by the host computer and verifies the configuration parameters. The configuration parameters include at least the synchronization configuration parameters, which are used for delay configuration. The main control unit issues a delay calibration command, including: After the configuration parameters are verified, the configuration parameters are broadcast to each slave control unit, the delay calibration command is sent to each slave control unit, and the configuration parameters are stored in the memory of the master control unit.

10. A screen testing system, characterized in that, The screen testing system includes a main control unit, multiple slave control units, and signal conversion chips connected to each slave control unit. The main control unit is used to issue delay calibration commands; Each of the slave control units is used to respond to the delay calibration command, obtain its own channel transmission time value, and upload it to the master control unit; The master control unit is also used to generate and send a first delay configuration parameter corresponding to each slave control unit and a second delay configuration parameter corresponding to each signal conversion chip, based on the channel transmission time value of all slave control units. The main control unit is also used to send a synchronization trigger signal and an image data signal to each of the slave control units after the delay configuration is completed; Each of the slave control units is further configured to, in response to the synchronization trigger signal, convert the image data signal into an image test signal, and after performing delay compensation according to the corresponding first delay configuration parameter, synchronously output the image test signal; Each of the signal conversion chips is used to convert the image test signal into a screen driving signal when it receives the image test signal, and output the screen driving signal to the corresponding screen under test after performing delay compensation according to the corresponding second delay configuration parameters.

Images