Driver module, display panel and driving method

Abstract

This invention provides a driving module, a display panel, and a driving method. The driving module includes 2M clock signal lines, N start voltage terminals, and N driving modules; N is an integer greater than 1; M is a positive integer; the input terminal of the first i-th stage driving circuit of the nth driving module is electrically connected to the nth start voltage terminal to receive the nth start voltage; i is a positive integer; the reset terminal of the last j-th stage driving circuit of the nth driving module is electrically connected to the carry output terminal of the first j-th stage driving circuit of the (n+1)th driving module to receive the corresponding carry signal; or, the reset terminal of the last j-th stage driving circuit of the nth driving module is electrically connected to the frame reset terminal to receive the frame reset signal; j is a positive integer; n is a positive integer less than N. This invention can save power consumption.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a driving module, a display panel, and a driving method. Background Technology

[0002] Large-screen, high-refresh-rate TV designs have always been a key focus in the display industry and one of the current design challenges.

[0003] High refresh rate TV products suffer from short scan times (1H per line) and low TFT (thin-film transistor) mobility at low temperatures. Therefore, after a long cascading of GOA (Gate On Array) circuitry, it's difficult to pull the first node's first-order potential to the required voltage within the necessary timeframe. This often results in difficulties with low-temperature startup and insufficient VGH margin. Typically, even reaching maximum clock duty cycle is insufficient to meet product specifications, necessitating increasing the number of clock signal lines to extend the first-order charging time of the first node. However, increasing the number of clock signal lines often leads to increased power consumption. Summary of the Invention

[0004] The main objective of this invention is to provide a driving module, a display panel, and a driving method to solve the problems of not being able to achieve driving partitioning and not being able to save power in related technologies.

[0005] In one aspect, embodiments of the present invention provide a driving module, including 2M clock signal lines, N start voltage terminals, and N driving modules, each of the driving modules being electrically connected to the clock signal lines; N is an integer greater than 1; M is a positive integer; each driving module includes multiple cascaded driving circuits; each driving circuit includes an input terminal, a reset terminal, and a carry output terminal;

[0006] The input terminal of the first i-th stage drive circuit included in the nth drive module is electrically connected to the nth starting voltage terminal, and receives the nth starting voltage provided by the nth starting voltage terminal; i is a positive integer;

[0007] The reset terminal of the last j-stage driving circuit included in the nth driving module is electrically connected to the carry output terminal of the first j-stage driving circuit included in the (n+1)th driving module, and receives the carry signal provided by the carry output terminal of the corresponding driving circuit; or, the reset terminal of the last j-stage driving circuit included in the nth driving module is electrically connected to the frame reset terminal, and receives the frame reset signal provided by the frame reset terminal; j is a positive integer.

[0008] n is a positive integer less than N.

[0009] In a second aspect, embodiments of the present invention provide a display panel including the aforementioned driving module; the display panel includes multiple columns of data lines and multiple rows of pixel circuits; the data lines and the pixel circuits are disposed in an effective display area;

[0010] The effective display area includes N display areas arranged along a first direction; N is an integer greater than 1; the first direction is the extension direction of the data line;

[0011] The multi-level driving circuit in the a-th driving module is used to provide driving signals to the multi-row pixel circuits set in the a-th display area respectively;

[0012] a is a positive integer less than or equal to N.

[0013] In a third aspect, embodiments of the present invention provide a driving method applied to the aforementioned driving module; the driving method includes:

[0014] The nth starting voltage terminal provides the nth starting voltage to the input terminal of the first i-th stage driving circuit included in the nth driving module;

[0015] The carry output terminal of the corresponding drive circuit included in the (n+1)th drive module provides a corresponding carry signal to the reset terminal of the last j-stage drive circuit included in the nth drive module; or, the frame reset terminal provides a frame reset signal to the reset terminal of the last j-stage drive circuit included in the nth drive module.

[0016] n is a positive integer less than N, N is an integer greater than 1; M is a positive integer, and i and j are positive integers.

[0017] The driving module, display panel, and driving method described in this embodiment of the invention can reduce power consumption and avoid unnecessary power waste. Attached Figure Description

[0018] Figure 1 This is a structural diagram of at least one embodiment of the driving circuit;

[0019] Figure 2 This is a circuit diagram of at least one embodiment of the driving circuit;

[0020] Figure 3A , Figure 3B This is a structural diagram of the first driving module and the second driving module of the driving module according to at least one embodiment of the present invention;

[0021] Figure 4 yes Figure 3A , Figure 3B The at least one embodiment shown in the figure, when in operation, includes the frame reset signal provided by the frame reset terminal STV0, the first start voltage provided by STV1, the second start voltage provided by STV2, and the waveforms of each clock signal.

[0022] Figure 5A , Figure 5B This is a structural diagram of the first driving module and the second driving module of the driving module according to at least one embodiment of the present invention;

[0023] Figure 6 yes Figure 5A , Figure 5B In at least one embodiment shown, during operation, the frame reset signal provided by the frame reset terminal STV0, the first start voltage provided by STV1, the second start voltage provided by STV2, and the waveforms of each clock signal are shown. Detailed Implementation

[0024] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0025] In all embodiments of this invention, the transistors used can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. In these embodiments, to distinguish between the two electrodes of the transistor other than the gate, one electrode is referred to as the first electrode, and the other as the second electrode.

[0026] In actual operation, when the transistor is a thin-film transistor or a field-effect transistor, the first electrode can be the drain and the second electrode can be the source; or, the first electrode can be the source and the second electrode can be the drain.

[0027] The driving module of at least one embodiment of the present invention includes 2M clock signal lines, N start voltage terminals and N driving modules, each of the driving modules being electrically connected to the clock signal lines; N is an integer greater than 1; M is a positive integer; the driving module includes multiple cascaded driving circuits; the driving circuit includes an input terminal, a reset terminal and a carry output terminal;

[0028] The input terminal of the first i-th stage drive circuit included in the nth drive module is electrically connected to the nth starting voltage terminal, and receives the nth starting voltage provided by the nth starting voltage terminal; i is a positive integer;

[0029] The reset terminal of the last j-stage driving circuit included in the nth driving module is electrically connected to the carry output terminal of the first j-stage driving circuit included in the (n+1)th driving module, and receives the carry signal provided by the carry output terminal of the corresponding driving circuit; or, the reset terminal of the last j-stage driving circuit included in the nth driving module is electrically connected to the frame reset terminal, and receives the frame reset signal provided by the frame reset terminal; j is a positive integer.

[0030] n is a positive integer less than N.

[0031] The driving module described in at least one embodiment of the present invention sets the driving module corresponding to the AA area (effective display area) to include N driving modules. The input terminal of the first i-stage driving circuit of each driving module is electrically connected to the corresponding starting voltage terminal, so as to enable the individual control of the driving signal output by each driving module.

[0032] In at least one embodiment of the present invention, the reset terminal of the last j-th stage drive circuit in the nth drive module can receive carry signals provided by the first j-th stage drive circuits included in the (n+1)th drive module, thereby enabling the complete cascaded operation of the entire drive module. This design reduces the number of input cascades for each drive module, and the more drive modules there are, the greater the reduction in the number of cascades. This significantly reduces the delay loss of carry signals in the cascade, significantly improving its low-temperature VGH margin, which is highly advantageous for the design of large-size high refresh rate display products. Alternatively...

[0033] In at least one embodiment of the present invention, the reset terminal of the last j-th stage driving circuit of the nth driving module is electrically connected to the frame reset terminal, and receives the frame reset signal provided by the frame reset terminal. That is, the frame reset signal provided by the frame reset terminal will reset the last j-th stage driving circuit of the non-end driving module, so that different driving modules are completely independent. The display of the display area corresponding to each driving module is independently controlled. When the screen is displayed in full screen, all starting voltage terminals are normally input with valid levels according to the timing. When the screen only involves the display or refresh of a part area, only the starting voltage terminal of the corresponding area is input with the starting voltage, which can reduce power consumption and avoid unnecessary power waste.

[0034] In at least one embodiment of the present invention, i=M, j=M+p;

[0035] p is a positive integer; M is a positive integer.

[0036] In at least one embodiment of the present invention, the driving module further includes a multi-level virtual driving circuit;

[0037] The reset terminal of the last j-stage drive circuit in the Nth drive module is electrically connected to the carry output terminal of the j-stage virtual drive circuit, and receives the carry signal provided by the carry output terminal of the corresponding virtual drive circuit.

[0038] In specific implementation, the driving module may also include multi-level virtual driving circuits. Each of the j-level virtual driving circuits can provide carry signals to the last j-level driving circuit of the last driving module included in the driving module, thereby realizing the complete cascade operation of the entire driving module.

[0039] In at least one embodiment of the present invention, the effective pulse widths of the starting voltages provided by the N starting voltage terminals are the same, and the effective pulse widths of the starting voltages are greater than the effective pulse widths of the clock signals provided by the clock signal lines, so that the first i-stage driving circuits included in the driving module can complete the input operation under the control of the corresponding starting voltages.

[0040] In at least one embodiment of the present invention, the driving circuit further includes an output clock signal terminal; a is a positive integer less than or equal to N; b is a positive integer; c is a positive integer;

[0041] The output clock signal terminal of the b-stage drive circuit included in the a-stage drive module is electrically connected to the c-stage clock signal line.

[0042] The carry output terminal of the b-th stage drive circuit included in the a-th drive module is electrically connected to the input terminal of the b+M-th stage drive circuit included in the a-th drive module.

[0043] When b is not divisible by 2M, c equals the remainder when b is divided by 2M; when b is divisible by 2M, c equals 2M.

[0044] For example, when M equals 6 and the driving module includes twelve clock signal lines, in the driving module, the output clock signal terminal of the q-th driving circuit is electrically connected to the q-th clock signal line, where q is a positive integer less than 12; the output clock signal terminal of the eleventh driving circuit is electrically connected to the twelfth clock signal line; and so on.

[0045] In at least one embodiment of the present invention, the reset terminal of the d-th stage driving circuit included in the a-th driving module is electrically connected to the carry output terminal of the d+j-th stage driving circuit included in the a-th driving module, and receives the carry signal provided by the carry output terminal of the d+j-th stage driving circuit included in the a-th driving module.

[0046] d is a positive integer; d is less than Rj; R is a positive integer, and R is the number of stages of the drive circuit included in the a-th drive module.

[0047] For example, when M equals 6, j can be 8; in the driving module, the carry output terminal of the first-stage driving circuit is electrically connected to the input terminal of the seventh-stage driving circuit, the carry output terminal of the ninth-stage driving circuit is electrically connected to the reset terminal of the first-stage driving circuit, the duty cycle of each clock signal can be 50%, and the reset is delayed by 2H (two lines of scanning time).

[0048] In at least one embodiment of the present invention, the driving circuit further includes a driving output terminal;

[0049] The driving circuit includes driving output terminals that are electrically connected to the corresponding scan lines, and are used to provide scanning signals to the scan lines.

[0050] In at least one embodiment of the present invention, the driving circuit includes an input circuit, a reset circuit, a second node control circuit, a carry output circuit, a drive output circuit, and an energy storage circuit.

[0051] The input circuit is electrically connected to the input terminal and the first node respectively, and is used to control the potential of the first node according to the input signal provided by the input terminal;

[0052] The reset circuit is electrically connected to the reset terminal, the first node, and the first voltage terminal, respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the reset signal provided by the reset terminal;

[0053] The second node control circuit is electrically connected to the control voltage terminal, the first node, and the second node, respectively, and is used to control the potential of the second node under the control of the control voltage provided by the control voltage terminal and the potential of the first node.

[0054] The carry-out circuit is electrically connected to the output clock signal terminal, the first node, the second node, the first voltage terminal, and the carry-out terminal, respectively. It is used to control the connection between the output clock signal terminal and the carry-out terminal under the control of the potential of the first node, and to control the connection between the carry-out terminal and the first voltage terminal under the control of the potential of the second node.

[0055] The drive output circuit is electrically connected to the output clock signal terminal, the first node, the second node, the second voltage terminal, and the drive output terminal, respectively. It is used to control the connection between the output clock signal terminal and the drive output terminal under the control of the potential of the first node, and to control the connection between the drive output terminal and the second voltage terminal under the control of the potential of the second node.

[0056] The first end of the energy storage circuit is electrically connected to the first node, and the second end of the energy storage circuit is electrically connected to the drive output end.

[0057] Optionally, the first voltage terminal can be a first low voltage terminal, and the second voltage terminal can be a second low voltage terminal.

[0058] In at least one embodiment of the present invention, the second node may include a first second node and a second second node, and the control voltage terminal may include a first control voltage terminal and a second control voltage terminal.

[0059] In at least one embodiment of the present invention, the driving circuit further includes a first node reset circuit;

[0060] The first node reset circuit is electrically connected to the frame reset terminal, the first node, and the first voltage terminal, respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the frame reset signal provided by the frame reset terminal.

[0061] like Figure 1 As shown, the driving circuit includes an input circuit 11, a reset circuit 12, a second node control circuit 13, a carry output circuit 14, a drive output circuit 15, an energy storage circuit 10, and a first node reset circuit 16.

[0062] The input circuit 11 is electrically connected to the input terminal IS and the first node PU respectively, and is used to control the potential of the first node PU according to the input signal provided by the input terminal IS;

[0063] The reset circuit 12 is electrically connected to the reset terminal RST, the first node PU, and the first voltage terminal V1, respectively, and is used to control the connection between the first node PU and the first voltage terminal V1 under the control of the reset signal provided by the reset terminal RST.

[0064] The second node control circuit 13 is electrically connected to the first control voltage terminal VDD1, the second control voltage terminal VDD2, the first node, the first second node PD1, and the second second node PD2, respectively. It is used to control the potential of the first second node PD1 under the control of the first control voltage provided by the first control voltage terminal VDD1 and the potential of the first node PU1, and to control the potential of the second second node PD2 under the control of the second control voltage provided by the second control voltage terminal VDD2 and the potential of the first node PU1.

[0065] The carry output circuit 14 is electrically connected to the output clock signal terminal CLKO, the first node PU, the first second node PD1, the second second node PD2, the first voltage terminal V1, and the carry output terminal GC, respectively. It is used to control the connection between the output clock signal terminal CLKO and the carry output terminal GC under the control of the potential of the first node PU, control the connection between the carry output terminal GC and the first voltage terminal V1 under the control of the potential of the first second node PD1, and control the connection between the carry output terminal GC and the first voltage terminal V1 under the control of the potential of the second second node PD2.

[0066] The drive output circuit 15 is electrically connected to the output clock signal terminal CLKO, the first node PU, the first second node PD1, the second second node PD2, the second voltage terminal V2, and the drive output terminal GT, respectively. It is used to control the connection between the output clock signal terminal CLKO and the drive output terminal GT under the control of the potential of the first node PU, control the connection between the drive output terminal GT and the second voltage terminal V2 under the control of the potential of the first second node PD1, and control the connection between the drive output terminal GT and the second voltage terminal V2 under the control of the potential of the second second node PD2.

[0067] The first end of the energy storage circuit 10 is electrically connected to the first node PU, and the second end of the energy storage circuit 10 is electrically connected to the drive output terminal GT.

[0068] The first node reset circuit 16 is electrically connected to the frame reset terminal STV0, the first node PU, and the first voltage terminal V1, respectively, and is used to control the connection between the first node PU and the first voltage terminal V1 under the control of the frame reset signal provided by the frame reset terminal STV0.

[0069] like Figure 2 As shown, the input circuit includes a first transistor M1; the gate and source of M1 are electrically connected to the input terminal IS, and the drain of M1 is electrically connected to the first node PU.

[0070] The reset circuit includes a second transistor M2; the gate of M2 is electrically connected to RST, the source of M2 is electrically connected to PU, and the drain of M2 is electrically connected to the first low voltage terminal LVSS.

[0071] The second node control circuit includes a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, and a tenth transistor M10.

[0072] The gate and source of M3 are electrically connected to VDD1, and the drain of M3 is electrically connected to the gate of M5.

[0073] The gate of M4 is electrically connected to PU, the source of M4 is electrically connected to the gate of M5, and the drain of M4 is electrically connected to LVSS.

[0074] The source of M5 is electrically connected to VDD1, and the drain of M5 is electrically connected to PD1.

[0075] The gate of M6 is electrically connected to PU, the source of M6 is electrically connected to PD1, and the drain of M6 is electrically connected to LVSS.

[0076] The gate and source of M7 are electrically connected to VDD2, and the drain of M7 is electrically connected to the gate of M9.

[0077] The gate of M8 is electrically connected to PU, the source of M8 is electrically connected to the gate of M9, and the drain of M8 is electrically connected to LVSS.

[0078] The source of M9 is electrically connected to VDD2, and the drain of M9 is electrically connected to PD2.

[0079] The gate of M10 is electrically connected to PU, the source of M10 is electrically connected to PD2, and the drain of M10 is electrically connected to LVSS.

[0080] The carry-out circuit includes an eleventh transistor M11, a twelfth transistor M12, and a thirteenth transistor M13;

[0081] The gate of M11 is electrically connected to PU, the source of M11 is electrically connected to CLKO, and the drain of M11 is electrically connected to GC.

[0082] The gate of M12 is electrically connected to PD1, the source of M12 is electrically connected to GC, and the drain of M12 is electrically connected to LVSS.

[0083] The gate of M13 is electrically connected to PD2, the source of M13 is electrically connected to GC, and the drain of M13 is electrically connected to LVSS.

[0084] The drive output circuit includes a fourteenth transistor M14, a fifteenth transistor M15, and a sixteenth transistor M16;

[0085] The gate of M14 is electrically connected to PU, the source of M14 is electrically connected to CLKO, and the drain of M14 is electrically connected to GT.

[0086] The gate of M15 is electrically connected to PD1, the source of M15 is electrically connected to GT, and the drain of M15 is electrically connected to the second low voltage terminal VSS.

[0087] The gate of M16 is electrically connected to PD2, the source of M16 is electrically connected to GT, and the drain of M16 is electrically connected to the second low voltage terminal VSS.

[0088] The first node reset circuit includes the seventeenth transistor M17;

[0089] The gate of M17 is electrically connected to STV0, the source of M17 is electrically connected to PU, and the drain of M17 is electrically connected to LVSS.

[0090] The first node reset circuit may further include an eighteenth transistor M18 and a nineteenth transistor M19;

[0091] The gate of M18 is electrically connected to PD1, the source of M18 is electrically connected to PU, and the drain of M18 is electrically connected to LVSS.

[0092] The gate of M19 is electrically connected to PD2, the source of M19 is electrically connected to PU, and the drain of M19 is electrically connected to LVSS.

[0093] The energy storage circuit includes a storage capacitor C0;

[0094] The first end of C0 is electrically connected to PU, and the second end of C0 is electrically connected to GT.

[0095] exist Figure 2 In at least one embodiment shown, all transistors are n-type transistors.

[0096] exist Figure 2 In at least one of the embodiments shown, GC is used for cascading, and GT is used to provide scan signals for the corresponding row scan lines.

[0097] In at least one embodiment of the present invention, the overall concept of the GOA (Gate On Array, gate driving circuit disposed on array substrate) design is to divide the GOA Area (region) corresponding to the AA area (effective display area) into multiple groups. The input terminal of the first i-th stage driving circuit of the nth driving module is electrically connected to the nth starting voltage terminal, and receives the nth starting voltage provided by the nth starting voltage terminal. The different starting voltage terminals provide input signals to the first i-th stage driving circuit of each driving module to realize the individual control of the driving signal output by each driving module.

[0098] like Figure 3A , Figure 3B As shown, the driving module may include twelve clock signal lines, a first starting voltage terminal STV1, a second starting voltage terminal STV2, a first driving module 31, and a second driving module 32 (in this case, the display panel is divided into two areas, that is, the first area corresponds to the first driving module 31 and the first starting voltage terminal STV1, and the second area corresponds to the second driving module 32 and the second starting voltage terminal STV2. Optionally, this case may also set three areas, four areas, etc., with each area corresponding to its own driving module and starting voltage terminal, which is not limited here).

[0099] The first drive module includes a first-stage first drive circuit GA11, a second-stage first drive circuit GA21, a third-stage first drive circuit GA31, a fourth-stage first drive circuit GA41, a fifth-stage first drive circuit GA51, a sixth-stage first drive circuit GA61, a seventh-stage first drive circuit GA71, an eighth-stage first drive circuit GA81, a ninth-stage first drive circuit GA91, and so on, with the 1072nd stage first drive circuit GA10721, the 1073rd stage first drive circuit GA10731, the 1074th stage first drive circuit GA10741, the 1075th stage first drive circuit GA10751, the 1076th stage first drive circuit GA10761, the 1077th stage first drive circuit GA10771, the 1078th stage first drive circuit GA10781, the 1079th stage first drive circuit GA10791, and the 1080th stage first drive circuit GA10801.

[0100] The input terminals of GA11, GA21, GA31, GA41, GA51 and GA61 are electrically connected to the first starting voltage terminal STV1.

[0101] GA11 includes a first-stage first-carry output terminal GC11, which provides an input signal for GA71; GA21 includes a second-stage first-carry output terminal GC21, which provides an input signal for GA81.

[0102] GA91 includes the ninth stage first carry output terminal GC91, which provides a reset signal for GA11;

[0103] In the first drive module, the first six stages of the first drive circuit receive the first starting voltage provided by STV1. After the first starting voltage is input, the circuits are cascaded downwards. After the output reaches GA10801, the input signal is no longer transmitted downwards. The first eight stages of the second drive module provide reset signals to the last eight stages of the first drive circuit in the first drive module.

[0104] The ninth-stage first driver circuit includes a ninth-stage first carry output terminal GC91, which provides a reset signal to the reset terminal of GA11; the tenth-stage first driver circuit includes a tenth-stage first carry output terminal GC101, which provides a reset signal to the reset terminal of GA21; the eleventh-stage first driver circuit includes an eleventh-stage first carry output terminal GC111, which provides a reset signal to the reset terminal of GA31; the twelfth-stage first driver circuit includes a twelfth-stage first carry output terminal GC121, which provides a reset signal to the reset terminal of GA41; and the thirteenth-stage first driver circuit includes a thirteenth-stage first carry output terminal GC131. GC131 provides a reset signal to the reset terminal of GA51; the fourteenth-stage first drive circuit includes a fourteenth-stage first carry output terminal GC141, which provides a reset signal to the reset terminal of GA61; the fifteenth-stage first drive circuit includes a fifteenth-stage first carry output terminal GC151, which provides a reset signal to the reset terminal of GA71; the sixteenth-stage first drive circuit includes a sixteenth-stage first carry output terminal GC161, which provides a reset signal to the reset terminal of GA81; the seventeenth-stage first drive circuit includes a seventeenth-stage first carry output terminal GC171, which provides a reset signal to the reset terminal of GA91.

[0105] GA12 includes a first-stage second-carry output terminal GC12, which provides a reset signal for the first driver circuit GA10731 of the GA1073 stage; GA22 includes a second-stage second-carry output terminal GC22, which provides a reset signal for the first driver circuit GA10741 of the GA1074 stage; GA32 includes a third-stage second-carry output terminal GC32, which provides a reset signal for the first driver circuit GA10751 of the GA1075 stage; GA42 includes a fourth-stage second-carry output terminal GC42, which provides a reset signal for the first driver circuit GA10761 of the GA1076 stage. GA52 includes a fifth-stage second-carry output terminal GC52, which provides a reset signal for the first driver circuit GA10771 of the GA1077 stage; GA62 includes a sixth-stage second-carry output terminal GC62, which provides a reset signal for the first driver circuit GA10781 of the GA1078 stage; GA72 includes a seventh-stage second-carry output terminal GC72, which provides a reset signal for the first driver circuit GA10791 of the GA1079 stage; GA82 includes an eighth-stage second-carry output terminal GC82, which provides a reset signal for the first driver circuit GA10801 of the GA1080 stage.

[0106] The second drive module includes the first-stage second drive circuit GA12, the second-stage second drive circuit GA22, the third-stage second drive circuit GA32, the fourth-stage second drive circuit GA42, the fifth-stage second drive circuit GA52, the sixth-stage second drive circuit GA62, the seventh-stage second drive circuit GA72, the eighth-stage second drive circuit GA82, the ninth-stage second drive circuit GA92, and so on, with the 1072nd-stage second drive circuit GA10722, the 1073rd-stage second drive circuit GA10732, the 1074th-stage second drive circuit GA10742, the 1075th-stage second drive circuit GA10752, the 1076th-stage second drive circuit GA10762, the 1077th-stage second drive circuit GA10772, the 1078th-stage second drive circuit GA10782, the 1079th-stage second drive circuit GA10792, and the 1080th-stage second drive circuit GA10802.

[0107] The input terminals of GA12, GA22, GA32, GA42, GA52 and GA62 are electrically connected to the second starting voltage terminal STV2.

[0108] GA12 includes a first-stage second-carry output terminal GC12, which provides input signals for GA72; GA22 includes a second-stage second-carry output terminal GC22, which provides input signals for GA82.

[0109] GA92 includes the ninth stage second carry output terminal GC92, which provides a reset signal for GA12;

[0110] In the second drive module, the first six stages of the second drive circuit receive the second starting voltage provided by STV2, and after the second starting voltage is input, the circuit begins to be cascaded downwards.

[0111] exist Figure 3A , Figure 3BIn the illustrated embodiment, D-GC1 represents the first virtual carry output terminal of the first-stage virtual drive circuit, D-GC2 represents the second virtual carry output terminal of the second-stage virtual drive circuit, D-GC3 represents the third virtual carry output terminal of the third-stage virtual drive circuit, D-GC4 represents the fourth virtual carry output terminal of the fourth-stage virtual drive circuit, D-GC5 represents the fifth virtual carry output terminal of the fifth-stage virtual drive circuit, D-GC6 represents the sixth virtual carry output terminal of the sixth-stage virtual drive circuit, and D-GC7 represents the seventh virtual carry output terminal of the sixth-stage virtual drive circuit. The seventh virtual carry output terminal is included in the first-level virtual drive circuit, and the eighth virtual carry output terminal is included in the eighth-level virtual drive circuit, labeled D-GC8; D-GC1 provides a reset signal for GA10732, D-GC2 provides a reset signal for GA10742, D-GC3 provides a reset signal for GA10752, D-GC4 provides a reset signal for GA10762, D-GC5 provides a reset signal for GA10772, D-GC6 provides a reset signal for GA10782, D-GC7 provides a reset signal for GA10792, and D-GC8 provides a reset signal for GA10802.

[0112] exist Figure 3A , Figure 3B In at least one embodiment shown, the second GOA module is the final GOA module, and the reset terminal of the last eight-stage second driving circuit is electrically connected to the carry output terminal of the corresponding stage virtual driving circuit, thereby completing the cascading of the entire driving module. The above design can reduce the number of input cascades in each driving module, and the more driving modules there are, the more the number of cascades is reduced. This can significantly reduce the delay loss of the carry signal in the cascade and significantly improve its low-temperature VGH margin, which is very beneficial for the design of large-size high refresh rate display products.

[0113] exist Figure 3A , Figure 3B In the diagram, GCh1 is the carry output of GAh1, GTh1 is the drive output of GAh1, and h is a positive integer.

[0114] The terminal labeled GCk2 is the carry output terminal of GAk2, and the terminal labeled GTk2 is the drive output terminal of GAk2, where k is a positive integer.

[0115] exist Figure 3A , Figure 3B In at least one embodiment shown, the output clock signal terminal of the b-th stage first driving circuit is electrically connected to the c-th clock signal line; the output clock signal terminal of the b-th stage second driving circuit is electrically connected to the c-th clock signal line.

[0116] When b is not divisible by 12, c equals the remainder when b is divided by 12; when b is divisible by 12, c equals 12.

[0117] Figure 4 yes Figure 3A , Figure 3B In at least one embodiment shown, during operation, the frame reset signal provided by the frame reset terminal STV0, the first start voltage provided by STV1, the second start voltage provided by STV2, and the waveforms of each clock signal are shown.

[0118] exist Figure 4 In the diagram, CLK1, CLK2, CLK3, CLK4, CLK5, CLK6, CLK7, CLK8, CLK9, CLK10, CLK11, and CLK12 are respectively the first clock signal line, the second clock signal line, the third clock signal line, the fourth clock signal line, the fifth clock signal line, the sixth clock signal line, the seventh clock signal line, the eighth clock signal line, the ninth clock signal line, the tenth clock signal line, the eleventh clock signal line, and the twelfth clock signal line.

[0119] like Figure 4 As shown, Figure 3A , Figure 3B In at least one of the embodiments shown, to ensure GOA low-temperature reliability during operation, the first-order charging time of the first node of each row of drive circuits needs to be greater than or equal to 6H (1H is the scan time of one row). The input signals of the first six-stage drive circuits in each drive module are provided by the corresponding start voltage. The start time of the high-level pulse of the first start voltage provided by STV1 is 6H earlier than the start time of the first high-level pulse of CLK1, and the start time of the high-level pulse of the second start voltage provided by STV2 is 6H earlier than the start time of the corresponding high-level pulse of CLK1. Furthermore, since STV2 is not electrically connected to the first drive module, the high-level pulse of the second start voltage provided by STV2 will not affect the first drive module.

[0120] like Figure 4 As shown, the effective pulse width of the first starting voltage and the effective pulse width of the second starting voltage can be greater than or equal to 6H, and the effective pulse width of each clock signal can be 6H; optionally, the effective pulse width of the starting voltage corresponding to each partition can be equal and greater than the effective pulse width of each clock signal.

[0121] exist Figure 4 In the embodiment shown, the effective pulse width of the first starting voltage can be the duration of the high-level pulse of the first starting voltage, the effective pulse width of the second starting voltage can be the duration of the high-level pulse of the second starting voltage, and the effective pulse width of each clock signal can be the duration of the high-level pulse of each clock signal.

[0122] Figure 5A , Figure 5B At least one embodiment shown and Figure 3A , Figure 3B The difference between at least one embodiment shown is as follows: the reset terminal of the last eight stages of the first drive circuit included in the first drive module is electrically connected to the frame reset terminal STV0; in Figure 5A , Figure 5B In at least one embodiment shown, the first driving module and the second driving module are completely independent, and the potential of the first node of the tail driving circuit of the non-end driving module is reset by the frame reset terminal (e.g., Figure 5A The diagram illustrates two drive modules; the first drive module is the non-end-stage drive module. The potential of the first node of the tail-end drive circuit in the end-stage drive module is still reset by the carry-out output of the virtual drive circuit (e.g., Figure 5A The diagram illustrates two drive modules, with the second drive module being the end drive module.

[0123] exist Figure 5A , Figure 5B In at least one embodiment shown, there are two types of cascaded transistors in the first driving module. The gate of the transistor that resets the first node in the last eight stages of the first driving circuit of the first driving module is electrically connected to the frame reset terminal STV0. In addition to the last eight stages of the first driving circuit, the gate of the transistor that resets the first node in the other first driving circuits included in the first driving module is electrically connected to the carry output terminal of the corresponding stage of the first driving circuit.

[0124] Figure 5A , Figure 5B In at least one embodiment shown, when the output of the drive output terminal GT10801 of GA10801 ends after 2H, the potential of the frame reset signal provided by STV0 is pulled high, discharging the first node of the first drive circuit from the 1073rd stage to the first node of the first drive circuit from the 1080th stage. The input signals of the first six stages of the second drive circuit included in the second drive module are provided by the second starting voltage, and the cascade continues until the end.

[0125] Figure 6 yes Figure 5A , Figure 5B In at least one embodiment shown, during operation, the frame reset signal provided by the frame reset terminal STV0, the first start voltage provided by STV1, the second start voltage provided by STV2, and the waveforms of each clock signal are shown.

[0126] like Figure 6 As shown, Figure 5A , Figure 5BIn at least one embodiment shown, during operation, the high-level pulse of the clock signal connected to the first driving module and the high-level pulse of the clock signal connected to the second driving module are not continuous. That is, within one frame, each clock signal line stops and re-inputs a high-level pulse multiple times.

[0127] Two hours after the first drive circuit of the 1080th stage finishes outputting, STV0 goes high to discharge the first node of the last eight stages of the first drive circuit. Since the frame reset signal provided by STV0 is a signal shared by the first drive module and the second drive module, CLK1 starts to output a high-level pulse 11 hours after CLK12 finishes outputting the high-level pulse, ensuring that the normal cascading of each stage of the second drive circuit in the second drive module is not affected.

[0128] like Figure 6 As shown, Figure 5A , Figure 5B In at least one of the embodiments shown, during operation, after the first drive module stops outputting the corresponding drive signal, after STV0 outputs a high-level pulse, the potential of the second starting voltage provided by STV2 is pulled high for 6 hours, and then CLK1 restarts outputting a high-level pulse, and then the cascading proceeds normally until the end; during this period, the data voltage has already jumped to the 1081st line of data voltage, and then the clock is maintained until the output of the first-stage second drive circuit ends, and the subsequent data voltage jumps normally. If the frame reset signal connected to each drive module included in the drive module is different, then only the clock signal and data voltage need to be input normally and continuously.

[0129] In practical implementation, the AA area (effective display area) can be divided into multiple areas according to the GOA grouping scheme, and the display of each area is independently controlled. When the screen is displayed in full screen, all starting voltage terminals are input high level normally according to the timing sequence. When the screen only involves the display or refresh of a part of the area, only the starting voltage terminal of the corresponding area is input. In this way, power consumption can be reduced and unnecessary power waste can be avoided.

[0130] The embodiments of the present invention can improve the GOA reliability of TV products and enhance the low-temperature VGH margin of display products without increasing the process flow. Under the same circuit IC (integrated circuit) support capability, it can ensure the improvement of TV product specifications and enhance market competitiveness.

[0131] The display panel described in this embodiment of the invention includes the aforementioned driving module; the display panel includes multiple columns of data lines and multiple rows of pixel circuits; the data lines and the pixel circuits are disposed in the effective display area;

[0132] The effective display area includes N display areas arranged along a first direction; N is an integer greater than 1; the first direction is the extension direction of the data line;

[0133] The multi-level driving circuit in the a-th driving module is used to provide driving signals to the multi-row pixel circuits set in the a-th display area respectively;

[0134] a is a positive integer less than or equal to N.

[0135] The driving method described in this embodiment of the invention is applied to the aforementioned driving module; the driving method includes:

[0136] The nth starting voltage terminal provides the nth starting voltage to the input terminal of the first i-th stage driving circuit included in the nth driving module;

[0137] The carry output terminal of the corresponding drive circuit included in the (n+1)th drive module provides a corresponding carry signal to the reset terminal of the last j-stage drive circuit included in the nth drive module; or, the frame reset terminal provides a frame reset signal to the reset terminal of the last j-stage drive circuit included in the nth drive module.

[0138] n is a positive integer less than N, N is an integer greater than 1; M is a positive integer, and i and j are positive integers.

[0139] In at least one embodiment of the present invention, the reset terminal of the last j-stage driving circuit of the nth driving module is electrically connected to the carry output terminal of the first j-stage driving circuit of the (n+1)th driving module, and receives the carry signal provided by the carry output terminal of the corresponding driving circuit; the display cycle includes multiple display frames, the display frame includes N display stages set sequentially; the display stage includes input time period and output time period set sequentially.

[0140] The driving method includes:

[0141] During the display cycle, each clock signal line provides a corresponding clock signal;

[0142] During the nth input time period, the nth starting voltage terminal provides the nth starting voltage to the input terminal of the first i-th stage driving circuit included in the nth driving module;

[0143] During the nth output time period, each stage of the drive circuit in the nth drive module outputs the corresponding carry signal and drive signal according to the clock signal provided by the corresponding clock signal line.

[0144] During the (n+1)th input time period, the (n+1)th starting voltage terminal provides the (n+1)th starting voltage to the input terminal of the first i-th stage driving circuit included in the (n+1)th driving module;

[0145] During the (n+1)th output time period, each stage of the drive circuit in the (n+1)th drive module outputs the corresponding carry signal and drive signal according to the clock signal provided by the corresponding clock signal line.

[0146] During the (n+1)th output time period, when the carry output terminal of the first j-th stage drive circuit included in the (n+1)th drive module provides a valid reset signal to the last j-th stage drive circuit included in the nth drive module, the reset circuit in the last j-th stage drive circuit included in the nth drive module controls the potential of the corresponding first node to be reset under the control of the corresponding valid reset signal.

[0147] In at least one embodiment of the present invention, the display period includes a frame reset time period set between adjacent display frames, and the driving circuit further includes a first node reset circuit; the driving method further includes:

[0148] During the frame reset time period, the frame reset terminal provides a valid frame reset signal. Under the control of the frame reset signal, the first node reset circuit controls the connection between the first node and the first voltage terminal to reset the first node.

[0149] In at least one embodiment of the present invention, the reset terminal of the last j-stage driving circuit of the nth driving module is electrically connected to the frame reset terminal, and receives the frame reset signal provided by the frame reset terminal; the display period includes multiple display frames, and the display frame includes N display stages set sequentially; the nth display stage includes an nth input time period, an nth output time period, and an nth frame reset time period set sequentially; the driving method includes:

[0150] During the nth input time period, the nth starting voltage terminal provides the nth starting voltage to the input terminal of the first i-th stage driving circuit included in the nth driving module;

[0151] During the nth output time period, each stage of the drive circuit in the nth drive module outputs the corresponding carry signal and drive signal according to the clock signal provided by the corresponding clock signal line.

[0152] During the nth frame reset time period, the frame reset terminal provides a valid frame reset signal, and the last j-stage drive circuit included in the nth drive module resets the potential of the first node under the control of the frame reset signal.

[0153] In at least one embodiment of the present invention, the driving method includes:

[0154] During each output time period, each clock signal line provides the corresponding clock signal;

[0155] During each frame reset period and each input period, each clock signal line stops providing clock signals.

[0156] In at least one embodiment of the present invention, the driving module further includes a multi-level virtual driving circuit; the reset terminal of the last j-level driving circuit included in the Nth driving module is electrically connected to the carry output terminal of the corresponding virtual driving circuit, and receives the carry signal provided by the carry output terminal of the corresponding virtual driving circuit; the Nth display stage includes a sequentially set Nth input time period, Nth output time period, and Nth reset time period; the driving method includes:

[0157] During the Nth input time period, the Nth starting voltage terminal provides the Nth starting voltage to the input terminal of the first i-th stage driving circuit included in the Nth driving module;

[0158] During the Nth output time period, each stage of the drive circuit in the Nth drive module outputs the corresponding carry signal and drive signal according to the clock signal provided by the corresponding clock signal line.

[0159] During the Nth reset time period, when the carry output terminal of the corresponding virtual drive circuit in the multi-level virtual drive circuit provides a valid reset signal to the reset terminal of the last j-level drive circuit included in the Nth drive module, the reset circuit in the last j-level drive circuit included in the Nth drive module controls the potential of the corresponding first node to be reset under the control of the corresponding valid reset signal.

[0160] The above description represents the preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A driver module, characterized in that, It includes 2M clock signal lines, N start voltage terminals, and N drive modules, each of which is electrically connected to one of the clock signal lines; N is an integer greater than 1; M is a positive integer; each drive module includes multiple cascaded drive circuits; each drive circuit includes an input terminal, a reset terminal, and a carry output terminal; The input terminal of the first i-th stage driving circuit included in the nth driving module is electrically connected to the nth starting voltage terminal, and receives the nth starting voltage provided by the nth starting voltage terminal; i is a positive integer; The reset terminal of the last j-stage driving circuit included in the nth driving module is electrically connected to the carry output terminal of the first j-stage driving circuit included in the (n+1)th driving module, and receives the carry signal provided by the carry output terminal of the corresponding driving circuit; or, the reset terminal of the last j-stage driving circuit included in the nth driving module is electrically connected to the frame reset terminal, and receives the frame reset signal provided by the frame reset terminal; j is a positive integer. n is a positive integer less than N.

2. The driving module as described in claim 1, characterized in that, i=M, j=M+p; p is a positive integer; M is a positive integer.

3. The driving module as described in claim 1, characterized in that, The driving module also includes multi-level virtual driving circuits; The reset terminal of the last j-stage drive circuit in the Nth drive module is electrically connected to the carry output terminal of the j-stage virtual drive circuit, and receives the carry signal provided by the carry output terminal of the corresponding virtual drive circuit.

4. The driving module as described in claim 1, characterized in that, The effective pulse widths of the starting voltages provided by the N starting voltage terminals are the same, and the effective pulse width of the starting voltages is greater than the effective pulse width of the clock signal provided by the clock signal line.

5. The driving module as described in claim 1, characterized in that, The driving circuit also includes an output clock signal terminal; a is a positive integer less than or equal to N; b is a positive integer; c is a positive integer; The output clock signal terminal of the b-stage drive circuit included in the a-stage drive module is electrically connected to the c-stage clock signal line. The carry output terminal of the b-th stage drive circuit included in the a-th drive module is electrically connected to the input terminal of the b+M-th stage drive circuit included in the a-th drive module. When b is not divisible by 2M, c equals the remainder when b is divided by 2M; when b is divisible by 2M, c equals 2M.

6. The driving module as described in claim 5, characterized in that, The reset terminal of the d-th stage driving circuit included in the a-th driving module is electrically connected to the carry output terminal of the d+j-th stage driving circuit included in the a-th driving module, and receives the carry signal provided by the carry output terminal of the d+j-th stage driving circuit included in the a-th driving module. d is a positive integer; d is less than Rj; R is a positive integer, and R is the number of stages of the drive circuit included in the a-th drive module.

7. The driving module according to any one of claims 1 to 6, characterized in that, The driving circuit also includes a driving output terminal; The driving circuit includes driving output terminals that are electrically connected to the corresponding scan lines, and are used to provide scanning signals to the scan lines.

8. The driving module as described in claim 7, characterized in that, The driving circuit includes an input circuit, a reset circuit, a second node control circuit, a carry output circuit, a drive output circuit, and an energy storage circuit. The input circuit is electrically connected to the input terminal and the first node respectively, and is used to control the potential of the first node according to the input signal provided by the input terminal; The reset circuit is electrically connected to the reset terminal, the first node, and the first voltage terminal, respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the reset signal provided by the reset terminal; The second node control circuit is electrically connected to the control voltage terminal, the first node, and the second node, respectively, and is used to control the potential of the second node under the control of the control voltage provided by the control voltage terminal and the potential of the first node. The carry-out circuit is electrically connected to the output clock signal terminal, the first node, the second node, the first voltage terminal, and the carry-out terminal, respectively. It is used to control the connection between the output clock signal terminal and the carry-out terminal under the control of the potential of the first node, and to control the connection between the carry-out terminal and the first voltage terminal under the control of the potential of the second node. The drive output circuit is electrically connected to the output clock signal terminal, the first node, the second node, the second voltage terminal, and the drive output terminal, respectively. It is used to control the connection between the output clock signal terminal and the drive output terminal under the control of the potential of the first node, and to control the connection between the drive output terminal and the second voltage terminal under the control of the potential of the second node. The first end of the energy storage circuit is electrically connected to the first node, and the second end of the energy storage circuit is electrically connected to the drive output end.

9. The driving module as described in claim 8, characterized in that, The driving circuit also includes a first node reset circuit. The first node reset circuit is electrically connected to the frame reset terminal, the first node, and the first voltage terminal, respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the frame reset signal provided by the frame reset terminal.

10. A display panel, characterized in that, Includes the driving module as described in any one of claims 1 to 9; the display panel includes multiple columns of data lines and multiple rows of pixel circuits; the data lines and the pixel circuits are disposed in the effective display area; The effective display area includes N display areas arranged along a first direction; N is an integer greater than 1; the first direction is the extension direction of the data line; The multi-level driving circuit in the a-th driving module is used to provide driving signals to the multi-row pixel circuits set in the a-th display area respectively; a is a positive integer less than or equal to N.

11. A driving method, applied to the driving module as described in any one of claims 1 to 9; characterized in that, The driving method includes: The nth starting voltage terminal provides the nth starting voltage to the input terminal of the first i-th stage driving circuit included in the nth driving module; The carry output terminal of the corresponding drive circuit included in the (n+1)th drive module provides a corresponding carry signal to the reset terminal of the last j-stage drive circuit included in the nth drive module; or, the frame reset terminal provides a frame reset signal to the reset terminal of the last j-stage drive circuit included in the nth drive module. n is a positive integer less than N, N is an integer greater than 1; M is a positive integer, and i and j are positive integers.

12. The driving method as described in claim 11, characterized in that, The reset terminal of the last j-stage driving circuit in the nth driving module is electrically connected to the carry output terminal of the first j-stage driving circuit in the (n+1)th driving module, and receives the carry signal provided by the carry output terminal of the corresponding driving circuit; the display cycle includes multiple display frames, and the display frame includes N display stages set sequentially. The display phase includes sequentially set input time periods and output time periods; The driving method includes: During the display cycle, each clock signal line provides a corresponding clock signal; During the nth input time period, the nth starting voltage terminal provides the nth starting voltage to the input terminal of the first i-th stage driving circuit included in the nth driving module; During the nth output time period, each stage of the drive circuit in the nth drive module outputs the corresponding carry signal and drive signal according to the clock signal provided by the corresponding clock signal line. During the (n+1)th input time period, the (n+1)th starting voltage terminal provides the (n+1)th starting voltage to the input terminal of the first i-th stage driving circuit included in the (n+1)th driving module; During the (n+1)th output time period, each stage of the drive circuit in the (n+1)th drive module outputs the corresponding carry signal and drive signal according to the clock signal provided by the corresponding clock signal line. During the (n+1)th output time period, when the carry output terminal of the first j-th stage drive circuit included in the (n+1)th drive module provides a valid reset signal to the last j-th stage drive circuit included in the nth drive module, the reset circuit in the last j-th stage drive circuit included in the nth drive module controls the potential of the corresponding first node to be reset under the control of the corresponding valid reset signal.

13. The driving method as described in claim 12, characterized in that, The display period includes a frame reset time interval set between adjacent display frames; the driving circuit further includes a first node reset circuit; the driving method further includes: During the frame reset time period, the frame reset terminal provides a valid frame reset signal, and the first node reset circuit controls the connection between the first node and the first voltage terminal under the control of the frame reset signal.

14. The driving method as described in claim 11, characterized in that, The reset terminal of the last j-stage drive circuit in the nth drive module is electrically connected to the frame reset terminal and receives the frame reset signal provided by the frame reset terminal; the display cycle includes multiple display frames, and the display frame includes N display stages set sequentially. The nth display stage includes the nth input time period, the nth output time period, and the nth frame reset time period, which are set sequentially; the driving method includes: During the nth input time period, the nth starting voltage terminal provides the nth starting voltage to the input terminal of the first i-th stage driving circuit included in the nth driving module; During the nth output time period, each stage of the drive circuit in the nth drive module outputs the corresponding carry signal and drive signal according to the clock signal provided by the corresponding clock signal line. During the nth frame reset time period, the frame reset terminal provides a valid frame reset signal, and the last j-stage drive circuit included in the nth drive module resets the potential of the first node under the control of the frame reset signal.

15. The driving method as described in claim 14, characterized in that, The driving method includes: During each output time period, each clock signal line provides the corresponding clock signal; During each frame reset period and each input period, each clock signal line stops providing clock signals.

16. The driving method according to any one of claims 12 to 15, characterized in that, The drive module also includes a multi-level virtual drive circuit; the reset terminal of the last j-level drive circuit included in the Nth drive module is electrically connected to the carry output terminal of the corresponding virtual drive circuit, and receives the carry signal provided by the carry output terminal of the corresponding virtual drive circuit. The Nth display phase includes a sequentially set Nth input time period, Nth output time period, and Nth reset time period; the driving method includes: During the Nth input time period, the Nth starting voltage terminal provides the Nth starting voltage to the input terminal of the first i-th stage driving circuit included in the Nth driving module; During the Nth output time period, each stage of the drive circuit in the Nth drive module outputs the corresponding carry signal and drive signal according to the clock signal provided by the corresponding clock signal line. During the Nth reset time period, when the carry output terminal of the corresponding virtual drive circuit in the multi-level virtual drive circuit provides a valid reset signal to the reset terminal of the last j-level drive circuit included in the Nth drive module, the reset circuit in the last j-level drive circuit included in the Nth drive module controls the potential of the corresponding first node to be reset under the control of the corresponding valid reset signal.

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