The driving circuit and display panel of the display panel

Abstract

This application discloses a driving circuit and a display panel, belonging to the field of display technology. The input terminal of the driving circuit is electrically connected to the gate driving circuit of the display panel, and the output terminal is electrically connected to the pixel array of the display panel. The driving circuit is configured to reconstruct the gate driving signal output by the gate driving circuit at a preset signal reconstruction node to obtain a reconstructed signal, and then output the reconstructed signal to the pixel array. By configuring the driving circuit of the display panel, this application can reconstruct the gate driving signal output by the gate driving circuit after it reaches the preset signal reconstruction node, ensuring that all pixel units in the same row of the pixel array can receive a gate driving signal whose timing does not gradually decay with transmission distance. This fundamentally improves the technical problem of uneven charging in large-size display panels.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a driving circuit for a display panel and a display panel. Background Technology

[0002] In large-size display panels, the TFT (Thin Film Transistor) circuit is too large, and the GDL (Gate Driver Line) trace length increases significantly, leading to increased resistance. Furthermore, parasitic capacitance is formed between the GDL and adjacent data lines or common electrodes. The gate capacitance of each TFT becomes densely distributed as the resolution increases, and the total parasitic capacitance increases significantly with the number of pixels. Due to the large area of ​​RC (resistance-capacitance) circuitry, the timing of the gate drive signal gradually decays with the transmission distance, resulting in a severe deterioration of the waveform in the middle of the panel. This manifests as good signal quality and short waveform fall time at the edges of large-size panels, while the signal deteriorates significantly and the waveform fall time becomes longer in the middle of the panel. Therefore, the charging between the panel edges and the middle of the panel is uneven.

[0003] Currently, the common solution is to input the gate drive signal from both sides of the panel simultaneously, thereby reducing the signal attenuation caused by RC on the gate drive signal. However, the uneven charging phenomenon is still very obvious, and the problem of uneven charging cannot be solved at its root. Summary of the Invention

[0004] The main objective of this application is to provide a driving circuit and a display panel for a display panel, aiming to solve the technical problem of how to overcome the gradual attenuation of the timing of the in-plane gate driving signal with the transmission distance and improve the uneven charging of large-size display panels.

[0005] To achieve the above objectives, this application provides a driving circuit for a display panel. The input terminal of the driving circuit is electrically connected to the gate driving circuit of the display panel, and the output terminal is electrically connected to the pixel array of the display panel. The driving circuit is configured to reconstruct the gate driving signal output by the gate driving circuit at a preset signal reconstruction node to obtain a reconstructed signal, and output the reconstructed signal to the pixel array.

[0006] In one embodiment, the driving circuit of the display panel includes: An analog-to-digital converter module, wherein the input terminal of the analog-to-digital converter module is electrically connected to the gate drive circuit, and the analog-to-digital converter module is configured to convert the gate drive signal into a digital signal; A first signal reconstruction module is configured to perform signal reconstruction on the digital signal at the signal reconstruction node to obtain the reconstructed signal, and output the reconstructed signal to the pixel array.

[0007] In one embodiment, the analog-to-digital conversion module includes a plurality of analog-to-digital converters, the number of which is the same as the number of pixel rows in the pixel array.

[0008] In one embodiment, the pixel array is divided into multiple pixel blocks by column based on the signal reconstruction nodes, and the multiple pixel blocks are divided into multiple groups of pixel units by row based on the number of pixel rows; The first signal reconstruction module includes a plurality of first signal reconstruction units, and each first signal reconstruction unit is connected to at least one group of pixel units.

[0009] In one embodiment, the number of the first signal reconstruction units is the same as the number of groups of pixel units. The plurality of first signal reconstruction units are disposed in the pixel array, and each first signal reconstruction unit is connected to a group of pixel units. The first signal reconstruction unit includes: A digital-to-analog converter, wherein the input terminal of the digital-to-analog converter is electrically connected to the output terminal of the analog-to-digital conversion module, and the digital-to-analog converter is configured to convert the digital signal into an analog signal; A level converter, wherein the input terminal of the level converter is electrically connected to the output terminal of the digital-to-analog converter, and the output terminal of the level converter is electrically connected to the gate of the switching transistor of each pixel in the pixel unit, the level converter is configured to convert the analog signal into the reconstructed signal and output the reconstructed signal to the gate of each of the switching transistors.

[0010] In one embodiment, the number of the first signal reconstruction units is the same as the number of the signal reconstruction nodes. The plurality of first signal reconstruction units are disposed in the logic board of the display panel, and each first signal reconstruction unit is connected to one pixel block. The first signal reconstruction unit includes: A digital-to-analog converter, wherein the input terminal of the digital-to-analog converter is electrically connected to the output terminal of the analog-to-digital conversion module, and the digital-to-analog converter is configured to convert the digital signal into an analog signal; A level converter, wherein the input terminal of the level converter is electrically connected to the output terminal of the digital-to-analog converter, and the level converter is configured to convert the analog signal into the reconstructed signal; A multiplexer, wherein the input terminal of the multiplexer is electrically connected to the output terminal of the level converter, and the output terminal of the multiplexer is electrically connected to the controlled terminal of each pixel unit in the pixel block, and the multiplexer is configured to output the reconstruction signal to the gate of the switching transistor of each pixel in the pixel unit of the corresponding pixel row.

[0011] In one embodiment, the pixel array is divided into multiple pixel blocks by column based on the signal reconstruction node, and the multiple pixel blocks are divided into multiple groups of pixel units by row based on the number of pixel rows of the pixel array. The controlled terminal of the first group of pixel units in each row is electrically connected to the output terminal of the gate driving circuit. The driving circuit of the display panel includes a plurality of second signal reconstruction units disposed in the pixel array, wherein the number of the second signal reconstruction units is the product of the number of signal reconstruction nodes and the number of pixel rows; Each of the second signal reconstruction units is connected between two adjacent groups of pixel units in the same row. The first end of each of the second signal reconstruction units is electrically connected to the controlled end of the preceding group of pixel units, and the second end of each of the second signal reconstruction units is electrically connected to the controlled end of the following group of pixel units. The third terminal of each second signal reconstruction unit is connected to a gate high voltage from the logic board of the display panel, and the fourth terminal of each second signal reconstruction unit is connected to a gate low voltage from the logic board. Each second signal reconstruction unit is configured to output the gate high voltage as the reconstruction signal to the next group of pixel units, or to output the gate low voltage to the next group of pixel units.

[0012] In one embodiment, the second signal reconstruction unit includes an NMOS transistor and a PMOS transistor. The gates of the NMOS transistor and the PMOS transistor are connected together as a first terminal of the second signal reconstruction unit. The sources of the NMOS transistor and the PMOS transistor are connected together as a second terminal of the second signal reconstruction unit. The drain of the NMOS transistor is a third terminal of the second signal reconstruction unit, and the drain of the PMOS transistor is a fourth terminal of the second signal reconstruction unit.

[0013] In one embodiment, when a high-level signal is received at the first terminal of the second signal reconstruction unit, the NMOS transistor is turned on and the PMOS transistor is turned off, and the second signal reconstruction unit outputs the high gate voltage as the reconstruction signal to the next group of pixel units; When a low-level signal is received at the first terminal of the second signal reconstruction unit, the NMOS transistor is turned off and the PMOS transistor is turned on, and the second signal reconstruction unit outputs the low gate voltage to the next group of pixel units.

[0014] In addition, to achieve the above objectives, this application embodiment also provides a display panel, the display panel including: a gate driving circuit, a pixel array and a driving circuit of the display panel as described above, the gate driving circuit being electrically connected to the pixel array and the driving circuit of the display panel, the gate driving signal output by the gate driving circuit being directly provided to the pixel array, or being output to the pixel array by the driving circuit of the display panel after signal reconstruction at a preset signal reconstruction node.

[0015] This application provides a driving circuit for a display panel and a display panel in its embodiments. The input terminal of the driving circuit is electrically connected to the gate driving circuit of the display panel, and the output terminal is electrically connected to the pixel array of the display panel. The driving circuit is configured to reconstruct the gate driving signal output by the gate driving circuit at a preset signal reconstruction node to obtain a reconstructed signal, and then output the reconstructed signal to the pixel array. By setting the driving circuit between the gate driving circuit and the pixel array, this application reconstructs the gate driving signal output by the gate driving circuit after it reaches the preset signal reconstruction node. This allows the reconstructed gate driving signal to continue transmitting a certain distance without attenuation until it reaches the next signal reconstruction node for reconstructing again. This ensures that all pixel units in the same row of the pixel array can receive a gate driving signal whose timing does not gradually attenuate with the transmission distance, avoiding the phenomenon that the signal quality is good at the edge of the panel but the signal deteriorates severely in the middle of the panel. This fundamentally improves the technical problem of uneven charging in large-size display panels. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only a part of the embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the GDL and display panel circuit layout provided in an embodiment of this application; Figure 2 A schematic diagram illustrating the principle of uneven charging of the display panel due to large-area RC, provided for an embodiment of this application; Figure 3 This is a schematic diagram comparing signals caused by uneven charging of the display panel due to large-area RC, provided as an embodiment of this application. Figure 4 This is a schematic diagram illustrating the signal principle that causes uneven charging of the display panel, provided in an embodiment of this application. Figure 5 A schematic diagram illustrating the connection relationship between the driving circuit of a display panel and other components in the display panel, provided for an embodiment of this application; Figure 6 A waveform diagram of the in-line gate drive signal of a 50-inch display panel provided for an embodiment of this application; Figure 7 A waveform diagram of the in-line gate drive signal of an 85-inch display panel provided for an embodiment of this application; Figure 8 A schematic diagram illustrating the location of a signal reconstruction node as provided in an embodiment of this application; Figure 9 A schematic diagram of the layout structure of the analog-to-digital conversion module and the first signal reconstruction module in the driving circuit of a display panel provided in an embodiment of this application; Figure 10 A schematic diagram of the structure of an analog-to-digital conversion module involved in the driving circuit of a display panel provided in an embodiment of this application; Figure 11 A schematic diagram of the structure of a first signal reconstruction module and a pixel array involved in a driving circuit for a display panel provided in an embodiment of this application; Figure 12 A schematic diagram of the layout structure of a first signal reconstruction unit involved in a driving circuit for a display panel provided in an embodiment of this application; Figure 13 A schematic diagram of the layout structure of another first signal reconstruction unit involved in a driving circuit for a display panel provided in an embodiment of this application; Figure 14 A schematic diagram of the layout structure of the second signal reconstruction unit relative to the pixel array in a driving circuit of a display panel provided in an embodiment of this application; Figure 15 This is a schematic diagram of the layout structure of the second signal reconstruction unit involved in the driving circuit of a display panel provided in an embodiment of this application.

[0018] The realization of the objectives, functional features and advantages of the embodiments of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings.

[0019] Explanation of icon numbers: 10. Analog-to-digital conversion module; 11. First signal reconstruction module; ADC (Analog-to-digital converter); DAC (Digital-to-analog converter); LS (Level converter); PM (Multiplexer); 12. Second signal reconstruction unit; Q1 (NMOS transistor); Q2 (PMOS transistor); VGH (Gate high voltage); VGL (Gate low voltage). Detailed Implementation

[0020] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that the embodiments of this application can also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods are omitted so as not to obscure the description of the embodiments of this application with unnecessary detail.

[0021] With the development of display technology, small-sized display panels can no longer meet people's needs. In recent years, large-sized display panels have emerged one after another, such as 85-inch and larger display panels, which have become a hot demand. However, large-sized display panels all have a fatal problem, namely uneven charging. This is because the TFT (Thin Film Transistor) circuits in large-sized display panels are too large, and the GDL (Gate Driver Line) trace length increases significantly, resulting in increased resistance. Furthermore, parasitic capacitance is formed between the GDL and adjacent data lines or common electrodes. The gate capacitance of each TFT becomes denser as the resolution increases, and the total parasitic capacitance increases significantly with the number of pixels. Due to the large area of ​​RC (resistance and capacitance), the timing of the gate drive signal gradually decays with the transmission distance, causing its waveform to deteriorate drastically in the middle of the panel. The phenomenon is that the signal quality is good and the waveform fall time is short at the edges of the large-sized panel, while the signal deteriorates severely and the waveform fall time becomes longer in the middle of the panel. Figures 1 to 3 As shown. This is equivalent to the pulse width of the gate drive signal in the same row gradually widening as it penetrates deeper into the plane, while the data signal is transmitted via differential pairs and through the source drive circuit into the plane. Therefore, the waveform of the data signal is fixed, as shown. Figure 4 As shown. Currently, the common solution is to input the gate drive signal from both sides of the panel simultaneously, thereby reducing the signal attenuation caused by RC on the gate drive signal. However, the uneven charging phenomenon is still very obvious, and the problem of uneven charging cannot be solved at its root.

[0022] Based on this, this application provides a driving circuit and a display panel for a display panel. By setting the driving circuit of the display panel between the gate driving circuit and the pixel array, the gate driving signal output by the gate driving circuit is reconstructed after reaching a preset signal reconstruction node. This allows the reconstructed gate driving signal to continue transmitting for a certain distance without time decay until it reaches the next signal reconstruction node for reconstructing again. As a result, all pixel units in the same row of the pixel array can receive a gate driving signal whose time decay does not gradually decrease with the transmission distance. This avoids the phenomenon that the signal quality at the edge of the panel is good, but the signal in the middle of the panel deteriorates severely. This fundamentally improves the technical problem of uneven charging in large-size display panels.

[0023] The driving circuit and display panel of the display panel provided in this application embodiment are specifically described through the following embodiments. First, the driving circuit of the display panel in this application embodiment is described.

[0024] This application provides a driving circuit for a display panel, referring to... Figure 5 , Figure 5 This is a schematic diagram of the structure of a driving circuit for a display panel provided in an embodiment of this application. In this embodiment, the input terminal of the driving circuit for the display panel is electrically connected to the gate driving circuit of the display panel, and the output terminal of the driving circuit for the display panel is electrically connected to the pixel array of the display panel. The driving circuit for the display panel is configured to perform signal reconstruction on the gate driving signal output by the gate driving circuit at a preset signal reconstruction node to obtain a reconstruction signal, and output the reconstruction signal to the pixel array.

[0025] In this embodiment, to prevent the gate drive signal provided by the gate drive circuit of the display panel to the display panel from gradually attenuating with the transmission distance, the gate drive signal can be reconstructed after entering the display panel or transmitting a certain distance. This allows the reconstructed gate drive signal to still transmit a certain distance without timing attenuation. Then, a signal reconstruction node is set on the transmission path of the gate drive signal, and the drive circuit of the display panel is deployed at the signal reconstruction node to reconstruct the gate drive signal. This ensures that the gate drive signals received by the pixel arrays before and after the signal reconstruction node remain consistent.

[0026] As an example, in this embodiment, the transmission distance of the gate drive signal without timing decay can be pre-estimated based on the actual in-plane RC loading (resistive-capacitive load). Generally, it is related to the size of the display panel; the larger the display panel, the greater the RC loading, and the more signal reconstruction nodes need to be set. In practical applications, adjustments need to be made according to the attenuation degree of the gate drive signal, referring to... Figure 6 , Figure 6 The diagram shows the gate drive signal waveforms corresponding to the same row of pixels in a 50-inch display panel with gate lineloading of R=4.2KΩ and C=840pF. Figure 6 As can be seen, the quality of the signal waveforms later in the same row deteriorates slightly, as shown in the reference. Figure 7 The same waveform difference will be more noticeable on panels 85 inches or larger.

[0027] As an example, this embodiment provides, for instance, the following: Figure 8The diagram shows the setting position of a signal reconstruction node. In practical applications, the setting interval of the signal reconstruction node can be estimated by analyzing the RC loading of the display panel; or it can be analyzed by measuring the waveform of the gate drive signal. As long as the signal reconstruction node is added before the waveform deteriorates, it can be ensured that the subsequent pixel array can still receive the gate drive signal without attenuation.

[0028] Reference Figure 9 In some feasible embodiments, the driving circuit of the above-mentioned display panel may include: The analog-to-digital converter module 10 has its input terminal electrically connected to the gate drive circuit of the display panel. The analog-to-digital converter module 10 is configured to convert the gate drive signal into a digital signal. The first signal reconstruction module 11 has its input terminal electrically connected to the output terminal of the analog-to-digital conversion module 10, and its output terminal electrically connected to the pixel array. The first signal reconstruction module 11 is configured to reconstruct the digital signal at the signal reconstruction node to obtain the reconstructed signal, and output the reconstructed signal to the pixel array.

[0029] In this embodiment, the gate drive signal generated by the gate drive circuit can be converted into a digital signal before entering the input plane by setting the analog-to-digital conversion module 10. A set of levels is preset according to the adjustment range of the gate high voltage VGH, and the gate drive signal is transmitted into the plane in the form of a digital signal. Then, at a fixed interval in the plane, i.e. at the signal reconstruction node, the digital signal of different levels is converted into an analog signal by the first signal reconstruction module 11 and then applied to the pixel array.

[0030] Reference Figure 10 In some feasible embodiments, the analog-to-digital conversion module 10 includes a plurality of analog-to-digital converters (ADCs), the number of which is the same as the number of pixel rows in the pixel array.

[0031] In this embodiment, the display panel generally adopts a row-by-row driving method to input gate driving signals to the in-plane row by row through the gate driving circuit. Therefore, for the gate driving signals of different rows, corresponding analog-to-digital converters (ADCs) are required for signal conversion. Thus, the analog-to-digital conversion module 10 contains an ADC with the same number as the number of pixel rows.

[0032] Reference Figure 11 In some feasible embodiments, the pixel array is divided into multiple pixel blocks by column based on the signal reconstruction nodes, and the multiple pixel blocks are divided into multiple groups of pixel units by row based on the number of pixel rows; The first signal reconstruction module 11 includes multiple first signal reconstruction units, each of which is connected to at least one set of pixel units.

[0033] In this embodiment, considering that the transmission line used to transmit the gate drive signal is long when the display panel is large, setting only one signal reconstruction node may not be enough to ensure that the gate drive signal will not attenuate in the subsequent transmission path. Therefore, setting multiple signal reconstruction nodes is equivalent to dividing the pixel array into multiple pixel blocks by column at the location of each signal reconstruction node, and then dividing the pixels in the same row of each pixel block into multiple groups of pixel units. The number of pixels included in a group of pixel units can be flexibly adjusted according to actual needs, and this embodiment does not limit this.

[0034] Meanwhile, in this embodiment, at least one first signal reconstruction unit is configured for each signal reconstruction node, so that the first signal reconstruction unit can provide reconstruction signals to at least one group of pixel units corresponding to it.

[0035] As an example, each signal reconstruction node can correspond to multiple signal reconstruction units, such that the number of signal reconstruction units is the same as the number of groups of pixel units. In this case, each first signal reconstruction unit only needs to provide reconstruction signals to the corresponding group of pixel units. Alternatively, each signal reconstruction node can correspond to only one first signal reconstruction unit. In this case, the first signal reconstruction unit can be used to provide reconstruction signals for the corresponding row to multiple groups of pixel units in a pixel block.

[0036] Reference Figure 12 In some feasible embodiments, the number of first signal reconstruction units is the same as the number of pixel unit groups. Multiple first signal reconstruction units are arranged in the pixel array, and each first signal reconstruction unit is connected to a corresponding group of pixel units. The first signal reconstruction unit may include: The digital-to-analog converter (DAC) has its input terminal electrically connected to the output terminal of the analog-to-digital converter module 10. The DAC is configured to convert digital signals into analog signals. The level converter LS has its input terminal electrically connected to the output terminal of the digital-to-analog converter DAC, and its output terminal electrically connected to the gate of the switching transistor of each pixel in the pixel unit. The level converter LS is configured to convert the analog signal into a reconstructed signal and output the reconstructed signal to the gate of each switching transistor.

[0037] In this embodiment, the first signal reconstruction unit may include a digital-to-analog converter (DAC) and a level shifter (LS) added in the plane. Although the DAC can convert digital signals into analog signals, the output voltage of common DACs is 0 to 10V, which cannot meet the amplitude requirements of the gate drive signal. Therefore, a level shifter (LS) is added after the DAC to perform voltage conversion. Since discrete 0s and 1s in digital signals represent information, the influence of RC on high and low levels on the large-size in-plane path can be filtered out by a threshold, ensuring high-quality propagation of the gate drive signal, thereby solving the problem of uneven charging in the plane from the root.

[0038] Reference Figure 13 In some feasible embodiments, the number of first signal reconstruction units is the same as the number of signal reconstruction nodes. Multiple first signal reconstruction units are disposed in the logic board of the display panel, and each first signal reconstruction unit is connected to a corresponding pixel block. The first signal reconstruction unit may include: The digital-to-analog converter (DAC) has its input terminal electrically connected to the output terminal of the analog-to-digital converter module 10. The DAC is configured to convert digital signals into analog signals. The level converter LS is electrically connected to the output of the digital-to-analog converter DAC. The level converter LS is configured to convert analog signals into reconstructed signals. The input of the multiplexer PM is electrically connected to the output of the level converter LS, and the output of the multiplexer PM is electrically connected to the controlled terminal of each pixel unit in the pixel block. The multiplexer PM is configured to output the reconstruction signal to the gate of the switching transistor of each pixel in the pixel unit of the corresponding pixel row.

[0039] In this embodiment, each first signal reconstruction unit may include a digital-to-analog converter (DAC), a level converter (LS), and a multiplexer (PM) (PinMux) integrated on the logic board XB of the display panel. These units are connected to the TFT circuitry of each row of pixels in the corresponding pixel block via data lines. The first signal reconstruction unit, composed of one or more sets of DACs and LSs, can output the converted reconstructed signal to each row of pixels. This approach ensures high-quality digital signal transmission while avoiding overly complex circuitry in the in-plane pixel array, demonstrating good feasibility. Furthermore, considering that the gate driving timing of each row of pixels is different, a multiplexer (PM) can be added to control the reconstructed signal output from the DAC and LS combination on the logic board, ensuring that the reconstructed signal is input to the correct pixel row.

[0040] Reference Figure 14 In some feasible embodiments, the pixel array is divided into multiple pixel blocks by column based on the signal reconstruction nodes, and the multiple pixel blocks are divided into multiple groups of pixel units by row based on the number of pixel rows in the pixel array. The controlled terminal of the first group of pixel units in each row is electrically connected to the output terminal of the gate drive circuit. The driving circuit of the display panel includes a plurality of second signal reconstruction units 12 disposed in the pixel array, the number of second signal reconstruction units 12 being the product of the number of signal reconstruction nodes and the number of pixel rows; Each second signal reconstruction unit 12 is connected between two adjacent groups of pixel units in the same row. The first end of each second signal reconstruction unit 12 is electrically connected to the controlled end of the previous group of pixel units, and the second end of each second signal reconstruction unit 12 is electrically connected to the controlled end of the next group of pixel units. The third terminal of each second signal reconstruction unit 12 is connected to the gate high voltage VGH from the logic board of the display panel, and the fourth terminal of each second signal reconstruction unit 12 is connected to the gate low voltage VGL from the logic board. Each second signal reconstruction unit 12 is configured to output the gate high voltage VGH as a reconstruction signal to the next group of pixel units, or to output the gate low voltage VGL to the next group of pixel units.

[0041] In this embodiment, considering that the gate drive signal does not immediately attenuate upon entering the plane, a signal reconstruction node can be set after the gate drive signal has been provided to some pixels. Considering that when the size of the display panel is large, the transmission line used to transmit the gate drive signal is long, setting only one signal reconstruction node may not be sufficient to ensure that the gate drive signal will not attenuate in the subsequent transmission path. Therefore, setting multiple signal reconstruction nodes is equivalent to dividing the pixel array into multiple pixel blocks by columns at the location of each signal reconstruction node, and then dividing the pixels in the same row of each pixel block into multiple groups of pixel units. A second signal reconstruction unit 12 is set between each pair of adjacent groups of pixel units. The second signal reconstruction unit 12 can output the gate high voltage VGH from the logic board as a reconstruction signal to the next group of pixel units so that the gate drive signal in the transmission path does not attenuate. Alternatively, it can pull down the level of the controlled terminal of the next group of pixel units by the gate low voltage VGL from the logic board when it is not necessary to turn on the next group of pixel units.

[0042] It should be noted that, in this embodiment, the first group of pixel units connected to the second signal reconstruction unit 12 refers to the pixel units that are relatively close to the gate driving circuit, and the second group of pixel units refers to the pixel units that are relatively far away from the gate driving circuit.

[0043] Reference Figure 15In some feasible embodiments, the second signal reconstruction unit 12 includes an NMOS transistor Q1 and a PMOS transistor Q2. The gates of the NMOS transistor Q1 and the PMOS transistor Q2 are connected together as the first terminal of the second signal reconstruction unit 12. The sources of the NMOS transistor Q1 and the PMOS transistor Q2 are connected together as the second terminal of the second signal reconstruction unit 12. The drain of the NMOS transistor Q1 is the third terminal of the second signal reconstruction unit 12, and the drain of the PMOS transistor Q2 is the fourth terminal of the second signal reconstruction unit 12. In this embodiment, the second signal reconstruction unit 12 may include a CMOS transistor composed of an NMOS transistor Q1 and a PMOS transistor Q2, or it may be implemented by other switching devices with similar functions.

[0044] As an example, after the gate drive circuit normally transmits the gate drive signal to the in-plane, this gate drive signal can be provided to a group of pixel units and reach the CMOS transistor at a signal reconstruction node after a certain interval, thereby controlling the turning on and off of the next group of pixel units. Specifically, the transmission line used to transmit the gate drive signal to the pixel array can be connected to the gates of NMOS transistors Q1 and Q2, and the sources of NMOS transistors Q1 and Q2 can be connected to the transmission line used to transmit the reconstruction signal to the next group of pixel units. Then, the drains of each NMOS transistor Q1 are connected to the logic board of the display panel through a vertical transmission line and connected to the circuit on the logic board used to provide the gate high voltage VGH. When the gate drive circuit controls the gate of a row of pixels to turn on, the gate drive signal is also transmitted to the gate of the in-plane NMOS transistor Q1, causing NMOS transistor Q1 to conduct, with the source and drain connected. The gate high voltage VGH transmitted from the logic board can then be used as the reconstructed gate drive signal to continue to be transmitted to the in-plane.

[0045] It is important to note that since the transmission lines of the pixel array also suffer losses that can degrade the gate drive signal waveform, it is necessary to set the turn-on and turn-off thresholds for the gate of the NMOS transistor Q1 to ensure that the newly generated gate drive signal has good rising and falling edges. Furthermore, the gate drive signal is at a low level voltage of VGL. Therefore, when the display panel is working and the NMOS transistor Q1 is off, the transmission line of the next set of pixel units connected to the source of the NMOS transistor Q1 needs to be pulled low to the gate low voltage VGL. This requires another vertical transmission line to be connected to the logic board. Therefore, the second signal reconstruction unit 12 cannot use NMOS transistor Q1 or PMOS transistor Q2 alone. Instead, it is necessary to combine NMOS transistor Q1 and PMOS transistor Q2 into a CMOS transistor. The gates of NMOS transistor Q1 and PMOS transistor Q2 are connected together and connected to the transmission line of the previous group of pixel units. The drain of NMOS transistor Q1 is connected to VGH on the logic board, the drain of PMOS transistor Q2 is connected to VGL on the logic board, and the sources of NMOS transistor Q1 and PMOS transistor Q2 are connected together and connected to the transmission line of the next group of pixel units.

[0046] In some feasible embodiments, when a high-level signal is received at the first terminal of the second signal reconstruction unit 12, the NMOS transistor Q1 is turned on and the PMOS transistor Q2 is turned off, and the second signal reconstruction unit 12 outputs the gate high voltage VGH as a reconstruction signal to the next group of pixel units. When a low-level signal is received at the first terminal of the second signal reconstruction unit 12, the NMOS transistor Q1 is turned off and the PMOS transistor Q2 is turned on, and the second signal reconstruction unit 12 outputs the gate low voltage VGL to the next group of pixel units.

[0047] In this embodiment, before the CMOS transistor receives the high-level gate drive signal, the next group of pixel units connected to the CMOS transistor is connected to VGL, and the output is low. When the high level arrives, the NMOS transistor Q1 is turned on, and the next group of pixel units is connected to VGH, resulting in a high-level output. The timing of the input gate drive signal has already been generated by the gate drive circuit at the edge of the display panel. The MOS transistor does not affect the timing; on the contrary, due to the threshold voltage of the MOS transistor gate, the quality of the gate drive signal is greatly improved, thereby improving the problem of uneven charging in large-size display panels.

[0048] In addition, this application embodiment also provides a display panel, which includes a gate driving circuit, a pixel array, and a driving circuit of the display panel provided in the above embodiment. The gate driving circuit is electrically connected to the pixel array and the driving circuit of the display panel. The gate driving signal output by the gate driving circuit is directly provided to the pixel array, or the driving circuit of the display panel performs signal reconstruction at a preset signal reconstruction node and outputs it to the pixel array.

[0049] In some feasible embodiments, the display panel may also include a logic board.

[0050] As an example, the display panel in this embodiment can be a TN (Twisted Nematic) display panel, an IPS (In-Plane Switching) display panel, a VA (Vertical Alignment) display panel, or an MVA (Multi-Domain Vertical Alignment) display panel. Of course, it can also be other types of display panels, such as an OLED (Organic Light-Emitting Diode) display panel.

[0051] As an example, the display panel can be applied to display devices, such as mobile phones, tablets, televisions, monitors, laptops, digital photo frames, navigators, and any other products or components with display functions.

[0052] Since the display panel proposed in this embodiment adopts all the technical solutions of all the above embodiments and belongs to the same technical concept, this embodiment has at least all the beneficial effects brought about by the technical solutions of the above embodiments, and will not be described in detail here.

[0053] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indication will also change accordingly.

[0054] Furthermore, in the embodiments of this application, descriptions involving "first," "second," etc., are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of the embodiments of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. Additionally, the meaning of "and / or" throughout the text includes three parallel solutions; for example, "A and / or B" includes solution A, solution B, or a solution that simultaneously satisfies A and B.

[0055] In the embodiments of this application, unless otherwise expressly specified and limited, the terms "connection" and "fixed" should be interpreted broadly. For example, "fixed" can mean a fixed connection, a detachable connection, or an integral part; it can mean a mechanical connection or an electrical connection; it can mean a direct connection or an indirect connection through an intermediate medium; it can mean the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in the embodiments of this application according to the specific circumstances.

[0056] It should also be understood that references to "one embodiment" or "some embodiments" in the specification of embodiments of this application mean that one or more embodiments of this application include the specific features, structures, or characteristics described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof all mean "including but not limited to," unless otherwise specifically emphasized.

[0057] It should be noted that the technical solutions of the various embodiments of this application can be combined with each other, but only if they are implemented by those skilled in the art. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such combination of technical solutions does not exist and is not within the scope of protection claimed by the embodiments of this application.

[0058] The above are merely optional embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the description and drawings of this application, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A driving circuit for a display panel, characterized in that, The input terminal of the driving circuit of the display panel is electrically connected to the gate driving circuit of the display panel, and the output terminal of the driving circuit of the display panel is electrically connected to the pixel array of the display panel. The driving circuit of the display panel is configured to perform signal reconstruction on the gate driving signal output by the gate driving circuit at a preset signal reconstruction node to obtain a reconstruction signal, and output the reconstruction signal to the pixel array.

2. The driving circuit for the display panel as described in claim 1, characterized in that, The driving circuit of the display panel includes: An analog-to-digital converter module, wherein the input terminal of the analog-to-digital converter module is electrically connected to the gate drive circuit, and the analog-to-digital converter module is configured to convert the gate drive signal into a digital signal; A first signal reconstruction module is configured to perform signal reconstruction on the digital signal at the signal reconstruction node to obtain the reconstructed signal, and output the reconstructed signal to the pixel array.

3. The driving circuit for the display panel as described in claim 2, characterized in that, The analog-to-digital conversion module includes multiple analog-to-digital converters, the number of which is the same as the number of pixel rows in the pixel array.

4. The driving circuit for the display panel as described in claim 3, characterized in that, The pixel array is divided into multiple pixel blocks by column based on the signal reconstruction nodes, and the multiple pixel blocks are divided into multiple groups of pixel units by row based on the number of pixel rows; The first signal reconstruction module includes a plurality of first signal reconstruction units, and each first signal reconstruction unit is connected to at least one group of pixel units.

5. The driving circuit for the display panel as described in claim 4, characterized in that, The number of the first signal reconstruction units is the same as the number of groups of pixel units. The plurality of first signal reconstruction units are disposed in the pixel array, and each first signal reconstruction unit is connected to a group of pixel units. The first signal reconstruction unit includes: A digital-to-analog converter, wherein the input terminal of the digital-to-analog converter is electrically connected to the output terminal of the analog-to-digital conversion module, and the digital-to-analog converter is configured to convert the digital signal into an analog signal; A level converter, wherein the input terminal of the level converter is electrically connected to the output terminal of the digital-to-analog converter, and the output terminal of the level converter is electrically connected to the gate of the switching transistor of each pixel in the pixel unit, the level converter is configured to convert the analog signal into the reconstructed signal and output the reconstructed signal to the gate of each of the switching transistors.

6. The driving circuit for the display panel as described in claim 4, characterized in that, The number of the first signal reconstruction units is the same as the number of the signal reconstruction nodes. The plurality of first signal reconstruction units are disposed in the logic board of the display panel, and each first signal reconstruction unit is connected to one pixel block. The first signal reconstruction unit includes: A digital-to-analog converter, wherein the input terminal of the digital-to-analog converter is electrically connected to the output terminal of the analog-to-digital conversion module, and the digital-to-analog converter is configured to convert the digital signal into an analog signal; A level converter, wherein the input terminal of the level converter is electrically connected to the output terminal of the digital-to-analog converter, and the level converter is configured to convert the analog signal into the reconstructed signal; A multiplexer, wherein the input terminal of the multiplexer is electrically connected to the output terminal of the level converter, and the output terminal of the multiplexer is electrically connected to the controlled terminal of each pixel unit in the pixel block, and the multiplexer is configured to output the reconstruction signal to the gate of the switching transistor of each pixel in the pixel unit of the corresponding pixel row.

7. The driving circuit for the display panel as described in claim 1, characterized in that, The pixel array is divided into multiple pixel blocks by column based on the signal reconstruction node. The multiple pixel blocks are divided into multiple groups of pixel units by row based on the number of pixel rows in the pixel array. The controlled terminal of the first group of pixel units in each row is electrically connected to the output terminal of the gate driving circuit. The driving circuit of the display panel includes a plurality of second signal reconstruction units disposed in the pixel array, wherein the number of the second signal reconstruction units is the product of the number of signal reconstruction nodes and the number of pixel rows; Each of the second signal reconstruction units is connected between two adjacent groups of pixel units in the same row. The first end of each of the second signal reconstruction units is electrically connected to the controlled end of the preceding group of pixel units, and the second end of each of the second signal reconstruction units is electrically connected to the controlled end of the following group of pixel units. The third terminal of each second signal reconstruction unit is connected to a gate high voltage from the logic board of the display panel, and the fourth terminal of each second signal reconstruction unit is connected to a gate low voltage from the logic board. Each second signal reconstruction unit is configured to output the gate high voltage as the reconstruction signal to the next group of pixel units, or to output the gate low voltage to the next group of pixel units.

8. The driving circuit for the display panel as described in claim 7, characterized in that, The second signal reconstruction unit includes an NMOS transistor and a PMOS transistor. The gates of the NMOS transistor and the PMOS transistor are connected together as the first terminal of the second signal reconstruction unit. The sources of the NMOS transistor and the PMOS transistor are connected together as the second terminal of the second signal reconstruction unit. The drain of the NMOS transistor is the third terminal of the second signal reconstruction unit, and the drain of the PMOS transistor is the fourth terminal of the second signal reconstruction unit.

9. The driving circuit for the display panel as described in claim 8, characterized in that, When a high-level signal is received at the first terminal of the second signal reconstruction unit, the NMOS transistor is turned on and the PMOS transistor is turned off. The second signal reconstruction unit outputs the high gate voltage as the reconstruction signal to the next group of pixel units. When a low-level signal is received at the first terminal of the second signal reconstruction unit, the NMOS transistor is turned off and the PMOS transistor is turned on, and the second signal reconstruction unit outputs the low gate voltage to the next group of pixel units.

10. A display panel, characterized in that, The display panel includes: a gate driving circuit, a pixel array, and a driving circuit for the display panel as described in any one of claims 1 to 9. The gate driving circuit is electrically connected to the pixel array and the driving circuit of the display panel. The gate driving signal output by the gate driving circuit is directly provided to the pixel array, or is output to the pixel array after signal reconstruction by the driving circuit of the display panel at a preset signal reconstruction node.

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