A display panel and display device

Abstract

This application discloses a display panel and a display device, relating to the field of display technology. The display panel includes a substrate, and multiple pixel circuits, multiple gating circuits, multiple data signal lines extending along a first direction, and multiple source signal lines located on one side of the substrate. Each gating circuit includes a gating input terminal and multiple gating output terminals. The gating input terminal is electrically connected to the source signal lines. The multiple gating output terminals are respectively electrically connected to the multiple data signal lines. The substrate includes a first edge extending along a second direction, where the first direction intersects the second direction. The source signal lines are located on the side of the gating circuit they are electrically connected to, closer to the first edge. The gating circuit is located on the side of some pixel circuits away from the first edge. Using the above technical solution simplifies the wiring arrangement and improves the display effect.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0002] Recently, with the development of display technology, display screens are getting larger and the bezels are getting smaller. However, reducing the bezel size makes it more difficult to arrange connecting cables, which is detrimental to the display effect. Summary of the Invention

[0003] This application provides a display panel and a display device to simplify the arrangement of connecting cables and improve the display effect.

[0004] According to one aspect of this application, a display panel is provided, including a substrate, and a plurality of pixel circuits, a plurality of gating circuits, a plurality of data signal lines extending along a first direction and a plurality of source signal lines located on one side of the substrate; The gating circuit includes a gating input terminal and multiple gating output terminals; the gating input terminal is electrically connected to the source signal line; the multiple gating output terminals are respectively electrically connected to multiple data signal lines. The substrate includes a first edge extending along a second direction, the first direction intersecting the second direction; the source signal line is located on the side of the gating circuit to which it is electrically connected, near the first edge; The gating circuit is located on the side of the pixel circuit that is far from the first edge.

[0005] Optionally, multiple pixel circuits are arranged in a pixel circuit row in a second direction, and the pixel circuit rows are arranged along a first direction; along the first direction, a gating circuit is located between adjacent pixel circuit rows.

[0006] In one embodiment, a spacing region is included between adjacent pixel circuit rows, and the gating circuit is located in the spacing region between adjacent pixel circuit rows.

[0007] Optionally, the pixel circuit row includes multiple pixel circuit groups arranged along the second direction, and each pixel circuit group includes M pixel circuits, where M ≥ 2; in the first direction, the gating circuit overlaps with the pixel circuit group.

[0008] In one embodiment, the gating circuit is located in the interval region between adjacent pixel circuit groups arranged along a first direction.

[0009] Optionally, the display panel also includes a plurality of signal line groups extending along a first direction and arranged along a second direction; along the second direction, signal line groups are provided on both sides of the pixel circuit group; the length of the gating circuit in the second direction is less than the minimum spacing between adjacent signal line groups.

[0010] Optionally, the gating circuit includes N gating output terminals, where N≥2; and M=N.

[0011] Optionally, the display panel includes a driving circuit, which includes a plurality of shift registers cascaded along a first direction; in the first direction, the shift registers overlap with pixel circuitry; wherein, The length of the gating circuit in the second direction is less than the length of the shift register in the second direction.

[0012] In other alternative implementations, the length of the shift register in the second direction may also be less than the length of the gating circuit in the second direction.

[0013] Optionally, the display panel includes a first area and a second area located in the first area away from the first edge, and the pixel circuit rows include a first pixel circuit row located in the first area and a second pixel circuit row located in the second area, wherein the minimum spacing between two adjacent second pixel circuit rows is greater than the minimum spacing between two adjacent first pixel circuit rows; wherein, The gating circuit is located between the adjacent first pixel circuit row and second pixel circuit row.

[0014] In other alternative implementations, the gating circuit may also be located in a first interval region between two adjacent first pixel circuit rows or a second interval region between two adjacent second pixel circuit rows.

[0015] Optionally, the minimum spacing between adjacent first pixel circuit rows and second pixel circuit rows is greater than the minimum spacing between two adjacent second pixel rows.

[0016] In some implementations, the minimum spacing between two adjacent second pixel circuit rows is equal to the minimum spacing between adjacent first pixel circuit rows and second pixel circuit rows.

[0017] In other embodiments, the minimum spacing between adjacent first pixel circuit rows and second pixel circuit rows may be greater than the minimum spacing between two adjacent second pixel rows.

[0018] Optional, also includes: Multiple sub-pixels, with sub-pixels electrically connected to pixel circuitry; Multiple subpixels are arranged in a subpixel row in a second direction. The subpixel row includes a first subpixel row and a second subpixel row. The subpixels in the first subpixel row are electrically connected to the pixel circuits in the first pixel circuit row, and the subpixels in the second subpixel row are electrically connected to the pixel circuits in the second pixel circuit row. Wherein, along the first direction, the minimum distance between the first sub-pixel row and the gating circuit is the first distance, and the minimum distance between the first pixel circuit row electrically connected to the first sub-pixel row and the gating circuit is the second distance, and the first distance is greater than or equal to the second distance.

[0019] Optional, also includes: Multiple sub-pixels, with sub-pixels electrically connected to pixel circuitry; The sub-pixel includes a first sub-pixel, and the first sub-pixel and its electrically connected pixel circuit are both located on the side of the gating circuit closer to the first edge; Along the first direction, the minimum distance between the first sub-pixel and its electrically connected pixel circuit is the third distance, and the minimum distance between the first sub-pixel and the gating circuit is the fourth distance. The third distance is less than the fourth distance.

[0020] Optionally, the gating circuit includes a plurality of gating transistors arranged along a second direction, the channel length of the gating transistors extending along a first direction, and the channel length of the gating transistors being less than their channel width.

[0021] Optionally, the display panel further includes a plurality of first color sub-pixels and second color sub-pixels, wherein the emission wavelength of the first color sub-pixels is greater than the emission wavelength of the second color sub-pixels; the pixel circuit includes a first pixel circuit and a second pixel circuit, wherein the first color sub-pixels are electrically connected to the first pixel circuit and the second color sub-pixels are electrically connected to the second pixel circuit. The gating transistor includes a first gating transistor and a second gating transistor, and the data signal line includes a first data signal line and a second data signal line. The first gating transistor is electrically connected to the first pixel circuit through the first data signal line, and the second gating transistor is electrically connected to the second pixel circuit through the second data signal line. The channel width of the first gate transistor is greater than the channel width of the second gate transistor.

[0022] Optionally, the pixel circuitry includes driving transistors; The channel width of the first gating transistor is greater than the channel width of the driving transistor; and / or, the channel width of the second gating transistor is less than the channel width of the driving transistor.

[0023] Optionally, the gating transistor includes a first gating transistor and a second gating transistor, and the data signal line includes a first data signal line and a second data signal line; the first gating transistor is electrically connected to the first data signal line, and the second gating transistor is electrically connected to the second data signal line; The display panel further includes: a data signal line group electrically connected to the gating circuit, the data signal line group including at least a first data signal line and a second data signal line; In the same gating circuit and its electrically connected data signal line group, the second gating transistor is located on the side of the first gating transistor away from the second data signal line, and the first data signal line is located on the side of the second data signal line away from the first gating transistor.

[0024] Optionally, the display panel further includes a plurality of first color sub-pixels and second color sub-pixels, wherein the emission wavelength of the first color sub-pixels is greater than the emission wavelength of the second color sub-pixels; the pixel circuit includes a first pixel circuit and a second pixel circuit, wherein the first color sub-pixels are electrically connected to the first pixel circuit and the second color sub-pixels are electrically connected to the second pixel circuit. The gating transistor includes a first gating transistor and a second gating transistor, and the data signal line includes a first data signal line and a second data signal line. The first gating transistor is electrically connected to the first pixel circuit through the first data signal line, and the second gating transistor is electrically connected to the second pixel circuit through the second data signal line. The minimum distance between the first select transistor and its electrically connected first data signal line is the fifth distance, and the minimum distance between the second select transistor and its electrically connected second data signal line is the sixth distance. The fifth distance is less than the sixth distance.

[0025] Optionally, the gating circuit includes N gating transistors, and the N gating transistors are electrically connected to N data signal lines; Among the N data signal lines electrically connected to the same gating circuit, there are at most K adjacent data signal lines without spacing between gating transistors, where K is a positive integer and K < N.

[0026] Optionally, among the N data signal lines electrically connected to the same gating circuit, K data signal lines are located on the first side of the gating circuit in the second direction, and NK data signal lines are located on the second side of the gating circuit in the second direction.

[0027] Optional, also includes: A data signal line group electrically connected to the gating circuit, the data signal line group including at least two data signal lines; in a second direction, the data signal line group is adjacent to the gating circuit; In the second direction, the source signal line is also adjacent to the gating circuit, and the source signal line is located on the side of the gating circuit away from the data signal line group.

[0028] Optional, also includes: A gating signal line group, comprising multiple gating signal lines extending along a second direction; along a first direction, the gating signal line group is adjacent to a gating circuit; The gating circuit further includes a gate connection portion extending at least partially along a first direction, the gate connection portion connecting the gate of the gating transistor and the gating signal line; the gating circuit further includes an electrode connection portion connecting the first electrode of an adjacent gating transistor; The gating transistor includes a first electrode and a second electrode arranged along a first direction, with the first electrode located on the side of the second electrode closer to the gating signal line group; the first electrode is electrically connected to the source signal line, and the second electrode is electrically connected to the data signal line.

[0029] Optional, also includes: The gating signal line includes a first gating portion and a second gating portion; along a direction perpendicular to the plane where the substrate is located, the first gating portion overlaps with the data signal line and / or the source signal line, while the second gating portion does not overlap with the data signal line; The gate, gate connection portion, and first selection portion of the selection transistor are located in the first conductive layer, and the first electrode, electrode connection portion, and second selection portion of the selection transistor are located in the second conductive layer. The electrode connection portion extends along the second direction; along the second direction, the electrode connection portion overlaps with the first electrode.

[0030] Optional, also includes: The gating signal line includes a first gating signal line and a second gating signal line. The first gating signal line is adjacent to the gating transistor, and the second gating signal line is located on the side of the first gating signal line away from the gating transistor. The gate connection portion includes a first gate connection portion and a second gate connection portion. The first gate connection portion is electrically connected to the first gating signal line, and the second gate connection portion is electrically connected to the second gating signal line. The second gate connection portion includes a first sub-connection portion and a second sub-connection portion. The first sub-connection portion is connected to the gate of the gating transistor and the second sub-connection portion. The second sub-connection portion is connected to the first sub-connection portion and the second gating signal line. The gate of the gate transistor, the first gate connection portion, the first sub-connection portion of the second gate connection portion, and the gate signal line are located in the first conductive layer, while the second sub-connection portion of the second gate connection portion, the first electrode of the gate transistor, and the electrode connection portion are located in the second conductive layer. At least a portion of the first sub-connection of the second gate connection extends along a second direction, and the second sub-connection of the second gate connection extends along a first direction; along the second direction, the second sub-connection of the second gate connection overlaps with the first electrode; along the first direction, the electrode connection is located on the side of the second sub-connection of the second gate connection away from the gate signal line.

[0031] Optionally, the pixel circuit includes a pulse amplitude modulation module and a pulse width modulation module; The data signal lines include pulse amplitude data signal lines and pulse width data signal lines. The pulse amplitude data signal lines are electrically connected to the pulse amplitude modulation module, and the pulse width data signal lines are electrically connected to the pulse width modulation module. The gating circuit is electrically connected to the pulse width modulation module via the pulse width data signal line.

[0032] According to another aspect of this application, a display device is provided, including the display panel provided in any embodiment of this application.

[0033] The technical solution of this application, by moving the gating circuit from the side of the pixel circuit closer to the first edge to the side of the partial pixel circuit farther from the first edge, enables the partial pixel circuit to be located on the side of the gating circuit closer to the first edge. This reduces the inward shrinkage of the partial pixel circuit, which helps to shorten the distance between the partial pixel circuit and the first edge, and reduces the connection length of the pixel connection line between the partial pixel circuit and the sub-pixel electrically connected to it. This helps to simplify the arrangement of the pixel connection line and improve display uniformity. At the same time, the reduction of the circuit on the side of the pixel circuit closer to the first edge also helps to increase the design flexibility of this area.

[0034] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this application, nor is it intended to limit the scope of this application. Other features of this application will become readily apparent from the following description. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1 This is a top view of a display panel provided in an embodiment of this application; Figure 2 yes Figure 1 A top-view structural diagram of a local area EA0 in the middle; Figure 3 yes Figure 2 A top-view structural diagram of the first sub-local region EA1 in the middle; Figure 4 yes Figure 1 Another top-view structural diagram of the local area EA0 in the middle; Figure 5 This is a schematic diagram of the circuit structure of a gating circuit provided in an embodiment of this application; Figure 6 yes Figure 2 A top-view structural diagram of the second sub-region EA2 in the middle. Figure 7 yes Figure 1 Another top-view structural diagram of the local area EA0 in the middle; Figure 8 This is a schematic diagram of the circuit structure of a pixel circuit provided in an embodiment of this application. Figure 9 yes Figure 1 Another top-view structural diagram of the local area EA0 in the middle; Figure 10 yes Figure 9 A top-view structural diagram of the third sub-region EA3 in the middle; Figure 11 This is a schematic diagram of the circuit structure of another pixel circuit provided in an embodiment of this application; Figure 12 yes Figure 1 Another top-view structural diagram of the local area EA0 in the middle; Figure 13 yes Figure 1 Another top-view structural diagram of the local area EA0 in the middle; Figure 14 yes Figure 9 Another top-view structural diagram of the third sub-region EA3 in the middle; Figure 15 yes Figure 9 A schematic diagram of a membrane structure in the local region EA4 of the fourth subunit; Figure 16 This is a top-view structural diagram of the fourth sub-region EA4 in 9; Figure 17 This is another top-view structural diagram of the fourth sub-region EA4 in 9; Figure 18 This is another top-view structural diagram of the fourth sub-region EA4 in 9; Figure 19 This is a top view schematic diagram of a gating circuit provided in an embodiment of this application; Figure 20 yes Figure 19 A schematic diagram of the cross-sectional structure with section B1-B1' in the middle; Figure 21 This is a top view schematic diagram of another gating circuit provided in an embodiment of this application; Figure 22 yes Figure 21 A schematic diagram of the cross-sectional structure with section B2-B2' in the middle; Figure 23 yes Figure 21 A top view of the first conductive layer in the middle; Figure 24 yes Figure 21 A top view of the second conductive layer in the middle; Figure 25 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. Detailed Implementation

[0037] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0038] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0039] As described in the background section, display screens are becoming larger and their bezels are becoming smaller. For large-size displays, the number of data signal lines used to transmit data signals is greater, resulting in a larger number of data signal input ports, which increases the complexity of the circuit design. To reduce the number of data signal input ports, related technologies employ gating circuits to connect multiple data signal lines. The gating circuit provides data signals to these electrically connected data signal lines in a time-division manner, and the data signal input ports only need to be connected to the gating circuit, thus reducing the number of data signal input ports to the number of data signal lines. Typically, the data signal input terminals are located in the bezel area, and the gating circuit is located on the side of the data signal line closest to the data signal input port; that is, the gating circuit is located on the side of the pixel circuit closest to the edge of the display.

[0040] For narrow-bezel displays, such as ultra-narrow bezel displays and borderless video wall displays, pixel circuit compression designs are used to effectively compress the bezel and reduce damage to circuit components during laser cutting. Pixel circuits near the display edge are recessed compared to their electrically connected sub-pixels (including light-emitting elements). In a direction perpendicular to the display plane, some sub-pixels near the display edge do not overlap with their electrically connected pixel circuits. These sub-pixels are located on the side of their electrically connected pixel circuits closest to the display edge. This necessitates longer connecting lines between some sub-pixels and their electrically connected pixel circuits, resulting in complex connection designs, potentially leading to more signal interference and larger conduction voltage drops, affecting display uniformity and negatively impacting display quality.

[0041] For narrow bezel displays, the gating circuit is also located in the display area. That is, the gating circuit can be located on the side of some sub-pixels away from the edge of the display. At the same time, the gating circuit is located on the side of the pixel circuit close to the edge of the display. This requires further compression of the pixel circuit, so that the position of the pixel circuit close to the edge of the display continues to shrink inward in the direction away from the edge. This increases the distance between the sub-pixels near the edge and the pixel circuits electrically connected to them, making the connection line design between these sub-pixels and their electrically connected pixel circuits more complex and reducing display uniformity.

[0042] To address the aforementioned technical problems, this application provides a display panel including a substrate, and multiple pixel circuits, multiple gating circuits, multiple data signal lines extending along a first direction, and multiple source signal lines located on one side of the substrate. Each gating circuit includes a gating input terminal and multiple gating output terminals. The gating input terminal is electrically connected to the source signal lines. The multiple gating output terminals are respectively electrically connected to the multiple data signal lines. The substrate includes a first edge extending along a second direction, where the first direction intersects the second direction. The source signal lines are located on the side of the gating circuit they are electrically connected to, closer to the first edge. The gating circuit is located on the side of some pixel circuits away from the first edge.

[0043] By adopting the above technical solution, by moving the gating circuit from the side of the pixel circuit closer to the first edge to the side of some pixel circuits farther away from the first edge, some pixel circuits can be located on the side of the gating circuit closer to the first edge. This reduces the inward shrinkage of these pixel circuits, which helps to shorten the distance between these pixel circuits and the first edge, and reduces the connection length of the pixel connection lines between these pixel circuits and their electrically connected sub-pixels. This helps to simplify the arrangement of pixel connection lines and improve display uniformity. At the same time, the reduction of the circuit on the side of the pixel circuit closer to the first edge also helps to increase the design flexibility of this area.

[0044] The above is the core idea of ​​this application. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings.

[0045] It should be noted that the implementation methods provided in this application can be combined with each other without contradiction.

[0046] Figure 1 This is a top view structural diagram of a display panel provided in an embodiment of this application. Figure 2 yes Figure 1 A top-view structural diagram of a local area EA0 in the middle. Figure 3 yes Figure 2 A top-view structural diagram of the first sub-local region EA1, referenced. Figures 1-3 The display panel 001 includes a substrate 100, and multiple pixel circuits PC, multiple gating circuits demux, multiple data signal lines DL extending along a first direction F1, and multiple source signal lines OL located on one side of the substrate 100. Each gating circuit demux includes a gating input terminal mux_in and multiple gating output terminals mux_out. The gating input terminal mux_in is electrically connected to the source signal lines OL, and the multiple gating output terminals mux_out are respectively electrically connected to the multiple data signal lines DL. The substrate 100 includes a first edge E1 extending along a second direction F2, where the first direction F1 intersects the second direction F2. The source signal lines OL are located on the side of the gating circuit demux to which they are electrically connected, closer to the first edge E1. The gating circuit demux is located on the side of a portion of the pixel circuits PC away from the first edge E1.

[0047] Among them, the display panel 001 includes, but is not limited to, large-size display panels, narrow-bezel display panels, borderless display panels, splicing display panels, etc., and the substrate 100 includes, but is not limited to, transparent, semi-transparent or opaque substrates, and the substrate 100 also includes, but is not limited to, glass substrates, silicon substrates, resin substrates, etc.

[0048] In some embodiments, the display panel 001 includes a plurality of pixels P located on one side of the substrate 100. Each pixel P includes a sub-pixel PX and a pixel circuit PC. Each sub-pixel PX includes a light-emitting element, and the sub-pixel PX is electrically connected to the pixel circuit PC. The pixel circuit PC can drive the light-emitting element of the sub-pixel PX to emit light for display. In some embodiments, the substrate 100 also includes a second edge E2 disposed opposite to the first edge E1 in the first direction F1, and a third edge E3 and a fourth edge E4 disposed adjacent to the first edge E1. A data signal input port may be disposed near the first edge E1. The first edge E1 is usually the lower edge of the display panel 001. Functional areas such as a bonding area for a driver chip and a fan-out routing area may be disposed near the lower edge. Therefore, compared with the vicinity of other edges, the number of connecting lines near the first edge E1 may be greater, and the arrangement of connecting lines may be more complex. The embodiments of this application mainly explain and describe the local area near the first edge E1.

[0049] To reduce the frame size near the first edge E1 and minimize device damage during laser cutting, along the first direction F1, the pixel circuit PC closest to the first edge is recessed inwards from the sub-pixel PX to which it is electrically connected, moving away from the first edge E1. For example, the pixel circuit PC closest to the first edge E1 can be electrically connected to the sub-pixel PX closest to the first edge E1, and the distance LC1 between the pixel circuit PC closest to the first edge E1 and the first edge E1 is greater than the distance LX1 between the sub-pixel PX closest to the first edge E1 and the first edge E1. In some embodiments, the pixel circuit PC closest to the first edge E1 and the sub-pixel PX closest to the first edge E1 do not overlap along the direction perpendicular to the substrate 100.

[0050] In some implementations, reference Figure 2 Along a direction perpendicular to the substrate 100, at least a portion of the sub-pixel PX overlaps with its electrically connected pixel circuit PC. In this case, the sub-pixel PX can be located on the side of the pixel circuit PC away from the substrate 100. In other embodiments, Figure 4 yes Figure 1 Another top-view structural diagram of the local area EA0 in the middle, see reference. Figure 4 Along the direction perpendicular to the substrate 100, the sub-pixel PX and the pixel circuit PC can also not overlap; that is, along the direction perpendicular to the substrate 100, any sub-pixel PX does not overlap with the pixel circuit PC. For ease of understanding and explanation, unless otherwise specified, the embodiments of this application all use... Figure 2 The embodiments of this application are illustrated by taking the example of at least some sub-pixels PX overlapping with their electrically connected pixel circuits PC.

[0051] In some embodiments, the display panel 001 further includes a plurality of pads pd located on one side of the substrate 100. Along the first direction F1, the pads pd may be located on the side of the sub-pixel PX near the first edge E1. At least some of the pads pd can serve as data signal input ports, receiving and outputting data signals. The source signal line OL can be electrically connected to the pads pd, receiving data signals through the pads pd and transmitting the data signals to the demux selection circuit. In some embodiments, Figure 5 This is a schematic diagram of the circuit structure of a gating circuit provided in an embodiment of this application, with reference to... Figure 5 The demux circuit can include multiple demux transistors SW. The gate of the demux transistor SW is connected to the demux signal line CL. The demux control signal on the demux signal line CL can control the demux transistor SW to be turned on in a time-division manner to decompose and transmit the data signal provided by the source signal line OL, and transmit it to different data signal lines DL respectively. In this way, multiple data signal lines DL can be connected to the pad pd through a single source signal line OL, which helps to reduce the number of pad pd and the number of connection lines connected to the pad pd, thereby reducing the bezel size.

[0052] Specifically, along the first direction F1, the demux of the gating circuit is located on the side of the partial pixel circuit PC away from the first edge E1. This allows the partial pixel circuit PC to be located on the side of the demux closer to the first edge E1. In other words, the demux of the gating circuit PC does not need to be set on the side of the partial pixel circuit PC closer to the first edge. This helps to compress the inward amount of the partial pixel circuit PC, shorten the distance between the partial pixel circuit PC and the first edge E1, thereby reducing the distance between the partial pixel circuit PC and its electrically connected sub-pixel PX. This also helps to simplify the layout of the pixel connection lines between the partial pixel circuit PC and its electrically connected sub-pixel PX.

[0053] For example, refer to Figure 2 Along the first direction F1, the sub-pixels PX near the first edge E1 are recessed inward relative to their electrically connected pixel circuits PC, moving away from the first edge E1; along the first direction F1, structures such as the demux gate circuit, fan-out traces, and electrostatic discharge protection circuits located near the first edge E1 ( Figure 2(The fan-out trace and electrostatic discharge protection circuit are not shown in the diagram.) The fan-out trace and electrostatic discharge protection circuit can be moved from the side of the sub-pixel PX closest to the first edge E1 to the side of the sub-pixel PX furthest from the first edge E1. In one embodiment, along the first direction F1, the area between the pixel circuit PC closest to the first edge E1 and the sub-pixel PX closest to the first edge E1 can be provided with structures such as fan-out traces and electrostatic discharge protection circuits. That is, the fan-out traces and electrostatic discharge protection circuits can be located on the side of the pixel circuit PC closest to the first edge E1 and the side of the sub-pixel PX closest to the first edge E1 furthest from the first edge E1. In another embodiment, structures such as fan-out traces, bonding electrodes (for connecting to pins of driving structures such as driver chips and printed circuit boards), and detection electrodes (for contacting probes during detection) are provided. Figure 2 (The fan-out traces, bonding electrodes, and detection electrodes are not shown in the figure) can be disposed on the side of the substrate 100 away from the pixel circuit PC and the sub-pixel PX. That is, these structures can be disposed on the back of the display panel 001, which is beneficial for compressing the bezel and simplifying the connection line layout on the front of the display panel 001.

[0054] Figure 6 yes Figure 2 A top-view structural diagram of the second sub-region EA2, referenced. Figure 6The display panel 001 also includes a pixel connection line PL, which connects the pixel circuit PC and the pixel electrode ed located on the side of the sub-pixel PX closest to the substrate 100. The pixel connection line PL is electrically connected to the sub-pixel PX through the pixel electrode ed. Along the direction perpendicular to the plane of the substrate 100, the pixel electrode ed overlaps with the sub-pixel PX it is electrically connected to. Therefore, the size of the pixel connection line PL in the first direction F1 is related to the distance between the pixel circuit PC and the sub-pixel PX in the first direction F1. In the second sub-local region EA2, the sub-pixel PX does not overlap with the pixel circuit PC it is electrically connected to. Along the first direction F1, the distance (LP1, LP2, LP3) between this part of the sub-pixel PX and the pixel circuit PC it is electrically connected to is relatively large, resulting in a longer pixel connection line PL between this part of the sub-pixel PX and the pixel circuit PC it is electrically connected to, and a more complex arrangement. This may result in more signal interference and a larger conduction voltage drop, affecting display uniformity and detrimental to display effect. By moving the demux from the side of the pixel circuit PC closest to the first edge E1 to the side of the partial pixel circuit PC away from the first edge E1, it is no longer necessary to place the demux on the side of the pixel circuit PC closest to the first edge E1 as in the conventional method. It is also unnecessary to reserve space for the demux on the side of the pixel circuit PC closest to the first edge E1. In other words, when designing the inward shrinkage of the partial pixel circuit PC, the demux does not need to be considered, which helps to reduce the inward shrinkage of the partial pixel circuit PC and shorten the distance (LP1, LP2, LP3) between the partial pixel circuit PC and its electrically connected pixel circuit PCs.

[0055] Understandably, reference Figure 2 and Figure 6 In the second sub-region EA2, both the pixel circuit PC and the sub-pixel PX are located on the side of the demux gate circuit closer to the first edge E1. That is, the demux gate circuit is not set on the side of the pixel circuit PC and / or the sub-pixel PX closer to the first edge E1 in the second sub-region EA2. However, the pixel circuit PC in the second sub-region EA2 still needs to be recessed to a certain extent so that the electrostatic protection circuit and other structures located on the side of the pixel circuit PC closer to the first edge E1 can be accommodated. Figure 6 (The electrostatic protection circuit is not shown in the image) can be located on the side of a portion of the sub-pixel PX away from the first edge E1 to compress the border size.

[0056] In the second sub-region EA2, along the first direction F1, from the first edge E1 to the pixel circuit PC, the distance LC1 between the pixel circuit PC closest to the first edge E1 and the first edge E1 is greater than the distance LX1 between the sub-pixel PX closest to the first edge E1 and the first edge E1. Similarly, the distance LC2 between the second pixel circuit PC closest to the first edge E1 and the first edge E1 is greater than the distance LX2 between the second sub-pixel PX closest to the first edge E1 and the first edge E1, and the distance LC3 between the third pixel circuit PC closest to the first edge E1 and the first edge E1 is greater than the distance LX3 between the third sub-pixel PX closest to the first edge E1 and the first edge E1. Distances LP1, LP2, and LP3 exist between the sub-pixel PX and its electrically connected pixel circuit PC. If the demux is not set on the side of some pixel circuit PCs away from the first edge E1, but instead set on the side of pixel circuit PCs closer to the first edge E1 as in the conventional setting method, in order to achieve… Achieving the same effect with narrow or borderless bezels requires increasing the indentation of the pixel circuit PC in the second sub-region EA2, increasing the distances LC1, LC2, and LC3 between the pixel circuit PC and the first edge E1, while keeping the distances LX1, LX2, and LX3 between the sub-pixel PX and the first edge E1 unchanged. This results in an increase in the distances LP1, LP2, and LP3 between the sub-pixel PX and its electrically connected pixel circuit PC, increasing the design complexity of the pixel connection line PL between the sub-pixel PX and its electrically connected pixel circuit PC. However, when the demux gate circuit is located on the side of these pixel circuit PCs away from the first edge E1, it helps to reduce the indentation of the pixel circuit PC in the second sub-region EA2, reducing the distances LC1, LC2, and LC3 between the pixel circuit PC and the first edge E1, thereby shortening the distances LP1, LP2, and LP3 between the sub-pixel PX and its electrically connected pixel circuit PC. This helps to shorten the connection length of the pixel connection line PL, simplify the wiring layout of the pixel connection line PL, and improve display uniformity.

[0057] In this embodiment, by moving the gating circuit from the side of the pixel circuit closer to the first edge to the side of the pixel circuit farther from the first edge, the partial pixel circuit can be located on the side of the gating circuit closer to the first edge. This reduces the inward shrinkage of the partial pixel circuit, which helps to shorten the distance between the partial pixel circuit and the first edge, and reduces the connection length of the pixel connection line between the partial pixel circuit and the sub-pixel electrically connected to it. This helps to simplify the arrangement of the pixel connection line and improve display uniformity. At the same time, the reduction of the circuit on the side of the pixel circuit closer to the first edge also helps to increase the design flexibility of this area.

[0058] Optional, continue to refer to Figure 2Multiple pixel circuits PC are arranged in the second direction F2 to form a pixel circuit row PCR, and the pixel circuit row PCR is arranged along the first direction F1; along the first direction F1, the demux gate circuit is located between adjacent pixel circuit rows PCR.

[0059] Specifically, there is a gap region IA between adjacent pixel circuit rows PCR, and the demux gate circuit is located in the gap region IA between adjacent pixel circuit rows PCR.

[0060] For example, multiple demuxes are located in the same interval region IA between two adjacent pixel circuit rows PCR, that is, multiple demuxes are arranged along the second direction F2, and any two demuxes overlap along the second direction F2. The number of demuxes is related to the number of data signal lines DL, and the number of data signal lines DL is related to the number of pixel circuits PC in the pixel circuit row PCR. When the number of pixel circuit PCs in the pixel circuit row PCR is large, the size of the interval region IA between adjacent pixel circuit rows PCR is also large in the second direction F2. By setting the demuxes to be located between adjacent pixel circuit rows PCR, there is enough space to set the demuxes, which is beneficial for flexibly setting the position and number of demuxes according to the number of pixel circuit PCs in the pixel circuit row PCR.

[0061] In some implementations, reference Figure 2 and Figure 3 Along the first direction F1, the center distance CD between the gating circuit demux and its adjacent pixel circuit row PCR is less than the center distance CP between at least some of the adjacent pixel circuit rows PCR. For example, a portion of the structure in the gating circuit demux and a portion of the structure in the pixel circuit PC can be disposed on the same layer, so that the gating circuit demux and the pixel circuit PC do not overlap along the direction perpendicular to the plane of the substrate 100.

[0062] In some implementations, reference Figure 3 Along the first direction F1, the center connection between the pixel circuit PC located on the side of the gating circuit demux closer to the first edge E1 and the pixel circuit PC located on the side of the gating circuit demux farther from the first edge E1 is a first connecting line B-B'; along the direction perpendicular to the plane where the substrate 100 is located, the first connecting line B-B' overlaps with the gating circuit demux. For example, the orthographic projection of the first connecting line B-B' onto the plane where the substrate 100 is located overlaps with the orthographic projection of the gating circuit demux onto the plane where the substrate 100 is located, and the orthographic projection of the first connecting line B-B' onto the plane where the substrate 100 is located will pass through the orthographic projection of the gating circuit demux onto the plane where the substrate 100 is located when the orthographic projection of the first connecting line B-B' extends.

[0063] In some implementations, reference continues. Figure 3 The data signal line DL includes multiple data connection nodes QP for electrically connecting to the pixel circuit PC. Along the first direction F1, some data connection nodes QP are located on the side of the gating circuit demux near the first edge E1. In other words, the data signal line DL also includes gating connection nodes QD for connecting to the gating circuit demux. On the same data signal line, the gating connection nodes QD are located between two adjacent data connection nodes QP.

[0064] Understandable, Figure 2 The example output shows that the demux is located on the side of the multiple pixel circuit rows PCR away from the first edge E1. In actual applications, the position of the demux can be different. The demux can be located on the side of at least one pixel circuit row PCR away from the first edge E1.

[0065] In an alternative embodiment, reference continues. Figure 2 and Figure 3 The pixel circuit row PCR includes multiple pixel circuit groups PG arranged along the second direction F2. Each pixel circuit group PG includes M pixel circuits PC, where M ≥ 2. In the first direction F1, the gating circuit demux overlaps with the pixel circuit group PG.

[0066] In this embodiment, a pixel circuit group PG can constitute a pixel circuit unit, and multiple pixel circuits PC in the pixel circuit group PG can be connected to M sub-pixels. In some embodiments, along the second direction F2, the minimum distance between adjacent pixel circuits PC in the same pixel circuit group PG is less than the minimum distance between adjacent pixel circuits PC in different pixel circuit groups PG. In this case, along the second direction F2, the minimum distance between adjacent sub-pixels PX connected to the same pixel circuit group PG can also be less than the minimum distance between adjacent sub-pixels PX connected to different pixel circuit groups PG. In some embodiments, M=3, and the three pixel circuits PC in the pixel circuit group PG can be electrically connected to the first color sub-pixel PX-1, the second color sub-pixel PX-2, and the third color sub-pixel PX-3, respectively.

[0067] Specifically, the demux gate circuit is located in the interval region between adjacent pixel circuit groups PG along the first direction F1.

[0068] For example, multiple pixel circuit groups PG are arranged into a pixel circuit group column in the first direction F1. Along the first direction F1, the gating circuit demux does not overlap with the spacing area between adjacent pixel circuit group columns. In other words, along the second direction F2, the gating circuit demux is not located between adjacent pixel circuit group columns. That is, multiple pixel circuits PC are arranged into a pixel circuit column in the first direction F1, and along the second direction F2, the gating circuit demux is not located between adjacent pixel circuit columns. The gating circuit demux is not located in the spacing area between adjacent pixel circuit group columns and / or adjacent pixel circuit columns. The data signal line DL extends along the first direction F1. The data signal line DL may be located in the spacing area between adjacent pixel circuit group columns and / or adjacent pixel circuit columns. By setting the gating circuit demux to overlap with the pixel circuit group PG in the first direction F1, it is beneficial to reduce the impact of the setting position of the gating circuit demux on the arrangement of the data signal line DL and simplify the arrangement of the data signal line DL.

[0069] In some implementations, along the second direction F2, the center line between adjacent pixel circuit groups PG ( Figure 2 The orthographic projection of the demux (not shown) onto the plane of substrate 100 does not overlap with the orthographic projection of the demux onto the plane of substrate 100. In one embodiment, multiple demuxes are arranged along the second direction F2, and the center line connecting adjacent demuxes ( Figure 2 (Not shown in the image) The orthographic projection of the image onto the plane of substrate 100 is parallel to the center line connecting adjacent pixel circuit groups PG along the second direction F2.

[0070] In some implementations, along the first direction F1, the regions between the demux of the gating circuit and the adjacent pixel circuit group PG in the same pixel circuit row PCR do not overlap; that is, along the second direction F2, the interval regions between adjacent pixel circuit groups PG do not overlap with the demux of the gating circuit in the first direction F1.

[0071] In some implementations, along the second direction F2, the demux and the pixel circuit PCR do not overlap, that is, along the second direction F2, the demux and the pixel circuit PC do not overlap.

[0072] Based on the above embodiments, Figure 7 yes Figure 1 Another top-view structural diagram of the local area EA0 in the middle, see reference. Figure 2 and Figure 7The display panel 001 also includes a plurality of signal line groups LG extending along a first direction and arranged along a second direction F2; along the second direction F2, signal line groups LG are provided on both sides of the pixel circuit group PG; the length of the demux gate circuit in the second direction F2 is less than the minimum spacing between adjacent signal line groups LG.

[0073] Among them, the signal line group LG includes, but is not limited to, the data signal line DL. For example, when the shift register VSR is also set in the display area, the signal line group LG also includes the power signal line, clock signal line and other signal lines connected to the shift register VSR.

[0074] For example, along the second direction F2, adjacent signal line groups LG can be located on opposite sides of pixel circuit group PG, or on opposite sides of gating circuit demux. By setting the length of gating circuit demux in the second direction F2 to be less than the minimum spacing between adjacent signal line groups LG, the orthographic projection of gating circuit demux on the plane of substrate 100 and the orthographic projection of signal line group LG on the plane of substrate 100 do not overlap. This helps to reduce the impact of the setting position of gating circuit demux on the arrangement of signal line group LG and simplifies the arrangement of signal line group LG.

[0075] In some implementations, along the second direction F2, the minimum distance between adjacent demuxes is greater than or equal to the distance between adjacent pixel circuit groups PG. For example, the number of demuxes arranged along the second direction F2 is less than or equal to the number of pixel circuit groups PG in the same pixel circuit row PCR; when the number of pixel circuit groups PG in the same pixel circuit row PCR is equal to the number of demuxes arranged along the second direction F2, the length of the demux in the second direction F2 can be less than or equal to the length of the pixel circuit group PG in the second direction.

[0076] Based on the above embodiments, refer to Figure 2 , Figure 3 and Figure 7 The demux circuit includes N demux output terminals mux_out, where N≥2; and M=N.

[0077] For example, M=N=3, the pixel circuit group PG includes three pixel circuits PC, and the gating circuit demux includes three gating outputs mux_out. The three gating outputs mux_out of the gating circuit demux can be connected to three data signal lines DL, which can be respectively connected to the three pixel circuits PC of the pixel circuit group PG. It can be understood that M and N can also be other integers greater than 2, as long as M=N≥2.

[0078] In some implementations, the number of pixel circuit groups (PGs) in the same pixel circuit row (PCR) is equal to the number of demuxes. For example, demuxes are configured corresponding to pixel circuit group columns, and each demux can be connected to M pixel circuit columns in the same pixel circuit group column via N data signal lines (DL), where M=N.

[0079] In some implementations, the M pixel circuits PC in the pixel circuit group PG are electrically connected to Q data signal lines DL, and the N gating outputs mux_out of the gating circuit demux are electrically connected to N data signal lines DL, M=N; along the second direction F2, Q data signal lines DL are provided between adjacent pixel circuit groups PG, and Q data signal lines DL are also provided between adjacent gating circuit demux, Q=M, or Q=M×2.

[0080] For example, taking Q=M=3 as an example, Figure 8 This is a schematic diagram of the circuit structure of a pixel circuit provided in an embodiment of this application, for reference. Figure 8 The pixel circuit PC includes an initialization transistor M05, a write transistor M02, a compensation transistor M04, a drive transistor M03, a first light-emitting control transistor M01, a second light-emitting control transistor M06, a reset transistor M07, and a storage capacitor Cst. The pixel circuit PC can receive a first power signal PVDD, a second power signal PVEE, a reset signal Vref, a first scan signal Scan1, a second scan signal Scan2, a data signal Data, and a light-emitting control signal Emit. The pixel circuit PC receives the data signal Data transmitted on the data signal line DL and drives the sub-pixel PX to present the corresponding brightness according to the data signal Data. One pixel circuit PC can be connected to one data signal line DL. The three pixel circuit PCs in the pixel circuit group PG are electrically connected to the three data signal lines DL respectively. Along the second direction F2, these three data signal lines DL can be located on one side of the pixel circuit group PG. Three data signal lines DL can be set between adjacent pixel circuit groups PG, such as... Figure 2 , Figure 3 , Figure 7 As shown.

[0081] It is understandable that when Q=M, the pixel circuit PC is Figure 8 The 7T1C circuit shown is for illustrative purposes only and is not intended to limit the specific circuit of the pixel circuit PC. In practical applications, the pixel circuit PC can also be a 2T1C, 6T2C, 8T1C, or other circuit structures.

[0082] Taking Q=M×2=6 as an example, Figure 9 yes Figure 1 Another top-view structural diagram of the local area EA0 in the middle. Figure 10 yes Figure 9 A top-view structural diagram of the third sub-region EA3 in the middle. Figure 11 This is a schematic diagram of the circuit structure of another pixel circuit provided in an embodiment of this application, see reference. Figures 9-11 The pixel circuit PC includes a pulse amplitude modulation module (PAM) and a pulse width modulation module (PWM). The data signal line DL includes a pulse amplitude data signal line DL_a and a pulse width data signal line DL_w. The pulse amplitude data signal line DL_a is electrically connected to the pulse amplitude modulation module PAM, and the pulse width data signal line DL_w is electrically connected to the pulse width modulation module PWM. The demux gate circuit is electrically connected to the pulse width modulation module PWM through the pulse width data signal line DL_w.

[0083] For example, the pulse amplitude modulation module (PAM) may include a first transistor M1 to a seventh transistor M7 and a first capacitor C1, and the pulse width modulation module (PWM) may include an eighth transistor M8 to a thirteenth transistor M13 and a second capacitor C2. The pixel circuit (PC) may receive a sweep signal Sweep, a pulse amplitude power signal PVDD1, a pulse width power signal PVDD2, a reset signal Vref, a first scan signal Scan1, a second scan signal Scan2, a pulse amplitude data signal Data_a, a pulse width data signal Data_w, a pulse amplitude emission control signal Emit_a, and a pulse width emission control signal Emit_w. The pixel circuit (PC) may control the emission duration of the sub-pixel PX based on the sweep signal Sweep and the pulse width data signal Data_w transmitted on the pulse width data signal line DL_w. The pixel circuit (PC) may also control the emission brightness of the sub-pixel PX based on the pulse amplitude data signal Data_a transmitted on the pulse amplitude data signal line DL_a. In some embodiments, the pulse amplitude data signal Data_a may be a fixed voltage, and the pulse amplitude data signal line DL_a and the pulse width data signal line DL_w may be alternately set. Figure 9 and Figure 10 (Not shown in the image), the pulse amplitude data signal line DL_a can isolate signal interference and avoid signal interference between adjacent pulse width data signal lines DL_w.

[0084] When a pixel circuit PC includes a pulse amplitude modulation module (PAM) and a pulse width modulation module (PWM), one pixel circuit PC can be connected to two data signal lines DL. The three pixel circuit PCs in a pixel circuit group PG can be electrically connected to six data signal lines DL. In some embodiments, along the second direction F2, three pulse amplitude data signal lines DL_a of the six data signal lines DL can be located on the first side of the pixel circuit group PG, and three pulse width data signal lines DL_w of the six data signal lines DL can be located on the second side of the pixel circuit group PG opposite to the first side. Adjacent pixel circuit groups PG... Six data signal lines DL can be set; in other embodiments, along the second direction F2, some pulse amplitude data signal lines DL_a of the six data signal lines DL electrically connected to the same pixel circuit group PG can be located on the first side of the pixel circuit group PG, some pulse amplitude data signal lines DL_a can be located on the second side of the pixel circuit group PG, and / or, some pulse width data signal lines DL_w can be located on the first side of the pixel circuit group PG, some pulse width data signal lines DL_w can be located on the second side of the pixel circuit group PG, and six data signal lines DL can also be set between adjacent pixel circuit groups PG.

[0085] It is understandable that when Q=M×2, the pixel circuit PC is Figure 8 The 13T2C circuit shown is for illustrative purposes only and is not intended to limit the specific circuit of the pixel circuit PC. In practical applications, the pixel circuit PC can also be a circuit structure such as 17T3C.

[0086] In other embodiments, at least the partial gate circuit demux can also be connected to the pulse amplitude data signal line DL_a, and electrically connected to the pulse amplitude modulation module PAM through the pulse amplitude data signal line DL_a.

[0087] In another alternative embodiment, refer to Figure 9 and Figure 10 The display panel 001 includes a driving circuit, which includes multiple shift registers VSR cascaded along a first direction F1; in the first direction F1, the shift registers VSR overlap with the pixel circuit PC; wherein, the length of the gating circuit demux in the second direction F2 is less than the length of the shift registers VSR in the second direction F2.

[0088] For example, the display panel 001 also includes multiple scan signal lines GL arranged along a first direction F1 and extending along a second direction F2, and the output of the shift register VSR is electrically connected to the pixel circuit PC through the scan signal lines GL. Figure 9 and Figure 10(The connection between the shift register VSR and the scan signal line GL is not shown in the diagram). The input of the shift register VSR can receive a start signal or the output signal of the previous stage shift register VSR. Along the direction perpendicular to the plane of the substrate 100, the projection of the scan signal line DL overlaps with the projection of the pixel circuit row PCR. When the shift register VSR is connected to the scan signal line GL, it may need to pass through the area where the gating circuit demux is located. By setting the length of the gating circuit demux in the second direction F2 to be less than the length of the shift register VSR in the second direction F2, it is beneficial to simplify the arrangement of the connection between the shift register VSR and the scan signal line GL and reduce its winding.

[0089] In other alternative implementations, the length of the shift register VSR in the second direction F2 can also be less than the length of the demux in the second direction F2. When the source signal line OL is connected to the data signal input port, it may need to pass through the area where the shift register VSR is located. By setting the length of the shift register VSR in the second direction F2 to be less than the length of the demux in the second direction F2, it is beneficial to simplify the arrangement of the source signal line OL and reduce its winding.

[0090] In some embodiments, a gap region IA is provided between adjacent pixel circuit rows PCR along the first direction F1, and a shift register VSR is disposed in the gap region IA. In the first direction F1, the shift register VSR may overlap with the pixel circuit group PG. In some embodiments, the length of the shift register VSR in the second direction F2 is less than the minimum spacing between adjacent signal line groups LG. In some embodiments, the driving circuit includes multiple cascaded shift registers VSR, with the i-th stage shift register VSR(i) and the (i+1)-th stage shift register VSR(i+1) arranged along the second direction F2; and the i-th stage shift register VSR(i) and the (i+2)-th stage shift register VSR(i+2) arranged along the first direction F1. Figure 7 and Figure 9 (not shown in the image), where i is a positive integer. The shift register VSR can be omitted in the interval region between some adjacent pixel circuit rows PCR, so that the shift register VSR and the gating circuit demux are not located in the interval region between the same adjacent pixel circuit rows PCR.

[0091] In yet another alternative embodiment, Figure 12 yes Figure 1 Another top-view structural diagram of the local area EA0 in the middle, for ease of understanding and explanation. Figure 12 Only the substrate 100, pixel circuit PC, sub-pixel PX, and gating circuit demux of the display panel 001 are shown; the data signal line DL, source signal line OL, and other structures are not shown. (Reference) Figure 12The display panel 001 includes a first region A1 and a second region A2 located in the first region A1 away from the first edge. The pixel circuit row PCR includes a first pixel circuit row PCR1 located in the first region A1 and a second pixel circuit row PCR2 located in the second region A2. The minimum spacing DJ2 between two adjacent second pixel circuit rows PCR2 is greater than the minimum spacing DJ1 between two adjacent first pixel circuit rows PCR1. The demux gate circuit is located between adjacent first pixel circuit rows PCR1 and second pixel circuit rows PCR2.

[0092] In this embodiment, the first region A1 is closer to the first edge E1, and the minimum spacing DJ1 between adjacent first pixel circuit rows PCR1 in the first region A1 is smaller. The pixel circuit PC in the first region A1 is recessed relative to its electrically connected sub-pixel PX. That is, along the first direction F1, at least some pixel circuit PCs in the first region A1 can be located on the side of their electrically connected sub-pixels PX away from the first edge E1. In some embodiments, along the first direction F1, the center distance between the pixel circuit PC in the second pixel circuit row PCR2 in the second region A2 and its connected sub-pixel PX is smaller than the center distance between the pixel circuit PC in the first pixel circuit row PCR1 in the first region A1 and its connected sub-pixel PX.

[0093] For example, the spacing region IA between adjacent pixel circuit rows includes a first spacing region IA1 between two adjacent first pixel circuit rows PCR1, a second spacing region IA2 between two adjacent second pixel circuit rows PCR2, and a third spacing region IA3 between adjacent first pixel circuit rows PCR1 and second pixel circuit rows PCR2. The demux gate circuit can be located in the third spacing region IA3, such as... Figure 12 As shown, the demux gate circuit can be located on the side of the first pixel circuit row PCR1 away from the first edge E1, and the demux gate circuit can also be located on the side of the second pixel circuit row PCR2 closer to the first edge E1. In some embodiments, the distance between the demux gate circuit and the first edge E1 is greater than the distance between the first pixel circuit row PCR1 and the first edge E1, and less than the distance between the second pixel circuit row PCR2 and the first edge E1.

[0094] In other alternative implementations, the demux gate circuit may also be located in a first interval region IA1 between two adjacent first pixel circuit rows PCR1 or a second interval region IA2 between two adjacent second pixel circuit rows PCR2.

[0095] In some implementations, the minimum spacing DJ2 between two adjacent second pixel circuit rows PCR2 is equal to the minimum spacing DJ3 between adjacent first pixel circuit rows PCR1 and second pixel circuit rows PCR2. DJ3 is greater than the minimum spacing DJ1 between two adjacent first pixel circuit rows PCR1, i.e., DJ2 = DJ3 > DJ1. DJ1, DJ2, and DJ3 are related to the dimensions of the first interval region IA1, the second interval region IA2, and the third interval region IA3 in the first direction F1, respectively. Setting the gating circuit demux in the third interval region IA3 between adjacent first pixel circuit rows PCR1 and second pixel circuit rows PCR2 provides sufficient space for the gating circuit demux. The gating circuit demux is not located in the first interval region IA1, which avoids the first interval region IA1 being too small in the first direction F1, affecting the arrangement of the circuit structure in the gating circuit demux. At the same time, the gating circuit demux is not located in the second interval region IA2, which also avoids the gating circuit demux being too far from the first edge E1, resulting in a too long source signal line OL, leading to a large conduction voltage drop and affecting the accuracy of the data signal.

[0096] Furthermore, in other embodiments, the minimum spacing DJ3 between adjacent first pixel circuit rows PCR1 and second pixel circuit rows PCR2 can be greater than the minimum spacing DJ2 between two adjacent second pixel circuit rows PCR2. For example, DJ3 > DJ2 > DJ1. By setting the size of the third interval region IA3 in the first direction F1 to be larger, sufficient space is available for setting the gating circuit demux when it is located in the third interval region IA3. In some embodiments, the shift register VSR and the gating circuit demux can be simultaneously located in the third interval region IA3. Additionally, setting the size of the third interval region IA3 in the first direction F1 also helps to reduce the distance between the first pixel circuit row PCR1 in the first region A1 and the first edge E1, thereby shortening the center distance between the pixel circuit PC in the first pixel circuit row PCR1 and its connected sub-pixel PX, which helps to simplify the arrangement of pixel connection lines between the pixel circuit PC in the first pixel circuit row PCR1 and its connected sub-pixel PX.

[0097] Based on the above embodiments, continue to refer to Figure 12Multiple sub-pixels PX are arranged in a sub-pixel row PXR in the second direction F2. The sub-pixel row PXR includes a first sub-pixel row PXR1 and a second sub-pixel row PXR2. The sub-pixels PX in the first sub-pixel row PXR1 are electrically connected to the pixel circuit PC in the first pixel circuit row PCR1, and the sub-pixels PX in the second sub-pixel row PXR2 are electrically connected to the pixel circuit PC in the second pixel circuit row PCR2. Along the first direction F1, the minimum distance between the first sub-pixel row PXR and the demux is a first distance LM1, and the minimum distance between the first pixel circuit row PCR1, which is electrically connected to the first sub-pixel row PXR1, and the demux is a second distance LM2. The first distance LM1 is greater than or equal to the second distance LM2.

[0098] In this embodiment, the first sub-pixel row PXR1 and the first pixel circuit row PCR1 are both located in the first region A1, and the second sub-pixel row PXR2 and the second pixel circuit row PCR2 are both located in the second region A2. In some embodiments, when the gating circuit demux is located in the third interval region IA3, the first sub-pixel row PXR1 and the first pixel circuit row PCR1 can both be located on the side of the gating circuit demux closer to the first edge E1, and the second sub-pixel row PXR2 and the second pixel circuit row PCR2 can both be located on the side of the gating circuit demux farther from the first edge E1. In some embodiments, the minimum spacing between two adjacent first sub-pixel rows PXR1 is equal to the minimum spacing between two adjacent second sub-pixel rows PXR2, or it can be equal to the minimum spacing between adjacent first sub-pixel rows PXR1 and second sub-pixel rows PXR2.

[0099] For example, taking the first sub-pixel row PXR1 closest to the first edge E1 and the first pixel circuit row PCR1 electrically connected to the first sub-pixel row PXR1 closest to the first edge E1 as an example, refer to... Figure 12 The first pixel circuit row PCR1 and the first sub-pixel row PXR1, which are closest to the first edge E1, are both located on the side of the demux gating circuit closest to the first edge E1. Compared to the first pixel circuit row PCR1, the first sub-pixel row PXR1, which is closest to the first edge E1, is closer to the first edge E1 along the first direction F1. That is, along the first direction F1, the first sub-pixel row PXR1, which is closest to the first edge E1, is farther from the demux gating circuit, making the first distance LM1 greater than or equal to the second distance LM2.

[0100] In conventional techniques, the demux gate circuit is located on the side of the first pixel circuit row PCR1 closest to the first edge E1. Figure 12(Not shown in the diagram) This may cause some of the first sub-pixel rows PXR1 to be closer to the demux, while the first pixel circuit row PCR1 electrically connected to these PXR1 may be farther from the demux, meaning the first distance LM1 is less than the second distance LM2. This would exacerbate the inward shrinkage of the first pixel circuit row PCR1, increasing the distance between the first sub-pixel rows PXR1 and PCR1, which is detrimental to shortening the pixel connection line between the sub-pixel PX in the first region A1 and its electrically connected pixel circuit PC. By placing the demux in the third interval region IA3, the first distance LM1 can be made greater than or equal to the second distance LM2. This would help reduce the inward shrinkage of the first pixel circuit row PCR1, shorten the distance between the first sub-pixel rows PXR1 and PCR1, and thus shorten the pixel connection line between the sub-pixel PX in the first region A1 and its electrically connected pixel circuit PC. In some implementations, along the first direction F1, the spacing between the sub-pixel PX in the first region A1 and its electrically connected pixel circuit PC is smaller than the spacing between two adjacent first sub-pixel rows PXR1. This can effectively shorten the pixel connection lines between the sub-pixel PX in the first region A1 and its electrically connected pixel circuit PC, simplify the arrangement of pixel connection lines, and help improve display uniformity.

[0101] Optional, Figure 13 yes Figure 1 Another top-view structural diagram of the local area EA0 in the middle, for ease of understanding and explanation. Figure 13 Only the substrate 100, pixel circuit PC, sub-pixel PX, and demux of the display panel 001 are shown; the data signal line DL, source signal line OL, and other structures are not shown. (Reference) Figure 12 and Figure 13 Sub-pixel PX includes a first sub-pixel PX1. The first sub-pixel PX1 and its electrically connected pixel circuit PC are both located on the side of the gating circuit demux close to the first edge E1. Along the first direction F1, the minimum distance between the first sub-pixel PX1 and its electrically connected pixel circuit PC is the third distance LM3, and the minimum distance between the first sub-pixel PX1 and the gating circuit demux is the fourth distance LM4. The third distance LM3 is less than the fourth distance LM4.

[0102] Specifically, by reducing the distance between the first sub-pixel PX1 located near the first edge of the demux gating circuit and the pixel circuit PC, the connection between the first sub-pixel PX1 and the demux gating circuit can be effectively shortened.

[0103] For example, the sub-pixel PX in the sub-pixel row PXR closest to the first edge E1 can be a first edge sub-pixel. The first sub-pixel PX1 includes the first edge sub-pixel. Taking the first edge sub-pixel and the pixel circuit PC electrically connected to the first edge sub-pixel as an example, refer to... Figure 12 and Figure 13 Along the first direction F1, the first edge sub-pixel is located on the side of its electrically connected pixel circuit PC closer to the first edge E1. The distance between the first edge sub-pixel and its electrically connected pixel circuit PC is less than the distance between the first edge sub-pixel and the demux gate circuit, which can effectively shorten the pixel connection line between the first edge sub-pixel and its electrically connected pixel circuit PC. Figure 12 and Figure 13 (Not shown in the image).

[0104] In conventional technology, the demux gate circuit is located on the side of the pixel circuit PC electrically connected to the first edge sub-pixel closer to the first edge E1, while the demux gate circuit is located on the side of the first edge sub-pixel farther from the first edge E1. Figure 12 and Figure 13 (Not shown in the diagram), that is, along the first direction F1, a demux is provided between the first edge sub-pixel and its electrically connected pixel circuit PC. This increases the distance between the first edge sub-pixel and its electrically connected pixel circuit PC, making the third distance LM3 greater than the fourth distance LM4, which is not conducive to shortening the pixel connection line between the first edge sub-pixel and its electrically connected pixel circuit PC. In this embodiment, by setting the demux along the first direction F1 to be located on the side of the pixel circuit PC away from the first edge E1, the third distance LM3 can be made greater than the fourth distance LM4, effectively shortening the distance between the first sub-pixel PX1 and its electrically connected pixel circuit PC, which is beneficial for shortening the pixel connection line between the first sub-pixel PX1 and its electrically connected pixel circuit PC.

[0105] Optional, Figure 14 yes Figure 9 Another top-view structural diagram of the third sub-region EA3, see reference. Figure 9 and Figure 14 The demux circuit includes a plurality of demux transistors SW arranged along the second direction F2. The channel length of the demux transistors SW extends along the first direction F1, and the channel length of the demux transistors SW is less than its channel width.

[0106] Specifically, the first and second terminals of the selection transistor SW are electrically connected to the source signal line PL and the data signal line DL, respectively. By arranging multiple selection transistors SW in the selection circuit demux sequentially along the second direction F2, and extending the channel length of the selection transistors SW along the first direction F1, it is beneficial to reduce the size of the selection circuit demux in the first direction F1. The channel length of the selection transistor SW is smaller than its channel width, and the channel length extends along the first direction F1, allowing the channel width to extend along the second direction F2. This can improve the current driving capability and response speed of the selection transistors SW while reducing the impact on the size of the selection circuit demux in the first direction F1, thus helping to compress the size of the selection circuit demux in the first direction F1.

[0107] In this embodiment, the channel length and channel width of the gate transistor SW are both its equivalent channel length and equivalent channel width. In some implementations, the gate transistor SW may include multiple sub-transistors connected in parallel. Figure 14 The example shows a gate transistor SW comprising five parallel sub-transistors. The multiple parallel sub-transistors can be arranged sequentially along the second direction F2. The channel length of the sub-transistors extends along the first direction F1, and the channel width of the sub-transistors extends along the second direction F2. The channel length of the sub-transistor can be less than the channel width of the sub-transistor, or the channel length of the sub-transistor can be greater than the channel width of the sub-transistor. The equivalent channel length after the multiple sub-transistors are connected in parallel is less than the equivalent channel width.

[0108] In some implementations, the gate transistor SW may include multiple sub-transistors connected in parallel, and these sub-transistors have the same channel length and the same channel width.

[0109] In an alternative embodiment, reference continues. Figure 9 and Figure 14 The selection transistor SW includes a first selection transistor SW1 and a second selection transistor SW2, and the data signal line DL includes a first data signal line DL1 and a second data signal line DL2. The first selection transistor SW1 is electrically connected to the first data signal line DL1, and the second selection transistor SW2 is electrically connected to the second data signal line DL2. The display panel 001 also includes a data signal line group DG electrically connected to the selection circuit demux. The data signal line group DG includes at least the first data signal line DL1 and the second data signal line DL2. In the same selection circuit demux and its electrically connected data signal line group DG, the second selection transistor SW2 is located on the side of the first selection transistor SW1 away from the second data signal line DL2, and the first data signal line DL1 is located on the side of the second data signal line DL2 away from the first selection transistor SW1.

[0110] Specifically, in the same demux and its electrically connected data signal line group DG, the first data signal line DL1 is located on the side of the second data signal line DL2 away from the demux, and the second demux transistor SW2 is located on the side of the first demux transistor SW1 away from the data signal line group DG. That is, the arrangement direction of the first data signal line DL1 and the second data signal line DL2 is the same as the arrangement direction of the first demux transistor SW1 and the second demux transistor SW2.

[0111] For example, the demux circuit further includes a third demux transistor SW3, and the data signal line group DG further includes a third data signal line DL3. The arrangement direction of the first data signal line DL1, the second data signal line DL2, and the third data signal line DL3 is the same as the arrangement direction of the first demux transistor SW1, the second demux transistor SW2, and the third demux transistor SW3.

[0112] For example, Figure 15 yes Figure 9 A schematic diagram of a membrane structure in the local region EA4 of the fourth subunit, referenced. Figure 9 , Figure 14 , Figure 15 The display panel 001 includes an active layer AM, a first conductive layer CM-1, a second conductive layer CM-2, a third conductive layer CM-3, and a fourth conductive layer CM-4, which are sequentially stacked on one side of the substrate 100. At least some of the transistor gates are located in the first conductive layer CM-1, while the data signal line DL and the source signal line OL may be located in the second conductive layer CM-2. In some embodiments, the pixel connection line PL between the sub-pixel PX and its electrically connected pixel circuit PC may be located in the third conductive layer CM-3, and the pixel electrode ed connecting the sub-pixel PX and the pixel connection line PL may be located in the fourth conductive layer CM-4. In some embodiments, the gating transistor SW of the gating circuit demux is electrically connected to the data signal line DL via a gating connection line WL, and the data signal line DL and the gating connection line WL can be connected via a conductive structure located in the first conductive layer CM-1; the data signal line DL and the pixel circuit PC can also be electrically connected via a conductive structure in the first conductive layer CM-1. In some embodiments, the gating signal line CL may be located in the first conductive layer CM-1.

[0113] It should be noted that, Figure 15 Only through the membrane structure Figure 9 The electrical connections of the fourth subregion EA4 and the positions of some membrane layers are illustrated, but this is not intended to limit the spatial relationships of the structures. In practical applications, the spatial relationships of some structures can be... Figure 15Unlike other applications, in practical applications, the demux (gating circuit) and PC (pixel circuit) electrically connected to the same data signal line DL can be located on the same side of the data signal line DL, without needing to be like... Figure 15 The setup shown has the demux and pixel circuits PC located on different sides of the data signal line DL.

[0114] In another alternative embodiment, Figure 16 This is a top-view structural diagram of the fourth sub-region EA4 in section 9, for reference. Figure 9 and Figure 16 The display panel 001 also includes multiple first color sub-pixels PX-1 and second color sub-pixels PX-2. The emission wavelength of the first color sub-pixels PX-1 is greater than the emission wavelength of the second color sub-pixels PX-2. The pixel circuit PC includes a first pixel circuit PC1 and a second pixel circuit PC2. The first color sub-pixels PX-1 are electrically connected to the first pixel circuit PC1, and the second color sub-pixels PX-2 are electrically connected to the second pixel circuit PC2. The gating transistor SW includes a first gating transistor SW1 and a second gating transistor SW2. The data signal line DL includes a first data signal line DL1 and a second data signal line DL2. The first gating transistor SW1 is electrically connected to the first pixel circuit PC1 through the first data signal line DL1, and the second gating transistor SW2 is electrically connected to the second pixel circuit PC2 through the second data signal line DL2. The channel width of the first gating transistor SW1 is greater than the channel width of the second gating transistor SW2.

[0115] Specifically, the luminous efficiency of the first color sub-pixel PX-1 is lower than that of the second color sub-pixel PX-2. The first selection transistor SW1 is used to selectively transmit the data signal used to drive the first color sub-pixel PX-1. By setting the channel width of the first selection transistor SW1 to be larger, it is beneficial to reduce the on-resistance and the influence of the first selection transistor SW1 on the luminous brightness of the first color sub-pixel PX-1. At the same time, the second selection transistor SW2 is used to selectively transmit the data signal used to drive the second color sub-pixel PX-2. By setting the channel width of the second selection transistor SW2 to be smaller, it is beneficial to appropriately increase the on-resistance and balance the brightness difference caused by the different luminous efficiencies, thereby improving the display effect of the display panel 001.

[0116] For example, refer to Figure 9 and Figure 16The display panel 001 also includes a plurality of third color sub-pixels PX-3, the emission wavelength of which is less than that of the second color sub-pixel PX-2; the pixel circuit PC also includes a third pixel circuit PC3, and the third color sub-pixel PX-3 is electrically connected to the third pixel circuit PC3; the selection transistor SW also includes a third selection transistor SW3, and the data signal line DL also includes a third data signal line DL3, the third selection transistor SW3 being connected to the third pixel circuit PC3 via the third data signal line DL3; the channel width of the third selection transistor SW3 is less than the channel width of the second selection transistor SW2. In some embodiments, the channel lengths of the first selection transistor SW1, the second selection transistor SW2, and the third selection transistor SW3 are the same.

[0117] In some embodiments, the gate transistor includes a plurality of sub-transistors connected in parallel, and these sub-transistors all have the same channel length and the same channel width. The number of sub-transistors connected in parallel in the first gate transistor SW1 is greater than the number of sub-transistors connected in parallel in the second gate transistor SW2, and the number of sub-transistors connected in parallel in the second gate transistor SW2 is greater than the number of sub-transistors connected in parallel in the third gate transistor SW3.

[0118] Based on the above embodiments, the pixel circuit PC includes a driving transistor ( Figure 9 and Figure 16 (Not shown in the diagram); the channel width of the first select transistor SW1 is greater than the channel width of the driving transistor; and / or, the channel width of the second select transistor SW2 is less than the channel width of the driving transistor. For example, the driving transistor, the first select transistor SW1, and the second select transistor SW2 each include multiple sub-transistors connected in parallel, and these sub-transistors all have the same channel length and the same channel width. The number of sub-transistors connected in parallel in the first select transistor SW1 is greater than the number of sub-transistors connected in parallel in the driving transistor, and / or, the number of sub-transistors connected in parallel in the second select transistor SW2 is less than the number of sub-transistors connected in parallel in the driving transistor.

[0119] In yet another alternative embodiment, refer to Figure 9 and Figure 16The display panel 001 includes multiple first color sub-pixels PX-1 and second color sub-pixels PX-2. The emission wavelength of the first color sub-pixels PX-1 is greater than the emission wavelength of the second color sub-pixels PX-2. The pixel circuit PC includes a first pixel circuit PC1 and a second pixel circuit PC2. The first color sub-pixels PX-1 are electrically connected to the first pixel circuit PC1, and the second color sub-pixels PX-2 are electrically connected to the second pixel circuit PC2. The gating transistor SW includes a first gating transistor SW1 and a second gating transistor SW2. The data signal line DL includes a first data signal line DL1 and a second data signal line DL2. The first gating transistor SW1 is electrically connected to the first pixel circuit PC1 through the first data signal line DL1, and the second gating transistor SW2 is electrically connected to the second pixel circuit PC2 through the second data signal line DL2. The minimum distance between the first gating transistor SW1 and its electrically connected first data signal line DL1 is a fifth distance LM5, and the minimum distance between the second gating transistor SW2 and its electrically connected second data signal line DL2 is a sixth distance LM6. The fifth distance LM5 is less than the sixth distance LM6.

[0120] Specifically, the luminous efficiency of the first color sub-pixel PX-1 is lower than that of the second color sub-pixel PX-2. The fifth distance LM5 between the first selection transistor SW1 and its electrically connected first data signal line DL1 is smaller, which helps to reduce the conduction impedance of the selection connection line WL between the first selection transistor SW1 and its electrically connected first data signal line DL1, and helps to reduce the influence of the selection connection line WL on the luminous brightness of the first color sub-pixel PX-1. At the same time, the sixth distance LM6 between the second selection transistor SW2 and its electrically connected second data signal line DL2 is larger, which helps to appropriately increase the conduction impedance of the selection connection line WL between the second selection transistor SW2 and its electrically connected second data signal line DL2, and helps to balance the brightness difference caused by the different luminous efficiencies, thereby improving the display effect of the display panel 001.

[0121] For example, refer to Figure 9 and Figure 16 The display panel 001 also includes multiple third color sub-pixels PX-3, the emission wavelength of the third color sub-pixels PX-3 is less than the emission wavelength of the second color sub-pixels PX-2; the pixel circuit PC also includes a third pixel circuit PC3, the third color sub-pixels PX-3 are electrically connected to the third pixel circuit PC3; the gating transistor SW also includes a third gating transistor SW3, the data signal line DL also includes a third data signal line DL3, the third gating transistor SW3 is connected to the third pixel circuit PC3 through the third data signal line DL3; the minimum distance between the third gating transistor SW3 and the third data signal line DL3 to which it is electrically connected is greater than the sixth distance LM6.

[0122] In one implementation, continue to refer to Figure 16 In the same demux circuit and its electrically connected data signal line group DG, the data signal line DL with the smallest distance from the electrically connected demux transistor SW can be located furthest from the demux transistor SW, the data signal line DL with a larger distance from the electrically connected demux transistor SW can be located closer to the demux transistor SW, and the data signal line with the largest distance from the electrically connected demux transistor SW can be located closest to the demux transistor SW2. That is, the arrangement direction of the first data signal line DL1, the second data signal line DL2, and the third data signal line DL3 is the same as the arrangement direction of the first demux transistor SW1, the second demux transistor SW2, and the third demux transistor SW3.

[0123] In another embodiment, Figure 17 This is another top-view structural diagram of the fourth sub-region EA4 in section 9, for reference. Figure 17 In the same demux circuit and its electrically connected data signal line group DG, the data signal line DL with the smallest distance from the electrically connected demux transistor SW can be located closest to the demux transistor SW, the data signal line DL with a larger distance from the electrically connected demux transistor SW can be located farther from the demux transistor SW, and the data signal line with the largest distance from the electrically connected demux transistor SW2 can be located farthest from the demux transistor SW2. That is, the arrangement direction of the first data signal line DL1, the second data signal line DL2, and the third data signal line DL3 is opposite to the arrangement direction of the first demux transistor SW1, the second demux transistor SW2, and the third demux transistor SW3.

[0124] In other embodiments, the arrangement directions of the first data signal line DL1, the second data signal line DL2, and the third data signal line DL3, and the arrangement directions of the first gating transistor SW1, the second gating transistor SW2, and the third gating transistor SW3, can also be out of order. For example, along the arrangement direction of the first data signal line DL1, the second data signal line DL2, and the third data signal line DL3, the second gating transistor SW2, the first gating transistor SW1, and the third gating transistor SW3 are arranged sequentially; or, for example, the second data signal line DL2, the third data signal line DL3, and the first data signal line DL1 are arranged sequentially, and along the arrangement direction of the second data signal line DL2, the third data signal line DL3, and the first data signal line DL1, the third gating transistor SW3, the first gating transistor SW1, and the second gating transistor SW2 are arranged sequentially.

[0125] In some embodiments, the minimum distance between the first pixel circuit PC1 and its electrically connected first data signal line DL1 is less than the minimum distance between the second pixel circuit PC2 and its electrically connected second data signal line DL2, and the minimum distance between the third pixel circuit PC3 and its electrically connected third data signal line DL3 is greater than the minimum distance between the second pixel circuit PC2 and its electrically connected second data signal line DL2. The arrangement direction of the first data signal line DL1, the second data signal line DL2, and the third data signal line DL3 may be the same as or different from the arrangement direction of the first pixel circuit PC1, the second pixel circuit PC2, and the third pixel circuit PC3.

[0126] Based on the above embodiments, Figure 18 This is another top-view structural diagram of the fourth sub-region EA4 in section 9, for reference. Figure 18 The demux circuit includes N demux transistors SW, which are electrically connected to N data signal lines DL. Among the N data signal lines DL electrically connected to the same demux circuit, there are at most K adjacent data signal lines without spaced-out demux transistors SW, where K is a positive integer and K < N.

[0127] Specifically, the N data signal lines DL electrically connected to the same demux gating circuit may not be located on the same side of the demux gating circuit, for example... Figure 18 As shown, of the three data signal lines DL electrically connected to the same demuxing circuit, two data signal lines DL are located on the first side of the demuxing circuit in the second direction F2, and one data signal line DL is located on the second side of the demuxing circuit in the second direction F3, opposite to the first side. Thus, the N gating connection lines WL between the N gating transistors SW and the N data signal lines DL in the same demuxing circuit do not need to be arranged sequentially along the first direction F1, which helps to reduce the space occupied by the demuxing circuit in the first direction F1.

[0128] For example, with N=3 and K=2, among the three data signal lines DL electrically connected to the same demuxing circuit, the first data signal line DL1 connected to the first color sub-pixel PX-1 and the second data signal line DL2 connected to the second color sub-pixel PX-2 are located on the first side of the demuxing circuit in the second direction F2, and the third data signal line DL3 connected to the third color sub-pixel PX-3 is located on the second side of the demuxing circuit in the second direction F2. In some embodiments, the emission wavelength of the first color sub-pixel PX-1 is greater than that of the second color sub-pixel PX-2, and the emission wavelength of the third color sub-pixel PX-3 is greater than that of the second color sub-pixel PX-2. This helps to balance the brightness differences caused by different luminous efficiencies and improves the display effect.

[0129] In other embodiments, among the N data signal lines DL electrically connected to the same demux gating circuit, some data signal lines DL may be located between two adjacent gating transistors SW in the same demux gating circuit. In some embodiments, the gating transistor SW may be arranged adjacent to the data signal lines DL to which it is electrically connected. Figure 18 (not shown in the image), which helps to reduce the number of gating connection lines WL arranged along the first direction F1, and further compresses the space occupied by the gating circuit demux in the first direction F1.

[0130] In yet another alternative embodiment, reference continues to... Figures 16-17 The display panel 001 also includes a data signal line group DG electrically connected to the demux gating circuit. The data signal line group DG includes at least two data signal lines DL. In the second direction F2, the data signal line group DG is adjacent to the demux gating circuit. In the second direction F2, the source signal line OL is also adjacent to the demux gating circuit, and the source signal line OL is located on the side of the demux gating circuit away from the data signal line group DG.

[0131] Specifically, the data signal line group DG is adjacent to the gating circuit demux along the second direction F2. No other structures are set between the data signal line group DG and the gating circuit demux, for example, no source signal line OL is set between the data signal line group DG and the gating circuit demux; the source signal line OL is also adjacent to the gating circuit demux, and no other structures are set between the source signal line OL and the gating circuit demux, for example, no data signal line DL is set between the source signal line OL and the gating circuit demux.

[0132] Optional, Figure 19 This is a top view schematic diagram of a gating circuit provided in an embodiment of this application, with reference to... Figures 16-19 The display panel 01 also includes a gating signal line group CG, which includes multiple gating signal lines CL extending along the second direction F2; along the first direction F1, the gating signal line group CG is adjacent to the gating circuit demux; the gating circuit demux also includes a gate connection portion WGC extending at least partially along the first direction F1, the gate connection portion WG connecting the gate Gsw of the gating transistor SW and the gating signal line CL; the gating circuit demux also includes an electrode connection portion WW, the electrode connection portion WW connecting the first electrode W1 of the adjacent gating transistor SW; the gating transistor SW includes a first electrode W1 and a second electrode W2 arranged along the first direction F1, the first electrode W1 being located on the side of the second electrode W2 closer to the gating signal line group CG; the first electrode W1 is electrically connected to the source signal line OL, and the second electrode W2 is electrically connected to the data signal line DL.

[0133] In this configuration, the gating signal line group CG is disposed adjacent to the gating circuit demux. Along the first direction F1, the gating signal line group CG can be located on the side of the gating circuit demux closer to the first edge E1, or it can be located on the side of the gating circuit demux farther from the first edge E1. In some embodiments, along the first direction F1, the gating signal line group CG is located between adjacent pixel circuit rows PCR.

[0134] For example, Figure 20 yes Figure 19 A sectional view of the structure with section B1-B1' is shown in the diagram. (Refer to...) Figures 19-20 The gate transistor SW includes an active layer AM, a gate Gsw, a first electrode W1, and a second electrode W2. In some embodiments, the gate Gsw is located on the first conductive layer CM-1, the first electrode W1 and the second electrode W2 are located on the second conductive layer CM-2, the active layer AM is located on the side of the first conductive layer CM-1 closer to the substrate 100, and the second conductive layer CM-2 is located on the side of the first conductive layer CM-1 away from the substrate 100. Specifically, along a direction perpendicular to the plane of the substrate 100, the gate Gsw overlaps with the active layer AM, and the first electrode W1 and the second electrode W2 also overlap with the active layer AM.

[0135] In some embodiments, within the same demux, the first electrodes W1 of multiple selection transistors SW, the electrode connection portions WW between the first electrodes W1, and the source signal line OL can all be located in the second conductive layer CM-2. Furthermore, within the same demux, the first electrodes W1, the electrode connection portions WW between the first electrodes W1, and the source signal line OL can be an integral structure. Specifically, along a direction perpendicular to the plane of the substrate 100, the electrode connection portions WW and the active layer AM do not overlap, nor does the source signal line OL overlap with the active layer AM.

[0136] In some embodiments, the second terminal W1 of the gate transistor SW can be electrically connected to the data signal line DL via a gate connection line WL, which is located on the side of the gate transistor SW away from the gate signal line group CG. The gate Gsw of the gate transistor SW can be electrically connected to the gate signal line CL via a gate connection portion WGC. Along a direction perpendicular to the plane of the substrate 100, the gate connection portion WGC does not overlap with the active layer AM, but it overlaps with the gate signal line CL.

[0137] In an alternative embodiment, reference continues. Figures 19-20The gate signal line CL includes a first gate portion CB1 and a second gate portion CB2. Along a direction perpendicular to the plane of the substrate 100, the first gate portion CB1 overlaps with the data signal line DL and / or the source signal line OL, and the second gate portion CB2 does not overlap with the data signal line DL. The gate Gsw, gate connection portion WGC, and first gate portion CB1 of the gate transistor SW are located in the first conductive layer CM-1, and the first electrode W1, electrode connection portion WW, and second gate portion CB2 of the gate transistor SW are located in the second conductive layer CM-2. The electrode connection portion WW extends along the second direction F2. Along the second direction F2, the electrode connection portion WW overlaps with the first electrode W1.

[0138] For example, both the data signal line DL and the source signal line OL extend along the first direction F1, and both the data signal line DL and the source signal line OL are located in the second conductive layer CM-2. The first electrode W1 and the electrode connection portion WW are also located in the second conductive layer CM-2. Along a direction perpendicular to the plane of the substrate 100, the first selection portion CB1 of the selection signal line CL, which overlaps with the data signal line DL and / or the source signal line OL, is located in a different conductive layer from the data signal line DL and the source signal line OL. The second selection portion CB2 of the selection signal line CL, which overlaps with the data signal line DL and the source signal line OL, can be located in the same conductive layer as the data signal line DL and the source signal line OL, so that the second selection portion CB2 can be located in the same conductive layer as the first electrode W1 and the electrode connection portion WW, all located in the second conductive layer CM-2. Thus, the gate G is connected... The gate connection portion WGC of sw and the gate signal line CL can be disposed in the same layer as the gate Gsw, both located in the first conductive layer CM-1. When the gate connection portion WGC extends to the end that connects to the second gate portion CB2 (this end is located at the end of the gate connection portion WGC away from the gate Gsw, located in the direction perpendicular to the plane of the substrate 100, and this end overlaps with the second gate portion CB2), it will not affect the electrode connection portion WW located in the direction perpendicular to the plane of the substrate 100 and overlapping with the gate connection portion WGC, which is beneficial to simplifying the structure of the electrode connection portion WW.

[0139] In some implementations, the first pole W1 and the electrode connection WW of the same demux gate circuit form a linear integrated structure.

[0140] In another alternative embodiment, Figure 21 This is a top view schematic diagram of another gating circuit provided in an embodiment of this application. Figure 22 yes Figure 21 A cross-sectional view of the structure with section B2-B2'. Figure 23 yes Figure 21 A top view of the first conductive layer in the middle. Figure 24 yes Figure 21 A top view of the second conductive layer, for reference. Figures 21-24 The strobe signal line CL includes a first strobe signal line CL1 and a second strobe signal line CL2. The first strobe signal line CL1 is adjacent to the strobe transistor SW, and the second strobe signal line CL2 is located on the side of the first strobe signal line CL1 away from the strobe transistor SW. The gate connection portion WGC includes a first gate connection portion WGC1 and a second gate connection portion WGC2. The first gate connection portion WGC1 is electrically connected to the first strobe signal line CL1, and the second gate connection portion WGC2 is electrically connected to the second strobe signal line CL2. The second gate connection portion WGC2 includes a first sub-connection portion CO1 and a second sub-connection portion CO2. The first sub-connection portion CO1 is connected to the gate Gsw of the strobe transistor SW and the second sub-connection portion CO2, and the second sub-connection portion CO2 is connected to the first sub-connection portion CO1 and the second strobe signal line CL2.

[0141] The gate Gsw of the gate transistor SW, the first gate connection portion WGC1, the first sub-connection portion C01 of the second gate connection portion WGC2, and the gate signal line CL are located in the first conductive layer CM-1. The second sub-connection portion C02 of the second gate connection portion WGC2, the first electrode W1 of the gate transistor SW, and the electrode connection portion WW are located in the second conductive layer CM-2. At least a portion of the first sub-connection portion C01 of the second gate connection portion WGC2 extends along the second direction F2, and the second sub-connection portion C02 of the second gate connection portion WGC2 extends along the first direction F1. Along the second direction F2, the second sub-connection portion C02 of the second gate connection portion WGC2 overlaps with the first electrode W1. Along the first direction, the electrode connection portion WW is located on the side of the second sub-connection portion C02 of the second gate connection portion WGC2 away from the gate signal line CL.

[0142] For example, refer to Figures 21-24 ,and Figures 19-20The difference is that the overlapping and non-overlapping portions of the gating signal line CL with the data signal line DL and the source signal line OL are both located in the first conductive layer CM-1. This helps reduce overlap, lowers the risk of overlap-related line replacement, and improves the reliability of the gating signal line CL. For the first gate connection portion WGC1, which overlaps only with one gating signal line CL (the first gating signal line CL1) along the direction perpendicular to the plane of the substrate 100, it can be located in the first conductive layer CM-1 along with the gate Gsw of the gating transistor SW and the first gating signal line CL1, and form an integral structure. For the second gate connection portion WGC2, which overlaps with multiple gate signal lines CL (including the first gate signal line CL1 and the second gate signal line CL2) in a direction perpendicular to the plane of the substrate 100, it can be connected to the corresponding gate signal line CL through the second sub-connection portion CO2 located in the second conductive layer CM-2. In order to avoid short circuit between the electrode connection portion WW and the second sub-connection portion CO2, the electrode connection portion WW can be located on the side of the second sub-connection portion CO2 away from the gate signal line CL. In order to avoid short circuit between the electrode connection portion WW and the first electrode W1 and the second electrode W2, the second gate connection portion WGC also includes a first sub-connection portion CO1 located in the first conductive layer CM-1. At least a portion of the first sub-connection portion CO1 extends along the second direction F2, and in a direction perpendicular to the plane of the substrate 100, the first sub-connection portion CO1 overlaps with the second sub-connection portion CO2, which is beneficial to increase the distance between the second sub-connection portion CO2 and the first electrode W1 or the second electrode W2 in the second direction F2, thereby improving signal reliability.

[0143] In some implementations, the electrode connection portion WW can be an "Ω" shaped structure.

[0144] In some embodiments, a portion of the first sub-connection C01 may also extend along the first direction F1. Compared to the portion extending along the second direction F2, the portion extending along the first direction F1 is closer to the gating signal line CL, which helps to compress the length of the second sub-connection C02 in the first direction F1, shortens the maximum distance between the electrode connection WW and the gating signal line CL, helps to compress the size of the electrode connection WW in the first direction F1, and simplifies the layout.

[0145] In some embodiments, along the second direction F2, the first sub-connection C01 overlaps with the gate Gsw of the gate transistor SW; along the direction perpendicular to the plane of the substrate 100, the electrode connection WW overlaps with the first sub-connection C01. This allows the orthographic projections of the electrode connection WW onto the plane of the substrate 100 and the gate Gsw onto the plane of the substrate 100 to be aligned along the second direction F2, and also helps to compress the size of the electrode connection WW in the first direction F1, simplifying the arrangement.

[0146] Based on the same inventive concept, embodiments of this application also provide a display device. Figure 25 This is a schematic diagram of the structure of a display device provided in an embodiment of this application, such as... Figure 25 The display device 002 includes the display panel 001 provided in any embodiment of this application. The display device 001 provided in the embodiments of this application can be... Figure 25 The rectangular display device shown can also be a display device of any shape. The display device 001 provided in this application embodiment can be any electronic product with display function, including but not limited to the following categories: splicing display, television, laptop, desktop display, tablet computer, digital camera, smart bracelet, smart glasses, vehicle display, medical equipment, industrial control equipment, touch interactive terminal, etc. This application embodiment does not make any special limitation in this regard.

[0147] Note that the above are merely preferred embodiments and the technical principles employed in this application. Those skilled in the art will understand that this application is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of this application. Therefore, although this application has been described in detail through the above embodiments, this application is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of this application, the scope of which is determined by the scope of the appended claims.

Claims

1. A display panel, characterized in that, It includes a substrate, and multiple pixel circuits, multiple gating circuits, multiple data signal lines extending along a first direction, and multiple source signal lines located on one side of the substrate; The gating circuit includes a gating input terminal and multiple gating output terminals; the gating input terminal is electrically connected to the source signal line; the multiple gating output terminals are respectively electrically connected to multiple data signal lines; The substrate includes a first edge extending along a second direction, the first direction intersecting the second direction; the source signal line is located on the side of the gating circuit to which it is electrically connected, near the first edge; The gating circuit is located on the side of a portion of the pixel circuit that is away from the first edge.

2. The display panel according to claim 1, characterized in that, The plurality of pixel circuits are arranged in a pixel circuit row in the second direction, and the pixel circuit row is arranged along the first direction; along the first direction, the gating circuit is located between adjacent pixel circuit rows.

3. The display panel according to claim 2, characterized in that, The pixel circuit row includes a plurality of pixel circuit groups arranged along the second direction, and the pixel circuit group includes M pixel circuits, M≥2; in the first direction, the gating circuit overlaps with the pixel circuit group.

4. The display panel according to claim 3, characterized in that, The display panel further includes a plurality of signal line groups extending along the first direction and arranged along the second direction; along the second direction, the signal line groups are provided on both sides of the pixel circuit group; the length of the gating circuit in the second direction is less than the minimum spacing between adjacent signal line groups.

5. The display panel according to claim 3, characterized in that, The gating circuit includes N gating output terminals, where N≥2; and M=N.

6. The display panel according to claim 2, characterized in that, The display panel includes a driving circuit, which includes a plurality of shift registers cascaded along the first direction; in the first direction, the shift registers overlap with the pixel circuit; wherein, The length of the gating circuit in the second direction is less than the length of the shift register in the second direction.

7. The display panel according to claim 2, characterized in that, The display panel includes a first area and a second area located in the first area away from the first edge. The pixel circuit rows include a first pixel circuit row located in the first area and a second pixel circuit row located in the second area. The minimum spacing between two adjacent second pixel circuit rows is greater than the minimum spacing between two adjacent first pixel circuit rows. The gating circuit is located between adjacent rows of the first and second pixel circuits.

8. The display panel according to claim 7, characterized in that, The minimum spacing between adjacent first pixel circuit rows and second pixel circuit rows is greater than the minimum spacing between two adjacent second pixel rows.

9. The display panel according to claim 7, characterized in that, Also includes: Multiple sub-pixels, wherein the sub-pixels are electrically connected to the pixel circuit; The plurality of said sub-pixels are arranged in a sub-pixel row in the second direction. The sub-pixel row includes a first sub-pixel row and a second sub-pixel row. The sub-pixels in the first sub-pixel row are electrically connected to the pixel circuits in the first pixel circuit row, and the sub-pixels in the second sub-pixel row are electrically connected to the pixel circuits in the second pixel circuit row. Wherein, along the first direction, the minimum distance between the first sub-pixel row and the gating circuit is the first distance, and the minimum distance between the first pixel circuit row electrically connected to the first sub-pixel row and the gating circuit is the second distance, and the first distance is greater than or equal to the second distance.

10. The display panel according to claim 1, characterized in that, Also includes: Multiple sub-pixels, wherein the sub-pixels are electrically connected to the pixel circuit; The sub-pixel includes a first sub-pixel, and the first sub-pixel and the pixel circuit electrically connected to it are both located on the side of the gating circuit closer to the first edge; Along the first direction, the minimum distance between the first sub-pixel and the pixel circuit electrically connected to it is the third distance, and the minimum distance between the first sub-pixel and the gating circuit is the fourth distance, wherein the third distance is less than the fourth distance.

11. The display panel according to claim 1, characterized in that, The gating circuit includes a plurality of gating transistors arranged along the second direction, the channel length of the gating transistors extending along the first direction, and the channel length of the gating transistors being less than their channel width.

12. The display panel according to claim 11, characterized in that, The display panel further includes a plurality of first color sub-pixels and second color sub-pixels, wherein the emission wavelength of the first color sub-pixels is greater than the emission wavelength of the second color sub-pixels; the pixel circuit includes a first pixel circuit and a second pixel circuit, wherein the first color sub-pixels are electrically connected to the first pixel circuit and the second color sub-pixels are electrically connected to the second pixel circuit. The gating transistor includes a first gating transistor and a second gating transistor, and the data signal line includes a first data signal line and a second data signal line. The first gating transistor is electrically connected to the first pixel circuit through the first data signal line, and the second gating transistor is electrically connected to the second pixel circuit through the second data signal line. The channel width of the first gate transistor is greater than the channel width of the second gate transistor.

13. The display panel according to claim 12, characterized in that, The pixel circuit includes a driving transistor; The channel width of the first gate transistor is greater than the channel width of the driving transistor; and / or, the channel width of the second gate transistor is less than the channel width of the driving transistor.

14. The display panel according to claim 11, characterized in that, The gating transistor includes a first gating transistor and a second gating transistor, and the data signal line includes a first data signal line and a second data signal line; the first gating transistor is electrically connected to the first data signal line, and the second gating transistor is electrically connected to the second data signal line; The display panel also includes: A group of data signal lines electrically connected to the gating circuit, the group of data signal lines including at least the first data signal line and the second data signal line; In the same gating circuit and the group of data signal lines electrically connected thereto, the second gating transistor is located on the side of the first gating transistor away from the second data signal line, and the first data signal line is located on the side of the second data signal line away from the first gating transistor.

15. The display panel according to claim 11, characterized in that, The display panel further includes a plurality of first color sub-pixels and second color sub-pixels, wherein the emission wavelength of the first color sub-pixels is greater than the emission wavelength of the second color sub-pixels; the pixel circuit includes a first pixel circuit and a second pixel circuit, wherein the first color sub-pixels are electrically connected to the first pixel circuit and the second color sub-pixels are electrically connected to the second pixel circuit. The gating transistor includes a first gating transistor and a second gating transistor, and the data signal line includes a first data signal line and a second data signal line. The first gating transistor is electrically connected to the first pixel circuit through the first data signal line, and the second gating transistor is electrically connected to the second pixel circuit through the second data signal line. The minimum distance between the first gating transistor and the first data signal line electrically connected to it is the fifth distance, and the minimum distance between the second gating transistor and the second data signal line electrically connected to it is the sixth distance, wherein the fifth distance is less than the sixth distance.

16. The display panel according to claim 11, characterized in that, The gating circuit includes N gating transistors, and the N gating transistors are electrically connected to N data signal lines; Of the N data signal lines electrically connected to the same gating circuit, at most K data signal lines are adjacent to each other and not separated by the gating transistors, where K is a positive integer and K < N.

17. The display panel according to claim 16, characterized in that, Of the N data signal lines electrically connected to the same gating circuit, K data signal lines are located on the first side of the gating circuit in the second direction, and NK data signal lines are located on the second side of the gating circuit in the second direction.

18. The display panel according to claim 11, characterized in that, Also includes: A data signal line group electrically connected to the gating circuit, the data signal line group comprising at least two data signal lines; in the second direction, the data signal line group is adjacent to the gating circuit; In the second direction, the source signal line is also adjacent to the gating circuit, and the source signal line is located on the side of the gating circuit away from the data signal line group.

19. The display panel according to claim 18, characterized in that, Also includes: A gating signal line group, the gating signal line group comprising a plurality of gating signal lines extending along the second direction; along the first direction, the gating signal line group is adjacent to the gating circuit; The gating circuit further includes a gate connection portion extending at least partially along the first direction, the gate connection portion connecting the gate of the gating transistor and the gating signal line; the gating circuit further includes an electrode connection portion connecting the first electrode of an adjacent gating transistor; The gating transistor includes a first electrode and a second electrode arranged along the first direction, with the first electrode located on the side of the second electrode closer to the gating signal line group; the first electrode is electrically connected to the source signal line, and the second electrode is electrically connected to the data signal line.

20. The display panel according to claim 19, characterized in that, Also includes: The gating signal line includes a first gating portion and a second gating portion; along a direction perpendicular to the plane where the substrate is located, the first gating portion overlaps with the data signal line and / or the source signal line, and the second gating portion does not overlap with the data signal line; Wherein, the gate of the selection transistor, the gate connection portion and the first selection portion are located in the first conductive layer, and the first electrode, the electrode connection portion and the second selection portion of the selection transistor are located in the second conductive layer; The electrode connection portion extends along the second direction; along the second direction, the electrode connection portion overlaps with the first electrode.

21. The display panel according to claim 19, characterized in that, Also includes: The gating signal line includes a first gating signal line and a second gating signal line. The first gating signal line is adjacent to the gating transistor, and the second gating signal line is located on the side of the first gating signal line away from the gating transistor. The gate connection portion includes a first gate connection portion and a second gate connection portion. The first gate connection portion is electrically connected to the first gating signal line, and the second gate connection portion is electrically connected to the second gating signal line. The second gate connection portion includes a first sub-connection portion and a second sub-connection portion. The first sub-connection portion connects the gate of the gate transistor and the second sub-connection portion, and the second sub-connection portion connects the first sub-connection portion and the second gate signal line. The gate of the gate transistor, the first gate connection portion, the first sub-connection portion of the second gate connection portion, and the gate signal line are located in the first conductive layer, while the second sub-connection portion of the second gate connection portion, the first electrode of the gate transistor, and the electrode connection portion are located in the second conductive layer. At least a portion of the first sub-connection of the second gate connection extends along the second direction, and the second sub-connection of the second gate connection extends along the first direction; along the second direction, the second sub-connection of the second gate connection overlaps with the first electrode; along the first direction, the electrode connection is located on the side of the second sub-connection of the second gate connection away from the gating signal line.

22. The display panel according to claim 1, characterized in that, The pixel circuit includes a pulse amplitude modulation module and a pulse width modulation module; The data signal lines include pulse amplitude data signal lines and pulse width data signal lines. The pulse amplitude data signal lines are electrically connected to the pulse amplitude modulation module, and the pulse width data signal lines are electrically connected to the pulse width modulation module. The gating circuit is electrically connected to the pulse width modulation module via the pulse width data signal line.

23. A display device, characterized in that, Includes the display panel as described in any one of claims 1-22.

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