An active display pixel circuit and an active display device

Abstract

This application relates to an active display pixel circuit, comprising: a light-emitting device; a PWM module configured to receive a reference signal and a display signal, and output a PWM signal; a constant current module configured to control the state of the light-emitting device according to the PWM signal; the PWM module includes a comparison unit, which includes a comparator configured to compare the input voltage of the comparator with the flip voltage of the comparator, and output a PWM signal according to the comparison result; a positive feedback unit coupled between the input and output terminals of the comparator, configured to increase the input voltage of the comparator by capacitor bootstrapping or decrease the flip voltage of the comparator when the relative relationship between the input voltage and the flip voltage of the comparator reverses during the light-emitting phase, thereby changing the operating region of the transistor in the comparator. The pixel circuit of this application exhibits high display accuracy, long effective light-emitting time, good stability, high step control accuracy, and superior display quality. This application also relates to an active display device.

Description

Technical Field

[0001] This application relates to the field of displays, and in particular to an active display pixel circuit and an active display device. Background Technology

[0002] In recent years, research on micro-LED (Micro Light-Emitting Diode) display technology has attracted widespread attention. Compared with traditional display technologies such as liquid crystal displays or OLED (Organic Light-Emitting Diode), micro-LED displays have advantages such as ultra-high brightness, high contrast, and fast switching response, as well as better stability and lower power consumption.

[0003] Due to the unique device characteristics of micro-LEDs, the PAM (Pulse Amplitude Modulation) driving method used in traditional display technologies is not suitable for micro-LED displays. This is mainly because, when using the PAM driving method, the EQE (External Quantum Efficiency) of the micro-LED changes with the driving current. At low driving currents, the EQE decreases significantly, leading to reduced luminous efficiency. Furthermore, the emission wavelength of the micro-LED also changes with the driving current, especially at low driving currents where a noticeable color shift occurs.

[0004] The above problems can be solved by using PWM (Pulse Width Modulation). The PWM driving method keeps the light-emitting current constant, changes the average current in a frame by controlling the duty cycle of the light-emitting current duration, and then controls the brightness of the micro LED by the magnitude of the average current, thereby expressing different display gray levels.

[0005] Compared to the PAM driving method, the PWM driving method can maintain high luminous efficiency and constant emission wavelength for micro-LEDs, while solving the problems of low luminous efficiency and color shift associated with the PAM driving method. This allows micro-LED displays to achieve optimal performance. The PWM driving method can also more accurately control the average display brightness at small grayscale levels. Furthermore, the PWM driving method is not only suitable for micro-LEDs but also for display circuits using LEDs, OLEDs, QLEDs (Quantum Dot Light-Emitting Diodes), and AMOLEDs (Active-Matrix Organic Light-Emitting Diodes) as light-emitting devices.

[0006] Existing PWM driving methods are mainly divided into digital PWM driving and analog PWM driving. Digital PWM divides a frame into multiple subframes, and externally input binary data is directly input into the pixels to control the brightness or darkness of the subframes. The advantage of digital PWM driving is its accurate control of grayscale (including small grayscale), but due to the large number of subframes, the overall programming time is long and the effective light emission time is insufficient. Especially at high frame rates and high resolutions, the data writing time is already close to the frame time, making digital PWM driving unable to meet the requirements of high frame rates and high resolutions. In addition, multiple high-frequency subframe switching within a frame will cause significant dynamic power consumption and may also cause damage to the human eye.

[0007] Compared to digital PWM drives, analog PWM drives are more likely to be a practically effective solution. Analog PWM drives first convert the externally input binary data into an analog voltage value using a DAC (Digital to Analog Converter) in the source drive circuit. This analog voltage value is then converted into PWM drive signals with different duty cycles by a voltage-to-time converter within the pixel (usually a comparator in the pixel circuit), thereby achieving grayscale control.

[0008] The advantages of analog PWM driving are short data write time and long light emission time. However, limited by pixel area, the comparators used in existing analog PWM drivers are usually single-transistor dynamic comparators composed of unipolar MOS transistors, or inverters composed of complementary CMOS transistors as static comparators. Both types of comparators have poor conversion performance, with long rise or fall times during output conversion. Therefore, due to the limitations of comparator accuracy, the actual achievable grayscale accuracy of micro-LED displays using existing analog PWM driving is relatively low.

[0009] In summary, existing analog PWM drivers cannot effectively achieve high-precision micro LED displays. A driving method is needed to support the further development of micro LED displays and other active light-emitting display technologies, thereby improving the display performance of active displays. Summary of the Invention

[0010] To address the technical problems existing in the prior art, this application proposes an active display pixel circuit, comprising: a light-emitting device, the cathode of which is configured to receive a ground level; a PWM module configured to receive at least a reference signal and a display signal, and output a PWM signal; a constant current module coupled to the PWM module at a first node, configured to receive the PWM signal and control the light-emitting state of the light-emitting device according to the PWM signal; wherein, the PWM module comprises: a comparison unit, the comparison unit including at least a comparator, the input terminal of the comparator receiving the reference signal or the display signal in a time-division multiplexing manner, the output terminal of the comparator being coupled to the first node and configured to compare the input voltage of the comparator and the flip voltage of the comparator, and output the PWM signal according to the comparison result; a positive feedback unit coupled between the input terminal and the output terminal of the comparator, configured to, during the light-emitting phase of the pixel circuit, when the relative relationship between the input voltage and the flip voltage of the comparator reverses, change the operating region of the transistor in the comparator by either increasing the input voltage of the comparator through capacitor bootstrapping or decreasing the flip voltage of the comparator.

[0011] Specifically, the reference signal gradually increases or decreases over time.

[0012] Specifically, the comparator includes: a first transistor (T52, T62, or T72) whose source is configured to receive a power supply voltage and whose drain is coupled to the first node (B5, B6, or B7); a second transistor (T53, T63, or T73) whose source is configured to receive a ground level, whose gate is coupled to the gate of the first transistor, and whose drain is coupled to the first node; wherein the comparison unit further includes: a first capacitor (C51, C61, or C71) whose first terminal is configured to receive the reference signal or the display signal in a time-division multiplexing manner, and whose second terminal is coupled to a second node (A5, A6, or A7) between the gate of the first transistor and the gate of the second transistor; and a third transistor (T51, T61, or T71) whose gate is configured to receive a scan signal, whose source is coupled to the second node, and whose drain is coupled to the first node; The positive feedback unit includes: a fourth transistor (T54, T64, or T74) whose drain is configured to receive an enable signal; a fifth transistor (T55, T65, or T75) whose gate is coupled to the gate of the fourth transistor, whose source is coupled to the source of the fourth transistor, and whose drain is configured to receive the scan signal; a second capacitor (C52, C62, or C72) whose first end is coupled to the second node, and whose second end is coupled to a third node (C5, C6, or C7) between the source of the fourth transistor and the source of the fifth transistor; wherein the fourth node (D5, D6, or D7) between the gate of the fourth transistor and the gate of the fifth transistor is coupled to the first node; wherein the types of the first transistor and the fourth transistor are complementary to the types of the second transistor, the third transistor, and the fifth transistor.

[0013] Specifically, the comparison unit further includes: a first transistor (T81) whose gate is configured to receive a scan signal and whose drain is coupled to the first node (B8); a second transistor (T82) whose gate is configured to receive a reset signal and whose drain is configured to receive a power supply voltage, and whose source is coupled to the first node; a first capacitor (C81) whose first terminal is configured to receive the reference signal or the display signal in a time-division manner, and whose second terminal is coupled to the source of the first transistor; wherein the comparator includes: a third transistor (T83) whose source is configured to receive a ground level, whose gate is coupled to the second node (A8) between the second terminal of the first capacitor and the source of the first transistor, and whose drain is coupled to the first node; wherein, the The positive feedback unit includes: a fourth transistor (T84) whose drain is configured to receive an enable signal; a fifth transistor (T85) whose gate is coupled to the gate of the fourth transistor, whose source is coupled to the source of the fourth transistor, and whose drain is configured to receive the scan signal; a second capacitor (C82) whose first terminal is coupled to the second node, and whose second terminal is coupled to a third node (C8) between the source of the fourth transistor and the source of the fifth transistor; wherein the fourth node (D8) between the gate of the fourth transistor and the gate of the fifth transistor is coupled to the first node; wherein the type of the fourth transistor is complementary to the types of the first transistor, the second transistor, the third transistor, and the fifth transistor.

[0014] Specifically, the comparator includes: a first transistor (T92) whose source is configured to receive a power supply voltage and whose drain is coupled to the first node (B9); a second transistor (T93), which is a dual-gate transistor, whose source is configured to receive a ground level, whose top gate is coupled to the gate of the first transistor, and whose drain is coupled to the first node; wherein the comparison unit further includes: a first capacitor (C91), whose first terminal is configured to receive the reference signal or the display signal in a time-division multiplexing manner, and whose second terminal is coupled to a second node (A9) between the gate of the first transistor and the top gate of the second transistor; a third transistor (T91), whose gate is configured to receive a scan signal, whose source is coupled to the second node, and whose drain is coupled to the first node; wherein the positive feedback unit includes: a fourth crystal. A transistor (T96) has its source configured to receive a power supply voltage; a fifth transistor (T97) has its source configured to receive a ground level, its gate coupled to the gate of the fourth transistor, and its drain coupled to the drain of the fourth transistor; wherein the positive feedback unit and the comparator in the comparison unit share the second transistor, and the bottom gate of the second transistor is coupled to a third node (C9) between the drain of the fourth transistor and the drain of the fifth transistor; wherein a fourth node (D9) between the gate of the fourth transistor and the gate of the fifth transistor is coupled to the first node; wherein the size of the fifth transistor is larger than the size of the fourth transistor; wherein the types of the first transistor and the fourth transistor are complementary to the types of the second transistor, the third transistor, and the fifth transistor.

[0015] Specifically, the constant current module includes: a sixth transistor (T58) whose gate is configured to receive the enable signal and whose source is configured to receive the power supply voltage; a seventh transistor (T57) whose drain is coupled to the drain of the sixth transistor; an eighth transistor (T511) whose gate is configured to receive a first gate drive signal and whose source is configured to receive the programming signal of the constant current module, and whose drain is coupled to a seventh node (G5) between the drains of the sixth transistor and the seventh transistor; a third capacitor (C53) whose first terminal is configured to receive the power supply voltage and whose second terminal is coupled to the gate of the seventh transistor; and a ninth transistor (T56) whose gate is coupled to the first node (B5) and whose drain is coupled to the... The source of the seventh transistor is coupled to the anode of the light-emitting device; the tenth transistor (T510) has a gate configured to receive a second gate drive signal, a source configured to receive ground level, and a drain coupled to a fifth node (E5) between the gate of the seventh transistor and the second terminal of the third capacitor; the eleventh transistor (T59) has a gate configured to receive the first gate drive signal, a source coupled to the fifth node, and a drain coupled to a sixth node (F5) between the source of the seventh transistor and the drain of the ninth transistor; wherein the type of the seventh transistor is complementary to the types of the sixth, eighth, ninth, tenth, and eleventh transistors.

[0016] Specifically, the constant current module includes: a sixth transistor (T67, T87, or T95) whose drain is configured to receive a power supply voltage and whose gate is configured to receive the enable signal; and a seventh transistor (T66, T86, or T94) whose gate is coupled to the first node (B6, B8, or B9), whose drain is coupled to the source of the sixth transistor, and whose source is coupled to the anode of the light-emitting device; wherein the sixth transistor and the seventh transistor are of the same type.

[0017] Specifically, the constant current module includes: a sixth transistor (T77) whose drain is configured to receive a power supply voltage; a third capacitor (C73) whose first terminal is configured to receive a power supply voltage and whose second terminal is coupled to the gate of the sixth transistor; a seventh transistor (T76) whose gate is coupled to the first node (B7) and whose drain is coupled to the source of the sixth transistor; an eighth transistor (T710) whose gate is configured to receive the enable signal, whose drain is coupled to the source of the seventh transistor, and whose source is coupled to the anode of the light-emitting device; and a ninth transistor (T79) whose gate is configured to receive the scan signal. A scanning signal, the source of which is coupled to a current source outside the pixel circuit, is configured to receive the bias current required by the pixel circuit, and the drain of which is coupled to a fifth node (E7) between the gate of the sixth transistor and the second terminal of the third capacitor; a tenth transistor (T78), the gate of which is configured to receive the scanning signal, the source of which is coupled to the fifth node, and the drain of which is coupled to a sixth node (F7) between the source of the sixth transistor and the drain of the seventh transistor; wherein the type of the sixth transistor is complementary to the types of the seventh transistor, the eighth transistor, the ninth transistor and the tenth transistor.

[0018] This application also proposes an active display device, comprising: an active display pixel array comprising n rows, each row containing m pixel circuits as described in any one of claims 1-8, wherein n and m are both integers greater than or equal to 1; a gate driving circuit module comprising n gate driving circuits, wherein the m pixel circuits in the same row of the active display pixel array share a single gate driving circuit; a source driving circuit module comprising m source driving circuits, wherein the n pixel circuits in the same column of the active display pixel array share a single source driving circuit, and each source driving circuit includes a DAC; and a timing control circuit coupled to the gate driving circuit module and the source driving circuit module respectively, configured to receive external data and control signals and transmit them to the source driving circuit module and the gate driving circuit module.

[0019] Specifically, the DAC is configured to convert display data received by the active display device into display signals.

[0020] The active display pixel circuit proposed in this application has high display accuracy, long effective light emission time, and good stability, which greatly improves the accuracy of grayscale control and enables the display quality to achieve better performance. Attached Figure Description

[0021] The preferred embodiments of this application will now be described in further detail with reference to the accompanying drawings, wherein:

[0022] Figure 1This is a schematic diagram of an active display device according to an embodiment of this application;

[0023] Figure 2(a) is a schematic diagram of the structure of an existing analog PWM driven active display pixel circuit;

[0024] Figure 2(b) is a schematic diagram of the operating timing of the active display pixel circuit shown in Figure 2(a);

[0025] Figure 3(a) is a schematic diagram of an existing analog PWM driven active display pixel circuit;

[0026] Figure 3(b) is a conceptual schematic diagram of an active display pixel circuit according to an embodiment of this application;

[0027] Figure 4(a) is a comparison of the working timing diagram of an active display pixel circuit according to an embodiment of the present application with that of the prior art;

[0028] Figure 4(b) is a comparison of the output accuracy of an active display pixel circuit according to an embodiment of this application with that of a comparator in the prior art;

[0029] Figure 5(a) is a circuit diagram of an active display pixel circuit according to an embodiment of the present application;

[0030] Figure 5(b) is a schematic diagram of the operating timing of the active display pixel circuit shown in Figure 5(a);

[0031] Figure 6(a) is a circuit diagram of an active display pixel circuit according to an embodiment of the present application;

[0032] Figure 6(b) is a schematic diagram of the operating timing of the active display pixel circuit shown in Figure 6(a);

[0033] Figure 7(a) is a circuit diagram of an active display pixel circuit according to an embodiment of the present application;

[0034] Figure 7(b) is a schematic diagram of the operating timing of the active display pixel circuit shown in Figure 7(a);

[0035] Figure 8(a) is a circuit diagram of an active display pixel circuit according to an embodiment of the present application;

[0036] Figure 8(b) is a schematic diagram of the operating timing of the active display pixel circuit shown in Figure 8(a);

[0037] Figure 9(a) is a circuit diagram of an active display pixel circuit according to an embodiment of the present application;

[0038] Figure 9(b) is a schematic diagram of the operating timing of the active display pixel circuit shown in Figure 9(a). Detailed Implementation

[0039] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0040] In the following detailed description, reference can be made to the accompanying drawings, which form part of this application and illustrate specific embodiments of the present application. In the drawings, similar reference numerals describe substantially similar components in different figures. Specific embodiments of the present application are described in sufficient detail below to enable those skilled in the art to implement the technical solutions of the present application. It should be understood that other embodiments may also be utilized, or structural, logical, or electrical changes may be made to the embodiments of the present application.

[0041] Techniques, methods, and apparatus known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and apparatus should be considered part of the specification. The lines connecting the units in the accompanying drawings are merely for illustrative purposes, indicating that at least the units at both ends of the line are communicating with each other, and are not intended to prevent unconnected units from communicating. Furthermore, the number of lines between two units is intended to indicate at least the number of signals involved in communication between the two units or at least the number of output terminals, and is not intended to limit communication between the two units to only the signals shown in the figures.

[0042] A transistor can refer to a transistor of any structure, such as a field-effect transistor (FET) or a bipolar junction transistor (BJT). When a transistor is a field-effect transistor, depending on the channel material, it can be hydrogenated amorphous silicon, metal oxide, low-temperature polycrystalline silicon, organic transistors, etc. Based on whether the charge carrier is electrons or holes, they can be divided into N-type transistors and P-type transistors. The gate of a field-effect transistor is its control electrode, and the first electrode can be either the drain or source, while the corresponding second electrode can be either the source or drain. When a transistor is a bipolar junction transistor (BJT), its control electrode is its base, and the first electrode can be either the collector or emitter, while the corresponding second electrode can be either the emitter or collector. Transistors can be manufactured using amorphous silicon, polycrystalline silicon, oxide semiconductors, organic semiconductors, NMOS / PMOS processes, or CMOS processes.

[0043] Figure 1 This is a schematic diagram of an active display device according to an embodiment of this application.

[0044] According to one embodiment, Figure 1 The active display device shown may include an active display pixel array, which may include n rows, each row containing m active display pixel circuits (not shown); where n and m are both integers greater than or equal to 1.

[0045] According to one embodiment, Figure 1 The active display device shown may include a gate driving circuit module, which may include n gate driving circuits (not shown). The m active display pixel circuits in the same row of the active display pixel array share a single gate driving circuit.

[0046] According to one embodiment, Figure 1 The active display device shown may include a source drive circuit module, which may include m source drive circuits (not shown). n active display pixel circuits in the same column of the active display pixel array share a single source drive circuit.

[0047] According to one embodiment, each source drive circuit may include a DAC (not shown).

[0048] According to one embodiment, Figure 1 The active display device shown may include a timing control circuit, which is coupled to the gate drive circuit module and the source drive circuit module respectively, and is configured to receive external data and control signals and transmit them to the source drive circuit module and the gate drive circuit module respectively.

[0049] According to one embodiment, when the active display pixel circuit in the active display device adopts analog PWM driving, after each source drive circuit receives external display data, the DAC (not shown) in the source drive circuit is configured to convert the display data into a display signal.

[0050] According to one embodiment, the displayed data may be grayscale data.

[0051] According to one embodiment, the display signal can be a grayscale voltage, that is, an analog voltage value carrying grayscale information.

[0052] According to one embodiment, the gate drive circuit module generates a scan signal S[n]. When S[n] is high, the m active display pixel circuits in the nth row of the active display pixel array will receive grayscale voltages from their corresponding source drive circuits in sequence.

[0053] According to one embodiment, when the active display pixel circuit in the active display device is driven by analog PWM, each active display pixel circuit converts the received grayscale voltage to time, thereby converting the grayscale information into an average current flowing through the light-emitting device (not shown) in the pixel circuit.

[0054] According to one embodiment, Figure 1 The active display device shown may include a power management circuit configured to provide power management to the active display device, including providing the power supply voltage VDD, ground level VSS required by the active display pixel circuit, and the drive voltage required by the gate drive circuit module and the source drive circuit module.

[0055] Figure 2(a) is a schematic diagram of the structure of an existing analog PWM driven active display pixel circuit.

[0056] The active display pixel circuit shown in Figure 2(a) includes light-emitting devices.

[0057] The active display pixel circuit shown in Figure 2(a) includes a PWM module configured to convert grayscale voltage from voltage to time.

[0058] The PWM module includes a comparator. The comparator is configured to compare its input voltage with the switching voltage and output a corresponding PWM signal based on the comparison result; that is, a voltage signal with different duty cycles. The comparator's input voltage equals the reference level minus the grayscale voltage plus the switching voltage. The reference level is a signal that increases or decreases over time, such as a ramp signal or a triangular wave signal.

[0059] The active display pixel circuit shown in Figure 2(a) includes a constant current module. The constant current module is configured to provide a constant current to the light-emitting device. The constant current module and the switch can also be referred to together as the constant current module, wherein the control terminal of the switch is configured to receive the PWM signal output by the comparator and control the light-emitting state of the light-emitting device according to the PWM signal.

[0060] Figure 2(b) is a schematic diagram of the operating timing of the active display pixel circuit shown in Figure 2(a); wherein, the reference level shown in Figure 2(b) is a ramp signal.

[0061] As shown in Figure 2(b), when the reference level is less than the grayscale voltage, the input voltage of the comparator is less than its switching voltage, the PWM signal output by the comparator is high, the control switch is turned on, and the light-emitting device emits light. As time increases, the reference level increases linearly. When the reference level is greater than the grayscale voltage, the input voltage of the comparator is greater than its switching voltage, the PWM signal output by the comparator jumps from high level to low level, the control switch is turned off, and the light-emitting device does not emit light.

[0062] Figure 3(a) is a schematic diagram of an existing analog PWM driven active display pixel circuit. Figure 3(a) shows a conceptual circuit diagram of the active display pixel circuit shown in Figure 2(a).

[0063] Figure 3(b) is a conceptual schematic diagram of an active display pixel circuit according to an embodiment of this application. As can be seen from Figure 3(b), compared with the circuit schematic diagram shown in Figure 3(a), the active display pixel circuit proposed in this application introduces a positive feedback unit.

[0064] Figure 4(a) is a comparison of the working timing diagram of an active display pixel circuit according to an embodiment of the present application and the prior art; Figure 4(b) is a comparison of the comparator output accuracy of an active display pixel circuit according to an embodiment of the present application and the prior art.

[0065] When an active display pixel circuit uses analog PWM drive, ideally the PWM signal output by the comparator should flip instantaneously when the relationship between the comparator's input voltage and its flip voltage reverses, i.e., the state of broken line 403 in Figure 4(b). However, due to the comparator input voltage V in the existing active display pixel circuit... IN Subtract its switching voltage V M The value is small, as shown by the dashed line 401 in Figure 4(a). The comparator is in the subthreshold region and cannot quickly flip the output result. Therefore, the output PWM signal actually presents the state of the dashed line 404 in Figure 4(b), with a flip time T. f The grayscale is relatively long, and there are obvious errors in grayscale control.

[0066] The active display pixel circuit proposed in this application, according to one embodiment, as shown in Figure 3(b), introduces a positive feedback unit. When the input voltage of the comparator is almost equal to its switching voltage, the output of the comparator will exhibit a transition from high to low level or from low to high level. This voltage transition will be superimposed on the input terminal of the comparator through the positive feedback unit. Due to the feedback signal from the output, the input voltage of the comparator minus its switching voltage (V) IN -V M The output will exhibit the state of line 402 as shown in Figure 4(a). At this time, due to the effect of the positive feedback unit, the overdrive voltage of the comparator will rapidly increase at the instant the relationship between the input voltage and the switching voltage of the comparator reverses. That is, the difference between the input voltage and the switching voltage of the comparator will cause the comparator to not operate in the subthreshold region, and the output result will rapidly flip, exhibiting the state of curve 405 in Figure 4(b). The flip time T f 'Significantly shortens, thereby reducing the error of grayscale control.'

[0067] According to one embodiment, the positive feedback unit introduced in the active display pixel circuit of this application can be implemented by capacitor bootstrapping or dual-gate control of the switching voltage.

[0068] Figure 5(a) is a circuit diagram of an active display pixel circuit according to an embodiment of the present application.

[0069] According to one embodiment, the active display pixel circuit 500 shown in FIG5(a) may include a light-emitting device LED5, the cathode of which is configured to receive ground level VSS.

[0070] According to one embodiment, the light-emitting device LED5 can be any one of LED, OLED, micro LED, QLED, AMOLED, etc.

[0071] According to one embodiment, the active display pixel circuit 500 shown in FIG5(a) may include a PWM module 501.

[0072] According to one embodiment, the PWM module 501 may include a comparison unit 5011.

[0073] According to one embodiment, the comparison unit 5011 may include a first transistor T52, which may be a P-type transistor whose source is configured to receive a power supply voltage VDD.

[0074] According to one embodiment, the comparison unit 5011 may include a second transistor T53, which may be an N-type transistor with its source configured to receive ground level VSS, its gate coupled to the gate of the first transistor T52, and its drain coupled to the drain of the first transistor T52.

[0075] According to one embodiment, the comparison unit 5011 may include a first capacitor C51, the first end of which is configured to receive a source drive signal SREF from the source drive circuit corresponding to the active display pixel circuit 500, and the second end of which is coupled to a second node A5 between the gate of the first transistor T52 and the gate of the second transistor T53.

[0076] According to one embodiment, the comparison unit 5011 may include a third transistor T51, which may be an N-type transistor, whose gate is configured to receive a scan signal S[n] from the gate drive circuit corresponding to the active display pixel circuit 500, whose source is coupled to a second node A5, and whose drain is coupled to a first node B5 between the drain of the first transistor T52 and the drain of the second transistor T53.

[0077] According to one embodiment, the PWM module 501 may include a positive feedback unit 5012.

[0078] According to one embodiment, the positive feedback unit 5012 may include a fourth transistor T54, which may be a P-type transistor whose drain is configured to receive an enable signal EM from the gate drive circuit corresponding to the active display pixel circuit 500.

[0079] According to one embodiment, the positive feedback unit 5012 may include a fifth transistor T55, which may be an N-type transistor with its gate coupled to the gate of a fourth transistor T54, its source coupled to the source of the fourth transistor T54, and its drain configured to receive a scan signal S[n].

[0080] According to one embodiment, the positive feedback unit 5012 may include a second capacitor C52, the first end of which is coupled to a second node A5, and the second end of which is coupled to a third node C5 between the source of the fourth transistor T54 and the source of the fifth transistor T55.

[0081] According to one embodiment, a fourth node D5 between the gate of the fourth transistor T54 and the gate of the fifth transistor T55 is coupled to a first node B5.

[0082] According to one embodiment, in the PWM module 501, the types of the first transistor T52 and the fourth transistor T54 are complementary to the types of the second transistor T53, the third transistor T51 and the fifth transistor T55.

[0083] According to one embodiment, the active display pixel circuit 500 shown in FIG5(a) may include a constant current module 502.

[0084] According to one embodiment, the constant current module 502 may include a sixth transistor T58, which may be an N-type transistor with its gate configured to receive an enable signal EM and its source configured to receive a power supply voltage VDD.

[0085] According to one embodiment, the constant current module 502 may include a seventh transistor T57, which may be a P-type transistor whose drain is coupled to the drain of a sixth transistor T58.

[0086] According to one embodiment, the constant current module 502 may include an eighth transistor T511, which may be an N-type transistor, and its gate is configured to receive a first gate drive signal S from the gate drive circuit corresponding to the active display pixel circuit 500. CCG Its source is configured to receive the programming signal D from the constant current module. PAM Its drain is coupled to the seventh node G5 between the drain of the sixth transistor T58 and the drain of the seventh transistor T57.

[0087] According to one embodiment, the constant current module 502 may include a third capacitor C53, the first end of which is configured to receive a power supply voltage VDD, and the second end of which is coupled to the gate of a seventh transistor T57.

[0088] According to one embodiment, the constant current module 502 may include a ninth transistor T56, which may be an N-type transistor with its gate coupled to the first node B5, its drain coupled to the source of the seventh transistor T57, and its source coupled to the anode of the light-emitting device LED5.

[0089] According to one embodiment, the constant current module 502 may include a tenth transistor T510, which may be an N-type transistor, and its gate is configured to receive a second gate drive signal S from the gate drive circuit corresponding to the active display pixel circuit 500. INI Its source is configured to receive ground level VSS, and its drain is coupled to the fifth node E5 between the gate of the seventh transistor T57 and the second terminal of the third capacitor C53.

[0090] According to one embodiment, the constant current module 502 may include an eleventh transistor T59, which may be an N-type transistor, and its gate is configured to receive a first gate drive signal S. CCG Its source is coupled to the fifth node E5, and its drain is coupled to the sixth node F5 between the source of the seventh transistor T57 and the drain of the ninth transistor T56.

[0091] According to one embodiment, in the constant current module 502, the type of the seventh transistor T57 is complementary to the types of the sixth transistor T58, the eighth transistor T511, the ninth transistor T56, the tenth transistor T510, and the eleventh transistor T59.

[0092] According to one embodiment, the first transistor T52 and the second transistor T53 form a switching voltage of V. M A static comparator. As the input voltage V of the static comparator... IN (i.e., the potential at the second node A5) rises, when the input voltage V of the static comparator... IN Higher than the switching voltage V M At that time, the potential at the first node B5, i.e., the output voltage V of the static comparator. PWM The voltage level flips from high to low, controlling the ninth transistor T56 to turn off, thereby slowly turning off the light-emitting device LED5. This is how the received grayscale voltage V is converted into a signal. DATA This is converted into the light-emitting time of the LED5 light-emitting device.

[0093] Figure 5(b) is a schematic diagram of the operating timing of the active display pixel circuit shown in Figure 5(a).

[0094] According to one embodiment, the active display pixel circuit 500 shown in FIG5(a) is designed based on the method of simultaneous light emission, that is: after the display signals of n rows in the active display pixel array where the active display pixel circuit 500 is located are written and converted into the light emission time of the light-emitting devices, all light-emitting devices emit light simultaneously.

[0095] According to one embodiment, for a single display frame time, as shown in Figure 5(b), the active display pixel circuit includes four operating stages:

[0096] P1: PWM module programming and compensation stage;

[0097] P2: Constant current module reset phase;

[0098] P3: Constant current module programming and compensation stage;

[0099] P4: The luminescent stage.

[0100] P1: During this stage, the scanning signal S[n] is high, and the source drive signal SREF is the grayscale voltage V. DATA Gray-scale voltage V DATA The voltage is written to the first terminal of the first capacitor C51. Simultaneously, a static comparator formed by the first transistor T52 and the second transistor T53 performs a self-zeroing process, with its input terminal (second node A5) connected to its output terminal (first node B5), and the input voltage V... IN and output voltage V PWM It will gradually approach, until it equals, the switching voltage V of the static comparator. M That is, the switching voltage V is completed. M Extracting the threshold voltage of the static comparator (i.e., the voltage difference ΔV across the first capacitor C51 at this time is V). DATA -V M .

[0101] For the positive feedback unit 5012, the enable signal EM is low and the scan signal S[n] is high during this stage. The fourth transistor T54 and the fifth transistor T55 form a Class B amplifier, which performs forward amplification with a gain of less than 1. Its input voltage is V. M Its output terminal outputs a fixed level V BT Therefore, self-excited oscillations will not occur during the compensation phase.

[0102] For constant current module 502, the enable signal EM is low at this stage, the constant current module circuit is open, and the light-emitting device LED5 does not emit light.

[0103] P2: The second gate drive signal S during this stage INIWhen the signal is high, the tenth transistor T510 is turned on, and its gate is reset to low; at the same time, the seventh transistor T57 is in the on state.

[0104] During this stage, both the enable signal EM and the scan signal S[n] are low. For the amplifier formed by the fourth transistor T54 and the fifth transistor T55, its input voltage is V. M Its output voltage V BT It will be discharged to a low level.

[0105] P3: The first gate drive signal S during this stage CCG When the voltage level is high, the eleventh transistor T59 and the eighth transistor T511 are turned on. Because the eleventh transistor T59 is on, the seventh transistor T57 forms a diode connection structure, and the programming signal D from the constant current module is written to its source. PAM .

[0106] At this stage, the diode structure formed by the seventh transistor T57 begins to extract the threshold voltage V of the seventh transistor T57. TH57 Until the voltage at its gate (i.e., the potential at the fifth node E5) V CCG Charge to D PAM -|V TH57 The seventh transistor, T57, is turned off.

[0107] During this stage, since the enable signal EM is at a low level, the sixth transistor T58, which controls the gate by the enable signal EM, remains in the off state.

[0108] P4: During this stage, the enable signal EM is high, and the source drive signal SREF is a ramp signal: SW[t] = k × t + b, where k is the slope of the ramp signal and b is a constant. Due to the coupling effect of the first capacitor C51, the static comparator input voltage V formed by the first transistor T52 and the second transistor T53 during this stage... IN It can be represented as: SW[t]-V DATA +V M .

[0109] When V IN Greater than V M At that time, the static comparator output voltage V PWM When pulled down to VSS, the ninth transistor T56 is turned off, and the light-emitting device LED5 does not emit light; when V IN Less than V M At that time, V PWM When the signal is pulled up to VDD, the ninth transistor T56 turns on, and the LED5 emits light. That is, when SW[t] - V... DATA +V M <V MWhen the light-emitting device LED5 emits light, it realizes the conversion from grayscale voltage to light emission time. The light emission time T of the light-emitting device LED5 is... EM for:

[0110] T EM =(V DATA -b) / k (1)

[0111] Equation (1) and the switching voltage V of the static comparator M It is irrelevant; the active display pixel circuit implements the comparator switching voltage V. M Compensation.

[0112] However, in the actual circuit, the static comparator formed by the first transistor T52 and the second transistor T53 in this stage is actually implemented by an inverter. Its input-output curve is not steep enough during the conversion process, the grayscale control is not accurate enough, and the current of the light-emitting device LED5 has a long drop time when it changes from the bright state to the dark state. Therefore, the positive feedback unit 5012 will play a role in the P4 stage. The specific process is as follows:

[0113] When V IN Greater than V M At that time, V PWM Pulled down to VSS, at this moment, the fourth transistor T54 and the fifth transistor T55 form an inverter, and the voltage at its output terminal (i.e., the third node C5) will jump from VSS to VDD. Through the instantaneous bootstrapping of the second capacitor C52 at this moment, VDD will be pulled down. IN A positive jump becomes:

[0114] (VDD-VSS)×[C52 / (C51+C52)](2)

[0115] At this moment, the overdrive voltage of the static comparator formed by the first transistor T52 and the second transistor T53 increases instantaneously, moving from the saturation region into the deep linear region; the overdrive voltage of the first transistor T52 decreases instantaneously, moving from the saturation region into the cutoff region; V PWM It will be quickly pulled down to VSS, the descent time is greatly shortened, and more precise grayscale control is achieved.

[0116] For the constant current module, the enable signal EM is high at this stage, the first transistor T52 is turned on, and the source voltage of the seventh transistor T57 is pulled to VDD. The current flowing through the seventh transistor T57 at this time, which is also the current flowing through the light-emitting device LED5, is:

[0117]

[0118] It can be seen from equation (3) that the current I flowing through the light-emitting device LED5 is 57The fact that it is independent of the threshold voltage of the seventh transistor T57 indicates that the active display pixel circuit can achieve the threshold voltage V of the seventh transistor T57 in the constant current module. TH57 Compensation.

[0119] Figure 6(a) is a circuit diagram of an active display pixel circuit according to an embodiment of the present application.

[0120] According to one embodiment, the active display pixel circuit 600 shown in FIG6(a) may include a light-emitting device LED6, the cathode of which is configured to receive ground level VSS.

[0121] According to one embodiment, the light-emitting device LED6 can be any one of LED, OLED, micro LED, QLED, AMOLED, etc.

[0122] According to one embodiment, the active display pixel circuit 600 shown in FIG6(a) may include a PWM module 601.

[0123] According to one embodiment, the PWM module 601 may include a comparison unit 6011.

[0124] According to one embodiment, the comparison unit 6011 may include a first transistor T62, which may be a P-type transistor whose source is configured to receive a power supply voltage VDD.

[0125] According to one embodiment, the comparison unit 6011 may include a second transistor T63, which may be an N-type transistor with its source configured to receive ground level VSS, its gate coupled to the gate of the first transistor T62, and its drain coupled to the drain of the first transistor T62.

[0126] According to one embodiment, the comparison unit 6011 may include a first capacitor C61, the first end of which is configured to receive a source drive signal SREF from the source drive circuit corresponding to the active display pixel circuit 600, and the second end of which is coupled to a second node A6 between the gate of the first transistor T62 and the gate of the second transistor T63.

[0127] According to one embodiment, the comparison unit 6011 may include a third transistor T61, which may be an N-type transistor, whose gate is configured to receive a scan signal S[n] from the gate drive circuit corresponding to the active display pixel circuit 600, whose source is coupled to a second node A6, and whose drain is coupled to a first node B6 between the drain of the first transistor T62 and the drain of the second transistor T63.

[0128] According to one embodiment, the PWM module 601 may include a positive feedback unit 6012.

[0129] According to one embodiment, the positive feedback unit 6012 may include a fourth transistor T64, which may be a P-type transistor whose drain is configured to receive an enable signal EM from the gate drive circuit corresponding to the active display pixel circuit 600.

[0130] According to one embodiment, the positive feedback unit 6012 may include a fifth transistor T65, which may be an N-type transistor with its gate coupled to the gate of a fourth transistor T64, its source coupled to the source of the fourth transistor T64, and its drain configured to receive a scan signal S[n].

[0131] According to one embodiment, the positive feedback unit 6012 may include a second capacitor C62, the first end of which is coupled to a second node A6, and the second end of which is coupled to a third node C6 between the source of the fourth transistor T64 and the source of the fifth transistor T65.

[0132] According to one embodiment, a fourth node D6 between the gate of the fourth transistor T64 and the gate of the fifth transistor T65 is coupled to a first node B6.

[0133] According to one embodiment, in the PWM module 601, the types of the first transistor T62 and the fourth transistor T64 are complementary to the types of the second transistor T63, the third transistor T61 and the fifth transistor T65.

[0134] According to one embodiment, the active display pixel circuit 600 shown in FIG6(a) may include a constant current module 602.

[0135] According to one embodiment, the constant current module 602 may include a sixth transistor T67, which may be an N-type transistor with its drain configured to receive a power supply voltage VDD and its gate configured to receive an enable signal EM.

[0136] According to one embodiment, the constant current module 602 may include a seventh transistor T66, which may be an N-type transistor with its gate coupled to the first node B6, its drain coupled to the source of a sixth transistor T67, and its source coupled to the anode of the light-emitting device LED6.

[0137] According to one embodiment, in the constant current module 602, the sixth transistor T67 and the seventh transistor T66 are of the same type.

[0138] According to one embodiment, the working principle of the comparison unit 6011 in the active display pixel circuit 600 shown in FIG. 6(a) is similar to that of the comparison unit 5011 in the active display pixel circuit 500 shown in FIG. 5(a), and will not be described again here.

[0139] Figure 6(b) is a schematic diagram of the operating timing of the active display pixel circuit shown in Figure 6(a).

[0140] According to one embodiment, the active display pixel circuit 600 shown in FIG6(a) is designed based on the method of simultaneous light emission, that is: after the display signals of n rows in the active display pixel array where the active display pixel circuit 600 is located are written and converted into the light emission time of the light-emitting devices, all the light-emitting devices emit light simultaneously.

[0141] According to one embodiment, for a single display frame time, as shown in Figure 6(b), the active display pixel circuit includes two operating stages:

[0142] P1: PWM module programming and compensation stage;

[0143] P2: Light-emitting stage.

[0144] According to one embodiment, the working principle of the active display pixel circuit 600 shown in FIG6(a) in the P1 stage is similar to that of the active display pixel circuit 500 shown in FIG5(a) in the P1 stage, and will not be described again here.

[0145] According to one embodiment, the positive feedback unit 6012 in the active display pixel circuit 600 shown in FIG. 6(a) will play a role in the P2 stage. Its working principle is similar to that of the positive feedback unit 5012 in the active display pixel circuit 500 shown in FIG. 5(a), and will not be described again here.

[0146] According to one embodiment, the active display pixel circuit 600 shown in FIG. 6(a) differs from the active display pixel circuit 500 shown in FIG. 5(a) in that the current flowing through the light-emitting device LED6 is determined by the sixth transistor T67 in the saturation region, and the constant current module 602 does not control the threshold voltage V of the sixth transistor T67 during operation. TH67 During the compensation process, the threshold voltage V of the sixth transistor T67 TH67 Drifting will affect the accuracy of the PWM signal output by the static comparator formed by the first transistor T62 and the second transistor T63.

[0147] However, the active display pixel circuit 600 has a smaller pixel area, making it suitable for use in high-resolution display panels.

[0148] Figure 7(a) is a circuit diagram of an active display pixel circuit according to an embodiment of the present application.

[0149] According to one embodiment, the active display pixel circuit 700 shown in FIG7(a) may include a light-emitting device LED7, the cathode of which is configured to receive ground level VSS.

[0150] According to one embodiment, the light-emitting device LED7 can be any one of LED, OLED, micro LED, QLED, AMOLED, etc.

[0151] According to one embodiment, the active display pixel circuit 700 shown in FIG7(a) may include a PWM module 701.

[0152] According to one embodiment, the PWM module 701 may include a comparison unit 7011.

[0153] According to one embodiment, the comparison unit 7011 may include a first transistor T72, which may be a P-type transistor whose source is configured to receive a power supply voltage VDD.

[0154] According to one embodiment, the comparison unit 7011 may include a second transistor T73, which may be an N-type transistor with its source configured to receive ground level VSS, its gate coupled to the gate of the first transistor T72, and its drain coupled to the drain of the first transistor T72.

[0155] According to one embodiment, the comparison unit 7011 may include a first capacitor C71, the first end of which is configured to receive a source drive signal SREF from the source drive circuit corresponding to the active display pixel circuit 700, and the second end of which is coupled to a second node A7 between the gate of the first transistor T72 and the gate of the second transistor T73.

[0156] According to one embodiment, the comparison unit 7011 may include a third transistor T71, which may be an N-type transistor, whose gate is configured to receive a scan signal S[n] from the gate drive circuit corresponding to the active display pixel circuit 700, whose source is coupled to a second node A7, and whose drain is coupled to a first node B7 between the drain of the first transistor T72 and the drain of the second transistor T73.

[0157] According to one embodiment, the PWM module 701 may include a positive feedback unit 7012.

[0158] According to one embodiment, the positive feedback unit 7012 may include a fourth transistor T74, which may be a P-type transistor whose drain is configured to receive an enable signal EM from the gate drive circuit corresponding to the active display pixel circuit 700.

[0159] According to one embodiment, the positive feedback unit 7012 may include a fifth transistor T75, which may be an N-type transistor with its gate coupled to the gate of a fourth transistor T74, its source coupled to the source of the fourth transistor T74, and its drain configured to receive a scan signal S[n].

[0160] According to one embodiment, the positive feedback unit 7012 may include a second capacitor C72, the first end of which is coupled to a second node A7, and the second end of which is coupled to a third node C7 between the source of the fourth transistor T74 and the source of the fifth transistor T75.

[0161] According to one embodiment, a fourth node D7 between the gate of the fourth transistor T74 and the gate of the fifth transistor T75 is coupled to a first node B7.

[0162] According to one embodiment, in the PWM module 701, the types of the first transistor T72 and the fourth transistor T74 are complementary to the types of the second transistor T73, the third transistor T71 and the fifth transistor T75.

[0163] According to one embodiment, the active display pixel circuit 700 shown in FIG7(a) may include a constant current module 702.

[0164] According to one embodiment, the constant current module 702 may include a sixth transistor T77, which may be a P-type transistor with its drain configured to receive the power supply voltage VDD.

[0165] According to one embodiment, the constant current module 702 may include a third capacitor C73, the first end of which is configured to receive a power supply voltage VDD, and the second end of which is coupled to the gate of a sixth transistor T77.

[0166] According to one embodiment, the constant current module 702 may include a seventh transistor T76, which may be an N-type transistor with its gate coupled to the first node B7 and its drain coupled to the source of the sixth transistor T77.

[0167] According to one embodiment, the constant current module 702 may include an eighth transistor T710, which may be an N-type transistor with its gate configured to receive an enable signal EM, its drain coupled to the source of a seventh transistor T76, and its source coupled to the anode of a light-emitting device LED7.

[0168] According to one embodiment, the constant current module 702 may include a ninth transistor T79, which may be an N-type transistor with its gate configured to receive a scan signal S[n], its source coupled to a current source outside the active display pixel circuit, configured to receive the bias current required by the constant current module 702, and its drain coupled to a fifth node E7 between the gate of the sixth transistor T77 and the second end of the third capacitor C73.

[0169] According to one embodiment, the constant current module 702 may include a tenth transistor T78, which may be an N-type transistor with its gate configured to receive a scan signal S[n], its source coupled to a fifth node E7, and its drain coupled to a sixth node F7 between the source of a sixth transistor T77 and the drain of a seventh transistor T76.

[0170] According to one embodiment, in the constant current module 702, the type of the sixth transistor T77 is complementary to the types of the seventh transistor T76, the eighth transistor T710, the ninth transistor T79, and the tenth transistor T78.

[0171] According to one embodiment, the working principle of the comparison unit 7011 in the active display pixel circuit 700 shown in FIG7(a) is similar to that of the comparison unit 5011 in the active display pixel circuit 500 shown in FIG5(a), and will not be described again here.

[0172] Figure 7(b) is a schematic diagram of the operating timing of the active display pixel circuit shown in Figure 7(a).

[0173] According to one embodiment, the active display pixel circuit 700 shown in FIG7(a) is designed based on the method of simultaneous light emission, that is: after the display signals of n rows in the active display pixel array where the active display pixel circuit 700 is located are written and converted into the light emission time of the light-emitting devices, all light-emitting devices emit light simultaneously.

[0174] According to one embodiment, for a single display frame time, as shown in Figure 7(b), the active display pixel circuit includes two operating stages:

[0175] P1: PWM module programming and compensation stage;

[0176] P2: Light-emitting stage.

[0177] According to one embodiment, the working principle of the active display pixel circuit 700 shown in FIG7(a) in the P1 stage is similar to that of the active display pixel circuit 500 shown in FIG5(a) in the P1 stage, and will not be described again here.

[0178] According to one embodiment, the positive feedback unit 7012 in the active display pixel circuit 700 shown in FIG7(a) will play a role in the P2 stage. Its working principle is similar to that of the positive feedback unit 5012 in the active display pixel circuit 500 shown in FIG5(a), and will not be described again here.

[0179] According to one embodiment, the active display pixel circuit 700 shown in FIG. 7(a) differs from the active display pixel circuit 500 shown in FIG. 5(a) in that the constant current module 502 in the active display pixel circuit 500 is a voltage-programmable structure, while the constant current module 702 in the active display pixel circuit 700 is a current-programmable structure. The active display pixel circuit 700 can also reduce the circuit layout area and further improve the compensation accuracy of the constant current module 702.

[0180] According to one embodiment, the active display pixel circuit 700 can be used in a device driven by a single-crystal silicon CMOS backplane.

[0181] Figure 8(a) is a circuit diagram of an active display pixel circuit according to an embodiment of the present application.

[0182] According to one embodiment, the active display pixel circuit 800 shown in FIG8(a) may include a light-emitting device LED8, the cathode of which is configured to receive ground level VSS.

[0183] According to one embodiment, the light-emitting device LED8 can be any one of LED, OLED, micro LED, QLED, AMOLED, etc.

[0184] According to one embodiment, the active display pixel circuit 800 shown in FIG8(a) may include a PWM module 801.

[0185] According to one embodiment, the PWM module 801 may include a comparison unit 8011.

[0186] According to one embodiment, the comparison unit 8011 may include a first transistor T81, which may be an N-type transistor, and its gate is configured to receive a scan signal S[n] from the gate drive circuit corresponding to the active display pixel circuit 800.

[0187] According to one embodiment, the comparison unit 8011 may include a second transistor T82, which may be an N-type transistor with its gate configured to receive a reset signal RST from the gate drive circuit corresponding to the active display pixel circuit 800, its drain configured to receive a power supply voltage VDD, and its source coupled to the drain of the first transistor T81.

[0188] According to one embodiment, the comparison unit 8011 may include a first capacitor C81, the first end of which is configured to receive a source drive signal SREF from the source drive circuit corresponding to the active display pixel circuit 800, and the second end of which is coupled to the source of the first transistor T81.

[0189] According to one embodiment, the comparison unit 8011 may include a third transistor T83, which may be an N-type transistor with its source configured to receive ground level VSS, its gate coupled to a second node A8 between the second terminal of the first capacitor C81 and the source of the first transistor T81, and its drain coupled to a first node B8 between the drain of the first transistor T81 and the source of the second transistor T82.

[0190] According to one embodiment, the PWM module 801 may include a positive feedback unit 8012.

[0191] According to one embodiment, the positive feedback unit 8012 may include a fourth transistor T84, which may be a P-type transistor whose drain is configured to receive an enable signal EM from the gate drive circuit corresponding to the active display pixel circuit 800.

[0192] According to one embodiment, the positive feedback unit 8012 may include a fifth transistor T85, which may be an N-type transistor with its gate coupled to the gate of a fourth transistor T84, its source coupled to the source of the fourth transistor T84, and its drain configured to receive a scan signal S[n].

[0193] According to one embodiment, the positive feedback unit 8012 may include a second capacitor C82, the first end of which is coupled to a second node A8, and the second end of which is coupled to a third node C8 between the source of the fourth transistor T84 and the source of the fifth transistor T85.

[0194] According to one embodiment, a fourth node D8 between the gate of the fourth transistor T84 and the gate of the fifth transistor T85 is coupled to a first node B8.

[0195] According to one embodiment, in the PWM module 801, the type of the fourth transistor T84 is complementary to the types of the first transistor T81, the second transistor T82, the third transistor T83, and the fifth transistor T85.

[0196] According to one embodiment, the active display pixel circuit 800 shown in FIG8(a) may include a constant current module 802.

[0197] According to one embodiment, the constant current module 802 may include a sixth transistor T87, which may be an N-type transistor with its drain configured to receive a power supply voltage VDD and its gate configured to receive an enable signal EM.

[0198] According to one embodiment, the constant current module 802 may include a seventh transistor T86, which may be an N-type transistor with its gate coupled to the first node B8 and its drain coupled to the source of the sixth transistor T87; its source is coupled to the anode of the light-emitting device LED8.

[0199] According to one embodiment, in the constant current module 802, the sixth transistor T87 and the seventh transistor T86 are of the same type.

[0200] According to one embodiment, the active display pixel circuit 800 shown in FIG8(a) differs from the active display pixel circuit 500 shown in FIG5(a) in that the comparator unit 8011 in the PWM module 801 includes a switching voltage of V formed by the third transistor T83. M A single-transistor dynamic comparator. As the input voltage V of the single-transistor dynamic comparator... IN (i.e., the potential at the second node A8) rises, when the input voltage V of the single-transistor dynamic comparator increases. IN Greater than the switching voltage V M At that time, the potential at the first node B8 is the output voltage V of the single-transistor dynamic comparator. PWM The voltage level flips from high to low, controlling the seventh transistor T86 to turn off, thereby slowly turning off the light-emitting device LED8. This is how the received grayscale voltage V is converted into a signal. DATA This is converted to the light-emitting time of the LED8 light-emitting device.

[0201] Figure 8(b) is a schematic diagram of the operating timing of the active display pixel circuit shown in Figure 8(a).

[0202] According to one embodiment, the active display pixel circuit 800 shown in FIG8(a) is designed based on the method of simultaneous light emission, that is: after the display signals of n rows in the active display pixel array where the active display pixel circuit 800 is located are written and converted into the light emission time of the light-emitting devices, all the light-emitting devices emit light simultaneously.

[0203] According to one embodiment, for a single display frame time, as shown in Figure 8(b), the active display pixel circuit includes three operating stages:

[0204] P1: Reset phase;

[0205] P2: PWM module programming and compensation stage;

[0206] P3: Light-emitting stage.

[0207] According to one embodiment, the active display pixel circuit 800 shown in Figure 8(a) differs from the active display pixel circuit 500 shown in Figure 5(a) in that, comparing the operating timing of Figure 8(b) and Figure 5(b), it can be seen that the active display pixel circuit 800 requires the initialization of the single-transistor dynamic comparator compensation process formed by the third transistor T83 through the reset signal RST. That is: in the P1 stage, the reset signal RST is high, controlling the second transistor T82 to turn on, and the potential at the first node B8 (i.e., the output voltage of the single-transistor dynamic comparator) V PWM It is initialized to a high level.

[0208] According to one embodiment, the active display pixel circuit 800 shown in FIG8(a) differs from the active display pixel circuit 500 shown in FIG5(a) in that, in the P2 stage, the source drive signal SREF is the grayscale voltage V. DATA When the first transistor T81 is turned on, the first transistor T81 and the second transistor T82 form a diode structure to extract the threshold voltage V of the third transistor T83, which forms a single-transistor dynamic comparator. TH83 Until the potential at the second node A8 (i.e., the input voltage of the single-transistor dynamic comparator) V IN The potential at the first node B8 (i.e., the output voltage of the single-transistor dynamic comparator) V PWM Both are equal to the threshold voltage V of the third transistor T83. TH83 (i.e., the switching voltage V of a single-transistor dynamic comparator) M ).

[0209] According to one embodiment, the positive feedback unit 8012 in the active display pixel circuit 800 shown in FIG8(a) will play a role in the P3 stage. Its working principle is similar to that of the positive feedback unit 5012 in the active display pixel circuit 500 shown in FIG5(a), and will not be described again here.

[0210] The active display pixel circuit 800 can also reduce the circuit layout area.

[0211] Figure 9(a) is a circuit diagram of an active display pixel circuit according to an embodiment of the present application.

[0212] According to one embodiment, the active display pixel circuit 900 shown in FIG9(a) may include a light-emitting device LED9, the cathode of which is configured to receive ground level VSS.

[0213] According to one embodiment, the light-emitting device LED9 can be any one of LED, OLED, micro LED, QLED, AMOLED, etc.

[0214] According to one embodiment, the active display pixel circuit 900 shown in FIG9(a) may include a PWM module 901.

[0215] According to one embodiment, the PWM module 901 may include a comparison unit 9011.

[0216] According to one embodiment, the comparison unit 9011 may include a first transistor T92, which may be a P-type transistor whose source is configured to receive a power supply voltage VDD.

[0217] According to one embodiment, the comparison unit 9011 may include a second transistor T93, which may be an N-type dual-gate transistor with its source configured to receive ground level VSS, its top gate coupled to the gate of the first transistor T92, and its drain coupled to the drain of the first transistor T92.

[0218] According to one embodiment, the comparison unit 9011 may include a first capacitor C91, the first end of which is configured to receive a source drive signal SREF from the source drive circuit corresponding to the active display pixel circuit 900, and the second end of which is coupled to a second node A9 between the gate of the first transistor T92 and the top gate of the second transistor T93.

[0219] According to one embodiment, the comparison unit 9011 may include a third transistor T91, which may be an N-type transistor, whose gate is configured to receive a scan signal S[n] from the gate drive circuit corresponding to the active display pixel circuit 900, whose source is coupled to a second node A9, and whose drain is coupled to a first node B9 between the drain of the first transistor T92 and the drain of the second transistor T93.

[0220] According to one embodiment, the PWM module 901 may include a positive feedback unit 9012.

[0221] According to one embodiment, the positive feedback unit 9012 may include a fourth transistor T96, which may be a P-type transistor whose source is configured to receive the power supply voltage VDD.

[0222] According to one embodiment, the positive feedback unit 9012 may include a fifth transistor T97, which may be an N-type transistor with its source configured to receive ground level VSS, its gate coupled to the gate of a fourth transistor T96, and its drain coupled to the drain of the fourth transistor T96.

[0223] According to one embodiment, the positive feedback unit 9012 and the comparator unit 9011 share a second transistor T93, the bottom gate of which is coupled to a third node C9 between the drain of the fourth transistor T96 and the drain of the fifth transistor T97.

[0224] According to one embodiment, a fourth node D9 between the gate of the fourth transistor T96 and the gate of the fifth transistor T97 is coupled to a first node B9.

[0225] According to one embodiment, the fifth transistor T97 is larger than the fourth transistor T96.

[0226] According to one embodiment, in the PWM module 901, the types of the first transistor T92 and the fourth transistor T96 are complementary to the types of the second transistor T93, the third transistor T91 and the fifth transistor T97.

[0227] According to one embodiment, the active display pixel circuit 900 shown in FIG9(a) may include a constant current module 902.

[0228] According to one embodiment, the constant current module 902 may include a sixth transistor T95, which may be an N-type transistor with its drain configured to receive a power supply voltage VDD and its gate configured to receive an enable signal EM from the gate drive circuit corresponding to the active display pixel circuit 900.

[0229] According to one embodiment, the constant current module 902 may include a seventh transistor T94, which may be an N-type transistor with its gate coupled to the first node B9, its drain coupled to the source of a sixth transistor T95, and its source coupled to the anode of the light-emitting device LED9.

[0230] According to one embodiment, in the constant current module 902, the sixth transistor T95 and the seventh transistor T94 are of the same type.

[0231] According to one embodiment, the active display pixel circuit 900 shown in FIG9(a) differs from the active display pixel circuit 500 shown in FIG5(a) in that the first transistor T92 and the second transistor T93 form a switching voltage of V. M The static comparator uses a second transistor, T93, which is a dual-gate transistor. Simultaneously, the fifth transistor, T97, is larger than the fourth transistor, T96, causing T96 and T97 to form an inverter. The potential at the fourth node, D9, is related to the output voltage V of the static comparator. PWM The voltage at the third node C9 can be considered as the input voltage of the inverter, and the voltage at the third node C9 can be considered as the output voltage of the inverter. The output voltage is sent to the bottom gate of the second transistor T93, which initializes the bottom gate of the second transistor T93 to a low level. Thereafter, the working principle of the comparator unit 9011 in the active display pixel circuit 900 shown in Figure 9(a) is similar to that of the comparator unit 5011 in the active display pixel circuit 500 shown in Figure 5(a), and will not be described again.

[0232] Figure 9(b) is a schematic diagram of the operating timing of the active display pixel circuit shown in Figure 9(a).

[0233] According to one embodiment, the active display pixel circuit 900 shown in FIG9(a) is designed based on the method of simultaneous light emission, that is: after the display signals of n rows in the active display pixel array where the active display pixel circuit 900 is located are written and converted into the light emission time of the light-emitting devices, all the light-emitting devices emit light simultaneously.

[0234] According to one embodiment, for a single display frame time, as shown in Figure 9(b), the active display pixel circuit includes two operating stages:

[0235] P1: PWM module programming and compensation stage;

[0236] P2: Light-emitting stage.

[0237] According to one embodiment, the active display pixel circuit 900 shown in Figure 9(a) operates in stage P1 as described above. In this stage, the potential at the fourth node D9 is the switching voltage V of the static comparator formed by the first transistor T92 and the second transistor T93. M The input is fed to the inverter formed by the fourth transistor T96 and the fifth transistor T97, so that the potential at the third node C9 is low and the bottom gate of the second transistor T93 is initialized to low. The other working principles are similar to those of the active display pixel circuit 500 shown in Figure 5(a) in the P1 stage, and will not be described in detail here.

[0238] According to one embodiment, the active display pixel circuit 900 shown in FIG. 9(a) differs from the active display pixel circuit 500 shown in FIG. 5(a) in that the positive feedback unit 9012 achieves positive feedback by adjusting the threshold voltage of the second transistor T93 through a dual-gate adjustment. In stage P2, the source drive signal SREF is a ramp signal, and the input voltage V of the static comparator formed by the first transistor T92 and the second transistor T93 increases accordingly. IN (i.e., the potential at the second node A9) increases, when V IN Greater than the switching voltage V of the static comparator M At that time, V PWM It is pulled down to a low level. When V PWM After being pulled down, the inverter formed by the fourth transistor T96 and the fifth transistor T97 reverses the potential at the third node C9 to a high level, causing the bottom gate voltage of the second transistor T93 to rise instantaneously. This instantly lowers the threshold voltage of the second transistor T93 and increases the overdrive voltage of the static comparator, thus causing V... PWM The pull-down speed is accelerated, achieving the same function as the positive feedback unit 5012 in the active display pixel circuit 500.

[0239] According to one embodiment, the active display pixel circuit 900 can be used in an LTPO TFT (Low Temperature Polysilicon Oxide TFT) device.

[0240] The active display pixel circuit proposed in this application has advantages such as high display accuracy, long effective light emission time, and good stability, which greatly improves the accuracy of grayscale control, thereby achieving better display quality.

[0241] This application also provides an active display device. Figure 1 This is a schematic diagram of an active display device according to an embodiment of this application.

[0242] According to one embodiment, Figure 1 The active display device shown may include an active display pixel array, which may include n rows, each row containing m active display pixel circuits (not shown) as described above; where n and m are both integers greater than or equal to 1.

[0243] According to one embodiment, Figure 1 The active display device shown may include a gate driving circuit module, which may include n gate driving circuits (not shown). The m active display pixel circuits in the same row of the active display pixel array share a single gate driving circuit.

[0244] According to one embodiment, Figure 1 The active display device shown may include a source drive circuit module, which may include m source drive circuits (not shown). n active display pixel circuits in the same column of the active display pixel array share a single source drive circuit.

[0245] According to one embodiment, each source drive circuit may include a DAC (not shown).

[0246] According to one embodiment, Figure 1 The active display device shown may include a timing control circuit, which is coupled to the gate drive circuit module and the source drive circuit module respectively, and is configured to receive external data and control signals and transmit them to the source drive circuit module and the gate drive circuit module.

[0247] According to one embodiment, Figure 1 The active display device shown may include a power management circuit configured to provide power management to the active display device, including providing the power supply voltage VDD, ground level VSS required by the active display pixel circuit, and the drive voltage required by the gate drive circuit module and the source drive circuit module.

[0248] The above embodiments are for illustrative purposes only and are not intended to limit the scope of this application. Those skilled in the art can make various changes and modifications without departing from the scope of this application. Therefore, all equivalent technical solutions should also fall within the scope of this application.

Claims

1. An active display pixel circuit, comprising: The light-emitting device has its cathode configured to receive ground level; The PWM module is configured to receive at least a reference signal and a display signal, and output a PWM signal. A constant current module, coupled to the PWM module at a first node, is configured to receive the PWM signal and control the light-emitting state of the light-emitting device according to the PWM signal; The PWM module includes: The comparison unit includes at least a comparator. The input terminal of the comparator receives the reference signal or the display signal in a time-division manner. The output terminal of the comparator is coupled to the first node and configured to compare the input voltage of the comparator with the flip voltage of the comparator, and output the PWM signal according to the comparison result. A positive feedback unit, coupled between the input and output terminals of the comparator, is configured to change the operating region of the transistors in the comparator by either increasing the input voltage of the comparator or decreasing the flip voltage of the comparator when the relative relationship between the input voltage and the flip voltage of the comparator is reversed during the light-emitting phase of the pixel circuit.

2. The pixel circuit according to claim 1, wherein the reference signal gradually increases or decreases over time.

3. The pixel circuit according to claim 2, wherein, The comparator includes: The first transistor (T52, T62, or T72) has its source configured to receive the power supply voltage and its drain coupled to the first node (B5, B6, or B7). The second transistor (T53, T63, or T73) has its source configured to receive ground level, its gate coupled to the gate of the first transistor, and its drain coupled to the first node. The comparison unit further includes: A first capacitor (C51, C61, or C71) has its first terminal configured to receive the reference signal or the display signal in a time-division manner, and its second terminal coupled to a second node (A5, A6, or A7) between the gate of the first transistor and the gate of the second transistor. The third transistor (T51, T61, or T71) has its gate configured to receive a scan signal, its source coupled to the second node, and its drain coupled to the first node; The positive feedback unit includes: The fourth transistor (T54, T64, or T74) has its drain configured to receive an enable signal; A fifth transistor (T55, T65, or T75) has its gate coupled to the gate of the fourth transistor, its source coupled to the source of the fourth transistor, and its drain configured to receive the scan signal. The second capacitor (C52, C62, or C72) has its first end coupled to the second node and its second end coupled to the third node (C5, C6, or C7) between the source of the fourth transistor and the source of the fifth transistor. The fourth node (D5, D6, or D7) between the gate of the fourth transistor and the gate of the fifth transistor is coupled to the first node. The types of the first transistor and the fourth transistor are complementary to the types of the second transistor, the third transistor and the fifth transistor.

4. The pixel circuit according to claim 2, wherein, The comparison unit further includes: The first transistor (T81) has its gate configured to receive a scan signal and its drain coupled to the first node (B8); The second transistor (T82) has a gate configured to receive a reset signal, a drain configured to receive a power supply voltage, and a source coupled to the first node. The first capacitor (C81) has a first terminal configured to receive the reference signal or the display signal in a time-division manner, and its second terminal is coupled to the source of the first transistor. The comparator includes: The third transistor (T83) has its source configured to receive ground level, its gate coupled to the second node (A8) between the second terminal of the first capacitor and the source of the first transistor, and its drain coupled to the first node. The positive feedback unit includes: The fourth transistor (T84) has its drain configured to receive an enable signal; The fifth transistor (T85) has its gate coupled to the gate of the fourth transistor, its source coupled to the source of the fourth transistor, and its drain configured to receive the scan signal. The second capacitor (C82) has its first end coupled to the second node and its second end coupled to the third node (C8) between the source of the fourth transistor and the source of the fifth transistor. The fourth node (D8) between the gate of the fourth transistor and the gate of the fifth transistor is coupled to the first node; The type of the fourth transistor is complementary to the types of the first transistor, the second transistor, the third transistor, and the fifth transistor.

5. The pixel circuit according to claim 2, wherein, The comparator includes: The first transistor (T92) has its source configured to receive the power supply voltage and its drain coupled to the first node (B9). The second transistor (T93) is a dual-gate transistor with its source configured to receive ground level, its top gate coupled to the gate of the first transistor, and its drain coupled to the first node. The comparison unit further includes: A first capacitor (C91) has a first terminal configured to receive the reference signal or the display signal in a time-division manner, and a second terminal coupled to a second node (A9) between the gate of the first transistor and the top gate of the second transistor. The third transistor (T91) has a gate configured to receive a scan signal, a source coupled to the second node, and a drain coupled to the first node; The positive feedback unit includes: The fourth transistor (T96) has its source configured to receive the power supply voltage; The fifth transistor (T97) has its source configured to receive ground level, its gate coupled to the gate of the fourth transistor, and its drain coupled to the drain of the fourth transistor. The positive feedback unit and the comparator in the comparison unit share the second transistor, and the bottom gate of the second transistor is coupled to the third node (C9) between the drain of the fourth transistor and the drain of the fifth transistor. The fourth node (D9) between the gate of the fourth transistor and the gate of the fifth transistor is coupled to the first node; The fifth transistor is larger than the fourth transistor. The types of the first transistor and the fourth transistor are complementary to the types of the second transistor, the third transistor and the fifth transistor.

6. The pixel circuit according to claim 3, wherein, The constant current module includes: The sixth transistor (T58) has its gate configured to receive the enable signal and its source configured to receive the power supply voltage. The seventh transistor (T57) has its drain coupled to the drain of the sixth transistor; The eighth transistor (T511) has a gate configured to receive a first gate drive signal, a source configured to receive a programming signal from the constant current module, and a drain coupled to a seventh node (G5) between the drain of the sixth transistor and the drain of the seventh transistor. The third capacitor (C53) has its first terminal configured to receive the power supply voltage and its second terminal coupled to the gate of the seventh transistor. The ninth transistor (T56) has its gate coupled to the first node (B5), its drain coupled to the source of the seventh transistor, and its source coupled to the anode of the light-emitting device; The tenth transistor (T510) has a gate configured to receive a second gate drive signal, a source configured to receive a ground level, and a drain coupled to the fifth node (E5) between the gate of the seventh transistor and the second terminal of the third capacitor. The eleventh transistor (T59) has a gate configured to receive the first gate drive signal, a source coupled to the fifth node, and a drain coupled to the sixth node (F5) between the source of the seventh transistor and the drain of the ninth transistor. The seventh transistor type is complementary to the types of the sixth, eighth, ninth, tenth, and eleventh transistors.

7. The pixel circuit according to any one of claims 3-5, wherein, The constant current module includes: The sixth transistor (T67, T87, or T95) has its drain configured to receive the power supply voltage and its gate configured to receive the enable signal. The seventh transistor (T66, T86, or T94) has its gate coupled to the first node (B6, B8, or B9), its drain coupled to the source of the sixth transistor, and its source coupled to the anode of the light-emitting device. The sixth transistor is of the same type as the seventh transistor.

8. The pixel circuit according to claim 3, wherein, The constant current module includes: The sixth transistor (T77) has its drain configured to receive the power supply voltage; The third capacitor (C73) has its first terminal configured to receive the power supply voltage and its second terminal coupled to the gate of the sixth transistor. The seventh transistor (T76) has its gate coupled to the first node (B7) and its drain coupled to the source of the sixth transistor; The eighth transistor (T710) has a gate configured to receive the enable signal, a drain coupled to the source of the seventh transistor, and a source coupled to the anode of the light-emitting device. The ninth transistor (T79) has a gate configured to receive the scan signal, a source coupled to a current source outside the pixel circuit, configured to receive the bias current required by the pixel circuit, and a drain coupled to the fifth node (E7) between the gate of the sixth transistor and the second terminal of the third capacitor. The tenth transistor (T78) has its gate configured to receive the scan signal, its source coupled to the fifth node, and its drain coupled to the sixth node (F7) between the source of the sixth transistor and the drain of the seventh transistor. The type of the sixth transistor is complementary to the types of the seventh, eighth, ninth, and tenth transistors.

9. An active display device, comprising: An active display pixel array comprising n rows, each row containing m pixel circuits as described in any one of claims 1-8, wherein n and m are both integers greater than or equal to 1; A gate driving circuit module, comprising n gate driving circuits, wherein m pixel circuits in the same row of the active display pixel array share one gate driving circuit; A source drive circuit module includes m source drive circuits, wherein n pixel circuits in the same column of the active display pixel array share a source drive circuit, and each source drive circuit includes a DAC. A timing control circuit, which is coupled to the gate drive circuit module and the source drive circuit module respectively, is configured to receive external data and control signals and transmit them to the source drive circuit module and the gate drive circuit module.

10. The active display device according to claim 9, wherein, The DAC is configured to convert the display data received by the active display device into a display signal.

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