A display panel, method and apparatus

Abstract

This application discloses a display panel, method, and device. The display panel includes multiple pixel driving circuits, each pixel driving circuit comprising multiple selection modules and driving modules. A source driving circuit connects to the selection modules and driving modules of each pixel driving circuit via data lines, and is also connected to multiple selection modules of each row of pixel driving circuits via multiple signal lines, each transmitting a different duty cycle of a light-emitting control signal. A control module selects one of the multiple signal lines based on a target signal, causing the light-emitting control signal corresponding to the selected signal line to control the light-emitting duration of the pixel's light-emitting element. Furthermore, based on the target signal and the light-emitting control signal corresponding to the selected signal line, the source driving circuit generates a first data signal to control the magnitude of the driving current flowing through the pixel's light-emitting element. This solution reduces the complexity of data signal design and improves the accuracy of grayscale display and the overall display effect.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more specifically to a display panel, method, and device. Background Technology

[0002] In the display field, the application of micro light-emitting diodes (μLEDs) is becoming increasingly widespread. However, the current-voltage characteristic curve of μLEDs is very steep, making it difficult to achieve precise grayscale adjustment using traditional analog voltage driving methods.

[0003] In related technologies, digital pulse width modulation (PWM) is usually used to achieve grayscale control. However, in the existing PWM driving architecture, the light emission control signal is directly controlled and output by the gate driver chip, and the same row of pixels shares the same light emission control signal. Moreover, due to the limitations of chip hardware architecture and manufacturing cost, this signal can only provide 2-3 different duty cycles, which cannot simultaneously adapt to the display needs of different grayscale levels in the same industry. This can easily lead to complex data signal design, reduced grayscale display accuracy, and thus affect the display quality. Summary of the Invention

[0004] This application discloses a display panel, method, and device that can reduce the complexity of data signal design and improve the accuracy of grayscale display and overall display effect.

[0005] The first aspect of this application discloses a display panel, including: Multiple pixel driving circuits are arranged in a matrix along the row and column directions. Each pixel driving circuit includes multiple selection modules and driving modules. The driving module in each pixel driving circuit is connected to a pixel light-emitting element. A gate driving circuit, wherein the gate driving circuit is connected to the plurality of selection modules in the pixel driving circuit arranged along the row direction; A source driving circuit, comprising a data line and multiple signal lines, wherein the source driving circuit is connected via the data line to the plurality of selection modules and driving modules in each of the pixel driving circuits arranged along the column direction; The source driving circuit is also connected one-to-one with multiple selection modules in the pixel driving circuit arranged along the row direction through the multiple signal lines, and is used to send light emission control signals to the pixel driving circuit through the multiple signal lines; wherein, the duty cycle of the light emission control signals transmitted by different signal lines is different. The plurality of selection modules are used to select one of the plurality of signal lines to send a light emission control signal to the driving module. The control module is connected to the source drive circuit and the gate drive circuit. The control module is specifically configured as follows: Receive a target signal, and based on the grayscale range represented by the target signal, control and select one of the multiple signal lines so that the light emission control signal corresponding to the selected signal line controls the light emission duration of the pixel light emission element; Furthermore, the source drive circuit generates a first data signal based on the target signal and the light emission control signal corresponding to the selected signal line to control the magnitude of the drive current flowing through the pixel light emission element.

[0006] In this scheme, the display panel includes multiple pixel driving circuits, gate driving circuits, source driving circuits, and a control module arranged in a matrix along the row and column directions. Each pixel driving circuit includes multiple selection modules and driving modules, with each driving module connected to a pixel light-emitting element. The source driving circuit connects to the selection modules and driving modules of each pixel driving circuit via data lines, and also connects to multiple selection modules of each row of pixel driving circuits via multiple signal lines, each transmitting a different duty cycle of the light-emitting control signal. After receiving a target signal representing the grayscale value of a target pixel, the control module, based on the grayscale value range of the target pixel represented by the target signal, controls the selection of one of the multiple signal lines so that the light-emitting control signal corresponding to the selected signal line controls the light-emitting duration of the pixel light-emitting element; and, based on the target signal and the light-emitting control signal corresponding to the selected signal line, controls the source driving circuit to generate a first data signal to control the magnitude of the driving current flowing through the pixel light-emitting element.

[0007] This solution, by setting up multiple signal lines to transmit emission control signals with different duty cycles, and having a selection module select the corresponding duty cycle signal based on the grayscale value range of the target pixel, can match appropriate emission duty cycles for pixels of different grayscale values ​​within the same row, no longer limited by a uniform duty cycle level for the entire row. Therefore, there is no need to adjust the data signal to compensate for grayscale adaptation differences, reducing the design complexity of the data signal and making the emission duration of each pixel more closely match its own grayscale requirements, effectively improving grayscale display accuracy and enhancing display quality.

[0008] The system receives a target signal and controls the source driving circuit to generate multiple second data signals based on the gray value range of the target pixel represented by the target signal. Different gray value ranges correspond to different multiple second data signals. As an optional implementation, in a first aspect of the embodiments of this application, the source driving circuit is controlled to send the plurality of second data signals to the plurality of selection modules respectively, so that each selection module is in a first working state when it receives the corresponding second data signal, so as to transmit the light emission control signal on the corresponding signal line to the driving module; or, each selection module is in a second working state when it receives the corresponding second data signal, so as to block the transmission of the light emission control signal on the corresponding signal line to the driving module.

[0009] In this scheme, the control module controls the source drive circuit to output multiple second data signals to multiple selection modules respectively. Each selection module switches its operating mode according to the received second data signal: in the first operating state, the line is turned on, and the light emission control signal on the corresponding signal line is sent to the drive module; in the second operating state, the line is turned off, and the transmission path of the light emission control signal to the drive module is cut off.

[0010] It is understandable that different grayscale value ranges correspond to different combinations of second data signals, which can flexibly control the on / off state of each selection module and complete the selective selection of multiple signal lines. Relying on the independent control of multiple selection paths, the effective transmission duration of the emission control signal can be finely configured. Pixel brightness adjustment is achieved through duration modulation, widening the grayscale adjustment range and effectively improving the grayscale level and display hierarchy of the image. The multiple signals are independent and do not interfere with each other, ensuring that each pixel can independently configure its emission duration, avoiding crosstalk between pixels, and ensuring uniform and stable grayscale control across the entire image.

[0011] As an optional implementation, in a first aspect of this application embodiment, the display panel includes a gate driving circuit, which is connected to the plurality of selection modules in the pixel driving circuits arranged along the row direction. The selection module includes a storage capacitor and a switching transistor module. The storage capacitor is connected to the switching transistor module and the ground terminal, respectively. The switching transistor module is connected to the source drive circuit, the gate drive circuit and the drive module, respectively. The control module is specifically configured as follows: The gate driving circuit controls the target scan signal sent to the switching transistor module, so that when the switching transistor module receives the target scan signal, it transmits the corresponding second data signal to the storage capacitor, and transmits the light emission control signal on the corresponding signal line to the driving module according to the voltage of the storage capacitor being in a first working state, or blocks the transmission of the light emission control signal on the corresponding signal line to the driving module according to the voltage of the storage capacitor being in a second working state.

[0012] In this scheme, the display panel also includes a gate driving circuit, which is connected to multiple selection modules in the pixel driving circuits arranged along the row direction. Each selection module includes a storage capacitor and a switching transistor module. The storage capacitor is connected to the switching transistor module and a ground terminal, respectively. The switching transistor module is connected to the source driving circuit via corresponding signal lines, and also to the gate driving circuit and the driving module. The control module controls the gate driving circuit to send a target scan signal to the switching transistor module. When the switching transistor module receives the target scan signal, it transmits the corresponding second data signal sent by the source driving circuit to the storage capacitor. Based on the voltage of the storage capacitor being in a first or second operating state, it accordingly turns on or blocks the transmission of the light-emitting control signal on the corresponding signal line to the driving module.

[0013] It is understandable that by storing the voltage corresponding to the second data signal in the storage capacitor, the operating state of the switching transistor module can be maintained continuously after the target scanning signal ends. This ensures the stability of the on / off state of the light emission control signal without continuous data input, improving the reliability of the circuit. Simultaneously, in conjunction with the row-by-row scanning control of the gate drive circuit, the state configuration of each selection module can be completed row by row, ensuring that different pixels within the same row stably select the light emission control signal corresponding to the duty cycle, thus guaranteeing the accuracy of grayscale display.

[0014] As an optional implementation, in a first aspect of the embodiments of this application, the switching module includes a write switching transistor and a transmit switching transistor; The write switch is connected to the storage capacitor, the source drive circuit, and the gate drive circuit respectively. The transmission switch is connected to the source drive circuit through a corresponding signal line. The transmission switch is also connected to the storage capacitor and the drive module respectively. The control module is specifically configured as follows: The gate drive circuit controls the target scan signal sent to the switching transistor module, so that the write switching transistor module is turned on when it receives the target scan signal, and transmits the corresponding second data signal sent by the source drive circuit to the storage capacitor. The transmission switch is in an on state according to the voltage of the storage capacitor to transmit the light emission control signal on the corresponding signal line to the driving module; or, the transmission switch is in an off state according to the voltage of the storage capacitor to block the transmission of the light emission control signal on the corresponding signal line to the driving module.

[0015] In this scheme, the switching module includes a write switch and a transmission switch. The write switch is connected to the storage capacitor, the source drive circuit, and the gate drive circuit, respectively. The transmission switch is connected to the source drive circuit via a corresponding signal line, and is also connected to the storage capacitor and the drive module. The control module controls the gate drive circuit to send a target scan signal to the switching module. When the write switch receives the target scan signal, it is in the on state, transmitting the data signal on the data line to the storage capacitor. The transmission switch is in the on or off state according to the voltage of the storage capacitor, correspondingly turning on or off the transmission of the light emission control signal on the corresponding signal line to the drive module. It can be understood that separating the data writing and signal on / off functions into write and transmission switches can avoid mutual interference between the data writing process and the light emission control process, improving the stability of circuit operation. At the same time, by maintaining the voltage of the storage capacitor to control the working state of the transmission switch, the on / off state of the light emission control signal can be maintained continuously after the scan signal ends, ensuring the stability of the pixel light emission process and improving the accuracy of grayscale display.

[0016] As an optional implementation, in a first aspect of the embodiments of this application, the driving module includes a writing module and a light-emitting control module. The writing module is connected to the light-emitting control module, the gate driving circuit, the source driving circuit and the ground terminal respectively. The light-emitting control module is connected to the plurality of selection modules, the pixel light-emitting element, the power supply voltage and the gate driving circuit respectively. The light-emitting control module includes a driving transistor and a first capacitor. The control module is specifically configured as follows: The gate drive circuit is controlled to send a first scan signal to the write module, so that the write module is in a conducting state when it receives the first scan signal, and the voltage of the stored first data signal is transmitted to the control terminal of the first capacitor through the write module. When the light emission control module receives the light emission control signal through the plurality of selection modules, it is in an on state. The driving transistor in the light emission control module in the on state generates a driving current according to the voltage of the first data signal stored at the control terminal of the first capacitor, and transmits the driving current to the pixel light emission element.

[0017] In this scheme, the driving module includes a writing module and a light-emitting control module. The writing module is connected to the light-emitting control module, the gate driving circuit, the source driving circuit, and the ground terminal. The light-emitting control module is connected to multiple selection modules, the pixel light-emitting element, the power supply voltage, and the gate driving circuit. The light-emitting control module includes a driving transistor and a first capacitor. The control module controls the gate driving circuit to send a first scan signal to the writing module. When the writing module receives the first scan signal, it is in a conducting state and transmits the voltage of the first data signal to the control terminal of the first capacitor. When the light-emitting control module receives the light-emitting control signal through multiple selection modules, it is turned on. The driving transistor in the selection module generates a driving current based on the first data signal voltage stored at the control terminal of the first capacitor and the power supply voltage, and transmits the driving current to the pixel light-emitting element.

[0018] It is understandable that separating the functions of the writing module and the light-emitting control module can avoid mutual interference between the data writing and light-emitting control processes, thereby improving the stability of circuit operation. The first capacitor continuously stores the voltage of the first data signal, ensuring the stability of the control voltage of the driving transistor, making the output driving current more stable. Combined with the light-emitting control signal with the corresponding duty cycle, it can accurately control the light-emitting duration of the pixel light-emitting element, effectively ensuring the accuracy of grayscale display.

[0019] As an optional implementation, in a first aspect of the embodiments of this application, the writing module includes a voltage writing unit and a transmission unit; The voltage writing unit is connected to the source driving circuit, the gate driving circuit, the transmission unit and the ground terminal respectively, and the transmission unit is connected to the gate driving circuit and the light emission control module respectively. The control module is specifically configured as follows: The source drive circuit is controlled to send the first data signal to the drive circuit, and the gate drive circuit is controlled to send a write signal to the voltage write unit, so that the voltage write unit is in the on state when it receives the write signal, and the first data signal is stored in the voltage write unit. The gate drive circuit is controlled to send a first scan signal to the transmission unit, so that the transmission unit is in a conducting state when it receives the first scan signal, and the voltage of the first data signal stored in the voltage writing unit is transmitted to the first capacitor.

[0020] In this scheme, the writing module includes a voltage writing unit and a transmission unit. The voltage writing unit is connected to the source driving circuit, the gate driving circuit, the transmission unit, and the ground terminal, respectively. The transmission unit is connected to the gate driving circuit and the light-emitting control module, respectively. The control module first controls the source driving circuit to send a first data signal, and simultaneously controls the gate driving circuit to send a write signal to the voltage writing unit. When the voltage writing unit receives the write signal, it is in a conducting state and stores the first data signal. The control module then controls the gate driving circuit to send a first scan signal to the transmission unit. When the transmission unit receives the first scan signal, it is in a conducting state and transmits the voltage of the first data signal stored in the voltage writing unit to the first capacitor. It can be understood that by using a time-division control method where the voltage writing unit first buffers the first data signal and then the transmission unit writes it to the first capacitor, the voltage of the first capacitor can be avoided from being directly interfered with during the writing process, ensuring that the voltage stored in the first capacitor is accurate and stable, making the driving current output by the driving transistor more precise, thereby improving the accuracy of grayscale display.

[0021] As an optional implementation, in a first aspect of the embodiments of this application, the voltage writing unit includes a writing transistor and a second capacitor; The write transistor is connected to the gate driving circuit, the source driving circuit and the second capacitor respectively, and the second capacitor is connected to the ground terminal and the transmission unit respectively. The control module is specifically configured as follows: The gate drive circuit is controlled to send the write signal to the write transistor, so that when the write transistor receives the write signal, it is in a conducting state and transmits the first data signal to the second capacitor.

[0022] In this scheme, the voltage writing unit includes a writing transistor and a second capacitor. The writing transistor is connected to the gate driving circuit, the source driving circuit, and the second capacitor, which is connected to the ground terminal and the transmission unit. The control module controls the gate driving circuit to send a write signal to the writing transistor. When the writing transistor receives the write signal, it is in a conducting state, transmitting the first data signal to the second capacitor, which stores the first data signal. It can be understood that using the second capacitor to independently store the first data signal can stably maintain the corresponding voltage and reduce deviations caused by signal fluctuations. Simultaneously, by independently controlling the data writing process through the writing transistor, reliable data caching can be achieved, ensuring the accurate and stable voltage subsequently transmitted to the first capacitor. This helps improve the control accuracy of the driving current and ensures the accuracy of grayscale display.

[0023] As an optional implementation, in a first aspect of the embodiments of this application, the transmission unit includes a first transmission transistor and a second transmission transistor. The first transmission transistor is connected to the gate driving circuit, the voltage writing unit, and the driving transistor, respectively; the second transmission transistor is connected to the gate driving circuit, the control terminal of the first capacitor, and the driving transistor, respectively. The control module is specifically configured as follows: The gate drive circuit is controlled to send the first scan signal to the first transmission transistor and the second transmission transistor, so that the first transmission transistor and the second transmission transistor are in the conducting state when they receive the first scan signal. The first transmission transistor in the conducting state, the second transmission transistor in the conducting state, and the drive transistor form a transmission loop for transmitting the voltage of the first data signal in the voltage writing unit to the control terminal of the first capacitor, so that the drive transistor is in the conducting state according to the voltage of the first data signal.

[0024] In this scheme, the gate driving circuit is connected to the first transmission transistor and the second transmission transistor respectively. The control module controls the gate driving circuit to output a first scan signal, causing the first transmission transistor and the second transmission transistor to conduct synchronously. After conduction, the first transmission transistor, the second transmission transistor, and the driving transistor form a complete transmission loop, writing the first data signal voltage output by the voltage writing unit to the control terminal of the first capacitor, thereby controlling the driving transistor to maintain conduction.

[0025] It is understandable that by simultaneously activating two transmission transistors using the same scan signal, a stable data writing path can be established, allowing the data voltage to be stored in the first capacitor in one go. After the scan pulse disappears, the voltage on the plate is maintained by the first capacitor, continuously locking the conduction state of the drive transistor, eliminating the need for continuous application of data voltage and reducing the data refresh pressure on the drive circuit.

[0026] As an optional implementation, in a first aspect of the embodiments of this application, the light emission control module further includes a first light emission control transistor and a second light emission control transistor. The first light emission control transistor is connected to the power supply voltage, the plurality of selection modules, the driving transistor, and the writing module, respectively. The second light emission control transistor is connected to the pixel light emission element, the driving transistor, the plurality of selection modules, and the writing module, respectively. The driving transistor is also connected to the control terminal of the first capacitor. When the first light-emitting control transistor receives the light-emitting control signal through the plurality of selection modules, it is in an on state and transmits the power supply voltage to the driving transistor. When the driving transistor receives the power supply voltage, it is in a conducting state and generates a driving current based on the voltage of the first data signal stored at the control terminal of the first capacitor, and transmits the driving current to the second light-emitting control transistor. When the second light-emitting control transistor receives the light-emitting control signal through the plurality of selection modules, it is in the conducting state, and the second light-emitting control transistor in the conducting state transmits the received driving current to the pixel light-emitting element.

[0027] In this scheme, the light-emitting control module further includes a first light-emitting control transistor and a second light-emitting control transistor. The first light-emitting control transistor is connected to the power supply voltage, multiple selection modules, a driving transistor, and a writing module. The second light-emitting control transistor is connected to the pixel light-emitting element, the driving transistor, multiple selection modules, and the writing module. The driving transistor is also connected to the control terminal of the first capacitor. When the first and second light-emitting control transistors receive the light-emitting control signal through the multiple selection modules, they are in a conducting state. The first light-emitting control transistor transmits the power supply voltage to the driving transistor, which generates a driving current based on the first data signal voltage stored at the control terminal of the first capacitor and the power supply voltage. The second light-emitting control transistor transmits the driving current to the pixel light-emitting element. It can be understood that using two light-emitting control transistors to separately control the on / off of the power input and current output paths can more stably control the opening and closing of the light-emitting circuit, reduce the risk of leakage current in the off state, ensure that the actual light-emitting duration of the pixel light-emitting element is accurately matched with the duty cycle of the light-emitting control signal, and effectively improve the accuracy of grayscale display.

[0028] As an optional implementation, in a first aspect of this application, the light-emitting control module further includes a compensation unit, which is connected to the power supply voltage, the reference voltage terminal, the compensation terminal of the first capacitor, the source driving circuit, and the gate driving circuit, respectively. The control module is also configured to: Before the light emission control module receives the light emission control signal through the plurality of selection modules, the source drive circuit is controlled to send a first signal to the compensation unit, and the gate drive circuit is controlled to send a second scan signal to the compensation unit, so that the compensation unit is in a first conduction state when it receives the first signal and the second scan signal, and sends the reference voltage to the compensation terminal of the first capacitor; When the light emission control module receives the light emission control signal through the plurality of selection modules, it controls the source drive circuit to send a target light emission control signal to the compensation unit and controls the gate drive circuit to send a third scan signal to the compensation unit, so that the compensation unit is in a second conduction state when it receives the target light emission control signal and the third scan signal, and sends the power supply voltage to the compensation terminal of the first capacitor. The voltage stored at the control terminal of the first capacitor reduces the target difference voltage according to the capacitive coupling principle. The target difference voltage is the difference between the power supply voltage and the reference voltage. The target light emission control signal is the signal with the largest duty cycle among the plurality of light emission control signals. The driving transistor in the light-emitting control module, which is in the conducting state, generates a stable driving current based on the voltage stored at the control terminal of the first capacitor, and transmits the stable driving current to the pixel light-emitting element.

[0029] In this scheme, the light-emitting control module also includes a compensation unit, which is connected to the power supply voltage, the reference voltage terminal, the compensation terminal of the first capacitor, the source driving circuit, and the gate driving circuit. Before the light-emitting control module receives the light-emitting control signal, the control module controls the source driving circuit to send a first signal to the compensation unit and the gate driving circuit to send a second scan signal. The compensation unit is in a first conducting state, transmitting the reference voltage to the compensation terminal of the first capacitor. When the light-emitting control module receives the light-emitting control signal, the control module controls the source driving circuit to send the target light-emitting control signal with the largest duty cycle and the gate driving circuit to send a third scan signal. The compensation unit is in a second conducting state, transmitting the power supply voltage to the compensation terminal of the first capacitor. The voltage stored at the control terminal of the first capacitor reduces the difference between the power supply voltage and the reference voltage through capacitive coupling, thereby enabling the driving transistor to generate a stable driving current and transmit it to the pixel light-emitting element. It can be understood that by adjusting the voltage at the control terminal of the driving transistor through the time-division multiplexing control of the compensation unit and the capacitive coupling effect of the first capacitor, the characteristic deviation of the driving transistor can be compensated, making the output driving current more stable. This method can reduce the impact of uneven device characteristics on pixel brightness, improve the uniformity and accuracy of grayscale display of each pixel, and ensure the consistency of display quality.

[0030] As an optional implementation, in a first aspect of the embodiments of this application, the compensation unit further includes a third light-emitting control transistor and a fourth light-emitting control transistor. The third light-emitting control transistor is connected to the power supply voltage, the fourth light-emitting control transistor, the compensation terminal of the first capacitor, and the gate driving circuit, respectively. The fourth light-emitting control transistor is connected to the gate driving circuit, the compensation terminal of the first capacitor, and the reference voltage terminal. The control module is also configured to: Before the light emission control module receives the light emission control signal through the plurality of selection modules, the source driving circuit is controlled to send a first signal to the third light emission control transistor, and the gate driving circuit is controlled to send a second scan signal to the fourth light emission control transistor, so that the third light emission control transistor is in the off state when it receives the first signal, and the fourth light emission control transistor is in the on state when it receives the second scan signal, so that the reference voltage is transmitted to the compensation terminal of the first capacitor. When the light-emitting control module receives the light-emitting control signal through the plurality of selection modules, it controls the source driving circuit to send a target light-emitting control signal to the third light-emitting control transistor, and controls the gate driving circuit to send a third scan signal to the fourth light-emitting control transistor, so that the third light-emitting control transistor is in the on state when it receives the target light-emitting control signal, and the fourth light-emitting control transistor is in the off state when it receives the second scan signal, so that the power supply voltage is transmitted to the compensation terminal of the first capacitor.

[0031] In this scheme, the compensation unit includes a third light-emitting control transistor and a fourth light-emitting control transistor. The third light-emitting control transistor is connected to the power supply voltage, the fourth light-emitting control transistor, the compensation terminal of the first capacitor, and the gate driving circuit. The fourth light-emitting control transistor is connected to the gate driving circuit, the compensation terminal of the first capacitor, and the reference voltage terminal. Before the light-emitting control module receives the light-emitting control signal, the control module controls the source driving circuit to send a first signal to the third light-emitting control transistor and the gate driving circuit to send a second scan signal to the fourth light-emitting control transistor, causing the third light-emitting control transistor to turn off and the fourth light-emitting control transistor to turn on, and the reference voltage is transmitted to the compensation terminal of the first capacitor. When the light-emitting control module receives the light-emitting control signal, the control module controls the source driving circuit to send a target light-emitting control signal to the third light-emitting control transistor and the gate driving circuit to send a third scan signal to the fourth light-emitting control transistor, causing the third light-emitting control transistor to turn on and the fourth light-emitting control transistor to turn off, and the power supply voltage is transmitted to the compensation terminal of the first capacitor. It can be understood that by switching the voltage of the first capacitor compensation terminal by the time-division multiplexing of the two light-emitting control transistors, the timing of capacitive coupling compensation can be precisely controlled, ensuring a stable and reliable compensation process. The control logic of this structure is simple and clear, and it can compensate for the characteristic deviation of the driving tube without complex circuits. It effectively reduces the current deviation caused by the unevenness of device characteristics and improves the uniformity and accuracy of pixel grayscale display.

[0032] As an optional implementation, in the first aspect of the embodiments of this application, each pixel driving circuit further includes a reset circuit. The reset circuit is connected to the gate drive circuit, the reset voltage terminal, and the drive module, respectively. The control module is also configured to: The gate drive circuit is controlled to send a reset signal to the reset circuit, so that the reset circuit is in a conducting state when it receives the reset signal, so that the reset circuit and the drive module form a discharge circuit to release the stored charge in the drive module.

[0033] In this scheme, each pixel driving circuit also includes a reset circuit, which is connected to the gate driving circuit, the reset voltage terminal, and the driving module. The control module controls the gate driving circuit to send a reset signal to the reset circuit. When the reset circuit receives the reset signal, it is in a conducting state, forming a discharge loop with the driving module to release the charge stored in the driving module. It can be understood that releasing the residual charge in the driving module through the reset circuit can clear the voltage deviation left over from the previous working stage, avoid residual charge interfering with the subsequent data writing process, ensure the accurate and stable voltage stored in the driving module, and enable precise matching of the output driving current with the target grayscale, thereby improving the stability and display quality of grayscale display.

[0034] A second aspect of this application discloses a control method applied to a display panel as described in any of the above embodiments. The method includes: Receive the target signal, and based on the gray value range of the target pixel represented by the target signal, control one of the multiple signal lines to control the light emission duration of the pixel light-emitting element by the light emission control signal corresponding to the selected signal line. Furthermore, the source drive circuit generates a first data signal based on the target signal and the light emission control signal corresponding to the selected signal line to control the magnitude of the drive current flowing through the pixel light emission element.

[0035] A third aspect of this application discloses a display device, including a display panel and a processor as described in any of the above embodiments; The processor is configured as follows: Upon receiving image data, a target signal is generated from the gray value range of each pixel in the image data, and the target signal is sent to the display panel. Different gray value ranges correspond to different target signals. The control module in the display panel is configured as follows: Receive the target signal, and according to the gray value range of the target pixel represented by the target signal, control one of the multiple signal lines to control the light emission duration of the pixel light emission element by the light emission control signal corresponding to the selected signal line; Furthermore, the source drive circuit generates a first data signal based on the target signal and the light emission control signal corresponding to the selected signal line to control the magnitude of the drive current flowing through the pixel light emission element. Attached Figure Description

[0036] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0037] Figure 1 This is a schematic structural diagram of a display panel disclosed in an embodiment of this application; Figure 2 This is a schematic flowchart illustrating a control method for a control module disclosed in an embodiment of this application; Figure 3 This is a schematic structural diagram of another display panel disclosed in an embodiment of this application; Figure 4 This is a schematic structural diagram of another display panel disclosed in an embodiment of this application; Figure 5 This is a schematic structural diagram of another display panel disclosed in an embodiment of this application; Figure 6 This is a schematic structural diagram of another display panel disclosed in an embodiment of this application; Figure 7 This is a schematic structural diagram of another display panel disclosed in an embodiment of this application; Figure 8 This is a schematic block diagram of a pixel driving circuit disclosed in an embodiment of this application; Figure 9 This is a control timing diagram of a pixel driving circuit disclosed in an embodiment of this application; Figure 10 This is a schematic flowchart illustrating a control method for a control module disclosed in an embodiment of this application; Figure 11 This is a schematic structural diagram of a display device disclosed in an embodiment of this application. Detailed Implementation

[0038] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0039] It should be noted that the terms "first, second, third" used in the embodiments of this application are used to distinguish similar or different objects and do not represent a specific order of objects. It can be understood that "first, second, third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0040] In the display industry, micro-light-emitting diodes (μLEDs) are being used more and more widely. However, the current-voltage characteristic curve of μLEDs is very steep, making it difficult to achieve precise grayscale adjustment using traditional analog voltage driving methods.

[0041] In related technologies, digital pulse width modulation (PWM) is usually used to achieve grayscale control. However, in the existing PWM driving architecture, the light emission control signal is directly controlled and output by the gate driver chip, and the same row of pixels shares the same light emission control signal. Moreover, due to the limitations of chip hardware architecture and manufacturing cost, this signal can only provide 2-3 different duty cycles, which cannot simultaneously adapt to the display needs of different grayscale levels of the same industry. This can easily lead to complex data signal design, reduced grayscale display accuracy, and thus affect the display quality.

[0042] To reduce the complexity of data signal design and improve the accuracy of grayscale display and overall display effect, embodiments of this application provide a display panel, method, and device. The display panel provided in this application will be described in detail below with reference to the accompanying drawings and embodiments to make the objectives and technical solutions of this application clearer and more intuitive. It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0043] It is understood that the display panels provided in this application embodiment can be applied to display devices including, but not limited to, smartphones, tablets, laptops, smart TVs, gaming monitors, smartwatches, and in-vehicle display terminals, etc., and no specific limitations are made here.

[0044] In some embodiments, the display panel includes a plurality of pixel driving circuits 10, which are arranged in a matrix along the row and column directions. Each pixel driving circuit 10 includes a plurality of selection modules 11 and driving modules 12, and the driving module 12 in each pixel driving circuit 10 is connected to a pixel light-emitting element 13.

[0045] For example, to better understand the structure of the display panel, we will describe it using two pixel driving circuits 10 along the row direction and two along the column direction. It can be understood that the number of pixel driving circuits 10 along the row and column directions can be other than these, and no specific limitation is made here. Figure 1 As shown, the display panel includes four pixel driving circuits 10, which are arranged in a matrix along the row and column directions. Each pixel driving circuit 10 includes multiple selection modules 11 and a driving module 12. The driving module 12 in each pixel driving circuit 10 is connected to a pixel light-emitting element 13. In addition, the display panel also includes a gate driving circuit 20, a source driving circuit 30, and a control module (not shown in the figure).

[0046] In this embodiment, multiple pixel driving circuits 10 are arranged in a matrix along the row and column directions, enabling parallel input of row-by-row scanning drive and column data signals, providing a hardware foundation for high-resolution, high-refresh-rate displays. Each pixel driving circuit 10 corresponds to an independent pixel light-emitting element 13, and by independently controlling the light-emitting state of each pixel, they are combined to form a complete display image.

[0047] Each pixel driving circuit 10 includes multiple selection modules 11 and driving modules 12, and the driving module 12 in each pixel driving circuit 10 is connected to a pixel light-emitting element 13.

[0048] Selection module 11 is a switching unit with signal on / off control function, which can turn on or block the transmission path of the corresponding light-emitting control signal according to the received second data signal.

[0049] Optionally, the selection module 11 can be a semiconductor switching device such as a thin-film transistor or a metal-oxide-semiconductor field-effect transistor, which receives a second data signal through the gate to control the conduction and cutoff between the source and the drain. No specific restrictions are imposed here.

[0050] The driving module 12 has the ability to store data and generate driving current. It can save the first input data signal information and output a corresponding driving current when it receives the light emission control signal.

[0051] Optionally, the driving module 12 can adopt various pixel driving architectures such as 2T1C, 5T1C, and 7T1C, and can include driving transistors and storage capacitors 111. The storage capacitors 111 are used to store the voltage information corresponding to the data signal, and the driving transistors are used to convert the voltage signal into driving current output. No specific restrictions are made here.

[0052] The pixel light-emitting element 13 is a self-emissive display device and is the light-emitting core of the display panel. It generates visible light by receiving driving current to excite the internal light-emitting material. Its brightness is positively correlated with the magnitude of the current flowing through it and the duration of light emission.

[0053] Optionally, the pixel light-emitting element 13 can be any self-emissive device such as a micro light-emitting diode, an organic light-emitting diode, or a quantum dot light-emitting diode, without any specific limitations.

[0054] Gate driving circuit 20 is connected to multiple selection modules 11 in pixel driving circuit 10 arranged along the row direction. The gate driving circuit 20 is arranged along the side of the display panel in the row direction. Its core function is to output the target scanning signal to each row pixel driving circuit 10 in sequence, and control the data writing timing of the corresponding row selection module 11 by gating row by row. It is the core circuit for realizing row scanning drive.

[0055] Optionally, the gate driving circuit 20 can adopt an array substrate row driving architecture, where the shift register unit is directly fabricated in the peripheral area of ​​the array substrate, and the line-by-line scanning output is achieved through cascading, without the need for additional bonding driver chips, which can effectively reduce the bezel width of the display panel; alternatively, a dedicated gate driving integrated circuit chip can be used, which is connected to the pins of the display panel through bonding technology, resulting in stronger driving capability and anti-interference capability of the output signal. The choice can be made according to the size, resolution and bezel design requirements of the display panel, and no specific restrictions are imposed here.

[0056] The source driving circuit 30 includes data lines and multiple signal lines. The source driving circuit 30 is connected to each selection module 11 and driving module 12 in the pixel driving circuit 10 arranged along the column direction via the data lines. The source driving circuit 30 is also connected one-to-one with multiple selection modules 11 in the pixel driving circuit 10 arranged along the row direction via multiple signal lines, for sending light emission control signals to the pixel driving circuit 10 via multiple signal lines. The duty cycle of the light emission control signals transmitted by different signal lines is different.

[0057] The source drive circuit 30 is arranged along the column side of the display panel and is the unified output terminal for data signals and light emission control signals. It contains two types of transmission lines: data lines and multiple signal lines, each undertaking different signal transmission functions.

[0058] The data lines serve as data signal transmission channels, extending along the column direction. They are connected to all selection modules 11 and driving modules 12 of all pixel driving circuits 10 in the same column, and are used to transmit the first data signal and the second data signal in parallel to all pixel driving circuits 10 in the same column. The number of data lines can correspond one-to-one with the number of pixel driving circuits 10 in the column direction, or a time-division multiplexing method can be used to reduce the number of data lines; no specific limitation is made here.

[0059] Multiple signal lines serve as transmission channels for the light emission control signals, extending along the row direction. Each signal line corresponds to a selection module 11 of the same type in a row of pixel driving circuit 10, used to transmit a light emission control signal with a fixed duty cycle to the target selection module 11 of the corresponding row. The duty cycles of the light emission control signals transmitted by different signal lines are different, thereby providing multiple different light emission duration control levels to adapt to the display requirements of different grayscale ranges.

[0060] For example, if each pixel driving circuit 10 includes two selection modules 11, then two signal lines are correspondingly set. The first signal line transmits a light emission control signal with a duty cycle of 50%, corresponding to the long-duration light emission level; the second signal line transmits a light emission control signal with a duty cycle of 12.5%, corresponding to the short-duration light emission level. It can be understood that the number of signal lines can be adjusted according to the number of selection modules 11, and the duty cycle value of each signal line can also be flexibly set according to the display grayscale division requirements, without specific limitations here.

[0061] Optionally, the source drive circuit 30 can adopt a digital-to-analog conversion architecture, a current-driven architecture, or a dedicated column drive integrated chip. The accuracy of the output signal can reach 8 bits, 10 bits, 12 bits, or even higher, and the output voltage range can be 0V~10V. It can be adjusted according to the driving requirements of the display panel, and no specific limitations are made here.

[0062] The control module is connected to the source drive circuit 30 and the gate drive circuit 20.

[0063] As the control center of the entire display panel, the control module is responsible for receiving externally input image signals, converting them into corresponding target signals, and sending them to the source drive circuit 30 and the gate drive circuit 20 respectively. At the same time, it coordinates the working timing of each circuit to ensure that data writing, signal transmission, pixel light emission and other processes are carried out in an orderly manner and avoid timing conflicts.

[0064] Optionally, the control module may be a microcontroller, digital signal processor, field-programmable gate array, or dedicated display control chip, without specific limitations.

[0065] Based on the schematic structural diagram of the display panel described above, this application also discloses a schematic flowchart of a control method for a control module, as shown below. Figure 2As shown, this flowchart includes at least the following steps: Step S102: Receive the target signal.

[0066] Step S103: Based on the gray value range of the target pixel represented by the target signal, control one of the multiple signal lines to control the light emission duration of the pixel light-emitting element by the light emission control signal corresponding to the selected signal line.

[0067] Step S104: Control the source driving circuit to generate a first data signal according to the target signal and the light emission control signal corresponding to the selected signal line, so as to control the magnitude of the driving current flowing through the pixel light emission element.

[0068] It is understood that this embodiment uses a two-dimensional hierarchical dimming method to adjust pixel brightness. First, the complete grayscale value range of the pixel is divided into multiple non-overlapping grayscale value intervals, each grayscale value interval uniquely corresponding to a signal line. After the control module obtains the grayscale value of the target pixel, it first determines the grayscale value interval to which the grayscale value belongs, and then selects the corresponding signal line according to the grayscale value interval. The emission duration of the pixel's light-emitting element is determined by the emission control signal corresponding to the signal line, thus completing the coarse adjustment of the PWM duration.

[0069] While keeping the selected grayscale value range, corresponding signal lines, and emission duration constant, the brightness levels within this grayscale value range are further subdivided. The control module generates first data signals of different amplitudes based on the current grayscale value range; these first data signals are PAM amplitude modulation voltages. Different amplitude first data signals correspond to different drive transistor on-state currents, and fine-tuning of brightness is achieved by adjusting the drive current.

[0070] In other words, the emission duration is uniquely locked by the grayscale value range, and the conduction duration of all pixels within the same range remains consistent; the multi-level brightness differences within the range are achieved entirely by changing the voltage amplitude of the first data signal and adjusting the emission current. The total emission brightness is determined by both the emission duration and the driving current, and the overall grayscale number is significantly expanded by relying on a two-dimensional combination of coarse PWM duration gradation and fine PWM current gradation.

[0071] For example, firstly, a target signal is received, and the source drive circuit 30 is controlled to generate a first data signal and a plurality of second data signals according to the target signal.

[0072] The target signal is used to characterize the grayscale value range of the target pixel. Different grayscale value ranges correspond to different second data signals. The first data signal is a PAM amplitude modulation voltage signal, the voltage amplitude of which is determined by the grayscale value of the target pixel and the selected signal line level. This voltage is applied to the driving transistor to adjust the conduction current of the driving transistor, thereby controlling the magnitude of the light emission current of the pixel light-emitting element.

[0073] In this embodiment, the control module receives an externally input target signal. The target signal carries the grayscale value information of the target pixel, which is used to indicate the brightness level that the pixel needs to display. The control module performs range judgment based on the grayscale value of the target pixel, generates corresponding control commands, and controls the source drive circuit 30 to generate one first data signal and multiple second data signals.

[0074] The first data signal is a voltage signal with continuously adjustable amplitude. Different signal amplitudes correspond to different single grayscale values, which are used to accurately configure the magnitude of the drive current output by the drive module 12.

[0075] The second data signal is a switch control signal. Different signal values ​​correspond to different grayscale value ranges and are used to control the working state of the corresponding selection module 11. The number of the second data signals corresponds one-to-one with the number of selection modules 11 in the pixel driving circuit 10.

[0076] In some embodiments, the plurality of second data signals may also be generated by the gate drive circuit based on the target signal.

[0077] Secondly, the source drive circuit 30 sends the first data signal to the drive circuit, the drive circuit stores the first data signal upon receiving it, and the source drive circuit 30 sends multiple second data signals to multiple selection modules 11 respectively.

[0078] The control module controls the source drive circuit 30 to send the first data signal to the drive module 12 of the corresponding column pixel drive circuit 10 through the data line.

[0079] After receiving the first data signal, the storage unit inside the drive module 12 saves the voltage information corresponding to the first data signal. It retains the voltage information during the stage when no light emission control signal is received, and waits for the light emission stage to use it.

[0080] At the same time, the control module controls the source drive circuit 30 to send multiple second data signals to multiple selection modules 11 of the corresponding column pixel drive circuit 10 via data lines.

[0081] Each selection module 11 receives a corresponding second data signal and switches its own working state according to the level value of the second data signal.

[0082] Next, each selection module 11, upon receiving the corresponding second data signal, is in a first operating state to transmit the light emission control signal on the corresponding signal line to the driver module 12; or, each selection module 11, upon receiving the corresponding second data signal, is in a second operating state to block the transmission of the light emission control signal on the corresponding signal line to the driver module 12.

[0083] In this embodiment, the selection module 11 has two working modes: a first working state and a second working state.

[0084] When the second data signal received by the selection module 11 is at an effective level, the selection module 11 is in the first working state. At this time, the switch path inside the selection module 11 is turned on, and the light emission control signal transmitted on the corresponding signal line can be transmitted to the control terminal of the drive module 12 through the selection module 11 to participate in the light emission control of the drive module 12.

[0085] When the second data signal received by the selection module 11 is invalid, the selection module 11 is in the second working state. At this time, the switch path inside the selection module 11 is cut off, and the light emission control signal on the corresponding signal line cannot be transmitted to the driving module 12. This light emission control signal does not participate in the light emission control of the current pixel.

[0086] In this embodiment, by controlling the on / off state of different selection modules 11 with different second data signals, it is possible to flexibly select to connect light emission control signals with different duty cycles to the drive module 12 to achieve switching of multiple light emission durations; it is also possible to simultaneously turn on multiple selection modules 11 to superimpose the durations of multiple light emission control signals, thereby further expanding the range and accuracy of grayscale adjustment.

[0087] Finally, upon receiving the light emission control signal, the driving module 12 generates a driving current based on the stored first data signal and sends the driving current to the pixel light emission element 13.

[0088] In this embodiment, when the control terminal of the driving module 12 receives a valid light emission control signal, the driving module 12 enters the conducting state. Based on the voltage value corresponding to the first data signal stored internally, it generates a corresponding driving current and outputs the driving current to the connected pixel light-emitting element 13. The pixel light-emitting element 13 begins to emit light under the action of the driving current. The duration of light emission is determined by the duty cycle of the light emission control signal, and the brightness is determined by the magnitude of the driving current. Both factors together determine the actual grayscale of the pixel.

[0089] When the light emission control signal becomes invalid, the drive module 12 is turned off, stops outputting drive current, and the pixel light emission element 13 is turned off. Within one frame display cycle, the actual total light emission time of the pixel light emission element 13 is determined by the duty cycle of the input light emission control signal, which, combined with the current magnitude adjusted by the first data signal, together achieves accurate display of the target grayscale value.

[0090] For example, taking a pixel driving circuit 10 that includes three selection modules 11 and three signal lines with different duty cycles as an example, the specific grayscale display process is explained.

[0091] Three signal lines are configured to transmit the first, second, and third light-emitting control signals, respectively. The first light-emitting control signal has a duty cycle of 50%, corresponding to long-duration illumination in the high grayscale range; the second light-emitting control signal has a duty cycle of 25%, corresponding to medium-duration illumination in the medium grayscale range; and the third light-emitting control signal has a duty cycle of 6.25%, corresponding to short-duration illumination in the low grayscale range. The total grayscale range of the display panel is 0~255 levels, divided into three grayscale value ranges: low grayscale (0~31 grayscale), medium grayscale (32~127 grayscale), and high grayscale (128~255 grayscale).

[0092] When the target pixel grayscale value is 16 gray levels, which belongs to the low gray range, the control module generates corresponding control instructions according to the target signal: the source drive circuit 30 outputs the first data signal with the corresponding 16 gray level amplitude to the drive module 12, and at the same time outputs the second data signal with an effective level to the selection module 11 corresponding to the third light emission control signal, and outputs the second data signal with an invalid level to the two selection modules 11 corresponding to the first light emission control signal and the second light emission control signal.

[0093] At this time, the selection module 11 corresponding to the third light emission control signal is in the first working state, and the third light emission control signal with a duty cycle of 6.25% can be transmitted to the driving module 12; the selection modules 11 corresponding to the first light emission control signal and the second light emission control signal are both in the second working state, and the two light emission control signals are blocked. The driving module 12 generates a driving current of a corresponding magnitude according to the first data signal, and conducts light emission under the control of the light emission control signal with a short duty cycle. By using a small current and an extremely short duration, the single-frame light emission time in the low gray stage is further compressed, effectively reducing the impact of device leakage current on brightness in low gray scenes, and improving the grayscale display accuracy and image uniformity in the low gray range.

[0094] When the target pixel grayscale value is 64 gray levels, which belongs to the mid-gray range, the control module generates corresponding control instructions according to the target signal: the source drive circuit 30 outputs the first data signal with the corresponding 64 gray level amplitude to the drive module 12, and at the same time outputs the second data signal with an effective level to the selection module 11 corresponding to the second light emission control signal, and outputs the second data signal with an invalid level to the two selection modules 11 corresponding to the first light emission control signal and the third light emission control signal.

[0095] At this time, the selection module 11 corresponding to the second light emission control signal is in the first working state, and the second light emission control signal with a 25% duty cycle can be transmitted to the drive module 12; the other two selection modules 11 remain in the blocked state. The drive module 12 generates a corresponding driving current according to the first data signal, and together with the light emission control signal of medium duration, realizes the brightness display in the mid-gray range. Through the independent mid-gray duty cycle level, the driving deviation caused by excessive current in the low gray level or insufficient current in the high gray level can be avoided, making the brightness transition of the mid-gray screen smoother and more natural.

[0096] When the target pixel grayscale value is 192 gray levels, which belongs to the high gray range, the control module generates corresponding control instructions according to the target signal: the control source drive circuit 30 outputs the first data signal with a grayscale amplitude of 192 gray levels to the drive module 12, and at the same time outputs the second data signal with an effective level to the selection module 11 corresponding to the first light emission control signal, and outputs the second data signal with an invalid level to the two selection modules 11 corresponding to the second light emission control signal and the third light emission control signal.

[0097] At this time, the selection module 11 corresponding to the first light emission control signal is in the first working state, and the first light emission control signal with a duty cycle of 50% is transmitted to the driving module 12; the other two selection modules 11 remain blocked. The driving module 12 generates a driving current of a corresponding magnitude according to the first data signal, and works in conjunction with the long-duration light emission control signal to achieve high brightness display in the high gray range, meeting the display requirements of high-brightness images.

[0098] In other embodiments, two or three selection modules 11 can be activated simultaneously, allowing multiple light emission control signals with different duty cycles to act on the driving module 12 together. This allows for the superposition and combination of light emission durations to create more effective duty cycles. For example, activating the selection modules 11 corresponding to the second and third light emission control signals simultaneously yields an equivalent duty cycle of 31.25%; activating the selection modules 11 corresponding to the first and second light emission control signals simultaneously yields an equivalent duty cycle of 75%; and activating all three yields an equivalent duty cycle of 81.25%. By combining multiple durations, grayscale levels can be further subdivided, significantly improving grayscale display accuracy and enriching the color gradations and detail of the displayed image.

[0099] In this embodiment, by using three selection modules 11 with three different duty cycle emission control signals, the grayscale display range can be divided into three more refined segments. The emission duration is matched and adapted for different grayscale ranges of low, medium and high. On the basis of simplifying the panel wiring structure, the uniformity of display and brightness accuracy of the entire grayscale range are further improved. At the same time, by combining and conducting multiple selection modules 11, more equivalent duty cycle levels can be expanded. Higher grayscale performance can be achieved without increasing the number of signal lines, which balances hardware cost and display quality.

[0100] It is understandable that this solution, by setting up multiple signal lines that transmit emission control signals with different duty cycles, and having the selection module 11 select the corresponding duty cycle signal based on the grayscale range of the pixel, can match appropriate emission duty cycles for pixels of different grayscales within the same row, no longer limited by a uniform duty cycle level for the entire row. Therefore, there is no need to compensate for grayscale adaptation differences by adjusting the data signal, reducing the design complexity of the data signal, and making the emission duration of each pixel more closely match its own grayscale requirements, effectively improving grayscale display accuracy and enhancing display quality.

[0101] In some embodiments, to better understand the pixel driving circuit 10 of the present application embodiments, the following embodiments will use the pixel driving circuit 10 as an example, with the number of multiple selection modules 11 in each pixel driving circuit 10 being three. It can be understood that the number of multiple selection modules 11 can also be 4, 5, 7 or 8, etc., and no detailed limitation is made here.

[0102] Furthermore, such as Figure 3 As shown, the selection module 11 includes a storage capacitor 111 and a switching transistor module 112. The storage capacitor 111 is connected to the switching transistor module 112 and the ground terminal respectively. The switching transistor module 112 is connected to the source drive circuit 30 through a corresponding signal line. The switching transistor module 112 is also connected to the gate drive circuit 20 and the drive module 12 respectively.

[0103] Storage capacitor 111 is a voltage holding element in selection module 11. Its core function is to continuously maintain the voltage stability at the control terminal of switching module 112 after data writing is completed, so that selection module 11 maintains the corresponding working state within one frame display cycle without the need for continuous input of control signals. One end of storage capacitor 111 is connected to the control node of switching module 112, and the other end is connected to the ground terminal. It relies on the charge storage effect of the capacitor to keep the voltage value of the control node basically unchanged.

[0104] Optionally, the storage capacitor 111 can adopt various process structures such as metal-insulator-metal capacitor and metal-oxide-semiconductor capacitor. The capacitance value can be matched according to the required voltage holding time, and no specific limitation is made here.

[0105] The switching module 112 is the switching execution unit in the selection module 11, and has the dual functions of data writing and signal on / off control: on the one hand, it can conduct the data writing path under the control of the target scanning signal and write the second data signal output by the source drive circuit 30 into the storage capacitor 111; on the other hand, it can conduct or disconnect the transmission path of the light emission control signal to the drive module 12 under the control of the voltage of the storage capacitor 111.

[0106] The switching module 112 includes at least one semiconductor switching device. Its control terminal receives the target scanning signal output by the gate driving circuit 20, its data input terminal receives the second data signal output by the source driving circuit 30, and its signal transmission terminal is connected to the signal line and the corresponding port of the driving module 12, respectively.

[0107] Optionally, the switching module 112 can be made of various types of field-effect transistors, such as amorphous silicon thin-film transistors, polycrystalline silicon thin-film transistors, and metal oxide thin-film transistors. It can be a single transistor to realize the basic switching function, or multiple transistors can be combined to form a transmission gate structure to further improve the linearity of signal transmission and the blocking capability when turned off. No specific restrictions are imposed here.

[0108] Furthermore, as can be seen from the figure, the switching transistor modules of multiple selection modules in the same column are connected to the source drive circuit through the same data line. These multiple switching transistor modules rely on the target scan signal sent by the gate drive circuit in a time-division manner to write the corresponding level to the storage capacitor of different selection modules in a time-division manner. Only one set of selection module data is written in the same timing sequence, there is no signal crosstalk, no need to add multiple columns of data lines, and the panel wiring is simplified.

[0109] In some embodiments, the controller module can also be configured to: control the gate drive circuit 20 to send a target scan signal to the switch module 112; when the switch module 112 receives the target scan signal, it transmits the corresponding second data signal sent by the source drive circuit 30 to the storage capacitor 111, and transmits the light emission control signal to the drive module 12 according to the voltage of the storage capacitor 111 being in a first working state, or blocks the transmission of the light emission control signal to the drive module 12 according to the voltage of the storage capacitor 111 being in a second working state.

[0110] In this embodiment, the specific working process can be divided into two stages: the data writing stage and the light emission control stage. First, during the data writing phase, the control module controls the gate drive circuit 20 to output a valid target scan signal to the switch modules 112 of the target row, causing all switch modules 112 in that row to enter the conducting state. Simultaneously, the control module controls the source drive circuit 30 to output a second data signal of the corresponding level to the corresponding selection modules 11 of each column via data lines. The conducting switch modules 112 transmit the second data signal to the upper plate of the storage capacitor 111, charging or discharging the storage capacitor 111 to maintain the voltage across the storage capacitor 111 at the same level as the second data signal. After the data writing for that row is complete, the gate drive circuit 20 removes the target scan signal for that row, and the data writing path of the switch modules 112 is cut off. The storage capacitor 111 maintains a constant voltage across its terminals due to its own charge retention capability, ensuring the stable operation of the selection modules 11 during subsequent light emission phases.

[0111] During the light emission control phase, the source drive circuit 30 continuously outputs light emission control signals with corresponding duty cycles through each signal line. If the voltage maintained on the storage capacitor 111 is at an effective on level, the switching module 112 is in the first operating state, the transmission path of the light emission control signal is open, and the light emission control signal on the corresponding signal line can be transmitted to the driving module 12 at the back end through the switching module 112 to participate in the light emission timing control of the driving module 12; if the voltage maintained on the storage capacitor 111 is at an invalid off level, the switching module 112 is in the second operating state, the transmission path of the light emission control signal is blocked, the light emission control signal on the corresponding signal line cannot be transmitted to the driving module 12, and does not participate in the light emission control of the current pixel.

[0112] In this embodiment, the second data signal is written row by row through the gate driving circuit 20. With the voltage holding characteristics of the storage capacitor 111 and the on / off control of the switching transistor module 112, the independent configuration of the working state of each selection module 11 can be achieved with a simple circuit structure. Only data line resources are occupied during the data writing stage, and no continuous input control signal is required during the light emission stage, which greatly reduces the real-time calculation and output load of the source driving circuit 30. At the same time, the voltage holding capability of the storage capacitor 111 can ensure the stable working state of the selection module 11 within one frame cycle, effectively avoiding signal jumps and brightness flicker during the light emission process, and improving the uniformity and stability of the display screen.

[0113] In some embodiments, such as Figure 4 As shown, the switching module 112 includes a write switching transistor 113 and a transmission switching transistor 114; The write switch is connected to the storage capacitor 111, the source drive circuit 30, and the gate drive circuit 20, respectively. The transmission switch is connected to the source drive circuit 30 through the corresponding signal line. The transmission switch is also connected to the storage capacitor 111 and the drive module 12, respectively.

[0114] The write switch is a path switching device during the data writing stage. Under the control of the target scan signal, it can turn on or off the writing path of the second data signal to the storage capacitor 111. The control terminal of the write switch is connected to the gate drive circuit 20 to receive the target scan signal; the input terminal is connected to the data line of the source drive circuit 30 to receive the second data signal; and the output terminal is connected to the upper plate of the storage capacitor 111 to write a voltage of the corresponding level to the storage capacitor 111.

[0115] Optionally, the write switch can be a field-effect device such as a P-type polysilicon thin-film transistor or a P-type metal-oxide thin-film transistor, or it can be an N-type thin-film transistor of the same process. No specific restrictions are imposed here.

[0116] In some embodiments, in addition to various thin-film transistors, other switching devices may be selected as the write switching transistor. For example, junction field-effect transistors, insulated-gate field-effect transistors, CMOS transmission gates, bidirectional analog switches, Schottky diode switching devices, etc., are not specifically limited here.

[0117] In another alternative implementation, the gate drive circuit performs time-division level control on the row scan lines. During the row selection period, the gate drive circuit outputs a valid scan level and turns on the write switch; during the data writing period, the gate drive circuit configures the level of the row scan line to the voltage level of the corresponding grayscale range, which is directly used as the second data signal and written to the storage capacitor via the turned-on write switch. At this time, the second data signal is directly generated by the gate drive circuit and transmitted through the row scan lines. The source drive circuit no longer needs to send the second data signal to the selection module, and is only responsible for outputting the first data signal used to adjust the drive current.

[0118] It is understandable that by time-division multiplexing the scan pulse and data level onto the row scan line, the scan control and the second data signal are multiplexed onto the same row line, eliminating the need for multiple column data control lines, simplifying array wiring, and reducing the number of output channels of the source driver chip. The second data level is synchronously written to the entire row of pixels, and each row is time-division multiplexed to ensure that the on / off state of the selection module in each row is latched uniformly, reducing crosstalk between column line signals.

[0119] The transmission switch is a path switching device in the light-emitting control stage. It can turn on or off the transmission path of the light-emitting control signal to the driving module 12 according to the voltage held by the storage capacitor 111. The control terminal of the transmission switch is connected to the upper plate of the storage capacitor 111, and its on / off state is directly controlled by the holding voltage of the storage capacitor 111; the input terminal is connected to the corresponding signal line to receive the light-emitting control signal output by the source driving circuit 30; the output terminal is connected to the corresponding control port of the driving module 12 to transmit the light-emitting control signal to the driving module 12.

[0120] Optionally, the device type of the transmission switch can be consistent with that of the write switch, using a P-type or N-type thin-film transistor with the same manufacturing process to unify the fabrication process and reduce process complexity; alternatively, devices with different size parameters can be selected according to signal transmission requirements, without specific restrictions.

[0121] In some embodiments, the control module can be configured as follows: The control gate drive circuit 20 sends a target scan signal to the switching transistor module 112. When the switching transistor module 112 receives the target scan signal, it is in an on state, transmitting the data signal on the data line to the storage capacitor 111. The transmission switch is in the on state according to the voltage of the storage capacitor 111, so as to transmit the light emission control signal on the corresponding signal line from the selection module 11 to the driving module 12; or, the transmission switch is in the off state according to the voltage of the storage capacitor 111, so as to block the transmission of the light emission control signal on the corresponding signal line to the driving module 12.

[0122] For example, the specific working process can be divided into a data writing stage and a light emission control stage. The two stages are executed in separate time periods and do not interfere with each other.

[0123] During the data writing phase, the control module controls the gate drive circuit 20 to output a valid target scan signal to the write switch transistor of the target row, causing the write switch transistors in all selection modules 11 of that row to be synchronously turned on. Simultaneously, the control module controls the source drive circuit 30 to output a second data signal of the corresponding level to the corresponding selection module 11 of each column via the data line; the write switch transistor in the on state transmits the second data signal to the upper plate of the storage capacitor 111, charging or discharging the storage capacitor 111, ensuring that the voltage across the storage capacitor 111 is consistent with the level of the second data signal. After the data writing for that row is completed, the gate drive circuit 20 cancels the target scan signal for that row, and the write switch transistor is turned off, disconnecting the data writing path; the storage capacitor 111 maintains a constant voltage across its terminals due to its own charge retention capability, providing a stable control voltage for the subsequent transmission switch transistors.

[0124] During the light emission control phase, the write switch remains off, and the voltage on the storage capacitor 111 continuously acts on the control terminal of the transmission switch. If the voltage maintained by the storage capacitor 111 is at the effective on-state of the transmission switch, the transmission switch is in the on-state, and the corresponding selection module 11 is in the first working state. The light emission control signal on the signal line can be transmitted to the driver module 12 through the transmission switch to participate in the light emission timing control of the driver module 12. If the voltage maintained by the storage capacitor 111 is at the ineffective off-state of the transmission switch, the transmission switch is in the off-state, and the corresponding selection module 11 is in the second working state. The transmission path of the light emission control signal is blocked and cannot be transmitted to the driver module 12.

[0125] In this embodiment, the functions of data writing and signal switching are separated and implemented by the write switch and the transmission switch, respectively. This avoids mutual interference between the data writing process and the light emission control process, improving the stability of circuit operation. Simultaneously, by maintaining the voltage through the storage capacitor 111 to control the operating state of the transmission switch, the on / off state of the light emission control signal can be continuously maintained after the scanning signal ends, ensuring the stability of the pixel light emission process and improving the accuracy of grayscale display.

[0126] In some embodiments, further as Figure 4 As shown, the driving module 12 includes a writing module 121 and a light-emitting control module 122. The writing module 121 is connected to the light-emitting control module 122, the gate driving circuit 20, the source driving circuit 30 and the ground terminal respectively. The light-emitting control module 122 is connected to multiple selection modules 11, pixel light-emitting elements 13, power supply voltage 14 and the gate driving circuit 20 respectively. The light-emitting control module 122 includes a driving transistor 55 and a first capacitor.

[0127] The writing module 121 is a data writing path switching device for the driving module 12. Under the control of the first scan signal, it can turn on or off the writing path of the first data signal to the first capacitor to complete the grayscale data storage operation.

[0128] The control terminal of the writing module 121 is connected to the gate driving circuit 20 to receive the first scan signal; the data terminal is connected to the first capacitor control terminal of the light emission control module 122 to transmit the voltage of the first data signal; and the reference terminal is connected to the ground terminal to provide a potential reference for data writing.

[0129] Optionally, the writing module 121 may employ semiconductor switching devices such as thin-film transistors, for example, amorphous silicon thin-film transistors, polycrystalline silicon thin-film transistors, metal oxide thin-film transistors, etc., without specific limitations.

[0130] The light-emitting control module 122 is the core unit of the driving module 12, responsible for data retention, current generation, and light-emitting path control. The light-emitting control module 122 is connected to multiple selection modules 11, pixel light-emitting elements 13, power supply voltage 14, and gate driving circuit 20. It receives light-emitting control signals transmitted from the selection modules 11 to control the on / off state of the light-emitting path, connects to the power supply voltage 14 to provide energy for the driving current, receives auxiliary control signals output from the gate driving circuit 20 to cooperate in completing operations such as data writing or potential reset, and finally outputs driving current to the pixel light-emitting element 13. The light-emitting control module 122 includes a driving transistor 55 and a first capacitor, which work together to complete the core functions of data retention and driving current generation.

[0131] The first capacitor is a voltage storage element in the light-emitting control module 122. After the data is written, it continuously maintains the voltage stability of the control terminal of the driving transistor 55, so that the driving transistor 55 remains in a stable conducting state within one frame display cycle and outputs a driving current with a stable amplitude. One end of the first capacitor is the control terminal, which is connected together with the output terminal of the writing module 121 and the control terminal of the driving transistor 55; the other end can be connected to the ground terminal or a fixed potential terminal, relying on the charge storage effect of the capacitor to keep the voltage of the control terminal basically unchanged.

[0132] Optionally, the first capacitor can adopt various process structures such as metal-insulator-metal capacitor and gate parasitic capacitor. The capacitance value can be matched and designed according to the required voltage holding time, and no specific restrictions are imposed here.

[0133] The driving transistor 55 is the device for generating and outputting the driving current, and is the core of the current-type pixel drive. The magnitude of its output driving current is determined by the difference between the control terminal voltage and the power supply voltage 14. The control terminal of the driving transistor 55 is connected to the control terminal of the first capacitor, and its conduction level is controlled by the voltage stored in the first capacitor. The first terminal is connected to the power supply voltage 14, and the second terminal is connected to the light-emitting path and finally to the pixel light-emitting element 13. When the driving transistor 55 operates in the saturation region, the output current corresponds to the gate-source voltage, and it can accurately convert the voltage corresponding to the first data signal into a current output.

[0134] Optionally, the driving transistor 55 can be a P-type or N-type thin-film transistor, which can be flexibly selected according to the system power supply polarity and manufacturing process, and no specific restrictions are imposed here.

[0135] Upon receiving a light emission control signal, the driving module 12 generates a driving current based on a first data signal and sends the driving current to the pixel light-emitting element 13. Specifically, the controlled module is configured as follows: The control gate drive circuit 20 sends a first scan signal to the write module 121. When the write module 121 receives the first scan signal, it is in the conducting state and transmits the voltage of the stored first data signal to the control terminal of the first capacitor through the write module 121. When the light emission control module 122 receives the light emission control signal through multiple selection modules 11, it is in the conducting state. The driving transistor 55 in the light emission control module 122 in the conducting state generates a driving current according to the voltage of the first data signal stored at the control terminal of the first capacitor and the power supply voltage 14, and transmits the driving current to the pixel light emission element 13.

[0136] In this embodiment, the complete working process of the driving module 12 can be divided into a data writing stage and a light output stage. The two stages are executed in a time-sharing manner and do not interfere with each other.

[0137] First, during the data writing phase, the control module controls the gate drive circuit 20 to output a valid first scan signal to the writing module 121 of the target row, causing all writing modules 121 in that row to synchronously enter the conduction state. Simultaneously, the control module controls the source drive circuit 30 to output a first data signal of corresponding amplitude to the corresponding driving module 12 of each column via the data line. The writing module 121 in the conduction state transmits the voltage of the first data signal to the control terminal of the first capacitor, charging or discharging the first capacitor to ensure that the voltage across the first capacitor matches the amplitude of the first data signal, thus completing the storage of grayscale data. After the data writing for that row is completed, the gate drive circuit 20 removes the first scan signal for that row, and the writing module 121 is turned off, disconnecting the data writing path. The first capacitor maintains its voltage by retaining its charge, ensuring that the control terminal voltage of the driving transistor 55 remains stable during subsequent light emission stages.

[0138] Secondly, during the light-emitting output stage, the write module 121 remains off, and the first capacitor continuously maintains a stable voltage at the control terminal of the driver transistor 55. At this time, if the corresponding selection module 11 is in the first operating state, the light-emitting control signal on the signal line is transmitted to the light-emitting control module 122 through the selection module 11, causing the light-emitting current path of the light-emitting control module 122 to be turned on. After the light-emitting path is turned on, the driver transistor 55 is connected to the current loop between the power supply voltage 14 and the pixel light-emitting element 13. The driver transistor 55 generates a corresponding driving current based on the first data signal voltage stored in the first capacitor, combined with the power supply voltage 14, and continuously outputs the driving current to the pixel light-emitting element 13, driving the pixel light-emitting element 13 to emit light. When the light-emitting control signal becomes invalid, the light-emitting path of the light-emitting control module 122 is turned off, the current loop is broken, the driver transistor 55 stops outputting current, and the pixel light-emitting element 13 is turned off.

[0139] Within a single frame display cycle, the actual total light emission duration of the pixel light-emitting element 13 is determined by the duty cycle of the input light emission control signal, and the light emission brightness is determined by the magnitude of the driving current. The two work together to achieve accurate display of the target grayscale value.

[0140] It is understandable that by separating the functions of the writing module 121 and the light-emitting control module 122, mutual interference between the data writing and light-emitting control processes can be avoided, thus improving the stability of circuit operation. The first capacitor continuously stores the voltage of the first data signal, ensuring the stability of the control voltage of the driving transistor 55, making the output driving current more stable. Combined with the light-emitting control signal with the corresponding duty cycle, the light-emitting duration of the pixel light-emitting element 13 can be precisely controlled, effectively ensuring the accuracy of grayscale display.

[0141] In some embodiments, such as Figure 5 As shown, the writing module 121 includes a voltage writing unit 51 and a transmission unit 52; The voltage writing unit 51 is connected to the source driving circuit 30, the gate driving circuit 20, the transmission unit 52 and the ground terminal respectively. The transmission unit 52 is connected to the gate driving circuit 20 and the light emission control module 122 respectively. The voltage writing unit 51 is the first-level data buffer unit in the writing module 121. Under the control of the write signal, it completes the sampling and temporary storage of the first data signal, preparing for the subsequent voltage transmission to the first capacitor. The input terminal of the voltage writing unit 51 is connected to the data line of the source driving circuit 30 to receive the first data signal; the control terminal is connected to the gate driving circuit 20 to receive the write signal; the output terminal is connected to the input terminal of the transmission unit 52; and the reference terminal is connected to the ground terminal to provide a potential reference for voltage storage.

[0142] Optionally, the voltage writing unit 51 can be composed of a thin-film transistor switch and a storage capacitor 111. Data sampling is completed by turning on the switch, and voltage is temporarily stored by the charge retention effect of the capacitor. Alternatively, other active unit structures with charge storage capabilities can be used. The device process can be consistent with other switches in the pixel driving circuit 10, such as amorphous silicon thin-film transistors, polycrystalline silicon thin-film transistors, metal oxide thin-film transistors, etc., without specific limitations.

[0143] The transmission unit 52 is the second-level path switching unit in the write module 121. Under the control of the first scan signal, it turns on or off the voltage transmission path between the voltage writing unit 51 and the first capacitor, and controls the transfer of the first data signal from the cache unit to the final storage unit.

[0144] The control terminal of the transmission unit 52 is connected to the gate driving circuit 20 to receive the first scan signal; the input terminal is connected to the output terminal of the voltage writing unit 51; and the output terminal is connected to the control terminal of the first capacitor in the light emission control module 122.

[0145] Optionally, the transmission unit 52 can use a single thin-film transistor as a switching device to control the on / off state of the source and drain through the gate voltage; or it can use a complementary transmission gate structure to further improve the range and accuracy of voltage transmission; the device type can be the same as the switching transistor in the voltage writing unit 51 using the same process technology to simplify the fabrication process, and no specific restrictions are made here.

[0146] The source drive circuit 30 sends the first data signal to the drive circuit. The drive circuit stores the first data signal upon receiving it. Specifically, the controlled module is configured as follows: The source drive circuit 30 controls the first data signal to be sent to the drive circuit, and the gate drive circuit 20 controls the gate drive circuit 20 to send a write signal to the voltage write unit 51. When the voltage write unit 51 receives the write signal, it is in the on state and stores the first data signal in the voltage write unit 51. The control gate drive circuit 20 sends a first scan signal to the write module 121. Upon receiving the signal, the write module 121 is in an on state and transmits the voltage of the stored first data signal to the first capacitor through the write module 121. Specifically, the controlled module is configured as follows: The control gate drive circuit 20 sends a first scan signal to the transmission unit 52. When the transmission unit 52 receives the first scan signal, it is in the conducting state and transmits the voltage of the first data signal stored in the voltage writing unit 51 to the first capacitor.

[0147] In this embodiment, the data writing stage of the driving module 12 can be further divided into a data pre-writing stage and a data transfer stage. The two stages are executed in a time-sharing manner and do not interfere with each other.

[0148] The first stage is the data pre-writing phase. The control module controls the source drive circuit 30 to output a first data signal of the target amplitude to the data line of the corresponding column, while simultaneously controlling the gate drive circuit 20 to output a valid write signal to the voltage write unit 51 of the target row. When the write signal is valid, the write path inside the voltage write unit 51 is turned on, and the first data signal voltage on the data line is written into the storage element inside the voltage write unit 51, completing the temporary storage of the first data signal. After the pre-writing is completed, the write signal becomes invalid, the write path of the voltage write unit 51 is turned off, and the internally stored first data signal voltage remains stable, awaiting subsequent transfer.

[0149] The control gate drive circuit 20 sends a first scan signal to the write module 121. Upon receiving the signal, the write module 121 is in an on state and transmits the voltage of the stored first data signal to the first capacitor through the write module 121. Specifically, the controlled module is configured as follows: The control gate drive circuit 20 sends a first scan signal to the transmission unit 52. When the transmission unit 52 receives the first scan signal, it is in the conducting state and transmits the voltage of the first data signal stored in the voltage writing unit 51 to the first capacitor.

[0150] Secondly, during the data transfer stage, the control module controls the gate drive circuit 20 to output a valid first scan signal to the transmission unit 52 of the target row. When the first scan signal is valid, the switching path of the transmission unit 52 is turned on, and the first data signal voltage temporarily stored in the voltage writing unit 51 is transmitted to the first capacitor control terminal of the light-emitting control module 122 through the transmission unit 52, charging or discharging the first capacitor to ensure that the voltage across the first capacitor is consistent with the first data signal voltage stored in the voltage writing unit 51, thus completing the final data storage of the drive module 12. After the data transfer is completed, the first scan signal becomes invalid, the transmission unit 52 is turned off, and the first capacitor maintains voltage stability by relying on its own charge retention capability, providing a foundation for the stable operation of the drive transistor 55 in the subsequent light-emitting stage.

[0151] In this embodiment, the time-division control method of first buffering the first data signal by the voltage writing unit 51 and then writing it to the first capacitor by the transmission unit 52 can avoid direct interference with the voltage of the first capacitor during the writing process, ensure that the voltage stored in the first capacitor is accurate and stable, make the driving current output by the driving transistor 55 more precise, and thus improve the accuracy of grayscale display.

[0152] In some embodiments, such as Figure 6 As shown, the voltage writing unit 51 includes a writing transistor 511 and a second capacitor 512; The write transistor 511 is connected to the gate drive circuit 20, the source drive circuit 30 and the second capacitor 512 respectively. The second capacitor 512 is connected to the ground terminal and the transmission unit 52 respectively.

[0153] The write transistor 511 is a path switching device in the voltage writing unit 51. It can control the writing path of the first data signal to the second capacitor 512 according to the write signal, so as to realize the sampling and writing of data. The control terminal of the write transistor 511 is connected to the gate driving circuit 20 to receive the write signal; the input terminal is connected to the data line of the source driving circuit 30 to receive the first data signal; and the output terminal is connected to the upper plate of the second capacitor 512 to transmit the voltage of the first data signal to the second capacitor 512.

[0154] Optionally, the write transistor 511 can be a variety of field-effect devices such as amorphous silicon thin-film transistors, polycrystalline silicon thin-film transistors, and metal oxide thin-film transistors, and can be selected as P-type or N-type conduction type, without specific restrictions.

[0155] The second capacitor 512 is a voltage temporary storage element in the voltage writing unit 51. Its core function is to temporarily maintain the voltage corresponding to the first data signal by relying on the charge storage effect after the writing path is turned off, so as to provide a stable data source for subsequent voltage transmission to the first capacitor. One end of the second capacitor 512 is connected to both the output terminal of the writing transistor 511 and the input terminal of the transmission unit 52, and the other end is connected to the ground terminal to maintain the voltage stability at both ends with the ground potential as a reference.

[0156] Optionally, the second capacitor 512 can adopt various process structures such as metal-insulator-metal capacitor and metal-oxide-semiconductor capacitor. The capacitance value can be matched and designed according to the required voltage holding time, and no specific restrictions are imposed here.

[0157] The source drive circuit 30 controls the first data signal to be sent to the drive circuit, and the gate drive circuit 20 controls the gate drive circuit 20 to send a write signal to the voltage write unit 51. When the voltage write unit 51 receives the write signal, it is in an on state. The voltage write unit 51 in the on state stores the first data signal. Specifically, the controlled module is configured as follows: The control gate drive circuit 20 sends a write signal to the write transistor 511. When the write transistor 511 receives the write signal, it is in the on state and transmits the first data signal to the second capacitor 512. The second capacitor 512 stores the first data signal.

[0158] In this embodiment, the specific working process described above corresponds to the data pre-writing stage: That is, during the data pre-writing stage, the control module controls the source drive circuit 30 to output a first data signal of the target amplitude to the data line of the corresponding column, and simultaneously controls the gate drive circuit 20 to output a valid write signal to the write transistor 511 of the target row. When the write transistor 511 receives the valid write signal, the source and drain of the write transistor 511 are turned on, and the voltage of the first data signal on the data line is transmitted to the upper plate of the second capacitor 512 through the turned-on write transistor 511, charging or discharging the second capacitor 512, so that the voltage across the second capacitor 512 is consistent with the amplitude of the first data signal, thus completing the temporary storage of the first data signal.

[0159] After the data in the first row is pre-written, the gate drive circuit 20 cancels the write signal, the write signal becomes invalid, the source and drain of the write transistor 511 are turned off, and the write path of the first data signal is disconnected. At this time, the second capacitor 512 maintains a constant voltage across its terminals by relying on its own charge retention capability, temporarily storing the voltage of the first data signal in the voltage writing unit 51, waiting for the subsequent transmission unit 52 to be turned on, and then transmitting the temporarily stored voltage to the first capacitor of the light emission control module 122.

[0160] In some embodiments, the pixel driving circuit has a frame data timing difference: the current frame emits light using the voltage of the first data signal pre-stored in the second capacitor in the previous frame, and the current frame emits light synchronously line by line, writing the first signal data of the next frame to the second capacitor.

[0161] It is understandable that writing data and the light emission process are completely parallel, which can significantly improve the maximum refresh rate of the display panel and reduce the instantaneous bandwidth load of the source drive circuit; in addition, the capacitor has no continuous discharge path, and the single frame delay will not produce visible ghosting or grayscale shift.

[0162] It is understandable that using the second capacitor 512 to independently store the first data signal can stably maintain the corresponding voltage and reduce the deviation caused by signal fluctuations; at the same time, by independently controlling the data writing process through the write transistor 511, reliable data caching can be achieved, ensuring that the voltage subsequently transmitted to the first capacitor is accurate and stable, which helps to improve the control accuracy of the drive current and ensure the accuracy of grayscale display.

[0163] In some embodiments, further as Figure 6 As shown, the transmission unit 52 includes a first transmission transistor 521 and a second transmission transistor 522. The first transmission transistor 521 is connected to the gate driving circuit 20, the voltage writing unit 51, and the driving transistor 55, respectively. The second transmission transistor 522 is connected to the gate driving circuit 20, the control terminal of the first capacitor, and the driving transistor 55, respectively.

[0164] Both the first transmission transistor 521 and the second transmission transistor 522 are switching control devices within the transmission unit 52. They are synchronously controlled by the first scan signal, turning on or off together to achieve voltage transmission with threshold compensation. The control terminal of the first transmission transistor 521 is connected to the gate driving circuit 20 to receive the first scan signal; its input terminal is connected to the output terminal of the voltage writing unit 51 to receive the temporarily stored first data signal voltage; and its output terminal is connected to the first terminal of the driving transistor 55. The control terminal of the second transmission transistor 522 is also connected to the gate driving circuit 20, sharing the same first scan signal as the first transmission transistor 521; its input terminal is connected to the second terminal of the driving transistor 55; and its output terminal is connected to the control terminal of the first capacitor and also connected to the control terminal of the driving transistor 55.

[0165] Optionally, both the first transmission transistor 521 and the second transmission transistor 522 can be field-effect devices such as amorphous silicon thin-film transistors, polycrystalline silicon thin-film transistors, and metal oxide thin-film transistors, and can be selected as P-type or N-type conduction types, without specific restrictions.

[0166] The control gate drive circuit 20 sends a first scan signal to the transmission unit 52. Upon receiving the first scan signal, the transmission unit 52 is in an on state and transmits the voltage of the first data signal stored in the voltage writing unit 51 to the first capacitor. Specifically, the controlled module is configured as follows: The control gate drive circuit 20 sends a first scan signal to the first transfer transistor 521 and the second transfer transistor 522. When the first transfer transistor 521 and the second transfer transistor 522 receive the second scan signal, they are turned on. The first transmission transistor 521 in the on state, the second transmission transistor 522 in the on state, and the driving transistor 55 form a transmission circuit for transmitting the voltage of the first data signal in the voltage writing unit 51 to the control terminal of the first capacitor.

[0167] In this embodiment, the specific working process corresponds to the data transfer stage. During this stage, the control module controls the gate drive circuit 20 to synchronously output a valid first scan signal to the first transfer transistor 521 and the second transfer transistor 522 of the target row. When the first scan signal is valid, the first transfer transistor 521 and the second transfer transistor 522 are simultaneously turned on, and the control terminals of the voltage writing unit 51, the first transfer transistor 521, the drive transistor 55, the second transfer transistor 522, and the first capacitor are sequentially connected, forming a closed transmission loop.

[0168] At this time, the control terminal of the driving transistor 55 is connected to its current terminal through the second transmission transistor 522, and the driving transistor 55 is in a diode-connected state. The first data signal voltage temporarily stored in the voltage writing unit 51 is applied to both ends of the driving transistor 55 through the transmission circuit, and the driving transistor 55 is turned on to charge the first capacitor. When the charging process reaches a stable state, the voltage at the control terminal of the first capacitor is equal to the first data signal voltage plus the threshold voltage of the driving transistor 55, that is, a voltage of the first data signal with threshold compensation is formed and stored in the first capacitor.

[0169] After the voltage of the first data signal is written, the first scan signal becomes invalid, the first transmission transistor 521 and the second transmission transistor 522 are turned off synchronously, and the transmission circuit is disconnected; the first capacitor maintains the voltage stability of the first data signal by relying on its own charge retention capability, and provides a control voltage with threshold compensation for the driving transistor 55 in the subsequent light emission stage.

[0170] It is understandable that the voltage of the first data signal written through the transmission circuit formed by the dual transmission transistors and the driving transistor 55 can compensate for the characteristic deviation of the driving transistor 55, making the voltage stored at the control terminal of the first capacitor more accurate, ensuring that the driving current output by the driving transistor 55 is stable and consistent, and effectively improving the uniformity and accuracy of grayscale display of each pixel.

[0171] In some embodiments, further as Figure 6 As shown, the light emission control module 122 also includes a first light emission control transistor 53 and a second light emission control transistor 54. The first light emission control transistor 53 is connected to the power supply voltage 14, multiple selection modules 11, driving transistor 55 and writing module 121 respectively. The second light emission control transistor 54 is connected to the pixel light emission element 13, driving transistor 55, multiple selection modules 11 and writing module 121 respectively. The driving transistor 55 is also connected to the control terminal of the first capacitor 56.

[0172] The first light-emitting control transistor 53 is an upstream switching device in the light-emitting current path. It can control the connection and disconnection of the power supply voltage 14 to the driving transistor 55 according to the light-emitting control signal, thereby realizing the power supply path control during the light-emitting stage. The control terminal of the first light-emitting control transistor 53 is connected to the output terminals of multiple selection modules 11 to receive the light-emitting control signal transmitted by the selection modules 11; the first terminal is connected to the power supply voltage 14 to provide energy for the driving current; and the second terminal is connected to the first terminal of the driving transistor 55.

[0173] Optionally, the first light-emitting control transistor 53 can be a variety of field-effect devices such as amorphous silicon thin-film transistors, polycrystalline silicon thin-film transistors, and metal oxide thin-film transistors, and can be selected as P-type or N-type conduction type, without specific restrictions.

[0174] The second light-emitting control transistor 54 is a downstream switching device in the light-emitting current path. It is controlled synchronously with the first light-emitting control transistor 53 by the light-emitting control signal, and the two work together to achieve complete on / off control of the light-emitting current path. The control terminal of the second light-emitting control transistor 54 is also connected to the output terminal of multiple selection modules 11, and shares the same light-emitting control signal with the first light-emitting control transistor 53; the first terminal is connected to the second terminal of the driving transistor 55; the second terminal is connected to the pixel light-emitting element 13, and is used to output the driving current to the pixel light-emitting element 13.

[0175] Optionally, the device type and parameters of the second light-emitting control transistor 54 can be consistent with those of the first light-emitting control transistor 53 to ensure that their switching timing is synchronized and their conduction impedance is matched. No specific restrictions are imposed here.

[0176] When the light emission control module 122 receives a light emission control signal through multiple selection modules 11, it is in an on state. In the on state, the driving transistor 55 in the light emission control module 122 generates a driving current based on the voltage of the first data signal stored in the first capacitor, and transmits the driving current to the pixel light emission element 13. Specifically, the controlled module is configured as follows: When the first light-emitting control transistor 53 receives a light-emitting control signal through multiple selection modules 11, it is in the conducting state and transmits the power supply voltage 14 to the driving transistor 55. When the driving transistor 55 receives the power supply voltage 14, it is in the conducting state and generates a driving current based on the voltage of the first data signal stored at the control terminal of the first capacitor and the power supply voltage 14. The driving current is then transmitted to the second light-emitting control transistor 54. When the second light-emitting control transistor 54 receives a light-emitting control signal from the multiple selection modules 11, it is in the conducting state and transmits the received driving current to the pixel light-emitting element 13.

[0177] In this embodiment, the specific operation of the control module corresponds to the light-emitting output stage. During this stage, if the selection module 11 is in the first operating state, the light-emitting control signal is simultaneously transmitted through the selection module 11 to the control terminals of the first light-emitting control transistor 53 and the second light-emitting control transistor 54. When the light-emitting control signal is at an effective level, the first light-emitting control transistor 53 and the second light-emitting control transistor 54 are synchronously turned on, and the power supply voltage 14, the first light-emitting control transistor 53, the driving transistor 55, the second light-emitting control transistor 54, and the pixel light-emitting element 13 are sequentially connected to form a complete light-emitting current loop.

[0178] At this time, the control terminal of the driving transistor 55 is maintained with a stable control voltage by the first capacitor, and the driving transistor 55 operates in the saturation region. Based on the difference between the first data signal voltage stored in the first capacitor and the power supply voltage 14, a corresponding driving current is generated. The driving current flows out from the power supply voltage 14, flows into the driving transistor 55 through the first light-emitting control transistor 53, and is then output from the driving transistor 55 to the second light-emitting control transistor 54. Finally, it is transmitted to the pixel light-emitting element 13 through the second light-emitting control transistor 54, driving the pixel light-emitting element 13 to emit light.

[0179] When the light emission control signal becomes invalid, the first light emission control transistor 53 and the second light emission control transistor 54 are simultaneously turned off, the light emission current loop is disconnected from both upstream and downstream ends, the driving transistor 55 stops outputting current, and the pixel light emission element 13 is turned off. Within one frame display cycle, the actual total light emission time of the pixel light emission element 13 is determined by the duty cycle of the light emission control signal, and the light emission brightness is determined by the magnitude of the driving current. The two work together to achieve accurate display of the target grayscale value.

[0180] It is understandable that using two light-emitting control transistors to control the on / off of the power input and current output paths respectively can more stably control the opening and closing of the light-emitting circuit, reduce the risk of leakage current in the off state, ensure that the actual light-emitting duration of the pixel light-emitting element 13 is accurately matched with the duty cycle of the light-emitting control signal, and effectively improve the accuracy of grayscale display.

[0181] In some embodiments, such as Figure 7 As shown, the light emission control module 122 also includes a compensation unit 15, which is connected to the power supply voltage 14, the reference voltage terminal, the compensation terminal of the first capacitor, the source driving circuit 30, and the gate driving circuit 20.

[0182] The compensation unit 15 is a voltage adjustment unit in the light emission control module 122. It can adjust the voltage of the control terminal of the first capacitor by switching the access potential of the compensation terminal of the first capacitor and using the capacitive coupling principle. On the one hand, it can offset the gate-source voltage fluctuation caused by the source potential jump of the driving transistor 55 during the light emission stage. On the other hand, it can eliminate the influence of the threshold voltage dispersion of the driving transistor 55 on the driving current, and suppress the current deviation caused by the voltage drop of the power supply line, so as to ensure the uniformity of the pixel driving current of the whole screen.

[0183] Optionally, the compensation unit 15 can be composed of multiple thin-film transistor switches. By time-division multiplexing different switches, the reference voltage terminal or the power supply voltage 14 can be connected to the compensation terminal of the first capacitor respectively. The device can be of the type of amorphous silicon thin-film transistor, polycrystalline silicon thin-film transistor, metal oxide thin-film transistor, etc., and no specific limitation is made here.

[0184] The reference voltage terminal is a fixed DC potential port used to provide a reference potential for the compensation terminal of the first capacitor during the compensation preparation phase, thus providing a potential difference basis for subsequent coupling compensation. In this embodiment, the reference voltage is VGH, used to provide a reference potential for the compensation terminal of the first capacitor during the compensation preparation phase, thus providing a potential difference basis for subsequent coupling compensation. VGH is a small-signal DC potential, providing a potential reference only for the capacitor, with no large current flowing through it. Therefore, it is not affected by the voltage drop of the power supply traces, resulting in high potential accuracy and good stability.

[0185] The potential value of the reference voltage terminal can be set according to the amplitude of the power supply voltage 14 and the compensation requirements. It is usually a stable fixed potential and no specific restrictions are imposed here.

[0186] The first capacitor has a two-terminal structure, consisting of a control terminal and a compensation terminal. The control terminal is connected to the control terminal of the driving transistor 55 and is used to store the voltage controlling the conduction level of the driving transistor 55. The compensation terminal is connected to the output terminal of the compensation unit 15 and is used to receive the potential switched by the compensation unit 15. The first capacitor maintains a stable voltage difference across its two terminals by relying on the charge storage effect. When the potential at the compensation terminal changes abruptly, the potential at the control terminal will synchronously shift by an equal amount through the capacitive coupling effect.

[0187] The control module is also configured to: before the light emission control module 122 receives the light emission control signal through multiple selection modules 11, control the source drive circuit 30 to send a first signal to the compensation unit 15, and control the gate drive circuit 20 to send a second scan signal to the compensation unit 15. When the compensation unit 15 receives the first signal and the second scanning signal, it is in the first conduction state and sends the reference voltage to the compensation terminal of the first capacitor. When the light emission control module 122 receives the light emission control signal through multiple selection modules 11, the source drive circuit 30 controls the source to send the target light emission control signal to the compensation unit 15, and the gate drive circuit 20 controls the gate to send the third scan signal to the compensation unit 15. The target light emission control signal is the signal with the largest duty cycle among the multiple light emission control signals. When the compensation unit 15 receives the target light emission control signal and the third scanning signal, it is in the second conduction state and sends the power supply voltage 14 to the compensation terminal of the first capacitor. The voltage stored at the control terminal of the first capacitor reduces the target difference voltage according to the capacitive coupling principle. The target difference voltage is the difference between the power supply voltage 14 and the reference voltage. The driving transistor 55 in the light-emitting control module 122, which is in the conducting state, generates a stable driving current based on the voltage stored at the control terminal of the first capacitor, and transmits the stable driving current to the pixel light-emitting element 13.

[0188] This process is the compensation preparation phase, which occurs after data writing and threshold compensation are completed and before the light emission phase begins. During the preceding threshold compensation phase, the driving transistor is in a diode-connected state, and the control terminal of the first capacitor has completed voltage writing; the stored voltage value is the sum of the first data signal voltage and the driving transistor threshold voltage V. th The sum of these is the control terminal voltage V. A =V Data +V th V Data This is the voltage value corresponding to the first data signal.

[0189] During the compensation preparation phase, the control module controls the gate drive circuit to output a valid second scan signal to the compensation unit, and simultaneously controls the source drive circuit to output a first signal to the compensation unit, causing the compensation unit to enter the first conduction state. The compensation unit in the first conduction state will adjust the reference voltage V... GH Connect the compensation terminal of the first capacitor to stabilize the potential of the compensation terminal of the first capacitor at V. GH At this time, the charge across the first capacitor remains stable, the voltage difference across it remains unchanged, and the voltage at the control terminal remains at V. A =V Data +V th Unaffected by the compensation preparation operation. When the light emission control module receives the light emission control signal through multiple selection modules, the control source drive circuit sends the target light emission control signal to the compensation unit, and the control gate drive circuit sends the third scan signal to the compensation unit. The target light emission control signal is the signal with the largest duty cycle among the multiple light emission control signals. When the compensation unit receives the target light emission control signal and the third scanning signal, it is in the second conduction state and sends the power supply voltage to the compensation terminal of the first capacitor. The voltage stored at the control terminal of the first capacitor generates a corresponding offset according to the capacitive coupling principle. The offset is the difference between the power supply voltage and the reference voltage, i.e., the target difference voltage. In the light-emitting control module, the driving transistor, which is in the conducting state, generates a stable driving current based on the voltage stored at the control terminal of the first capacitor, and transmits this stable driving current to the pixel light-emitting element. This process is the light-emitting compensation stage, which is executed synchronously with the light-emitting output stage. Upon entering the light-emitting stage, the first light-emitting control transistor is turned on, and the source potential of the driving transistor jumps to the power supply voltage V. DD2 If the control terminal potential of the driving transistor remains constant, the gate-source voltage will change with the jump in the source potential. Simultaneously, the voltage drop across the power supply trace will cause the voltage of pixels at different locations to fluctuate. DD2 These differences ultimately lead to deviations in the driving current, affecting the uniformity of brightness across the entire screen.

[0190] To counteract the aforementioned effects, the control module synchronously controls the gate drive circuit to output a valid third scan signal to the compensation unit, while simultaneously controlling the source drive circuit to output a target emission control signal to the compensation unit, causing the compensation unit to enter the second conduction state. The target emission control signal is selected from all emission control signals transmitted through multiple signal lines, choosing the signal with the largest duty cycle. This ensures that, at any emission duty cycle level, the conduction duration of the compensation unit fully covers the emission phase, guaranteeing the continuous effectiveness of the compensation process.

[0191] The compensation unit in the second conduction state will convert the power supply voltage V DD2 Connect the compensation terminal of the first capacitor, so that the potential of the compensation terminal of the first capacitor changes from the reference voltage V. GHThe voltage jumps to the supply voltage V DD2 The magnitude of the potential increase is V DD2 -V GH This refers to the target difference voltage. According to the capacitive coupling principle, the total charge inside the first capacitor remains constant when there is no discharge path; therefore, the voltage difference across the capacitor remains stable. When the compensation terminal potential increases to the target difference voltage, the control terminal potential will simultaneously increase to the target difference voltage. The compensated control terminal voltage is:

[0192] At this time, the source potential of the driving transistor is VDD2, and the gate-source voltage Vgs of the driving transistor is the difference between the control terminal voltage and the source voltage.

[0193] When the driver transistor operates in the saturation region, the output drive current satisfies the following formula:

[0194] in, C represents the carrier mobility. ox The gate oxide capacitance per unit area is given by W / L, where W / L is the width-to-length ratio of the driving transistor, and V is the capacitance per unit area. th This is the threshold voltage for the driving transistor. The gate-source voltage V... gs Substituting into the current formula, we get:

[0195] The derivation shows that the threshold voltage V of the driving transistor is... th These are completely canceled out in the formula, and the drive current is not affected by the discreteness of the threshold voltage of the drive transistor itself; at the same time, the power supply voltage V DD2 It also does not appear in the final current formula, and the voltage drop of the power supply trace will not affect the drive current. Pixels at different positions across the entire screen can output a consistent drive current, significantly improving brightness uniformity. The stable drive current is transmitted to the pixel light-emitting element through the light-emitting control path, making the pixel light emission brightness uniform and accurate, unaffected by device process deviations and power supply voltage drops.

[0196] In this embodiment, by adjusting the voltage at the control terminal of the driving transistor 55 through the time-division conduction control of the compensation unit 15 and the capacitive coupling effect of the first capacitor, the characteristic deviation of the driving transistor 55 can be compensated, making the output driving current more stable. This method can reduce the impact of uneven device characteristics on pixel brightness, improve the uniformity and accuracy of grayscale display of each pixel, and ensure the consistency of display quality.

[0197] Furthermore, such as Figure 7 The compensation unit 15 shown also includes a third light-emitting control transistor 151 and a fourth light-emitting control transistor 152. The third light-emitting control transistor 151 is connected to the power supply voltage 14, the fourth light-emitting control transistor 152, the compensation terminal of the first capacitor, and the gate driving circuit 20, respectively. The fourth light-emitting control transistor 152 is connected to the gate driving circuit 20, the compensation terminal of the first capacitor, and the reference voltage terminal.

[0198] The third light-emitting control transistor 151 is a switching control device for the power supply voltage 14 path in the compensation unit 15. It is turned on during the light-emitting stage, connecting the power supply voltage 14 to the compensation terminal of the first capacitor to complete the capacitive coupling compensation. The control terminal of the third light-emitting control transistor 151 is connected to the source driving circuit 30 and is used to receive the first signal output by the source driving circuit 30 and the target light-emitting control signal; the first terminal is connected to the power supply voltage 14, and the second terminal is connected to the compensation terminal of the first capacitor.

[0199] Optionally, the third light-emitting control transistor 151 can be a variety of field-effect devices such as amorphous silicon thin-film transistors, polycrystalline silicon thin-film transistors, and metal oxide thin-film transistors, and can be selected as P-type or N-type conduction type, without specific restrictions.

[0200] The fourth light-emitting control transistor 152 is the switching control device for the reference voltage path in the compensation unit 15. It is turned on during the preparation stage before light emission, connecting the reference voltage terminal to the compensation terminal of the first capacitor to provide a potential reference for subsequent coupling compensation. The control terminal of the fourth light-emitting control transistor 152 is connected to the gate driving circuit 20 to receive the second and third scan signals output by the gate driving circuit 20; the first terminal is connected to the reference voltage terminal, and the second terminal is connected to the compensation terminal of the first capacitor.

[0201] Optionally, the device type and parameters of the fourth light-emitting control transistor 152 can be consistent with those of the third light-emitting control transistor 151, or can be adjusted according to the requirements of the path load and switching speed, without specific limitations.

[0202] In some embodiments, the control module is further configured to: Before the light emission control module 122 receives the light emission control signal through multiple selection modules 11, the source drive circuit 30 sends a first signal to the third light emission control transistor 151, and the gate drive circuit 20 sends a second scan signal to the fourth light emission control transistor 152. When the third light-emitting control transistor 151 receives the first signal, it is in the off state, and when the fourth light-emitting control transistor receives the second scan signal, it is in the on state, so that the reference voltage is transmitted to the compensation terminal of the first capacitor. When the light emission control module 122 receives the light emission control signal through multiple selection modules 11, it is in the on state and controls the source drive circuit 30 to send the target light emission control signal to the third light emission control transistor 151, and controls the gate drive circuit 20 to send the third scan signal to the fourth light emission control transistor 152. When the third light-emitting control transistor 151 receives the target light-emitting control signal, it is in the on state, and when the fourth light-emitting control transistor receives the second scan signal, it is in the off state, so that the power supply voltage 14 is transmitted to the compensation terminal of the first capacitor.

[0203] In this embodiment, the control program of the aforementioned control module is a compensation preparation stage, which occurs after data writing and threshold compensation are completed and before the light emission stage is started. During this stage, the control module controls the source drive circuit 30 to output a first signal with an invalid level to the third light emission control transistor 151, keeping the third light emission control transistor 151 off and disconnecting the path between the power supply voltage 14 and the first capacitor compensation terminal; at the same time, it controls the gate drive circuit 20 to output a second scan signal with an effective level to the fourth light emission control transistor 152, turning on the fourth light emission control transistor 152 and connecting the path between the reference voltage terminal and the first capacitor compensation terminal.

[0204] The reference voltage is transmitted to the compensation terminal of the first capacitor through the conducting fourth light-emitting control transistor 152, stabilizing the potential of the compensation terminal at the reference voltage. At this time, there is no charging or discharging path across the first capacitor, the total charge remains unchanged, the voltage difference across the two terminals remains stable, and the voltage at the control terminal of the first capacitor maintains the value with threshold compensation completed during the data writing phase, unaffected by the compensation preparation operation.

[0205] When the light emission control module 122 receives the light emission control signal through multiple selection modules 11, the source drive circuit 30 sends the target light emission control signal to the third light emission control transistor 151, and the gate drive circuit 20 sends the third scan signal to the fourth light emission control transistor 152. The third light-emitting control transistor 151 is turned on when it receives the target light-emitting control signal, and the fourth light-emitting control transistor 152 is turned off when it receives the third scanning signal, so that the power supply voltage 14 is transmitted to the compensation terminal of the first capacitor.

[0206] This process is the light emission compensation stage, which is executed synchronously with the light emission output stage. After entering the light emission stage, the light emission current path of the light emission control module 122 is turned on, and the source potential of the driving transistor 55 jumps to the power supply voltage 14. In order to counteract the influence of the source potential jump and the voltage drop of the power supply line on the driving current, the compensation unit 15 synchronously switches the access potential of the compensation terminal.

[0207] The control module controls the source drive circuit 30 to output a target light emission control signal with an effective level to the third light emission control transistor 151, so that the third light emission control transistor 151 is turned on and the path between the power supply voltage 14 and the first capacitor compensation terminal is connected; at the same time, the control module controls the gate drive circuit 20 to output a third scan signal with an invalid level to the fourth light emission control transistor 152, so that the fourth light emission control transistor 152 is turned off and the path between the reference voltage terminal and the compensation terminal is disconnected.

[0208] The power supply voltage 14 is transmitted to the compensation terminal of the first capacitor through the conducting third light-emitting control transistor 151. The potential at the compensation terminal jumps from the reference voltage to the power supply voltage 14, and the potential change is the difference between the power supply voltage 14 and the reference voltage. According to the capacitive coupling principle, the total charge inside the first capacitor remains constant, and the voltage difference across it remains stable. When the potential at the compensation terminal increases, the potential at the control terminal will synchronously generate a corresponding amplitude shift, ultimately keeping the gate-source voltage of the driving transistor 55 stable and unaffected by the source potential jump and the voltage drop of the power supply trace, thus outputting a driving current with a consistent amplitude.

[0209] Among them, the target light emission control signal is selected from all the light emission control signals transmitted by multiple signal lines, which has the largest duty cycle. This ensures that the conduction time of the third light emission control transistor 151 can fully cover the light emission stage under any light emission duty cycle, ensuring that the compensation process is continuously effective and avoiding current fluctuations caused by compensation interruption.

[0210] It is understandable that by switching the voltage at the first capacitor compensation terminal through a time-division multiplexing of two light-emitting control transistors, the timing of capacitive coupling compensation can be precisely controlled, ensuring a stable and reliable compensation process. This structure has a simple and clear control logic, achieving compensation for the characteristic deviation of the 55-speed driver transistor without complex circuitry. This effectively reduces current deviation caused by uneven device characteristics, improving the uniformity and accuracy of pixel grayscale display.

[0211] In some embodiments, further as Figure 7 As shown, each pixel driving circuit 10 also includes a reset circuit 16. The reset circuit 16 is connected to the gate drive circuit 20, the reset voltage terminal, and the drive module 12, respectively. The reset circuit 16 is a charge discharge unit in the pixel driving circuit 10. Before each frame of grayscale data is written, it releases the charge of the previous frame remaining in the storage element in the driving module 12 to the reset voltage terminal, so that the storage node of the driving module 12 is reset to a fixed reference potential, so as to avoid the previous frame data from interfering with the grayscale writing of the current frame and ensuring the accuracy of each frame of data.

[0212] Optionally, the reset circuit 16 can use a thin-film transistor as a switching device. Its control terminal receives the reset signal output by the gate drive circuit 20 and controls the on / off state between the source and drain through the signal level, thereby controlling the conduction and off state of the discharge circuit. The device can be of the type of amorphous silicon thin-film transistor, polycrystalline silicon thin-film transistor, metal oxide thin-film transistor, etc., and no specific restrictions are made here.

[0213] The reset voltage terminal is a fixed DC potential port, used to provide a reference potential for the reset process, so that the storage node of the drive module 12 is reset to the preset initial potential.

[0214] The potential value of the reset voltage terminal can be set according to the device type and operating level range of the drive module 12 to ensure that the storage node can fully discharge residual charge. No specific restrictions are imposed here.

[0215] The control module is also configured as follows: The control gate drive circuit 20 sends a reset signal to the reset circuit 16. When the reset circuit 16 receives the reset signal, it is in the conducting state, so that the reset circuit 16 and the drive module 12 form a discharge circuit to release the stored charge in the drive module 12.

[0216] It is understandable that by releasing the residual charge in the drive module 12 through the reset circuit 16, the voltage deviation left over from the previous working stage can be cleared, the residual charge can be prevented from interfering with the subsequent data writing process, the voltage stored in the drive module 12 can be accurately and stably maintained, the output drive current can be precisely matched with the target grayscale, and the stability and display quality of grayscale display can be improved.

[0217] The reset operation is typically performed before the data writing phase of each frame to provide a uniform initial potential state for the writing of grayscale data in the current frame. The specific working process is as follows: The control module controls the gate drive circuit 20 to output a valid reset signal to the reset circuit 16 of the target row. After receiving the valid reset signal, the reset circuit 16 enters the conducting state. At this time, a closed discharge circuit is formed between the storage node of the drive module 12 and the reset voltage terminal through the conducting reset circuit 16. The charge of the previous frame remaining on the storage elements such as the first capacitor in the drive module 12 flows to the reset voltage terminal through the discharge circuit. The potential of the storage node is gradually pulled to the potential of the reset voltage terminal, completing the reset operation.

[0218] After the reset is completed, the gate drive circuit 20 cancels the reset signal, the reset signal becomes invalid, the reset circuit 16 is turned off, and the discharge circuit is disconnected. The storage node potential of the drive module 12 stabilizes at the reset reference potential, waiting to receive the first data signal of the current frame and enter the data writing stage.

[0219] Furthermore, such as Figure 7As shown, the reset circuit 16 can be a P-type reset transistor 58 and a P-type reset transistor 59. It can be understood that the conduction characteristics of the P-type reset transistor are: when the gate voltage is lower than the source voltage, the source and drain are turned on; when the gate voltage is higher than the source voltage, the source and drain are turned off.

[0220] Taking reset transistor 58 as an example, when the reset signal is low, the gate of reset transistor 58 receives a low level, satisfying the conduction condition. The source and drain are connected, and the storage node of drive module 12 is connected to the reset voltage terminal Vef1. The residual charge from the previous frame on the storage node is discharged to the reset voltage terminal Vef1 through the conducting reset transistor 58. The node potential is pulled to the value of the reset voltage Vef1, completing the node reset. After the reset is complete, the reset signal becomes high, the gate voltage of reset transistor 58 increases, the conduction condition is no longer met, reset transistor 58 is turned off, the discharge circuit is disconnected, the storage node maintains the reset potential, and waits for subsequent data write operations.

[0221] It is understandable that when the reset circuit 16 uses an N-type thin-film transistor, the corresponding effective logic level is reversed, which will not be elaborated here.

[0222] For example, such as Figure 8As shown, multiple selection modules are configured, including a first selection module, a second selection module, and a third selection module. The transistors in the pixel driving circuit are all P-type. Furthermore, the first data signal is set to Data1, the second data signal to Data2, the reset signal to S1, the target scan signal of the first selection module to S1, the target scan signal of the second selection module to S2, the target scan signal of the third selection module to S3, the first signal to S4, the light emission control signal of the first selection module to EM1 (the signal with the smallest duty cycle), the light emission control signal of the second selection module to EM2 (the duty cycle of EM2 is greater than that of EM1), and the light emission control signal of the third selection module to EM3 (the duty cycle of EM3 is greater than that of EM2). The reset circuit includes a first reset transistor T1 and a second reset transistor T2. The circuit consists of transistor T8, a first reset transistor T1 with reset voltage Vref1, a second reset transistor T8 with reset voltage Vref2, a first selection module with storage capacitor C3, a write switch transistor T10, a transmission switch transistor T9, a second selection module with storage capacitor C4, a write switch transistor T12, a transmission switch transistor T11, a third selection module with storage capacitor C5, a write switch transistor T14, a transmission switch transistor T13, a write transistor set to T5, a second capacitor C2, a first transmission transistor T4, a second transmission transistor T3, a driver transistor T2, a first light-emitting control transistor set to T6, a second light-emitting control transistor set to T7, a third light-emitting control transistor T16, a fourth light-emitting control transistor T15, a reference voltage VGH, a power supply voltage VDD, a ground terminal VSS, and a write signal set to Gn. For a clearer understanding of the above, combined with... Figure 9 The timing diagram is explained as follows.

[0223] For example, such as Figure 8As shown, multiple selection modules are configured, including a first selection module, a second selection module, and a third selection module. The first data signal is set as Data1, the second data signal is set as Data2, the reset signal is set as S1, the target scan signal of the first selection module is set as S1, the target scan signal of the second selection module is set as S2, the first scan signal of the first transmission transistor and the second transmission transistor is set as S2, the target scan signal of the third selection module is set as S3, the first signal is set as S4, the light emission control signal of the first selection module is EM1, which is the signal with the smallest duty cycle, the light emission control signal of the second selection module is EM2, the duty cycle of the EM2 signal is greater than that of the EM1 signal, and the light emission control signal of the third selection module is EM3, the duty cycle of the EM3 signal is greater than that of the EM2 signal. The reset circuit is further configured with a first reset transistor T1 and a second reset transistor T8. The reset voltage terminal of the first reset transistor T1 is Vref1, and the reset voltage terminal of the second reset transistor T8 is Vref2. The storage capacitor of the first selection module is C3, the write switch is T10, and the transmission switch is T9. The storage capacitor of the second selection module is C4, the write switch is T12, and the transmission switch is T11. The storage capacitor of the third selection module is C5, the write switch is T14, and the transmission switch is T13. The write transistor is set to T5, the second capacitor is C2, and the first transmission transistor... The first selection module is set to T4, the second transmission transistor to T3, and the driving transistor to T2; the first light-emitting control transistor is set to T6, the second light-emitting control transistor to T7, the third light-emitting control transistor to T16, and the fourth light-emitting control transistor to T15; the reference voltage is VGH, the power supply voltage is VDD, the ground terminal is VSS, and the write signal is set to Gn. It can be understood that the settings of the target scan signal and the reset signal of the first selection module can be different, and no specific restrictions are made here. The settings of the first scan signal of the first transmission transistor and the second transmission transistor can be different from the target scan signal of the second selection module.

[0224] To better understand the above content, in conjunction with Figure 8 The timing diagram below explains the current control flow of this scheme. A complete working cycle of this scheme can be divided into four stages: node reset and first selection module data writing stage, driver transistor threshold compensation and first data writing and second selection module data writing stage, third selection module data writing stage, and light emission stage. The specific control process of each stage is as follows: The first stage is the node reset and first selection module data writing stage, which corresponds to stage (1) in the timing diagram: This stage marks the beginning of a frame's working cycle and involves two main tasks: first, resetting the storage nodes of the driving module to eliminate the influence of residual charge from the previous frame; and second, writing a second data signal to the first selection module to configure its on / off state.

[0225] Its control logic is as follows: When the S4 signal becomes low, it is active low. S4 is connected to the control terminal of the fourth light-emitting control transistor T15. When S4 is active, T15 is turned on, connecting the reference voltage VGH to the compensation terminal of the first capacitor C1, stabilizing the potential of the C1 compensation terminal at VGH, thus preparing for capacitive coupling compensation in the subsequent light-emitting stage. VGH is a small-signal DC potential, providing only a potential reference for the capacitor, with no large current flowing through it. Therefore, it is not affected by the voltage drop of the power supply traces, resulting in high potential accuracy.

[0226] The S1 signal outputs the first low-level pulse: S1 is a reset signal, simultaneously connected to the control terminals of the first reset transistor T1 and the second reset transistor T8. When S1 is active, T1 and T8 are synchronously turned on. After T1 is turned on, the reset voltage terminal Vref1 is connected to the gate node of the driving transistor T2 through T1, which charges the control terminal of the first capacitor C1, causing the potential of node A to be pulled to Vref1, and the driving transistor T2 is in the conducting state, thus completing the node reset of the driving module. After T8 is turned on, the reset voltage terminal Vref2 is connected to the corresponding node through T8 to complete the potential reset of the relevant storage node.

[0227] First selection module data writing: S1 is simultaneously multiplexed as the target scan signal for the first selection module and connected to the control terminal of the write switch T10. When S1 is active, T10 is turned on, and the second data signal Data2, corresponding to the first selection module, output on the data line Data, is written into the storage capacitor C3 through T10, writing the D1 voltage at point C. After the data writing is complete, S1 returns to a high level, T10 is turned off, and the storage capacitor C3 maintains the D1 voltage unchanged due to the charge retention effect. The transmission switch T9 is controlled by the voltage of C3: if D1 is active, T9 is turned on, and the corresponding EM1 signal can be transmitted to the driver module; if D1 is inactive, T9 is turned off, and the EM1 signal is blocked.

[0228] Secondly, there is the stage of driver threshold compensation and first data writing and second selection module data writing, which corresponds to stage (2) in the timing diagram: This stage primarily accomplishes two tasks: first, it writes the first data signal Data1 to the drive module and completes threshold voltage compensation for the drive transistor T2, enabling the first capacitor to store the compensated control voltage; second, it writes the second data signal to the second selection module and configures the on / off state of the second selection module.

[0229] Its control logic is as follows: When the S2 signal outputs a low-level pulse, S2 is simultaneously connected to the control terminal of the first transmission transistor T4, the second transmission transistor T3, and the second selection module write switch T12. When S2 is active, T3, T4, and T12 are synchronously turned on.

[0230] After transistors T3 and T4 are turned on, the control terminals of the second capacitor C2, T4, driving transistors T2 and T3, and the first capacitor C1 are sequentially connected, forming a closed compensation circuit. At this time, driving transistor T2 is in a diode-connected state. The potential at point B, written according to the first data signal Data1 in the previous frame and stored on the second capacitor C2, charges the first capacitor C1 through T4, T2, and T3 until the potential at node A satisfies V. A =V B +V th V B V is the data voltage stored in the second capacitor. th This is the threshold voltage for driving transistor T2. Once this potential is reached, driving transistor T2 completes the threshold compensation process.

[0231] After compensation is completed, the control terminal of the first capacitor C1 stores the voltage of the first data signal containing the threshold voltage of the driving tube, laying the foundation for the output of a stable current in the subsequent light-emitting stage.

[0232] Simultaneously, due to the low-level pulse output of the S2 signal, after T12 is turned on, the second data signal Data2, corresponding to the second selection module, is written into the storage capacitor C4 through T12, and the voltage D2 is written at point D. After the writing is completed, S2 returns to a high level, T12 is turned off, C4 maintains the voltage D2 unchanged, controlling the on / off state of the transmission switch T11, and thus determining whether the EM2 signal is connected to the driver module.

[0233] Next is the module data writing stage, which corresponds to stage (3) in the timing diagram: This stage primarily involves writing the second data signal to the third selection module and configuring its on / off state. Once all three selection modules have been written, the path selection for each light-emitting control signal is complete.

[0234] Its control logic is as follows: S3 outputs a low-level pulse: S3 is the target scan signal of the third selection module, which is connected to the control terminal of the switch T14. When S3 is valid, T14 is turned on.

[0235] The third selection module data writing refers to the second data signal Data2, output from the data line Data, corresponding to the third selection module, being written into the storage capacitor C5 via T14, and the voltage D3 is written at point E. After the writing is completed, S3 returns to a high level, T14 is turned off, C5 keeps the voltage D3 unchanged, controlling the on / off state of the transmission switch T13, and thus determining whether the EM3 signal is connected to the driver module.

[0236] After all three selection modules have been written, the on / off states of each selection module have been configured, and the corresponding duty cycle light emission control signal path has been selected, awaiting the effect of the subsequent light emission stage.

[0237] Finally, there is the emission stage, which corresponds to stage (4) in the time sequence diagram, and corresponds to the effective periods of EM1, EM2, and EM3 in sequence: This stage is the pixel emission stage. Three emission control signals with different duty cycles are effective in sequence. They are connected to the driving module through the selected path of the selection module. With the coupling compensation mechanism of the first capacitor, the driving tube outputs a stable driving current, driving the pixel emission element to emit light according to the target grayscale.

[0238] Its control logic is that the S4 signal becomes invalid when it goes high: before the light emission stage begins, the S4 signal returns to a high level, the fourth light emission control transistor T15 is turned off, and the path between the reference voltage VGH and the compensation terminal of the first capacitor C1 is disconnected.

[0239] The light emission control signals are activated sequentially, and the light emission path is turned on: If the corresponding selection module is configured to be in the on state, the light emission control signal is transmitted to the light emission control module through the transmission switch of the selection module, and is simultaneously connected to the control terminals of the first light emission control transistor T6, the second light emission control transistor T7, and the third light emission control transistor T16.

[0240] T6 and T7 are turned on synchronously, and the power supply voltage VDD, T6, driving transistors T2 and T7, and pixel light-emitting elements are connected in sequence to form a complete light-emitting current loop.

[0241] At the same time, T16 is turned on, and the power supply voltage VDD is connected to the compensation terminal of the first capacitor C1 through T16, and the potential of the compensation terminal jumps from VGH to VDD.

[0242] Regarding the capacitive coupling compensation and stable current output of the compensation unit, according to the capacitive coupling principle, the total charge inside the first capacitor C1 remains constant when there is no discharge path, thus maintaining a stable voltage difference across the capacitor. When the compensation terminal potential rises from VGH to VDD, the potential change is VDD-VGH, and the control terminal potential will rise synchronously by the corresponding amplitude.

[0243] The potential of node A before compensation is V A =V B +V th After compensation, the potential at node A becomes V. A' =V B +Vth+VDD-VGH.

[0244] At this time, the source potential of the driving transistor T2 is VDD, and the gate-source voltage is V gs =VA' -VDD=(V B +V th +VDD-VGH)-VDD=V B +V th -VGH.

[0245] At this time, the threshold voltage V of the driving transistor T2 th The effects are completely canceled out in the formula, and the driving current is not affected by the threshold voltage dispersion of the driving transistor itself; at the same time, the power supply voltage VDD does not appear in the final current formula, and the voltage drop of the power supply trace will not affect the driving current. Pixels at different positions on the entire screen can output a consistent driving current, and the brightness uniformity is significantly improved.

[0246] like Figure 9 The timing diagram shows that the three emission duty cycles operate sequentially. During the effective period of the EM1 signal, short-duration emission corresponds to the low grayscale range, and the duration of the driving current is determined by the duty cycle of EM1, suitable for fine display of low grayscale images. During the effective period of the EM2 signal, medium-duration emission corresponds to the medium grayscale range, and the duration of the driving current is determined by the duty cycle of EM2, suitable for smooth transition of medium grayscale images. During the effective period of the EM3 signal, long-duration emission corresponds to the high grayscale range, and the duration of the driving current is determined by the duty cycle of EM3, suitable for high-brightness display of high grayscale images. Among them, EM3 is the emission control signal with the largest duty cycle, and it also drives the third emission control transistor T16 as the target emission control signal. This ensures that the compensation process can completely cover the emission stage under any emission duty cycle, ensuring that the compensation is continuously effective. After the emission stage ends, the S1 signal outputs a reset pulse again, entering the reset stage of the next frame and starting a new working cycle.

[0247] It is understood that this application directly connects the third light-emitting control transistor T16 to the global target light-emitting control signal EM3 with the longest duty cycle. The effective range of EM3 completely includes the entire light-emitting period of EM1 and EM2. For scenarios where only EM1 or EM2 is selected for low and medium gray pixels: When EM3 is turned on in advance, it only completes the potential jump at the compensation terminal of the first capacitor in advance. There is no current loop during the non-conducting stages of the light-emitting path T6 and T7, and the capacitor has no charge discharge, which will not change the storage voltage at the control terminal of the first capacitor. When EM1 or EM2 is active and the light-emitting path is open, the compensation terminal of C1 is stable at VDD, the coupling offset is fixed, and the driving current formula completely cancels out VDD and V th Advancing the timing sequence does not affect brightness accuracy; If EM1 or EM2 is turned off prematurely, the light-emitting circuit is completely shut off, and C1 has no charging or discharging path. Even if T16 continues to conduct, the compensation terminal potential will not cause the control terminal to drift. The potential will be reset only when the next frame is reset.

[0248] As an alternative embodiment, the T16 gate can be reconnected to the output of the corresponding selection module to make the compensation and light emission completely synchronized, adapting to low duty cycle and extremely low grayscale scenarios.

[0249] In this embodiment, Gn is a write signal, connected to the control terminal of the write transistor T5, which can control the writing of the first data signal to the second capacitor C2. Figure 9 In the timing diagram, multiple pulses such as G1, G2, and G3 correspond to the write pulses of different rows of pixels in the display panel. The first data signal of the corresponding gray level is written to the second capacitor of each row of pixels in turn by scanning row by row, which is the pre-stored data voltage for threshold compensation and light emission driving of the next frame.

[0250] Its specific control logic is as follows: G1 pulse (first row write): G1 is the write pulse for the first row of pixels. When G1 is valid, the write transistor T5 for the first row of pixels is turned on. The first data signal Data1, which corresponds to the gray level of the first row of pixels, is output on the data line Data and written into the second capacitor C2 of the row through T5. The corresponding data voltage is temporarily stored at point B.

[0251] After the write operation is complete, G1 becomes invalid, T5 is turned off, and the second capacitor C2 maintains stable data voltage by relying on charge retention effect, waiting for the threshold compensation stage of the next frame to be used.

[0252] G2 pulse (second row write): G2 is the write pulse for the second row of pixels. When G2 is active, the write transistor T5 for the second row of pixels is turned on, and the first data signal corresponding to the grayscale of the second row of pixels output on the data line Data is written into the second capacitor C2 of that row.

[0253] After the write operation is complete, G2 becomes invalid, T5 is turned off, and the second capacitor temporarily stores the data voltage.

[0254] G3 pulse and subsequent pulses (writing the third row and subsequent rows): G3 and subsequent pulses correspond to the write pulses of the third row and subsequent rows of pixels in sequence. Following the order of scanning row by row, the first data signal of the corresponding gray level is written to the second capacitor of each row of pixels in sequence until all rows of the screen are written.

[0255] Furthermore, the timing diagram shows that pulse G1 occurs before the EM1 emission signal is active, pulse G2 occurs during the active period of EM1, pulse G3 occurs during the active period of EM2, and so on. This indicates that the line-by-line writing process of the first data signal and the emission stage are executed in parallel: while the emission stage of the current frame is underway, the write signal Gn writes the first data signal required for the next frame to the second capacitor of each row of pixels line by line, realizing time multiplexing of data pre-writing and emission display. This effectively shortens the total duration of a single frame and reserves timing margin for high refresh rate displays.

[0256] After the writing is completed, the data voltage stored in the second capacitor C2 will be transferred to the first capacitor C1 through the first transmission transistor T4 and the second transmission transistor T3 during the threshold compensation stage of the next frame, and the threshold voltage of the driving transistor will be superimposed to complete the compensation, which will ultimately be used to control the magnitude of the driving current in the light emission stage of the next frame.

[0257] Based on the aforementioned display panel, this application embodiment also provides a display device, such as... Figure 11 As shown, the display device includes a display panel as described above and a processor.

[0258] Based on the aforementioned display panel and display device, this application also provides a schematic flowchart of another control method, such as... Figure 10 As shown, the flowchart includes the following steps.

[0259] Step S201: Upon receiving image data, generate a target signal from the gray value range of each pixel in the image data, and send the target signal to the display panel.

[0260] Different grayscale value ranges correspond to different target signals; In some embodiments, this step is performed by a control module. During the operation of the display panel, the control module continuously receives externally input image data. The image data includes grayscale information corresponding to all pixels on the display panel, where each pixel corresponds to an independent grayscale value. The grayscale value is used to characterize the brightness level that the pixel needs to present. The higher the grayscale value, the higher the brightness of the pixel; the lower the grayscale value, the lower the brightness of the pixel.

[0261] The grayscale value range is a pre-defined grayscale division range set by the control module. The control module divides the total range of pixel grayscale into multiple continuous grayscale value ranges, each corresponding to a specific combination of light emission control signals. Pixels within different grayscale value ranges are driven by light emission control signals with different duty cycles, in conjunction with corresponding drive current amplitudes, to achieve accurate display of the target grayscale.

[0262] After receiving image data, the control module analyzes and determines the grayscale value of each pixel, identifying the grayscale range to which the grayscale value belongs. Based on the control parameters corresponding to that range, it generates a corresponding target signal for each pixel. Different grayscale ranges correspond to different target signals. Each target signal carries a first data signal amplitude parameter corresponding to the pixel, as well as level parameters for multiple second data signals. The first data signal parameters configure the drive current of the drive module, while the second data signal parameters configure the on / off states of multiple selection modules, thereby selecting the corresponding duty cycle emission control signal to be connected to the drive module.

[0263] After generating the target signal, the control module converts the target signal into the corresponding drive control command and sends it to the source drive circuit and gate drive circuit of the display panel. This provides parameter basis and timing reference for subsequent steps such as row-by-row reset, data writing, light emission path selection, and drive current output, ensuring that each pixel can emit light accurately according to the gray value corresponding to the image data.

[0264] For example, the total grayscale range of the display panel is set to 0~255 gray levels. The control module pre-divides the total grayscale range into three grayscale value ranges: low gray range, medium gray range, and high gray range, corresponding to the three levels of light emission control signals of the three selection modules. The target signal generation method for each range is described below: Low gray range: Corresponding to grayscale values ​​0-31. Pixel brightness is low in this range, requiring a low-duty-cycle control signal with a small current drive to improve grayscale uniformity. Medium gray range: Corresponding to grayscale values ​​32-127. Pixel brightness is moderate in this range, requiring a medium-duty-cycle control signal with a medium current drive to ensure smooth grayscale transitions. High gray range: Corresponding to grayscale values ​​128-255. Pixel brightness is high in this range, requiring a high-duty-cycle control signal with a large current drive to meet high-brightness display requirements. When the target pixel's grayscale value falls within this range, the control module generates the corresponding high grayscale target signal.

[0265] It is understood that the number of grayscale value intervals and the threshold values ​​mentioned above are only illustrative examples. In actual applications, the number of intervals and the grayscale range of each interval can be adjusted according to display requirements. More combinations of duty cycle levels can also be achieved by simultaneously enabling multiple selection modules. No specific restrictions are imposed here.

[0266] Step S202: Receive the target signal; Step S203: Based on the gray value range of the target pixel represented by the target signal, control one of the multiple signal lines to control the light emission duration of the pixel light emission element by the light emission control signal corresponding to the selected signal line; Step S204: Control the source driving circuit to generate a first data signal according to the target signal and the light emission control signal corresponding to the selected signal line, so as to control the magnitude of the driving current flowing through the pixel light emission element.

[0267] It should be understood that in the various embodiments of this application, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The description of the various embodiments above tends to emphasize the differences between the various embodiments. The similarities or similarities can be referred to each other. For the sake of brevity, they will not be repeated here.

[0268] Those skilled in the art will understand that the processor and control module of the display panel of the display device can implement all or part of the steps of the above control method embodiments through hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it performs the steps of the above method embodiments. The aforementioned storage medium includes various media that can store program code, such as mobile storage devices, read-only memory, magnetic disks, or optical disks.

[0269] The display panel, control method, and display device disclosed in the embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only for the purpose of helping to understand the methods and core ideas of this application. At the same time, those skilled in the art will recognize that, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A display panel, characterized in that, include: Multiple pixel driving circuits are arranged in a matrix along the row and column directions. Each pixel driving circuit includes multiple selection modules and driving modules. The driving module in each pixel driving circuit is connected to a pixel light-emitting element. A gate driving circuit, wherein the gate driving circuit is connected to the plurality of selection modules in the pixel driving circuit arranged along the row direction; A source driving circuit, comprising a data line and multiple signal lines, wherein the source driving circuit is connected via the data line to the plurality of selection modules and driving modules in each of the pixel driving circuits arranged along the column direction; The source driving circuit is also connected one-to-one with multiple selection modules in the pixel driving circuit arranged along the row direction through the multiple signal lines, for sending light emission control signals to the pixel driving circuit through the multiple signal lines; wherein, the duty cycle of the light emission control signals transmitted by different signal lines is different. The plurality of selection modules are used to select one of the plurality of signal lines to send a light emission control signal to the driving module; The control module is connected to the source drive circuit and the gate drive circuit. The control module is specifically configured as follows: Receive a target signal, and based on the gray value range of the target pixel represented by the target signal, control one of the multiple signal lines to control the light emission duration of the pixel light-emitting element by the light emission control signal corresponding to the selected signal line; Furthermore, the source drive circuit generates a first data signal based on the target signal and the light emission control signal corresponding to the selected signal line to control the magnitude of the drive current flowing through the pixel light emission element.

2. The display panel according to claim 1, characterized in that, The control module is specifically configured as follows: The system receives a target signal and controls the source driving circuit to generate multiple second data signals based on the gray value range of the target pixel represented by the target signal. Different gray value ranges correspond to different multiple second data signals. The source drive circuit is controlled to send the plurality of second data signals to the plurality of selection modules respectively, so that each selection module is in a first working state when it receives the corresponding second data signal, so as to transmit the light emission control signal on the corresponding signal line to the drive module; or, each selection module is in a second working state when it receives the corresponding second data signal, so as to block the transmission of the light emission control signal on the corresponding signal line to the drive module.

3. The display panel according to claim 2, characterized in that, The selection module includes a storage capacitor and a switching transistor module. The storage capacitor is connected to the switching transistor module and the ground terminal, respectively. The switching transistor module is connected to the source drive circuit, the gate drive circuit and the drive module, respectively. The control module is specifically configured as follows: The gate driving circuit controls the target scan signal sent to the switching transistor module, so that when the switching transistor module receives the target scan signal, it transmits the corresponding second data signal to the storage capacitor, and transmits the light emission control signal on the corresponding signal line to the driving module according to the voltage of the storage capacitor being in a first working state, or blocks the transmission of the light emission control signal on the corresponding signal line to the driving module according to the voltage of the storage capacitor being in a second working state.

4. The display panel according to claim 3, characterized in that, The switching module includes a write switching transistor and a transmission switching transistor; The write switch is connected to the storage capacitor, the source drive circuit, and the gate drive circuit respectively. The transmission switch is connected to the source drive circuit through a corresponding signal line. The transmission switch is also connected to the storage capacitor and the drive module respectively. The control module is specifically configured as follows: The gate drive circuit controls the target scan signal sent to the switching transistor module, so that the write switching transistor module is turned on when it receives the target scan signal, and transmits the corresponding second data signal sent by the source drive circuit to the storage capacitor. The transmission switch is in an on state according to the voltage of the storage capacitor to transmit the light emission control signal on the corresponding signal line to the driving module; or, the transmission switch is in an off state according to the voltage of the storage capacitor to block the transmission of the light emission control signal on the corresponding signal line to the driving module.

5. The display panel according to claim 3, characterized in that, The driving module includes a writing module and a light-emitting control module. The writing module is connected to the light-emitting control module, the gate driving circuit, the source driving circuit, and the ground terminal. The light-emitting control module is connected to the plurality of selection modules, the pixel light-emitting element, the power supply voltage, and the gate driving circuit. The light-emitting control module includes a driving transistor and a first capacitor. The control module is specifically configured as follows: The gate drive circuit is controlled to send a first scan signal to the write module, so that the write module is in a conducting state when it receives the first scan signal, and the voltage of the stored first data signal is transmitted to the control terminal of the first capacitor through the write module. When the light emission control module receives the light emission control signal through the plurality of selection modules, it is in an on state. The driving transistor in the light emission control module in the on state generates a driving current according to the voltage of the first data signal stored at the control terminal of the first capacitor, and transmits the driving current to the pixel light emission element.

6. The display panel according to claim 5, characterized in that, The writing module includes a voltage writing unit and a transmission unit; The voltage writing unit is connected to the source driving circuit, the gate driving circuit, the transmission unit and the ground terminal respectively, and the transmission unit is connected to the gate driving circuit and the light emission control module respectively. The control module is specifically configured as follows: The source drive circuit is controlled to send the first data signal to the drive circuit, and the gate drive circuit is controlled to send a write signal to the voltage write unit, so that the voltage write unit is in the on state when it receives the write signal, and the first data signal is stored in the voltage write unit. The gate drive circuit is controlled to send a first scan signal to the transmission unit, so that the transmission unit is in a conducting state when it receives the first scan signal, and the voltage of the first data signal stored in the voltage writing unit is transmitted to the first capacitor.

7. The display panel according to claim 6, characterized in that, The voltage writing unit includes a writing transistor and a second capacitor; The write transistor is connected to the gate driving circuit, the source driving circuit and the second capacitor respectively, and the second capacitor is connected to the ground terminal and the transmission unit respectively. The control module is specifically configured as follows: The gate drive circuit is controlled to send the write signal to the write transistor, so that when the write transistor receives the write signal, it is in a conducting state and transmits the first data signal to the second capacitor.

8. The display panel according to claim 6, characterized in that, The transmission unit includes a first transmission transistor and a second transmission transistor. The first transmission transistor is connected to the gate driving circuit, the voltage writing unit, and the driving transistor, respectively; the second transmission transistor is connected to the gate driving circuit, the control terminal of the first capacitor, and the driving transistor, respectively. The control module is specifically configured as follows: The gate drive circuit is controlled to send the first scan signal to the first transmission transistor and the second transmission transistor, so that the first transmission transistor and the second transmission transistor are in the conducting state when they receive the first scan signal. The first transmission transistor in the conducting state, the second transmission transistor in the conducting state, and the drive transistor form a transmission loop for transmitting the voltage of the first data signal in the voltage writing unit to the control terminal of the first capacitor, so that the drive transistor is in the conducting state according to the voltage of the first data signal.

9. The display panel according to claim 5, characterized in that, The light emission control module further includes a first light emission control transistor and a second light emission control transistor. The first light emission control transistor is connected to the power supply voltage, the plurality of selection modules, the driving transistor, and the writing module, respectively. The second light emission control transistor is connected to the pixel light emission element, the driving transistor, the plurality of selection modules, and the writing module, respectively. The driving transistor is also connected to the control terminal of the first capacitor. When the first light-emitting control transistor receives the light-emitting control signal through the plurality of selection modules, it is in an on state and transmits the power supply voltage to the driving transistor. When the driving transistor receives the power supply voltage, it is in a conducting state and generates a driving current based on the voltage of the first data signal stored at the control terminal of the first capacitor, and transmits the driving current to the second light-emitting control transistor. When the second light-emitting control transistor receives the light-emitting control signal through the plurality of selection modules, it is in the conducting state, and the second light-emitting control transistor in the conducting state transmits the received driving current to the pixel light-emitting element.

10. The display panel according to claim 9, characterized in that, The light-emitting control module further includes a compensation unit, which is connected to the power supply voltage terminal, the reference voltage terminal, the compensation terminal of the first capacitor, the source driving circuit, and the gate driving circuit, respectively. The control module is also configured to: Before the light emission control module receives the light emission control signal through the plurality of selection modules, the source drive circuit is controlled to send a first signal to the compensation unit, and the gate drive circuit is controlled to send a second scan signal to the compensation unit, so that the compensation unit is in a first conduction state when it receives the first signal and the second scan signal, and sends the reference voltage to the compensation terminal of the first capacitor; When the light emission control module receives the light emission control signal through the plurality of selection modules, it controls the source drive circuit to send a target light emission control signal to the compensation unit and controls the gate drive circuit to send a third scan signal to the compensation unit, so that the compensation unit is in a second conduction state when it receives the target light emission control signal and the third scan signal, and sends the power supply voltage to the compensation terminal of the first capacitor. The voltage stored at the control terminal of the first capacitor reduces the target difference voltage according to the capacitive coupling principle. The target difference voltage is the difference between the power supply voltage and the reference voltage. The target light emission control signal is the signal with the largest duty cycle among the plurality of light emission control signals. The driving transistor in the light-emitting control module, which is in the conducting state, generates a stable driving current based on the voltage stored at the control terminal of the first capacitor, and transmits the stable driving current to the pixel light-emitting element.

11. The display panel according to claim 10, characterized in that, The compensation unit also includes a third light-emitting control transistor and a fourth light-emitting control transistor. The third light-emitting control transistor is connected to the power supply voltage, the fourth light-emitting control transistor, the compensation terminal of the first capacitor, and the gate driving circuit, respectively. The fourth light-emitting control transistor is connected to the gate driving circuit, the compensation terminal of the first capacitor, and the reference voltage terminal. The control module is also configured to: Before the light emission control module receives the light emission control signal through the plurality of selection modules, the source driving circuit is controlled to send a first signal to the third light emission control transistor, and the gate driving circuit is controlled to send a second scan signal to the fourth light emission control transistor, so that the third light emission control transistor is in the off state when it receives the first signal, and the fourth light emission control transistor is in the on state when it receives the second scan signal, so that the reference voltage is transmitted to the compensation terminal of the first capacitor. When the light-emitting control module receives the light-emitting control signal through the plurality of selection modules, it controls the source driving circuit to send a target light-emitting control signal to the third light-emitting control transistor, and controls the gate driving circuit to send a third scan signal to the fourth light-emitting control transistor, so that the third light-emitting control transistor is in the on state when it receives the target light-emitting control signal, and the fourth light-emitting control transistor is in the off state when it receives the third scan signal, so that the power supply voltage is transmitted to the compensation terminal of the first capacitor.

12. The display panel according to claim 1, characterized in that, Each pixel driving circuit also includes a reset circuit. The reset circuit is connected to the gate drive circuit, the reset voltage terminal, and the drive module, respectively. The control module is also configured to: The gate drive circuit is controlled to send a reset signal to the reset circuit, so that the reset circuit is in a conducting state when it receives the reset signal, so that the reset circuit and the drive module form a discharge circuit to release the stored charge in the drive module.

13. A control method, characterized in that, Applied to the display panel as described in any one of claims 1-12, The method includes: Receive the target signal, and based on the gray value range of the target pixel represented by the target signal, control one of the multiple signal lines to control the light emission duration of the pixel light-emitting element by the light emission control signal corresponding to the selected signal line. Furthermore, the source drive circuit generates a first data signal based on the target signal and the light emission control signal corresponding to the selected signal line to control the magnitude of the drive current flowing through the pixel light emission element.

14. A display device, characterized in that, Includes the display panel and processor as described in any one of claims 1-12; The processor is configured as follows: Upon receiving image data, a target signal is generated from the gray value range of each pixel in the image data, and the target signal is sent to the display panel. Different gray value ranges correspond to different target signals. The control module in the display panel is configured as follows: Receive the target signal, and according to the gray value range of the target pixel represented by the target signal, control one of the multiple signal lines to control the light emission duration of the pixel light emission element by the light emission control signal corresponding to the selected signal line; Furthermore, the source drive circuit generates a first data signal based on the target signal and the light emission control signal corresponding to the selected signal line to control the magnitude of the drive current flowing through the pixel light emission element.

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