Display driver chip and display module

Abstract

This disclosure provides a display driver chip and a display module. The display driver chip includes: a plurality of metal bumps disposed on a first boundary, and a data processing circuit for receiving multiple display data. The data processing circuit divides the multiple chip signal channels into multiple chip signal channel groups, connects them to the corresponding panel signal channel groups using opposite connection patterns, and controls the filling order of display data based on the connection patterns. Through this design, this disclosure achieves a narrow bezel effect, while avoiding the metal layer resource consumption problem of traditional recessed bump solutions, and simplifies part number management and improves production efficiency through standardized bump structure and configuration.

Description

Technical Field

[0001] This disclosure relates to the field of display driver technology, and in particular to a display driver chip and a display module having the display driver chip. Background Technology

[0002] With the development of automotive display technology, applications such as floating in-vehicle displays (CID) and digital rearview mirrors are becoming increasingly common. These applications place high demands on the narrow bezel design of the display modules. Currently, there are two main technical solutions for achieving narrow bezel designs: one is to use chip-on-film (COF) packaging technology, and the other is to use chip-on-glass (COG) packaging combined with under-mount bump technology.

[0003] While COF technology can achieve a narrow bezel effect, its manufacturing cost is relatively high. The COG combined with recessed bumps solution can reduce costs, but it has two main drawbacks: First, recessed bumps require a metal layer to achieve the fan-out of the bump connection, reducing the available metal wiring resources in that area; second, driver chips using recessed bumps cannot be shared with driver chips using traditional bumps, requiring additional part number management and increasing the complexity of production management.

[0004] Therefore, how to achieve a narrow bezel design while reducing costs, and overcome the limitations of metal layer resources and part number management issues in existing technologies, has become a pressing technical challenge in this field. Summary of the Invention

[0005] In view of the above problems, this disclosure provides a display driver chip and a display module having the display driver chip. The technical solution of this disclosure achieves a narrow bezel effect while maintaining the traditional bump structure through a special signal channel grouping and data filling control mechanism.

[0006] One or more embodiments of this disclosure provide a display driver chip suitable for driving a pixel array of a display module. The display driver chip includes: a plurality of metal bumps disposed at a first boundary of the display driver chip, wherein the plurality of metal bumps respectively correspond to a plurality of chip signal channels of the display driver chip, and the plurality of metal bumps are electrically connected to a plurality of panel signal channels of the pixel array via a plurality of source lines; a data processing circuit for receiving multiple pieces of display data, wherein the data processing circuit is further configured to divide the plurality of chip signal channels into at least a plurality of chip signal channel groups, the plurality of chip signal channel groups including at least one first chip signal channel group and at least one second chip signal channel group, wherein the at least one first chip signal channel group and the at least one second chip signal channel group each correspond to at least one of the plurality of panel signal channel groups. A first panel signal channel group and the at least one second panel signal channel, wherein each panel signal channel group includes multiple panel signal channels, wherein multiple first chip signal channels of each first chip signal channel group are respectively connected to multiple first panel signal channels of the corresponding first panel signal channel group in a first connection state, wherein multiple second chip signal channels of each second chip signal channel group are connected to multiple second panel signal channels of the corresponding second panel signal channel group in a second connection state, wherein the first connection state and the second connection state are opposite, wherein the data processing circuit is further used to control the order in which the multiple display data are filled into the multiple chip signal channels based on the first connection state and the second connection state.

[0007] In one embodiment of this disclosure, the first connection state refers to the (i+1)th first chip signal channel in each first chip signal channel group being connected to the (i+1)th first panel signal channel in the corresponding first panel signal channel group, where i is an integer from 0 to N-1, and N is the total number of the plurality of first chip signal channels in the first chip signal channel group. The second connection state refers to the (Mj)th second chip signal channel in each second chip signal channel group being connected to the (j+1)th second panel signal channel in the corresponding second panel signal channel group, where j is an integer from 0 to M-1, and M is the total number of the plurality of second chip signal channels in the second chip signal channel group.

[0008] In one embodiment of this disclosure, the data processing circuit includes: a shift register for temporarily storing the multiple display data entries; and a drive control circuit electrically connected to the shift register for controlling the filling of the multiple display data entries from the shift register into the multiple chip signal channels based on the first connection state and the second connection state.

[0009] In one embodiment of this disclosure, the drive control circuit is further configured to: sequentially fill N first display data corresponding to each first chip signal channel group into the first first chip signal channel to the Nth first chip signal channel in the first chip signal channel group; and sequentially fill M second display data corresponding to each second chip signal channel group into the Mth second chip signal channel to the first second chip signal channel in the second chip signal channel group.

[0010] In one embodiment of this disclosure, the data processing circuit further includes: a timing controller electrically connected to the drive control circuit, for adjusting the arrangement order of M second display data corresponding to each second chip signal channel group before the multiple display data are input to the multiple chip signal channels.

[0011] In one embodiment of this disclosure, the timing controller is further configured to: reverse-sort the first to the Mth second display data in the M second display data corresponding to each second chip signal channel group, so as to obtain M adjusted second display data.

[0012] In one embodiment of this disclosure, the drive control circuit is further configured to: sequentially fill N first display data corresponding to each first chip signal channel group into the first first chip signal channel to the Nth first chip signal channel in the first chip signal channel group; and sequentially fill M adjusted second display data corresponding to each second chip signal channel group into the first second chip signal channel to the Mth second chip signal channel in the second chip signal channel group.

[0013] In one embodiment of this disclosure, the display module has a glass substrate, and the pixel array and the plurality of source lines are formed on the glass substrate.

[0014] In one embodiment of this disclosure, the drive control circuit is further configured to: apply a delay time to each first chip signal channel group, such that the first signal drive time curve of the first chip signal channel group and the second signal drive time curve of the adjacent second chip signal channel group form a continuous drive timing sequence.

[0015] In one embodiment of this disclosure, the drive control circuit is further configured to: detect the signal drive time difference between the first signal drive time curve of the first chip signal channel group and the second signal drive time curve of the adjacent second chip signal channel group; and apply the delay time to multiple first display data output by multiple first chip signal channels of the first chip signal channel group according to the signal drive time difference, so that the delayed first signal drive time curve and the second signal drive time curve form a continuous drive timing sequence.

[0016] One or more embodiments of this disclosure provide a display module, including: a pixel array; a plurality of panel signal channels formed on a glass substrate, wherein the pixel array is electrically connected to the plurality of panel signal channels; and a display driver chip. The display driver chip includes: a plurality of metal bumps disposed at a first boundary of the display driver chip, wherein each of the plurality of metal bumps corresponds to a plurality of chip signal channels of the display driver chip, and the plurality of metal bumps are electrically connected to the plurality of panel signal channels via a plurality of source lines; and a data processing circuit for receiving multiple pieces of display data. The data processing circuit is further configured to divide the plurality of chip signal channels into at least a plurality of chip signal channel groups, the plurality of chip signal channel groups including at least one first chip signal channel group and at least one second chip signal channel group, wherein the at least one first chip signal channel group and the at least one second chip signal channel group each correspond to at least one first panel signal channel group and the at least one second panel signal channel group in the plurality of panel signal channel groups, wherein each panel signal channel group includes a plurality of panel signal channels, wherein the plurality of first chip signal channels of each first chip signal channel group are respectively connected to the plurality of first panel signal channels of the corresponding first panel signal channel group in a first connection mode, wherein the plurality of second chip signal channels of each second chip signal channel group are connected to the plurality of second panel signal channels of the corresponding second panel signal channel group in a second connection mode, wherein the first connection mode and the second connection mode are opposite, wherein the data processing circuit is further configured to control the order in which the plurality of display data are filled into the plurality of chip signal channels based on the first connection mode and the second connection mode.

[0017] Based on the above, the display driver chip and display module provided in this disclosure, by dividing multiple chip signal channels into multiple chip signal channel groups and adopting opposite connection patterns, can achieve a narrow bezel effect without changing the existing bump structure, avoiding additional metal layer resource consumption. Specifically, the solution of this disclosure does not require the use of recessed bumps for fan-out routing, thus preserving complete metal layer resources and improving the routing flexibility of the chip. In addition, through the special design of the data processing circuit, this disclosure achieves flexible control over the order of display data filling. This control mechanism ensures that the display data can correctly correspond to the target pixel position under different connection patterns, thereby maintaining display quality. In particular, since this disclosure adopts a standard bump structure, the same driver chip can be used in both traditional bezel and narrow bezel products, significantly simplifying product part number management and improving production efficiency. At the same time, through precise control of driving timing and delay compensation mechanisms, this disclosure effectively solves the problem of discontinuous driving timing between different channel groups, ensuring the uniformity of the displayed image. Attached Figure Description

[0018] Figure 1 This is a block diagram illustrating the basic architecture of a display module according to an embodiment of the present disclosure;

[0019] Figure 2 This is a schematic diagram of the internal architecture of a display driver chip according to an embodiment of the present disclosure;

[0020] Figure 3A This is a schematic diagram of the wiring layout for a traditional display module;

[0021] Figure 3B A schematic diagram of the wiring layout for a recessed display module;

[0022] Figure 3C This is a schematic diagram of the wiring layout of a display module provided in an embodiment of the present disclosure;

[0023] Figure 4 This is a flowchart of a signal channel grouping and data processing method according to an embodiment of the present disclosure;

[0024] Figure 5 This is a schematic diagram showing the connection state between the chip signal channel and the panel signal channel according to an embodiment of the present disclosure;

[0025] Figure 6 This is a schematic diagram of a first data filling and sorting method according to an embodiment of the present disclosure;

[0026] Figure 7 This is a schematic diagram illustrating a second data filling and sorting method according to an embodiment of the present disclosure;

[0027] Figure 8AThis is a schematic diagram illustrating the sequence of rearranging multiple chip signal channels according to an embodiment of the present disclosure;

[0028] Figure 8B This is a schematic diagram illustrating the data entry order according to an embodiment of the present disclosure;

[0029] Figure 9A This is a schematic diagram of a traditional signal-driven time curve;

[0030] Figure 9B This is a schematic diagram illustrating the measurement of signal drive time difference according to an embodiment of the present disclosure;

[0031] Figure 9C This is a schematic diagram of the signal drive time curve after delay compensation according to an embodiment of the present disclosure.

[0032] Explanation of icon numbers

[0033] 10: Display Module

[0034] 100: Display driver chip

[0035] 101: Data Processing Circuit

[0036] 110: Shift Register

[0037] 120: Drive control circuit

[0038] 130: Timing Controller

[0039] 140: Data receiving interface

[0040] 150: Data output interface

[0041] 200: Pixel array

[0042] 151(1)-151(6): Chip signal channels

[0043] 152(1)-152(6): Metal bumps (traditional configuration)

[0044] 153(1)-153(6): Metal bumps (sunken configuration)

[0045] 154(1)-154(6): Metal bumps (configuration in this disclosure)

[0046] 210(1)-210(6): Panel signal channels

[0047] 220(1)-220(6): Source line (traditional configuration)

[0048] 221(1)-221(6): Source line (sunken configuration)

[0049] 222(1)-222(6): Source line (configuration disclosed herein)

[0050] CG11: First Chip Signal Channel Group

[0051] CG21: Second chip signal channel group

[0052] CG22: Second chip signal channel group

[0053] DG11, DG21, DG22: Display data groups

[0054] L1, L2, L1', L2', L1", L2": Spacing / Width

[0055] A71: Second filling order

[0056] A72, A83: First filling order

[0057] A73: Second filling order

[0058] A711-A734, A811-A812: Arrows

[0059] A81, A82, A91: Arrows

[0060] DT21(1)-DT21(N), DT11(1)-DT11(M), DT22(1)-DT22(N), Data_1-Data_2N+M: Display data

[0061] PH21(1)-PH21(N), PH11(1)-PH11(M), PH22(1)-PH22(N): Panel signal channels; DH21(1)-DH21(N), DH11(1)-DH11(M), DH22(1)-DH22(N): Chip signal channels

[0062] DTD1: Signal Drive Time Difference

[0063] S410, S420, S430: Steps Detailed Implementation

[0064] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0065] Figure 1 This is a block diagram illustrating the basic architecture of a display module according to an embodiment of the present disclosure.

[0066] refer to Figure 1In one embodiment, this disclosure provides a display module 10, which includes a display driver chip 100 and a pixel array 200. The display driver chip 100 is used to drive the pixel array 200.

[0067] Specifically, the display driver chip 100 has a plurality of metal bumps disposed on a first boundary of the display driver chip 100, wherein each of the plurality of metal bumps corresponds to a plurality of chip signal channels of the display driver chip 100, and the plurality of metal bumps are electrically connected to a plurality of panel signal channels of the pixel array 200 through a plurality of source lines. The pixel array 200 is used to receive and display the display data transmitted by the display driver chip 100.

[0068] In this embodiment, the display driver chip 100 is mainly responsible for receiving and processing display data from external sources (e.g., application processors), and distributing the data to each chip signal channel according to a predetermined connection pattern based on the control logic set by the internal data processing circuit. Through multiple metal bumps located at the first boundary of the chip, the chip 100 can make precise electrical connections with the panel signal channels on the pixel array 200, thereby driving each sub-pixel unit to correctly display the corresponding image information. This chip also integrates a shift register, a drive control circuit, and a timing controller to ensure the continuity of data filling order and transmission timing, effectively solving the problems of uneven brightness or excessively wide bezels caused by inconsistent drive timing in traditional drive technologies, and further achieving the technical effect of narrow bezels and high-resolution displays.

[0069] In one embodiment, the pixel array 200 is a group of sub-pixel arrays fabricated on a glass substrate using thin-film technology. Its main function is to receive and display the display data output by the display driver chip 100. Specifically, the pixel array 200 includes multiple pixel units arranged in the horizontal and vertical directions. Each pixel unit includes at least one light-emitting element (e.g., a liquid crystal display or organic light-emitting diode element) and a corresponding electrode structure. Simultaneously, a panel signal channel is formed on the glass substrate in the same layer as the pixel structure. This panel signal channel is electrically connected to the display driver chip 100 via a source line to transmit driving signals, enabling each pixel to output light correctly according to the input display data.

[0070] In one embodiment, the display module 10 is formed on a glass substrate, wherein the pixel array 200 and the plurality of source lines are formed on the glass substrate.

[0071] In one embodiment, the manufacturing method of the display module 10 involves fabricating a structure on a glass substrate. Specifically, the glass substrate is first pre-cleaned, and then a thin-film transistor array process is performed to form the basic structure of the pixel array 200. On the glass substrate, a multilayer structure including a gate metal layer, an insulating layer, a semiconductor layer, and source / drain metal layers is sequentially formed to construct the driving circuit of the pixel array 200.

[0072] In one embodiment, the formation of the source lines is performed concurrently with the process of the source / drain metal layers. Specifically, the plurality of source lines are made of a conductive material, such as aluminum, copper, or their alloys, and are electrically connected to the sources of the thin-film transistors in the pixel array 200. One end of the plurality of source lines extends to the edge region of the glass substrate, forming a bonding region corresponding to the metal bumps of the display driver chip 100. A bonding region for mounting the display driver chip 100 is formed in the edge region of the glass substrate. This bonding region includes a plurality of bonding pads for electrically connecting to the metal bumps of the display driver chip 100. The ends of the plurality of source lines are respectively connected to these bonding pads to establish an electrical connection path between the pixel array 200 and the display driver chip 100.

[0073] In one embodiment, the display module 10 can be applied to an in-vehicle display device, such as a floating in-vehicle display (CID) or a digital rearview mirror. In such applications, the narrow bezel design of the display module 10 improves the overall visual effect and installation flexibility. Specifically, the display driver chip 100 employs a special signal channel grouping and data filling control mechanism, enabling the display module 10 to achieve a narrow bezel effect comparable to a recessed bump design while maintaining a traditional bump structure. Through this design, the display module 10 not only maintains a low manufacturing cost but also avoids the consumption of additional metal layer resources.

[0074] Figure 2 This is a schematic diagram of the internal architecture of a display driver chip according to an embodiment of the present disclosure.

[0075] Reference Figure 2 In one embodiment, the display driver chip 100 includes a data processing circuit 101, wherein the data processing circuit 101 includes: a data receiving interface 140, a data output interface 150, a shift register 110, a drive control circuit 120, and a timing controller 130.

[0076] Specifically, the data receiving interface 140 is used to receive multiple pieces of display data for driving the pixel array 200. These multiple pieces of display data may include color information, brightness information, and control information. After receiving this display data, the data receiving interface 140 performs data format conversion and preliminary processing, and then transmits the processed data to the data processing circuit 101. In the data processing circuit 101, this display data undergoes further processing according to a preset data processing flow.

[0077] The shift register 110 is used to temporarily store the multiple display data, and according to the control signal of the drive control circuit 120, the display data is sequentially filled into the multiple chip signal channels.

[0078] The drive control circuit 120 controls the data filling order of the multiple chip signal channels to achieve data correspondence with the multiple panel signal channels. Specifically, the multiple metal bumps are disposed on the first boundary of the display driver chip 100, each metal bump corresponding to a chip signal channel and electrically connected to the corresponding panel signal channel through a source line. By using different connection patterns, the data filling order in some areas is reversed compared to the order of the panel signal channels, thereby achieving a narrow bezel design.

[0079] The timing controller 130 is electrically connected to the drive control circuit 120 and is used to adjust the arrangement order of M pieces of second display data corresponding to each second chip signal channel group before the multiple pieces of display data are input to the multiple chip signal channels. Specifically, the timing controller 130 can reverse the sorting of the M pieces of second display data to obtain M pieces of adjusted second display data.

[0080] The data output interface 150 is used to output the processed display data to the plurality of panel signal channels through the plurality of chip signal channels. Furthermore, the data output interface 150 further includes a plurality of metal bumps disposed on the first boundary of the display driver chip 100 and a plurality of corresponding chip signal channels. Each metal bump and its corresponding chip signal channel together constitute an output port, which is electrically connected to the panel signal channel via a source line, thereby outputting the display data processed by the data processing circuit 101 to the panel signal channel.

[0081] In this embodiment, the data processing circuit 101, shift register 110, drive control circuit 120, timing controller 130, data receiving interface 140, and data output interface 150 can be hardware circuits with data processing, storage, and control capabilities. For example, the data processing circuit 101 can be an application-specific integrated circuit (ASIC); the shift register 110 can be a static random access memory (SRAM); the drive control circuit 120 and timing controller 130 can be a field-programmable gate array (FPGA) or a complex programmable logic device (CPLD); and the data receiving interface 140 and data output interface 150 can be standardized serial or parallel communication interface circuits.

[0082] In another embodiment, the timing controller 130 can also implement a drive timing compensation function. Specifically, the timing controller 130 can apply an appropriate delay time to a specific channel group based on the drive time differences between different channel groups to ensure the continuity of the overall drive timing. This compensation mechanism can effectively avoid unevenness in the displayed image.

[0083] Figure 3A This is a schematic diagram of the wiring layout for a traditional display module. Please refer to it. Figure 3A The presents a conventional wiring configuration for a display module 10. The display module 10 includes a display driver chip 100 and a pixel array 200, wherein the display driver chip 100 drives the pixel array 200 using a conventional wiring layout.

[0084] For example, suppose the display driver chip 100 has multiple chip signal channels 151(1) to 151(6) and corresponding multiple metal bumps 152(1) to 152(6) are provided thereon. These metal bumps 152(1) to 152(6) are electrically connected to multiple panel signal channels 210(1) to 210(6) of the pixel array 200 through multiple source lines 220(1) to 220(6). In this conventional configuration, the source lines 220(1) to 220(6) are directly connected, that is, the first chip signal channel 151(1) is connected to the first panel signal channel 210(1), the second chip signal channel 151(2) is connected to the second panel signal channel 210(2), and so on.

[0085] It should be noted that in this application, source lines 220(1) to 220(6) are wires located in the fan-out area, extending from the source lines (or data lines) within the pixel array 200 and electrically connected to the corresponding metal bumps. The panel signal channel refers to the source lines within the pixel array 200 and all pixel units connected to those source lines. The chip signal channel refers to the data channel circuit used by the display driver chip 100 to transmit display signals to the source lines in the pixel array, including metal wires, ESD protection units, amplifiers, analog-to-digital converters, etc. In one embodiment, source lines 220(1) to 220(6) are generated in the same manner as the circuitry within the pixel array 200.

[0086] In this traditional wiring layout, because each source line 220(1) to 220(6) needs to maintain a certain spacing to avoid signal interference, a relatively wide bezel area is formed between the display driver chip 100 and the pixel array 200. As shown in the figure, the width of the spacing L1 between the pixel array 200 and the display driver chip 100 is difficult to shorten due to the limitations of the wiring process, which leads to the bezel width L2 of the display module needing to be above a certain length (a relatively wide bezel). Although this layout is relatively simple in terms of process, it is not conducive to achieving a narrow bezel design, especially in application scenarios such as automotive displays, which may affect the overall visual effect and installation flexibility.

[0087] Figure 3B A schematic diagram of the wiring layout for a recessed display module.

[0088] Please refer to Figure 3B Another approach is to use a modified display module 10. The display module 10 includes a display driver chip 100 and a pixel array 200, wherein the display driver chip 100 adopts a recessed metal bump design to achieve a narrow bezel effect.

[0089] For example, suppose the display driver chip 100 has multiple chip signal channels 151(1) to 151(6) and corresponding multiple metal bumps 153(1) to 153(6) are provided thereon. These metal bumps 153(1) to 153(6) are electrically connected to multiple panel signal channels 210(1) to 210(6) of the pixel array 200 through multiple source lines 221(1) to 221(6). In this modified configuration, the metal bumps 153(1) to 153(6) adopt a recessed design (or an inward design), so that their position extends from the edge of the chip inward.

[0090] In this recessed design, the trace paths of the source lines 221(1) to 221(6) can more effectively utilize the area within the boundary of the display driver chip 100. Because some connection paths are moved to the area within the chip boundary, the gap L1' between the display driver chip 100 and the pixel array 200 is reduced, thereby achieving a narrower bezel width L2'. However, while this design achieves a narrow bezel effect, it requires an additional metal layer inside the chip for the fan-out connections of the recessed metal bumps 153(1) to 153(6), thus reducing the metal layer resources available for other applications.

[0091] On the other hand, the design of recessed metal bumps requires special processes to achieve bump structures of different depths, which increases the complexity of the process. In addition, due to the special bump structure, the driver chip with this design cannot share the same process as the driver chip with the traditional bump structure, resulting in the need for additional part number management and increasing the complexity of production management.

[0092] Figure 3C This is a schematic diagram of the wiring layout of a display module provided in an embodiment of the present disclosure.

[0093] Please refer to Figure 3C In one embodiment, this disclosure provides an improved display module 10, which includes a display driver chip 100 and a pixel array 200. The display driver chip 100 adopts an innovative signal channel grouping and wiring configuration to achieve a narrow bezel design.

[0094] Specifically, the display driver chip 100 has multiple chip signal channels 151(1) to 151(6), and corresponding multiple metal bumps 154(1) to 154(6) are disposed thereon. These metal bumps 154(1) to 154(6) are electrically connected to multiple panel signal channels 210(1) to 210(6) of the pixel array 200 through multiple source lines 222(1) to 222(6). However, unlike conventional configurations, this disclosure divides the multiple chip signal channels 151(1) to 151(6) into multiple groups, and uses different connection patterns for different groups. For example... Figure 3C As shown, source lines 222(1), 222(2), 222(5) and 222(6) overlap with the display driver chip 100, which can reduce the spacing L1.

[0095] exist Figure 3CIn the example, the chip signal channels can be divided into two categories: the first category (also called the first chip signal channel group) includes chip signal channels 151(3) to 151(4) corresponding to panel signal channels 210(3) to 210(4), which are connected in the forward direction (also called the first connection state); the second category (also called the second chip signal channel group) is, for example, chip signal channels 151(1) to 151(2) and chip signal channels 151(5) to 151(6) corresponding to panel signal channels 210(1) to 210(2) and panel signal channels 210(5) to 210(6), which are connected in the reverse direction (also called the second connection state).

[0096] More specifically, in the first chip signal channel group corresponding to the first connection state, chip signal channel 151(3) is connected to panel signal channel 210(3) through source line 222(3), and chip signal channel 151(4) is connected to panel signal channel 210(4) through source line 222(4), and they are connected in the order of the corresponding numbers.

[0097] In the second chip signal channel group corresponding to the second connection state (e.g., chip signal channels 151(1) to 151(2) corresponding to panel signal channels 210(1) to 210(2)), chip signal channel 151(1) is connected to panel signal channel 210(2) via source line 222(2) and chip signal channel 151(2) is connected to panel signal channel 210(1) via source line 222(1), showing the opposite connection state in the order of the connected numbers.

[0098] More specifically, in one embodiment, the data processing circuit 101 divides all chip signal channels into two groups: a first chip signal channel group and a second chip signal channel group. The first chip signal channel group contains N channels, while the second chip signal channel group contains M channels. Correspondingly, the panel also has a first panel signal channel group and a second panel signal channel group, containing N and M panel signal channels respectively.

[0099] For the first connection state, this embodiment adopts a direct ascending order mapping method, that is:

[0100] The (i+1)th chip signal channel in each first chip signal channel group (where i ranges from 0 to N–1) is directly connected to the (i+1)th panel signal channel in the corresponding first panel signal channel group.

[0101] For example, assuming the first chip signal channel group has 4 channels (i.e., N=4), the mapping relationship is as follows:

[0102] The first chip signal channel is connected to the first panel signal channel in the first panel signal channel group; the second chip signal channel is connected to the second panel signal channel; the third chip signal channel is connected to the third panel signal channel; and the fourth chip signal channel is connected to the fourth panel signal channel.

[0103] For the second connection state, this embodiment adopts a reverse sorting mapping method, that is:

[0104] The (M–j)th chip signal channel in each second chip signal channel group (where j ranges from 0 to M–1) is connected to the (j+1)th panel signal channel in the corresponding second panel signal channel group.

[0105] For example, assuming there are 3 channels in the second chip signal channel group (i.e., M=3), the mapping relationship is as follows: when j=0, the (3-0)th chip signal channel is connected to the (0+1)th panel signal channel in the second panel signal channel group; when j=1, the (3-1)th chip signal channel is connected to the (1+1)th panel signal channel in the second panel signal channel group; when j=2, the (3-2)th chip signal channel is connected to the (2+1)th panel signal channel in the second panel signal channel group.

[0106] Through the specific implementation of the two connection modes described above, this example enables precise adjustment of data transmission in different areas. The first chip signal channel group maintains a forward alignment with the first panel signal channel group, while the second chip signal channel group adopts a reverse connection strategy to better adapt to panel trace layout and driving timing compensation requirements. This mapping method helps ensure that display data correctly and continuously drives each sub-pixel of the panel, even with a narrow bezel design, thereby improving display effect and uniformity.

[0107] Through this innovative grouping and connection configuration, the traces of source lines 220(1) to 220(6) can utilize the area of ​​the display driver chip 100 more effectively. This design allows for a significant reduction in the spacing L1” between the display driver chip 100 and the pixel array 200, thereby achieving a narrower bezel width L2”. Compared to conventional configurations, this disclosure does not require the use of recessed metal bumps, thus eliminating the need for additional metal layer resources and ensuring compatibility with standard processes.

[0108] This improved design also offers advantages in production management. The use of a standard metal bump structure allows the same driver chip to be used in both traditional bezel and narrow bezel products, significantly simplifying product part number management. Furthermore, by controlling the data entry order, it ensures that the display signal correctly corresponds to the target pixel position, maintaining display quality.

[0109] Figure 4 This is a flowchart of a signal channel grouping and data processing method according to an embodiment of the present disclosure.

[0110] Reference Figure 4 In one embodiment, this disclosure provides a signal channel grouping and data processing method. The method includes the following steps: step S410, step S420, and step S430.

[0111] In step S410, the data processing circuit of the display driver chip 100 receives multiple pieces of display data. This display data is used to drive the pixel array 200 of the display module 10 to display corresponding image content.

[0112] In step S420, the data processing circuit groups the multiple chip signal channels of the display driver chip 100. Specifically, the multiple chip signal channels are divided into at least one first chip signal channel group and at least one second chip signal channel group. Each chip signal channel group corresponds to a specific panel signal channel group of the pixel array 200. Each panel signal channel group includes multiple panel signal channels.

[0113] In step S420, the plurality of first chip signal channels in each first chip signal channel group adopt a first connection pattern to connect to the plurality of first panel signal channels in the corresponding first panel signal channel group. Conversely, the plurality of second chip signal channels in each second chip signal channel group adopt a second connection pattern to connect to the plurality of second panel signal channels in the corresponding second panel signal channel group. It is worth noting that the first connection pattern and the second connection pattern are opposite connection methods.

[0114] In step S430, the data processing circuit controls the order in which the multiple display data entries are filled into the multiple chip signal channels based on the first connection state and the second connection state. This control of the data entry order ensures that the display data correctly corresponds to the target pixel position.

[0115] Figure 5 This is a schematic diagram showing the connection between the chip signal channel and the panel signal channel according to an embodiment of the present disclosure.

[0116] Reference Figure 5 In one embodiment, this disclosure proposes an optimized channel connection configuration. For example, in order to achieve a narrow bezel design, the multiple chip signal channels 151(1) to 151(6) of the display driver chip 100 are divided into multiple chip signal channel groups and different connection patterns are adopted to correspond to the panel signal channels 210(1) to 210(6) (for ease of explanation, 6 signal channels are used as an example for simple illustration).

[0117] Specifically, the plurality of chip signal channel groups include: a first chip signal channel group CG11, which includes chip signal channels 151(3) to 151(4); and two second chip signal channel groups CG21 and CG22, wherein CG21 includes chip signal channels 151(1) to 151(2), and CG22 includes chip signal channels 151(5) to 151(6). These chip signal channel groups are electrically connected to panel signal channels 210(1) to 210(6) through their corresponding metal bumps 154(1) to 154(6) and source lines 222(1) to 222(6).

[0118] In the first chip signal channel group CG11, the first connection pattern is adopted, that is, the sequential connection order is maintained. For example, chip signal channel 151(3) is connected to panel signal channel 210(3) through source line 222(3), and chip signal channel 151(4) is connected to panel signal channel 210(4) through source line 220(4), presenting a sequential connection method.

[0119] In contrast, in the second chip signal channel groups CG21 and CG22, a second connection pattern is adopted, that is, a reverse connection sequence. Taking CG21 as an example, chip signal channel 151(1) is connected to panel signal channel 210(2) through source line 222(2), and chip signal channel 151(2) is connected to panel signal channel 210(1) through source line 222(1); similarly, a similar reverse connection method is adopted in CG22.

[0120] Through this special grouping and connection configuration, this disclosure achieves the same narrow bezel effect as recessed bumps without altering the metal bump structure. This design not only avoids the consumption of additional metal layer resources but also maintains compatibility with standard processes.

[0121] Another advantage of this connectivity configuration is its flexibility. By adjusting the number of channel groups and the size of each group, the bezel width can be optimized to meet different application requirements. Furthermore, due to the use of a standard metal bump structure, the same driver chip design can be used in products with different bezel requirements.

[0122] It should be understood that the connection configuration of this disclosure is not limited to the three chip signal channel groups shown in this embodiment. Depending on the actual hardware specifications, application requirements, and design considerations, the chip signal channels can be divided into more groups, and the number of channels in each group can also be adjusted according to specific circumstances to achieve optimal bezel width and other performance indicators.

[0123] Figure 6 This is a schematic diagram of a first data filling and sorting method according to an embodiment of the present disclosure.

[0124] Reference Figure 6 In one embodiment, this disclosure provides a data filling configuration with an incrementally numbered sequence. The figure shows the grouping of chip signal channels in the display driver chip 100 and their corresponding data transmission paths.

[0125] Specifically, the multiple chip signal channels are divided into three signal channel groups: a first chip signal channel group CG11, a second chip signal channel group CG21, and CG22. The channels in the first chip signal channel group CG11 maintain a first connection state, wherein the data of PH11(1) to PH11(M) are respectively connected to DH11(1) to DH11(M). This connection configuration indicates that in the first chip signal channel group CG11, the data filling order is consistent with the physical order of the channels.

[0126] Conversely, in the second chip signal channel groups CG21 and CG22, a second connection pattern is adopted, presenting a reverse connection sequence. Taking CG21 as an example, the data of PH21(1) to PH21(N) are connected to DH21(N) to DH21(1) respectively, showing a reverse correspondence. Similarly, in CG22, the data of PH22(1) to PH22(N) also adopt the same reverse connection method, connected to DH22(N) to DH22(1).

[0127] Figure 7 This is a schematic diagram illustrating a second data filling and sorting method according to an embodiment of the present disclosure.

[0128] Please refer to Figure 7 In one embodiment, this disclosure provides a data filling mechanism for controlling the filling order of display data in different chip signal channel groups.

[0129] Specifically, the display driver chip 100 uses different filling orders according to different chip signal channel groups. For the second chip signal channel group CG21, the second filling order A71, as shown by arrows A711 to A714, is used. Under this filling order, the N display data DT21(1) to DT21(N) corresponding to the second chip signal channel group CG21 in the received display data Data_1 to Data_2N+M will be filled into the chip signal channels DH21(N) to DH21(1) in reverse order according to the second filling order. For example, as shown by arrow A711, display data DT21(1) is filled into chip signal channel DH21(N); as shown by arrow A712, display data DT21(2) is filled into chip signal channel DH21(N-1); and so on, as shown by arrow A713, display data DT21(N-1) is filled into chip signal channel DH21(2); as shown by arrow A714, display data DT21(N) is filled into chip signal channel DH21(1).

[0130] For the first chip signal channel group CG11, the first filling order A72, as shown by arrows A721 to A724, is adopted. Under this filling order, the M display data DT11(1) to DT21(M) corresponding to the first chip signal channel group CG11 from the received display data Data_1 to Data_2N+M will be sequentially filled into the chip signal channels DH11(1) to DH11(M) in the first filling order. For example, as shown by arrow A721, display data DT11(1) is filled into the chip signal channel DH11(1); as shown by arrow A722, display data DT11(2) is filled into the chip signal channel DH11(2); and so on, as shown by arrow A723, display data DT11(M-1) is filled into the chip signal channel DH11(M-1); as shown by arrow A724, display data DT11(M) is filled into the chip signal channel DH11(M).

[0131] Similar to the second chip signal channel group CG21, for the second chip signal channel group CG22, the second filling order A73, as shown by arrows A731 to A734, is adopted. Under this filling order, the N display data DT22(1) to DT22(N) corresponding to the second chip signal channel group CG22 in the received display data Data_1 to Data_2N+M will be filled into the chip signal channels DH22(N) to DH22(1) in reverse order according to the second filling order.

[0132] In one embodiment, the timing controller 130 is configured to preprocess the multiple display data entries before they are input to multiple chip signal channels. During the preprocessing, the timing controller 130 identifies multiple second display data entries corresponding to each second chip signal channel group and adjusts the order of these second display data entries.

[0133] For example, when the multiple display data entries include N entries of second display data corresponding to the second chip signal channel group CG21, the timing controller 130 will perform a reverse sorting operation on these N entries of second display data. Specifically, the timing controller 130 will adjust the original first entry of second display data to the Nth adjusted entry of second display data, adjust the original second entry of second display data to the (N-1)th adjusted entry of second display data, and so on, until the original Nth entry of second display data is adjusted to the first adjusted entry of second display data.

[0134] After the timing controller 130 completes the data sorting and adjustment, it transmits the adjusted second display data to the drive control circuit 120. The drive control circuit 120 then fills the adjusted second display data into the corresponding chip signal channels according to the preset filling order.

[0135] Through this preprocessing mechanism, the display driver chip 100 can complete the necessary data sorting adjustment before the data is actually filled into the chip signal channel, temporarily storing all the data in the data queue (or the corresponding register), and using the normal data filling order to fill all the display data in the data queue into the corresponding signal channel. Furthermore, since the sorting adjustment operation is completed before data filling, complex real-time adjustments during the filling process are avoided, thereby improving overall processing efficiency.

[0136] Figure 8A This is a schematic diagram illustrating the sequence of switching multiple chip signal channels according to an embodiment of the present disclosure.

[0137] Reference Figure 8A In one embodiment, this disclosure provides a method for swapping display data. The display driver chip 100 divides the display data corresponding to different chip signal channel groups into multiple display data groups DG11, DG21, and DG22, and applies a specific data processing strategy to a specific display data group.

[0138] Specifically, for the display data group DG11 corresponding to the first chip signal channel group, a strategy of maintaining the arrangement order is adopted to ensure that the data in the first chip signal channel group maintains its original order.

[0139] For the display data group DG21 corresponding to the second chip signal channel group CG21, as shown by arrow A81, a strategy of swapping the order is adopted. Under this strategy, the display data DT21(1) to DT21(N) are swapped in order. For example, if the original display data was sorted from DT21(1) to DT21(N), after adjustment, it will become DT21(N) sorted from DT21(1).

[0140] Similarly, for the display data group DG22 corresponding to the second chip signal channel group CG22, as shown by arrow A82, a strategy of swapping the order is also adopted. Under this strategy, the display data DT22(1) to DT22(N) are swapped in order. For example, if the original display data was ordered from DT22(1) to DT22(N), after adjustment, it will become DT22(N) ordered from DT22(1).

[0141] Figure 8B This is a schematic diagram illustrating the data entry order according to an embodiment of the present disclosure.

[0142] Please refer to Figure 8B In another embodiment, this disclosure provides a simplified data entry mechanism. In this embodiment, the drive control circuit 120 uses a uniform first entry sequence A83 to process all display data, including adjusted second display data and unadjusted first display data.

[0143] Specifically, after the timing controller 130 completes the reverse sorting adjustment of the second display data, the drive control circuit 120 can process all display data using a single forward filling order. For example... Figure 8B As shown, this forward filling order means: as indicated by arrows A811, A812..., the adjusted second display data DT21(N) to DT21(1), the first display data DT11(1) to DT11(M), and the adjusted second display data DT22(N) to DT22(1) are sequentially filled into the multiple chip signal channels DH21(1) to DH21(N) of the second chip signal channel group, the multiple chip signal channels DH11(1) to DH11(M) of the first chip signal channel group, and the multiple chip signal channels DH22(1) to DH22(N) of the second chip signal channel group.

[0144] Since the corresponding display data has been reverse-ordered and adjusted by the timing controller 130, the required reverse connection effect can still be maintained even if forward filling is used. For the first chip signal channel group, since its corresponding display data does not need to be adjusted, forward filling can maintain the required forward connection effect.

[0145] By adopting this unified filling order, this embodiment significantly simplifies the implementation complexity of the data filling mechanism. Furthermore, since the data sorting and adjustment work has been pre-completed by the timing controller 130, the drive control circuit 120 only needs to perform a single type of filling operation, thereby improving the system's stability and reliability.

[0146] Figure 9A This is a schematic diagram of a traditional signal-driven time curve.

[0147] Reference Figure 9A This presents the signal driving time curves under traditional display driving methods. The signal driving time curves demonstrate the timing characteristics of different chip signal channel groups when driving display data.

[0148] Specifically, the signal driving time curve includes: a second signal driving time curve corresponding to the second chip signal channel group, a first signal driving time curve corresponding to the first chip signal channel group, and a second signal driving time curve corresponding to another second chip signal channel group. The horizontal axis represents the driven display data, from Data_2N+M to Data_1; the vertical axis represents the driving time required for the signal to reach the target value.

[0149] Due to the physical characteristics of the display driver chip 100, the chip signal channel located at the chip center has a shorter signal transmission path, and therefore its driving time is shorter. Conversely, the chip signal channel located at the chip edge has a longer signal transmission path, and therefore its driving time is relatively longer. Thus, the signal driving time curve exhibits a curve characteristic that gradually rises towards both sides, with the chip center as the lowest point.

[0150] With this traditional drive timing curve configuration, the drive timing difference between adjacent channels exhibits a continuous and smooth change. This continuity helps avoid abrupt changes in brightness and darkness in the displayed image, thereby ensuring the uniformity of overall display quality. However, when adopting a new narrow bezel design, the need to change the channel connection configuration may affect this continuity, thus requiring appropriate compensation mechanisms.

[0151] In this embodiment, the drive control circuit 120 of the display driver chip 100 is designed to adjust the drive timing of each chip signal channel group to achieve continuity of display data output. Specifically, after the chip signal channels are divided into a first chip signal channel group and a second chip signal channel group, the drive control circuit first applies a preset delay time to each first chip signal channel group. The purpose of this delay is to shift the drive time curves of all first signals (first display data) in that group backward, thereby forming a continuous drive timing with the drive time curves of the second signals (second display data) in the adjacent second chip signal channel group. In this mechanism, by appropriately delaying the drive time of the first signals in the first chip signal channel group, its output waveform is precisely aligned with the drive waveform of the second signals in the immediately following second chip signal channel group on the time axis. In other words, although there may be differences in transmission delay or drive speed between the two groups of channels, after the delay adjustment, the first group of signals and the second group of signals are seamlessly connected in time, thereby forming a continuous and smooth drive timing, ensuring that the brightness and color of the displayed image are consistent and uniform.

[0152] In another embodiment, to further enhance the flexibility and stability of delay adjustment, the drive control circuit 120 also includes a preset delay time level selection module. This preset delay time level selection module provides multiple fixed delay time levels, each corresponding to a preset delay value. When the time difference detection module measures the time difference between the first signal drive time curve of the first chip signal channel group and the second signal drive time curve of the adjacent second chip signal channel group, the control logic automatically selects the corresponding fixed delay value from the delay time levels based on the specific range within which the difference falls. Subsequently, this fixed delay value is applied to all output first display data in the first chip signal channel group to adjust its drive time curve. This mechanism of adjustment through preset delay time levels can quickly and stably respond to timing changes caused by various environmental conditions (such as temperature changes or power supply fluctuations), further ensuring that the first and second signal drive time curves can be approximately seamlessly connected, thereby achieving a continuous and uniform display effect.

[0153] The aforementioned delay compensation mechanism ensures that the driving timing between channels is continuous and uniform after data is input to the chip signal channels, thereby avoiding problems such as uneven display brightness and color distortion that may be caused by discontinuous timing. Ultimately, in this way, the display driver chip 100 can achieve a high-quality and uniform display effect while meeting the requirements of narrow bezel design.

[0154] Figure 9B This is a schematic diagram of the measurement of signal drive time difference according to an embodiment of the present disclosure.

[0155] Please refer to Figure 9B In one embodiment, this disclosure presents a drive timing state without delay compensation. Due to the special channel grouping and connection configuration employed in this disclosure, significant discontinuities will appear in the drive time curves between different chip signal channel groups without timing compensation.

[0156] Specifically, there is a driving time difference (DTD1) between the first signal driving time curve of the first chip signal channel group and the second signal driving time curve of the adjacent second chip signal channel group. This driving time difference (DTD1) is particularly evident at the boundary between the consecutively filled display data Data_1 and Data_N+1, where Data_N+1 corresponds to the first chip signal channel group, and Data_1 corresponds to the adjacent second chip signal channel group.

[0157] This discontinuity in drive timing primarily stems from the unique channel grouping configuration employed in this disclosure. Specifically, when the chip signal channels of the first chip signal channel group employ a first connection pattern, while the adjacent second chip signal channel group employs a second connection pattern, the differences in signal transmission path lengths are not only due to the different physical locations of these chip signal channels on the chip, but may also be influenced by other structural factors such as the physical address and source line length of the panel signal channels. The combined effect of these factors leads to differences in the drive timing of each channel, resulting in a discontinuity in the drive timing sequence.

[0158] If this drive timing difference (DTD1) is not compensated for, it may cause significant brightness differences at the boundaries between different channel groups in the displayed image. For example, when the drive time of Data_1 is shorter than that of Data_N+1, it may cause a sudden change in the brightness of the corresponding pixels, affecting the overall display quality. Therefore, an appropriate delay compensation mechanism is needed to eliminate this discontinuity in drive timing.

[0159] Figure 9C This is a schematic diagram of the signal drive time curve after delay compensation according to an embodiment of the present disclosure.

[0160] Reference Figure 9C In one embodiment, this disclosure provides a drive timing compensation mechanism, wherein the drive control circuit 120 applies an appropriate delay time A91 to adjust the first signal drive time curve to a delayed first signal drive time curve.

[0161] Specifically, as indicated by arrow A91, the delayed first signal drive time curve is achieved by applying a delay time to the drive timing of the first chip signal channel group. The magnitude of the delay time can be determined based on the previously detected drive time difference DTD1. Through this delay compensation mechanism, the first signal drive time curve is shifted upward, thereby eliminating the timing discontinuity between it and the adjacent second signal drive time curve.

[0162] In this improved driving timing configuration, the delayed first signal driving time curve and its adjacent second signal driving time curve can form a continuous transition at the boundary between Data_N+M and Data_2N+M, and at the boundary between Data_1 and Data_N+1. This continuous and smooth driving timing characteristic not only eliminates the original driving time difference, but also ensures the uniformity of the overall display screen.

[0163] By using this timing compensation mechanism, the timing discontinuity problem that may occur when using special channel grouping configuration can be solved, thereby achieving a narrow bezel design while maintaining good display quality.

[0164] Based on the above, the display driver chip and display module provided in this disclosure, by dividing multiple chip signal channels into multiple chip signal channel groups and adopting opposite connection patterns, can achieve a narrow bezel effect without changing the existing bump structure, avoiding additional metal layer resource consumption. Specifically, the solution of this disclosure does not require the use of recessed bumps for fan-out routing, thus preserving complete metal layer resources and improving the routing flexibility of the chip. In addition, through the special design of the data processing circuit, this disclosure achieves flexible control over the order of display data filling. This control mechanism ensures that the display data can correctly correspond to the target pixel position under different connection patterns, thereby maintaining display quality. In particular, since this disclosure adopts a standard bump structure, the same driver chip can be used in both traditional bezel and narrow bezel products, significantly simplifying product part number management and improving production efficiency. At the same time, through precise control of driving timing and delay compensation mechanisms, this disclosure effectively solves the problem of discontinuous driving timing between different channel groups, ensuring the uniformity of the displayed image.

[0165] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display driver chip, suitable for driving the pixel array of a display module, characterized in that, The display driver chip includes: Multiple metal bumps are disposed on the first boundary of the display driver chip, wherein the multiple metal bumps correspond to multiple chip signal channels of the display driver chip, and the multiple metal bumps are electrically connected to multiple panel signal channels of the pixel array through multiple source lines. The data processing circuit is used to receive multiple display data entries. The data processing circuit further divides the plurality of chip signal channels into at least a plurality of chip signal channel groups, each chip signal channel group including at least one first chip signal channel group and at least one second chip signal channel group. The at least one first chip signal channel group and the at least one second chip signal channel group each correspond to at least one first panel signal channel group and the at least one second panel signal channel in a plurality of panel signal channel groups. Each panel signal channel group includes a plurality of panel signal channels. In each first chip signal channel group, multiple first chip signal channels are connected to multiple first panel signal channels of the corresponding first panel signal channel group in a first connection configuration. In each second chip signal channel group, multiple second chip signal channels are connected to multiple second panel signal channels of the corresponding second panel signal channel group in a second connection pattern, wherein the first connection pattern and the second connection pattern are opposite. The data processing circuit is further configured to control the order in which the multiple display data entries are filled into the multiple chip signal channels based on the first connection state and the second connection state.

2. The display driver chip according to claim 1, characterized in that, The first connection state refers to the (i+1)th first chip signal channel in each first chip signal channel group being connected to the (i+1)th first panel signal channel in the corresponding first panel signal channel group, where i is an integer from 0 to N-1, and N is the total number of the plurality of first chip signal channels in the first chip signal channel group. The second connection state refers to the Mj-th second chip signal channel in each second chip signal channel group being connected to the (j+1)-th second panel signal channel in the corresponding second panel signal channel group, where j is an integer from 0 to M-1, and M is the total number of the plurality of second chip signal channels in the second chip signal channel group.

3. The display driver chip according to claim 2, characterized in that, The data processing circuit mentioned above includes: A shift register is used to temporarily store the multiple display data entries; and A drive control circuit, electrically connected to the shift register, is used to control the filling of the multiple display data entries from the shift register into the multiple chip signal channels based on the first connection state and the second connection state.

4. The display driver chip according to claim 3, characterized in that, The drive control circuit is further used for: The N first display data corresponding to each first chip signal channel group are sequentially filled into the first first chip signal channel to the Nth first chip signal channel in the first chip signal channel group; as well as The M second display data corresponding to each second chip signal channel group are sequentially filled into the Mth second chip signal channel to the 1st second chip signal channel in the second chip signal channel group.

5. The display driver chip according to claim 3, characterized in that, The data processing circuit further includes: The timing controller, electrically connected to the drive control circuit, is used to: Before the multiple display data entries are input to the multiple chip signal channels, the arrangement order of the M second display data entries corresponding to each second chip signal channel group is adjusted.

6. The display driver chip according to claim 5, characterized in that, The timing controller is further used for: For each of the M second display data corresponding to the second chip signal channel group, the first to the Mth second display data in the M second display data are sorted in reverse order to obtain the M adjusted second display data.

7. The display driver chip according to claim 6, characterized in that, The drive control circuit is further used for: The N first display data corresponding to each first chip signal channel group are sequentially filled into the first first chip signal channel to the Nth first chip signal channel in the first chip signal channel group; as well as The M-pen adjusted second display data corresponding to each second chip signal channel group are sequentially filled into the first to the Mth second chip signal channels in that second chip signal channel group.

8. The display driver chip according to claim 1, characterized in that, The display module has a glass substrate, and the pixel array and the plurality of source lines are formed on the glass substrate.

9. The display driver chip according to claim 3, characterized in that, The drive control circuit is further used for: A delay time is applied to each first chip signal channel group so that the first signal drive time curve of the first chip signal channel group and the second signal drive time curve of the adjacent second chip signal channel group form a continuous drive timing.

10. The display driver chip according to claim 9, characterized in that, The drive control circuit is further used for: The signal drive time difference between the first signal drive time curve of the first chip signal channel group and the second signal drive time curve of the adjacent second chip signal channel group is detected. as well as Based on the signal driving time difference, the delay time is applied to multiple first display data output by multiple first chip signal channels of the first chip signal channel group, so that the delayed first signal driving time curve and the second signal driving time curve form a continuous driving timing sequence.

11. A display module, characterized in that, include: Pixel array; Multiple panel signal channels are formed on a glass substrate, wherein the pixel array is electrically connected to the multiple panel signal channels; as well as Display driver chips include: Multiple metal bumps are disposed on the first boundary of the display driver chip, wherein each of the multiple metal bumps corresponds to a multiple chip signal channel of the display driver chip, and the multiple metal bumps are electrically connected to the multiple panel signal channels through multiple source lines respectively. as well as The data processing circuit is used to receive multiple display data entries. The data processing circuit further divides the plurality of chip signal channels into at least a plurality of chip signal channel groups, each chip signal channel group including at least one first chip signal channel group and at least one second chip signal channel group. The at least one first chip signal channel group and the at least one second chip signal channel group each correspond to at least one first panel signal channel group and at least one second panel signal channel group in a plurality of panel signal channel groups. Each panel signal channel group includes a plurality of panel signal channels. In each first chip signal channel group, multiple first chip signal channels are connected to multiple first panel signal channels of the corresponding first panel signal channel group in a first connection configuration. In each second chip signal channel group, multiple second chip signal channels are connected to multiple second panel signal channels of the corresponding second panel signal channel group in a second connection pattern, wherein the first connection pattern and the second connection pattern are opposite. The data processing circuit is further configured to control the order in which the multiple display data entries are filled into the multiple chip signal channels based on the first connection state and the second connection state.

12. The display module according to claim 11, characterized in that, The first connection state refers to the (i+1)th first chip signal channel in each first chip signal channel group being connected to the (i+1)th first panel signal channel in the corresponding first panel signal channel group, where i is an integer from 0 to N-1, and N is the total number of the plurality of first chip signal channels in the first chip signal channel group. The second connection state refers to the Mj-th second chip signal channel in each second chip signal channel group being connected to the (j+1)-th second panel signal channel in the corresponding second panel signal channel group, where j is an integer from 0 to M-1, and M is the total number of the plurality of second chip signal channels in the second chip signal channel group.

13. The display module according to claim 12, characterized in that, The data processing circuit mentioned above includes: A shift register is used to temporarily store the multiple display data entries; and A drive control circuit, electrically connected to the shift register, is used to control the filling of the multiple display data entries from the shift register into the multiple chip signal channels based on the first connection state and the second connection state.

14. The display module according to claim 13, characterized in that, The drive control circuit is further configured to: The N first display data corresponding to each first chip signal channel group are sequentially filled into the first first chip signal channel to the Nth first chip signal channel in the first chip signal channel group; as well as The M second display data corresponding to each second chip signal channel group are sequentially filled into the Mth second chip signal channel to the 1st second chip signal channel in the second chip signal channel group.

15. The display module according to claim 13, characterized in that, The data processing circuit further includes: The timing controller, electrically connected to the drive control circuit, is used to: Before the multiple display data entries are input to the multiple chip signal channels, the arrangement order of the M second display data entries corresponding to each second chip signal channel group is adjusted.

16. The display module according to claim 15, characterized in that, The timing controller is further used for: For each of the M second display data corresponding to the second chip signal channel group, the first to the Mth second display data in the M second display data are sorted in reverse order to obtain the M adjusted second display data.

17. The display module according to claim 16, characterized in that, The drive control circuit is further used for: The N first display data corresponding to each first chip signal channel group are sequentially filled into the first first chip signal channel to the Nth first chip signal channel in the first chip signal channel group; as well as The M-pen adjusted second display data corresponding to each second chip signal channel group are sequentially filled into the first to the Mth second chip signal channels in that second chip signal channel group.

18. The display module according to claim 11, characterized in that, The plurality of source lines are formed on the glass substrate.

19. The display module according to claim 13, characterized in that, The drive control circuit is further used for: A delay time is applied to each first chip signal channel group so that the first signal drive time curve of the first chip signal channel group and the second signal drive time curve of the adjacent second chip signal channel group form a continuous drive timing.

20. The display module according to claim 19, characterized in that, The drive control circuit is further used for: The signal drive time difference between the first signal drive time curve of the first chip signal channel group and the second signal drive time curve of the adjacent second chip signal channel group is detected. as well as Based on the signal driving time difference, the delay time is applied to multiple first display data output by multiple first chip signal channels of the first chip signal channel group, so that the first signal driving time curve and the second signal driving time curve form a continuous driving timing sequence.

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