Pixel circuits and their driving methods, display panels

Abstract

This invention relates to the field of display technology, and specifically discloses a pixel circuit and its driving method, as well as a display panel. A first storage module is connected between a first node and the control terminal of a driving module; a first switch module is connected between a first terminal of the driving module and the control terminal, and conducts the first terminal of the driving module and the control terminal at least during the threshold compensation stage according to a first control signal; a second switch module is connected between the first node and a second node, and conducts the first node and the second node at least during the threshold compensation stage and the data writing stage according to a second control signal; a data writing module is connected to the second node, and transmits a data signal to the second node during the data writing stage according to a first scan signal; a first initialization module is connected between the second node and a first initialization signal line, and conducts the second node and the first initialization signal line at least during the threshold compensation stage according to the first control signal; the first terminal of the second storage module is connected to the first node.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a pixel circuit and its driving method, and a display panel. Background Technology

[0002] With the continuous development of display technology, the application range of display panels is becoming increasingly wide, and people's requirements for display panels are also getting higher and higher. Organic Light Emitting Display (OLED) flat panel display devices are widely used in various consumer electronics products such as mobile phones, televisions, laptops, and desktop computers due to their advantages such as high image quality, energy saving, thin body, and wide application range, becoming the mainstream display device. However, the display performance of OLED products still needs improvement. Summary of the Invention

[0003] Therefore, it is necessary to provide a pixel circuit and its driving method, as well as a display panel, to address the issue of the need to improve the performance of existing display products.

[0004] A pixel circuit, comprising: The driver module is connected between the first power line and the light-emitting module and is used to output drive signals; A first storage module is connected between the first node and the control terminal of the drive module, and is used to store the voltage difference between the first node and the control terminal of the drive module; A first switch module is connected between the first end of the drive module and the control end, and is used to conduct the connection between the first end of the drive module and the control end according to the first control signal at least during the threshold compensation stage; A second switch module is connected between the first node and the second node, and is used to activate the connection between the first node and the second node at least during the threshold compensation stage and the data writing stage according to a second control signal; wherein, the second node is located on the signal transmission path from the driving module to the light-emitting module; A data writing module, connected to the second node, is used to transmit a data signal to the second node during the data writing stage according to the first scan signal; A first initialization module is connected between the second node and the first initialization signal line, and is used to conduct the connection between the second node and the first initialization signal line at least during the threshold compensation stage according to a first control signal; The second storage module has a first end connected to the first node, and a second end of the second storage module is connected to a second initialization signal at least during the threshold compensation phase and the data writing phase.

[0005] In one possible implementation, the driving module includes a first transistor, the gate of the first transistor serving as the control terminal of the driving module, the first electrode of the first transistor serving as the first terminal of the driving module, and the second electrode of the first transistor serving as the second terminal of the driving module.

[0006] In one possible implementation, the first switching module includes a second transistor, the gate of the second transistor serves as the control terminal of the first switching module and is connected to the first control signal, the first electrode of the second transistor serves as the first terminal of the first switching module and is connected to the first terminal of the driving module, and the second electrode of the second transistor serves as the second terminal of the first switching module and is connected to the control terminal of the light-emitting module.

[0007] In one possible implementation, the second switching module includes a third transistor, the gate of which serves as the control terminal of the second switching module and is connected to the second control signal, the first terminal of which serves as the first terminal of the second switching module and is connected to the first node, and the second terminal of which serves as the second terminal of the second switching module and is connected to the second node.

[0008] In one possible implementation, the data writing module includes a fourth transistor, the gate of which serves as the control terminal of the data writing module and is connected to the first scan signal, the first electrode of which serves as the first terminal of the data writing module and is connected to the data signal, and the second electrode of which serves as the second terminal of the data writing module and is connected to the second node.

[0009] In one possible implementation, the first initialization module includes a fifth transistor, the gate of which serves as the control terminal of the first initialization module and is connected to the first control signal, the first electrode of which serves as the first terminal of the first initialization module and is connected to the first initialization signal line, and the second electrode of which serves as the second terminal of the first initialization module and is connected to the second node.

[0010] In one possible implementation, the first storage module includes a first capacitor, with a first terminal of the first capacitor connected to the first node as a first end of the first storage module, and a second terminal of the first capacitor connected to the control terminal of the drive module as a second end of the first storage module.

[0011] In one possible implementation, the second storage module includes a second capacitor, with the first terminal of the second capacitor serving as the first end of the second storage module and connected to the first node, and the second terminal of the second capacitor serving as the second end of the second storage module.

[0012] In one possible implementation, the pixel circuit further includes: A third switch module is connected between the second end of the drive module and the second node, and is used to conduct the connection between the second end of the drive module and the second node according to a third control signal during the threshold compensation stage and the data writing stage.

[0013] In one possible implementation, the third switching module includes a sixth transistor, the gate of which serves as the control terminal of the third switching module and is connected to the third control signal, the first terminal of which serves as the first terminal of the third switching module and is connected to the second terminal of the driving module, and the second terminal of which serves as the second terminal of the third switching module and is connected to the second node.

[0014] In one possible implementation, the pixel circuit further includes: A first light-emitting control module is connected between the first power line and the first end of the driving module, and is used to conduct the connection between the first power line and the first end of the driving module according to the fourth control signal during the first initialization phase and the first light-emitting phase.

[0015] In one possible implementation, the first light-emitting control module includes a seventh transistor, the gate of which serves as the control terminal of the first light-emitting control module and is connected to the fourth control signal, the first electrode of which serves as the first terminal of the first light-emitting control module and is connected to the first power line, and the second electrode of which serves as the second terminal of the first light-emitting control module and is connected to the first terminal of the driving module.

[0016] In one possible implementation, the pixel circuit further includes: A light-emitting module, connected between the second node and the second power line, is used to emit light according to the driving signal; The second light-emitting control module is connected between the second node and the first end of the light-emitting module, and is used to conduct the connection between the second node and the first end of the light-emitting module in the first light-emitting stage according to the fifth control signal.

[0017] In one possible implementation, the second light-emitting control module includes an eighth transistor, the gate of which serves as the control terminal of the second light-emitting control module and is connected to the fifth control signal, the first electrode of which serves as the first terminal of the second light-emitting control module and is connected to the second node, and the second electrode of which serves as the second terminal of the second light-emitting control module and is connected to the first terminal of the light-emitting module.

[0018] In one possible implementation, the pixel circuit further includes: The second initialization module is connected to the first end of the light-emitting module and the second end of the second storage module, and is used to transmit the second initialization signal to the first end of the light-emitting module and the second end of the second storage module according to the fifth control signal during the first initialization stage, the threshold compensation stage and the data writing stage.

[0019] In one possible implementation, the second initialization module includes a ninth transistor, the gate of which serves as the control terminal of the second initialization module and is connected to the fifth control signal, the first terminal of which serves as the first terminal of the second initialization module and is connected to the second initialization signal, and the second terminal of which serves as the second terminal of the second initialization module and is connected to the first terminal of the light-emitting module and the second terminal of the second storage module.

[0020] In one possible implementation, the pixel circuit includes a write frame in one working cycle. The write frame includes at least a first initialization phase. In the first initialization phase, the first initialization module transmits a first initialization signal to the second node according to the first control signal. The second switching module connects the connection between the first node and the second node according to the second control signal. The second initialization module transmits a second initialization signal to the second terminal of the first storage module according to the fifth control signal. The first light emission control module connects the connection between the first power line and the first terminal of the driving module according to the fifth control signal. The first switching module connects the connection between the first terminal of the driving module and the control terminal according to the first control signal.

[0021] In one possible implementation, after the initialization phase, the write frame includes a threshold compensation phase. In the threshold compensation phase, the second switch module connects the connection between the first node and the second node according to the second control signal, the first initialization module connects the connection between the first end of the driver module and the control end according to the first control signal, the second initialization module transmits the second initialization signal to the second end of the first storage module according to the fifth control signal, the first switch module connects the connection between the first end of the driver module and the control end according to the first control signal, the third switch module connects the connection between the second end of the driver module and the second node according to the third control signal, and the control end of the driver module discharges to the first initialization signal line sequentially through the second switch module, the driver module, the third switch module and the first initialization module to perform threshold compensation on the driver module.

[0022] In one possible implementation, after the threshold compensation phase, the write frame includes a data write phase, in which the data write module transmits the data signal to the second node according to the first scan signal, the second switch module connects the connection between the first node and the second node according to the second control signal, the third switch module connects the connection between the second end of the drive module and the second node according to the third control signal, and the second initialization module transmits the second initialization signal to the second end of the first storage module according to the fifth control signal.

[0023] In one possible implementation, after the data writing phase, the write frame includes a first light-emitting phase, in which the first light-emitting control module activates the connection between the first power line and the first end of the drive module according to the fourth control signal, the third switch module activates the connection between the second end of the drive module and the second node according to the third control signal, and the second light-emitting control module activates the connection between the second node and the first end of the light-emitting module according to the fifth control signal.

[0024] In one possible implementation, the pixel circuit includes a hold frame in one operating cycle, wherein the levels of the first control signal and the second control signal are the cutoff levels of the first switching module, the second switching module, and the first initialization module in the hold frame.

[0025] In one possible implementation, the timing waveform of the third control signal in the write frame is the same as the timing waveform in the hold frame, the timing waveform of the fourth control signal in the write frame is the same as the timing waveform in the hold frame, and the timing waveforms of the fifth control signal and the first scan signal in the write frame are the same as the timing waveforms in the hold frame.

[0026] In one possible implementation, the first control signal and the second control signal originate from the same set of shift registers.

[0027] In one possible implementation, the pixel circuit includes at least one of a metal-oxide-semiconductor transistor and a low-temperature polysilicon transistor.

[0028] In one possible implementation, the pixel circuit includes at least one metal oxide transistor and at least one low-temperature polysilicon transistor.

[0029] In one possible implementation, the driving module, the first switch module, the second switch module, the first initialization module, and the second initialization module all include metal-oxide transistors, and the data writing module, the third switch module, the first light-emitting control module, and the second light-emitting control module all include low-temperature polycrystalline silicon transistors.

[0030] In one possible implementation, the driving module, the first switch module, the second switch module, the first initialization module, and the second initialization module all include N-type transistors, and the data writing module, the third switch module, the first light-emitting control module, and the second light-emitting control module all include P-type transistors.

[0031] A driving method for a pixel circuit, used to drive a pixel circuit as described in any of the above embodiments, wherein a working cycle of the pixel circuit includes a write frame, the write frame including at least a first initialization stage, a threshold compensation stage, a data writing stage, and a first emission stage, the driving method comprising: During the first initialization phase, the level of the first control signal is configured to a first level, the level of the second control signal is configured to a first level, and the level of the first scan signal is configured to a first level. During the threshold compensation stage, the level of the first control signal is configured to a first level, the level of the second control signal is configured to a first level, and the level of the first scan signal is configured to a first level. During the data writing phase, the level of the first control signal is configured to a second level, the level of the second control signal is configured to a first level, and the level of the first scan signal is configured to a second level. During the first light emission stage, the level of the first control signal is configured to a second level, the level of the second control signal is configured to a second level, and the level of the first scan signal is configured to a first level, wherein the first level is greater than the second level.

[0032] In one possible implementation, the driving method further includes: During the first initialization phase, the level of the third control signal is configured to a first level, the level of the fourth control signal is configured to a second level, and the level of the fifth scan signal is configured to a first level. During the threshold compensation stage, the level of the third control signal is configured to the second level, the level of the fourth control signal is configured to the first level, and the level of the fifth scan signal is configured to the first level. During the data writing phase, the level of the third control signal is configured to the second level, the level of the fourth control signal is configured to the first level, and the level of the fifth scan signal is configured to the first level. During the first light emission stage, the level of the third control signal is configured to the second level, the level of the fourth control signal is configured to the second level, and the level of the fifth scan signal is configured to the second level.

[0033] In one possible implementation, the pixel circuit includes a hold frame in one operating cycle, wherein the levels of the first control signal and the second control signal are at a second level in the hold frame.

[0034] In one possible implementation, the timing waveform of the third control signal in the write frame is the same as the timing waveform in the hold frame, the timing waveform of the fourth control signal in the write frame is the same as the timing waveform in the hold frame, and the timing waveforms of the fifth control signal and the first scan signal in the write frame are the same as the timing waveforms in the hold frame.

[0035] In one possible implementation, the first control signal and the second control signal originate from the same set of shift registers.

[0036] A display panel includes a pixel circuit as described in any of the above embodiments. The display panel further includes multiple sets of shift register units. The first control signal and the second control signal accessed in the pixel circuit originate from the same set of shift register units. The third control signal, the fourth control signal, the fifth control signal, and the first scan signal accessed in the pixel circuit originate from different sets of shift register units. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1 This is a schematic diagram of the structure of the first pixel circuit provided in the embodiments of this application; Figure 2 A schematic diagram of the circuit structure of a first pixel circuit provided in an embodiment of this application; Figure 3 This is a schematic diagram of the structure of the second pixel circuit provided in the embodiments of this application; Figure 4 A schematic diagram of the circuit structure of the second pixel circuit provided in the embodiments of this application; Figure 5 This is a schematic diagram of the structure of the third pixel circuit provided in the embodiments of this application; Figure 6 A schematic diagram of the circuit structure of the third pixel circuit provided in the embodiments of this application; Figure 7 This is a schematic diagram of the structure of the fourth pixel circuit provided in the embodiments of this application; Figure 8 A schematic diagram of the circuit structure of the fourth pixel circuit provided in the embodiments of this application; Figure 9 This is a schematic diagram of the signal timing of a pixel circuit during frame writing, provided in an embodiment of this application. Figure 10 This is a schematic diagram of the signal timing of a pixel circuit in a holding frame, provided in an embodiment of this application. Figure 11 This is a flowchart illustrating the driving method of the pixel circuit in one embodiment of this application. Detailed Implementation

[0039] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of the invention.

[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0041] When using the terms “including,” “having,” and “comprising” as described herein, another component may be added unless explicitly qualifying terms such as “only,” “consisting of,” etc. are used. Unless otherwise stated, singular terms may include plural forms and should not be construed as having a quantity of one.

[0042] It should be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this application, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0043] In this application, unless otherwise expressly specified and limited, the terms "connected" and "linked" should be interpreted broadly. For example, they can refer to a direct connection or an indirect connection through an intermediate medium, or they can refer to the internal connection of two elements or the interaction between two elements. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0044] With the continuous development of display technology, people's demand for high refresh rate products is increasing. Currently, due to the large differences in the characteristics of small / medium-sized TFT (Thin Film Transistor) devices, it is easy to cause uneven image quality, such as mura (i.e., uneven brightness, with the unevenness being more severe at low gray levels). Figure 1 The first pixel circuit provided in this application embodiment is shown in a schematic diagram. In one possible implementation, the pixel circuit may include a driving module 110, a first switching module 120, a second switching module 130, a data writing module 140, a first initialization module 150, a first storage module 210, and a second storage module 220.

[0045] The driving module 110 can be located between the first power line and the light-emitting module. The driving module 110 can be used to output a driving signal according to the voltage at its control terminal. The first power line can output a first power signal VDD to the pixel circuit to provide the voltage required for operation. The first storage module 210 can be connected between the first node N1 and the control terminal G of the driving module 110. The first storage module 210 can be configured to store the voltage difference between the first node N1 and the control terminal G of the driving module 110. In some specific embodiments, the first terminal of the first storage module 210 can be connected to the second switch module 130 and the second storage module 220 at the first node N1, and the second terminal of the first storage module 210 can be connected to the control terminal of the driving module 110.

[0046] The first switch module 120 can be connected between the first terminal and the control terminal of the drive module 110. The first switch module 120 can be configured to control the connection between the first terminal and the control terminal of the drive module 110 to be turned on or off according to the first control signal EMB1. In some specific embodiments, the first terminal of the first switch module 120 can be connected to the first terminal of the drive module 110, the control terminal of the first switch module 120 can be connected to the first control signal EMB1, and the second terminal of the first switch module 120 can be connected to the control terminal of the drive module 110. The first switch module 120 can be configured to turn on the connection between the first terminal and the control terminal of the drive module 110 at least during the threshold compensation stage. Further, the first control signal EMB1 can be output by a gate in panel (GIP) circuit located in the non-display area (also commonly referred to as the bezel area) of the array substrate.

[0047] The second switch module 130 can be connected between the first node N1 and the second node N2. The second switch module 130 can be configured to control the connection between the first node N1 and the second node N2 based on the second control signal EMB2. In some specific embodiments, the first terminal of the second switch module 130 can be connected to the first node N1, the control terminal of the second switch module 130 can be connected to the second control signal EMB2, and the second terminal of the second switch module 130 can be connected to the second node N2. The second switch module 130 can be configured to enable the connection between the first node N1 and the second node N2 at least during the threshold compensation phase and the data writing phase. Further, the second control signal EMB2 can also be output by a shift register unit located in the non-display area of ​​the array substrate.

[0048] The data writing module 140 can be connected to the second node N2, and can be configured to transmit the data signal Vdata to the second node N2 according to the first scan signal S1. In some specific embodiments, the first end of the data writing module 140 can be connected to a data line, and the data line can transmit the data signal Vdata to the first end of the data writing module 140. The control end of the data writing module 140 can be connected to the first scan line, and the first scan line can transmit the first scan signal S1 to the control end of the data writing module 140. The second end of the data writing module 140 can be connected to the second node N2. The data writing module 140 can be configured to transmit the data signal Vdata to the second node N2 during the data writing phase, so that the data writing module 140 can transmit the data signal Vdata to the second node N2 according to the control of the first scan signal S1. Further, the first scan signal S1 can also be output by a shift register unit located in the non-display area of ​​the array substrate.

[0049] The first initialization module 150 can be connected between the first initialization signal line and the second node N2. The first initialization module 150 can be configured to turn on or off the connection between the first initialization signal line and the second node N2 according to a first control signal. In some specific embodiments, the first end of the first initialization module 150 can be connected to the first initialization signal line, and the first initialization signal line can transmit the first initialization signal Vini to the first end of the first initialization module 150. The control end of the first initialization module 150 can be connected to the first control signal EMB1, and the second end of the first initialization module 150 can be connected to the second node N2, so that the threshold compensation module 400 can turn on the connection between the first initialization signal line and the second node N2 at least during the threshold compensation phase.

[0050] The first terminal of the second storage module 220 can be connected to the first node N1, and the second terminal of the second storage module 220 can be connected to the second initialization signal Vref at least during the threshold compensation phase and the data writing phase. That is, the second terminal of the second storage module 220 is maintained at a fixed potential Vref at least during the threshold compensation phase and the data writing phase. The second storage module 220 can be configured to store potential changes at the first node N1.

[0051] In the pixel circuit provided in this application, during the threshold compensation stage, the connection between the control terminal of the driving module 110 and the first terminal is made conductive, and the connection between the second node and the first initialization signal line is made conductive, so that the control terminal of the driving module 110 can discharge to the first initialization signal line until the driving module 110 is turned off. During this process, the threshold voltage information of the driving module 110 can be stored in the first storage module 210. During the data writing stage, the connection between the second node N2 and the first node N1 is made conductive, and the data signal Vdata can be transmitted to the first node N1. The second storage module 220 stores the data signal Vdata according to the potential change at the first node N1. Furthermore, the first storage module 160 and the second storage module 220 can couple the threshold-compensated data signal Vdata to the control terminal of the driving module 110 instantaneously through coupling. It can be seen that the pixel circuit described above can achieve fast data writing through coupling, and can achieve high-frequency driving. At the same time, by compensating the threshold voltage of the driving module 110, the influence of TFT device characteristic differences on the driving effect can be reduced, and the display uniformity can be improved. In addition, the threshold compensation process in the pixel circuit is separated from the data writing process, so the threshold compensation time is adjustable and is not affected by the data writing time. This allows for sufficient threshold compensation of the drive module 110, thereby ensuring uniformity while achieving high-frequency drive.

[0052] This application proposes a coupled driving scheme that can achieve high-frequency, high-brightness driving. By adopting a new circuit architecture formed by modules such as driving module 110, first switch module 120, second switch module 130, data writing module 140, first initialization module 150, first storage module 210 and second storage module 220, and coordinating the timing of various input signals, it can not only realize functions such as resetting each node in the circuit and threshold compensation of driving module 110, thereby improving image retention, crosstalk and enhancing brightness uniformity, but also realize high-frequency driving and high-brightness display.

[0053] In embodiments of this disclosure, a transistor can refer to a device that includes at least a gate, a drain, and a source. In this disclosure, the first terminal of a transistor can be the drain and the second terminal can be the source, or vice versa. When using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged. In embodiments of this disclosure, the first and second terminals of all or some transistors can be interchanged as needed.

[0054] It should be noted that the transistors in the embodiments of this application can be either N-type or P-type transistors. For N-type transistors, the on-level is high and the off-level is low. That is, when the gate of an N-type transistor is high, its first and second terminals are connected; when the gate of an N-type transistor is low, its first and second terminals are off. For P-type transistors, the on-level is low and the off-level is high. That is, when the control terminal of a P-type transistor is low, its first and second terminals are connected; when the control terminal of a P-type transistor is high, its first and second terminals are off. Furthermore, the on-level and off-level in the embodiments of this invention are general terms; the on-level refers to any level that enables the transistor to conduct, and the off-level refers to any level that enables the transistor to turn off / become off.

[0055] Figure 2 This is a schematic diagram of the circuit structure of a first pixel circuit provided in an embodiment of this application. In one possible implementation, the driving module 110 may include a first transistor M1, the gate of which may serve as the control terminal of the driving module 110. The first electrode of the first transistor M1 may serve as the first terminal of the driving module 110, and the second electrode of the first transistor M1 may serve as the second terminal of the driving module 110.

[0056] In one possible implementation, the first switching module 120 may include a second transistor M2. The gate of the second transistor M2 can be used as the control terminal of the first switching module 120 and connected to the first control signal EMB1. The first terminal of the second transistor M2 can be used as the first terminal of the first switching module 120 and connected to the first terminal of the driving module 110. The second terminal of the second transistor M2 can be used as the second terminal of the first switching module 120 and connected to the control terminal of the driving module 110. More specifically, the first terminal of the second transistor M2 is connected to the first terminal of the first transistor M1, and the second terminal of the second transistor M2 is connected to the gate G of the first transistor M1.

[0057] In one possible implementation, the second switching module 130 may include a third transistor M3. The gate of the third transistor M3 may be used as the control terminal of the second switching module 130 and connected to the second control signal EMB2. The first terminal of the third transistor M3 may be used as the first terminal of the second switching module 130 and connected to the first node N1. The second terminal of the third transistor M3 may be used as the second terminal of the second switching module 130 and connected to the second node N2.

[0058] In one possible implementation, the data writing module 140 may include a fourth transistor M4. The gate of the fourth transistor M4 can be used as the control terminal of the data writing module 140 to connect to the first scan signal S1. The first terminal of the fourth transistor M4 can be used as the first terminal of the data writing module 140, and the second terminal of the fourth transistor M4 can be used as the second terminal of the data writing module 140. The gate of the fourth transistor M4 can be connected to the first scan line to connect to the first scan signal S1. The first terminal of the second transistor M2 can be connected to the data line to connect to the data signal Vdata, and the second terminal of the second transistor M2 can be connected to the second node N2.

[0059] In one possible implementation, the first initialization module 150 may include a fifth transistor M5. The gate of the fifth transistor M5 can serve as the control terminal of the first initialization module 150, the first terminal of the fifth transistor M5 can serve as the first terminal of the first initialization module 150, and the second terminal of the fifth transistor M5 can serve as the second terminal of the first initialization module 150. The gate of the fifth transistor M5 can be connected to a first control signal EMB1, the first terminal of the fifth transistor M5 can be connected to a first initialization signal line to receive a first initialization signal Vini, and the second terminal of the fifth transistor M5 can be connected to a second node N2.

[0060] In one possible implementation, the first storage module 210 may include a first capacitor C1. The first terminal of the first capacitor C1 can be connected to the first node N1 as the first end of the first storage module 210, and the second terminal of the first capacitor C1 can be connected to the control terminal of the driving module 110 as the second end of the first storage module 210. More specifically, the second terminal of the first capacitor C1 is connected to the gate G of the first transistor M1.

[0061] In one possible implementation, the second storage module 220 may include a second capacitor C2, the first terminal of the second capacitor C2 may be connected to the first node N1 as the first end of the second storage module 220, and the second terminal of the second capacitor C2 may be used as the second end of the second storage module 220.

[0062] Figure 3 This is a schematic diagram of a second pixel circuit provided in an embodiment of this application. In one embodiment, the pixel circuit may further include a third switch module 160. The third switch module 160 may be connected between the second terminal S of the driving module 110 and the second node N2. The third switch module 160 may be configured to turn on or off the connection between the second terminal of the driving module 110 and the second node N2 according to a third control signal EM3. Specifically, the third switch module 160 may be configured to turn on the connection between the second terminal of the driving module 110 and the second node N2 during the threshold compensation stage and the data writing stage. In some specific embodiments, the third switch module 160 may be connected to the second terminal of the driving module 110, the control terminal of the third switch module 160 may be connected to the third control signal EM3, and the second terminal of the third switch module 160 may be connected to the second node N2. Further, the third control signal EM3 may also be output by a shift register unit located in the non-display area of ​​the array substrate.

[0063] Figure 4 This is a schematic diagram of the circuit structure of a second pixel circuit provided in an embodiment of this application. In one possible implementation, the third switching module 160 may include a sixth transistor M6. The gate of the sixth transistor M6 can serve as the control terminal of the third switching module 160, the first terminal of the sixth transistor M6 can serve as the first terminal of the third switching module 160, and the second terminal of the sixth transistor M6 can serve as the second terminal of the third switching module 160. The gate of the sixth transistor M6 can be connected to a third control signal EM3, the first terminal of the sixth transistor M6 can be connected to the second terminal of the driving module 110, and the second terminal of the sixth transistor M6 can be connected to the second node N2.

[0064] Figure 5This is a schematic diagram of the structure of a third pixel circuit provided in an embodiment of this application. In one possible implementation, the pixel circuit may further include a first light-emitting control module 170. The first light-emitting control module 170 may be connected between a first power supply line and a first terminal of a driving module 110. The first light-emitting control module 170 is configured to conduct the connection between the first power supply line and the first terminal of the driving module 110 according to a fourth control signal EM1 during a first initialization phase and a first light-emitting phase. In some specific embodiments, the first terminal of the first light-emitting control module 170 may be connected to the first power supply line, the control terminal of the first light-emitting control module 170 may be connected to the fourth control signal EM1, and the second terminal of the first light-emitting control module 170 may be connected to the first terminal of the driving module 110. Further, the fourth control signal EM1 may also be output by a shift register unit located in the non-display area of ​​the array substrate.

[0065] Figure 6 This is a schematic diagram of the circuit structure of a third pixel circuit provided in an embodiment of this application. In one possible implementation, the first light-emitting control module 170 may include a seventh transistor M7. The gate of the seventh transistor M7 can serve as the control terminal of the first light-emitting control module 170, the first electrode of the seventh transistor M7 can serve as the first terminal of the first light-emitting control module 170, and the second electrode of the seventh transistor M7 can serve as the second terminal of the first light-emitting control module 170. The gate of the seventh transistor M7 can be connected to a fourth control signal EM1, the first electrode of the seventh transistor M7 can be connected to a first power supply line, and the second electrode of the seventh transistor M7 can be connected to the first terminal of the driving module 110.

[0066] Figure 7 This is a schematic diagram of the structure of a fourth pixel circuit provided in an embodiment of this application. In one possible implementation, the pixel circuit may further include a light-emitting module 230, a second light-emitting control module 180, and a second initialization module 190. The light-emitting module 230 can be connected between the second terminal of the driving module 100 and the second power line, and the second power line can provide a second power signal VSS to the second terminal of the light-emitting module 230.

[0067] In this embodiment, a first power line is used to transmit a first power signal VDD, and a second power line is used to transmit a second power signal VSS. In one feasible implementation, the first power signal VDD is greater than the second power signal VSS. For example, the first power signal VDD can be a positive voltage, and the second power signal VSS can be a negative voltage.

[0068] In one possible implementation, the second light-emitting control module 180 can be connected between the second node N2 and the first end of the light-emitting module 230. The second light-emitting control module 180 can be configured to turn the connection between the second node N2 and the first end of the light-emitting module 230 on or off according to the fifth control signal EM2. The second light-emitting control module 180 can be configured to turn the connection between the second node N2 and the first end of the light-emitting module 230 on during a first light-emitting phase. In some specific implementations, the first end of the second light-emitting control module 180 can be connected to the second node N2, the control terminal of the second light-emitting control module 180 can be connected to the fifth control signal EM2, and the second end of the second light-emitting control module 180 can be connected to the first end of the light-emitting module 230. Further, the fifth control signal EM2 can also be output by a shift register unit located in the non-display area of ​​the array substrate.

[0069] In one possible implementation, the second initialization module 190 can be connected to the first terminal of the light-emitting module 700 and the second terminal of the second storage module 220. The second initialization module 190 can be configured to transmit a second initialization signal Vref to the first terminal of the light-emitting module 700 and the second terminal of the second storage module 220 according to the fifth control signal EM2. Specifically, the second initialization module 190 is configured to transmit the second initialization signal Vref to the first terminal of the light-emitting module 700 and the second terminal of the second storage module 220 during the first initialization phase, the threshold compensation phase, and the data writing module. In some specific implementations, the first terminal of the second initialization module 190 can be connected to the second initialization signal Vref, the control terminal of the second initialization module 190 can be connected to the fifth control signal EM2, and the second terminal of the second initialization module 190 can be connected to the first terminal of the light-emitting module 230 and the second terminal of the second storage module 220.

[0070] Figure 8 This is a schematic diagram of the circuit structure of the fourth pixel circuit provided in an embodiment of this application. In one possible implementation, the second light-emitting control module 180 may include an eighth transistor M8. The gate of the eighth transistor M8 can serve as the control terminal of the second light-emitting control module 180, the first electrode of the eighth transistor M8 can serve as the first terminal of the second light-emitting control module 180, and the second electrode of the eighth transistor M8 can serve as the second terminal of the second light-emitting control module 180. The gate of the eighth transistor M8 can be connected to a fifth control signal EM2, the first electrode of the eighth transistor M8 can be connected to a second node N2, and the second electrode of the eighth transistor M8 can be connected to the first terminal of the light-emitting module 230.

[0071] In one possible implementation, the second initialization module 190 may include a ninth transistor M9. The gate of the ninth transistor M9 can serve as the control terminal of the second initialization module 190, the first terminal of the ninth transistor M9 can serve as the first terminal of the second initialization module 190, and the second terminal of the ninth transistor M9 can serve as the second terminal of the second initialization module 190. The gate of the ninth transistor M9 can be connected to a fifth control signal EM2, the first terminal of the ninth transistor M9 can be connected to a second initialization signal line, the second initialization signal line can transmit a second initialization signal Vref to the first terminal of the ninth transistor M9, and the second terminal of the ninth transistor M9 can be connected to the first terminal of the light-emitting module 230 and the second terminal of the second storage module 220.

[0072] In one possible implementation, the light-emitting module 230 may include a light-emitting diode (OLED) D1. The OLED (Organic Light-Emitting Diode) may include an anode and a cathode, with the anode of the OLED D1 serving as the first terminal of the light-emitting module 230 and the cathode serving as the second terminal. When a driving signal output from the driving module 110 is transmitted to the OLED D1, the OLED D1 can emit light with a brightness corresponding to the driving signal.

[0073] In one possible implementation, the pixel circuit includes at least one of a metal-oxide-semiconductor (MOD) transistor and a low-temperature polysilicon (LTPS) transistor. The LTP transistor is a transistor fabricated using low-temperature polysilicon as the active semiconductor layer; the MOD transistor is a transistor fabricated using metal-oxide-semiconductor as the active semiconductor layer. The LTP transistor can be a P-type transistor or an N-type transistor, and the MOD transistor can be an N-type transistor.

[0074] In one possible implementation, the pixel circuit may include at least one metal-oxide transistor and at least one low-temperature polycrystalline silicon (LTPS) transistor. The metal-oxide material may be, for example, at least one of IGZO (Indium Gallium Zinc Oxide), IGTO (Indium Gallium Tin Oxide), and IZTO (Indium Zinc Tin Oxide). That is, the pixel circuit may be a circuit fabricated using LTPO (Low Temperature Poly Silicon-Oxide) technology, which is a hybrid OLED backplane technology combining LTPS (Low Temperature Polycrystalline Silicon) and IGZO (Indium Gallium Zinc Oxide). In one possible implementation, at least one of the first transistor M1, the second transistor M2, and the third transistors M3 through M9 is a metal-oxide transistor, and at least one is a low-temperature polycrystalline silicon transistor.

[0075] In one possible implementation, the driving module 110, the first switch module 120, the second switch module 130, the first initialization module 150, and the second initialization module 190 all include metal-oxide transistors (MOS transistors), and the data writing module 140, the third switch module 160, the first light-emitting control module 170, and the second light-emitting control module 180 all include low-temperature polysilicon transistors (LTPS). Specifically, the first transistor M1, the second transistor M2, the third transistor M3, the fifth transistor M5, and the ninth transistor M9 are N-type MOS transistors, and the fourth transistor M4, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 are P-type LPS transistors.

[0076] In one possible implementation, Figure 8 The pixel circuit shown is a 9T2C structure, in which the first transistor M1 is a DTFT (Driver Thin Film Transistor), and the remaining transistors are STFTs (Switch Thin Film Transistors).

[0077] Coupled-type circuits can instantaneously couple data signals to the gate of the driving transistor, thus allowing for greater use of coupled-type pixel circuits in high refresh rate applications. However, during frame switching (such as switching from high frequency to low frequency or vice versa), pixel circuits may experience screen flicker (i.e., unexpected brightness jumps) due to sudden changes in node potential.

[0078] The pixel circuit provided in this application can reset the control terminal and the first terminal of the driving module 110 using the first power signal VDD, reset the first node N1 and the second node N2 using the first initialization signal Vini, and reset the anode of the light-emitting diode D1 using the second initialization signal Vref, so as to eliminate the signal residue in the previous frame, avoid inter-frame potential changes, and thus improve the screen switching flicker problem.

[0079] In one possible implementation, the pixel circuit may include at least a write frame in one operating cycle, which is a display frame that updates the pixel data. The operation of one display frame may include a first initialization phase t11, a threshold compensation phase t12, a data writing phase t13, and a first emission phase t14.

[0080] Figure 9 This is a schematic diagram of the signal timing of a pixel circuit during frame writing, provided in one embodiment of this application. It can be applied to, for example... Figure 8 The pixel circuit shown in this embodiment is combined with Figure 8 and Figure 9 The working process of the pixel circuit provided in one embodiment of this application will be described in detail, but this should not be construed as limiting the scope of the invention. In this embodiment, the fourth transistor M4, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 in the pixel circuit are all P-type transistors, with a low conduction level and a high cutoff level; the first transistor M1, the second transistor M2, the third transistor M3, the fifth transistor M5, and the ninth transistor M9 are all N-type transistors, with a high conduction level VGH and a low cutoff level VGL.

[0081] In the first initialization phase t11, the levels of the first control signal EMB1, the second control signal EMB2, and the first scan signal S1 are all high (VGH). The second transistor M2 and the fifth transistor M5 are turned on according to the first control signal EM1, the third transistor M3 is turned on according to the second control signal EM2, and the fourth transistor M4 is turned off according to the first scan signal S1. Additionally, the level of the third control signal EM3 is high (VGH), the level of the fourth control signal EM1 is low (VGL), and the level of the fifth control signal EM2 is high (VGH). The sixth transistor M6 is turned off according to the third control signal EM3, the seventh transistor M7 is turned on according to the fourth control signal EM1, the eighth transistor M8 is turned off according to the fifth control signal EM2, and the ninth transistor M9 is turned on according to the fifth control signal EM2.

[0082] In the first initialization phase t11, after the seventh transistor M7 and the second transistor M2 are turned on, the first power signal VDD transmitted on the first power line can be transmitted sequentially through the seventh transistor M7 and the second transistor M2 to the first terminal D and the gate G of the first transistor M1. The first power signal VDD resets the first terminal D and the gate G of the first transistor M1, resulting in VG=VD=VDD. After the fifth transistor M5 and the third transistor M3 are turned on, the first initialization signal Vini transmitted on the first initialization signal line can be transmitted sequentially through the fifth transistor M5 and the third transistor M3 to the first node N1 and the second node N2. The first initialization signal resets the first node N1 and the second node N2, resulting in VN1=VN2=Vini. After the ninth transistor M9 is turned on, the second initialization signal Vref can be transmitted to the second terminal of the second capacitor C2 and the anode of the light-emitting diode D1. The second initialization signal Vref resets the second terminal of the second capacitor C2 and the anode of the light-emitting diode D1, resulting in VAno=Vref. In addition, the first transistor M1 is turned on according to the potential at its gate, so the potential at the second pole S point of the first transistor M1 is VS=VDD-Vth.

[0083] In one possible implementation, after the first initialization phase t11, the frame writing phase may include a threshold compensation phase t12. In the threshold compensation phase t12, the level of the first control signal EMB1 is high (VGH), the level of the second control signal EMB2 is high (VGH), and the level of the first scan signal S1 is high (VGH). The second transistor M2 and the fifth transistor M5 are turned on according to the first control signal EM1, the third transistor M3 is turned on according to the second control signal EM2, and the fourth transistor M4 is turned off according to the first scan signal S1. Additionally, the level of the third control signal EM3 is low (VGL), the level of the fourth control signal EM1 is high (VGH), and the level of the fifth control signal EM2 is high (VGH). The sixth transistor M6 is turned on according to the third control signal EM3, the seventh transistor M7 is turned off according to the fourth control signal EM1, the eighth transistor M8 is turned off according to the fifth control signal EM2, and the ninth transistor M9 is turned on according to the fifth control signal EM2.

[0084] During the threshold compensation phase t12, the gate G of the first transistor M1 discharges to Vini through the second transistor M2, the first transistor M1, the sixth transistor M6, and the fifth transistor M5, respectively, thus compensating for the threshold voltage Vth of the DTFT. The compensation process continues until the potential of the gate G and the first terminal D of the first transistor M1 becomes Vini + Vth, and this compensation time is adjustable. Furthermore, at this time, the potentials at the first node N1, the second node N2, and the second terminal S of the first transistor M1 are all Vini, VN1 = VN2 = VS = Vini. It can be seen that the first capacitor C1 stores the threshold information of the first transistor M1 (i.e., the driving transistor). At this time, the voltage difference across the first capacitor C1 is Vth. The second initialization signal Vref is still transmitted through the ninth transistor M9 to the second terminal of the second capacitor C2 and the anode of the light-emitting diode D1, VAno = Vref.

[0085] In one possible implementation, after the threshold compensation stage t12, the write frame may include a data write stage t13. During the data write stage t13, the level of the first control signal EMB1 is low (VGL), the level of the second control signal EMB2 is high (VGH), and the level of the first scan signal S1 is low (VGL). The second transistor M2 and the fifth transistor M5 are turned off according to the first control signal EM1, the third transistor M3 is turned on according to the second control signal EM2, and the fourth transistor M4 is turned on according to the first scan signal S1. Additionally, the level of the third control signal EM3 is low (VGL), the level of the fourth control signal EM1 is high (VGH), and the level of the fifth control signal EM2 is high (VGH). The sixth transistor M6 is turned on according to the third control signal EM3, the seventh transistor M7 is turned off according to the fourth control signal EM1, the eighth transistor M8 is turned off according to the fifth control signal EM2, and the ninth transistor M9 is turned on according to the fifth control signal EM2.

[0086] During the data writing phase t13, after the third transistor M3, the fourth transistor M4, and the sixth transistor M6 are turned on, the data signal Vdata transmitted on the data line is sequentially transmitted to the second node N2 and the first node N1 through the fourth transistor M4 and the third transistor M3. The data signal Vdata can also be transmitted to the second terminal S of the first transistor M1 through the sixth transistor M6. At this time, the potentials at the first node N1, the second node N2, and point S are all Vdata, that is, VN1=VN2=VS=Vdata. The second initialization signal Vref is still transmitted to the second terminal of the second capacitor C2 and the anode of the light-emitting diode D1 through the ninth transistor M9, VAno=Vref. The potential at the second terminal of the first capacitor C1 changes synchronously with the potential at its first terminal, that is, the potential at the gate G of the first transistor M1 becomes VG=Vth+data.

[0087] In one possible implementation, after the data writing stage t13, the write frame may include a first light-emitting stage t14. In the first light-emitting stage t14, the level of the first control signal EMB1 is low (VGL), the level of the second control signal EMB2 is low (VGL), and the level of the first scan signal S1 is high (VGH). The second transistor M2 and the fifth transistor M5 are turned off according to the first control signal EM1, the third transistor M3 is turned off according to the second control signal EM2, and the fourth transistor M4 is turned off according to the first scan signal S1. Additionally, the level of the third control signal EM3 is low (VGL), the level of the fourth control signal EM1 is low (VGL), and the level of the fifth control signal EM2 is low (VGL). The sixth transistor M6 is turned on according to the third control signal EM3, the seventh transistor M7 is turned on according to the fourth control signal EM1, the eighth transistor M8 is turned on according to the fifth control signal EM2, and the ninth transistor M9 is turned off according to the fifth control signal EM2.

[0088] During the first light-emitting stage t14, the first transistor M1, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 are turned on, while the rest are turned off.

[0089] The first capacitor C1 couples the data signal Vdata to the gate of the first transistor M1. The first transistor M1 can generate a drive signal based on its gate-source voltage. The drive current output by the first transistor M1 can be calculated as follows: I D =1 / 2*μ C OX (W / L)(Vgs-Vth) 2 In this circuit, the gate voltage of the first transistor M1 is VG = Vth + Vdata, and the source voltage is VS = Vref. This means the voltage difference between the gate and source of the first transistor M1 is Vgs = Vth + Vdata - Vref. Therefore, Vgs - Vth = Vdata - Vref, indicating that the driving current is a function of (Vdata - Vref). This function does not include VDD, VSS, or Vth. This demonstrates that the driving current output by this pixel circuit is unaffected by differences in VDD, VSS, and Vth at different locations on the display panel, providing good compensation for VDD, VSS, and Vth.

[0090] The drive current I output by the first transistor M1 D The current can be transmitted sequentially through the sixth transistor M6 and the eighth transistor M8 to the anode of the light-emitting diode D1, so that the light-emitting diode D1 can be driven by the driving current I. D Glowing light.

[0091] In one possible implementation, the first control signal EMB1 and the second control signal EMB2 can originate from the same set of shift registers. For example... Figure 9 As shown, the waveform of the second control signal EMB2 is the same as that of the first control signal EMB1. The difference is that the second control signal EMB2 is shifted by a preset time relative to the first control signal EMB1. That is, the first control signal EMB1 and the second control signal EMB2 can be generated by the same set of GIP circuits.

[0092] In the aforementioned pixel circuit, each node is reset during the first initialization phase t11, and there are no micro-short circuits between signals, effectively improving image retention and reducing power consumption. Simultaneously, in the pixel circuit, the gate G of the first transistor M1 and the first node N1 are each connected to only one TFT, effectively reducing the parasitic capacitance of the gate G of the first transistor M1 and the first node N1, thus improving crosstalk and brightness uniformity. When compensating for the threshold voltage Vth of the first transistor M1, the threshold voltage information Vth is stored in the first capacitor C1, and the compensation time for the threshold voltage is adjustable, enabling simultaneous compensation of multiple rows of pixel circuits, thereby achieving high-frequency driving. During data writing, the data signal Vdata is written to the second capacitor C2. The first capacitor C1 can couple the threshold-compensated data signal Vdata to the first transistor M1. Capacitive coupling enables rapid data writing without data range loss, achieving high-brightness display. In the pixel circuit, the second transistor M2 and the fifth transistor M5 are both controlled by the first control signal EMB1. The first control signal EMB1 and the second control signal EMB2 can be generated by the same set of GIP (Gate In Panel) circuits. The gate drive signals required in the circuit can be generated using 5 sets of GIP circuits, which is more conducive to layout and to achieving narrow bezels.

[0093] In one possible implementation, the pixel circuit may further include a hold frame in one duty cycle. The hold frame can be a display frame that does not update but only maintains the current image. The combination of the write frame and the hold frame can achieve a dynamic refresh rate and reduce power consumption. Specifically, the pixel circuit can operate at different refresh rates. At a high refresh rate, each display frame is a write frame; at a low refresh rate, at least one display frame can be designed as a write frame, and the other display frames as hold frames. The distinction between high and low refresh rates can be set according to different application requirements. For example, a refresh rate greater than or equal to 120Hz is considered a high refresh rate, and a refresh rate lower than 120Hz is considered a low refresh rate.

[0094] In one possible implementation, the levels of the first control signal EMB1 and the second control signal EMB2 can remain at the cutoff levels of the first switch module 120, the second switch module 130, and the first initialization module 150 during the hold frame, that is, the levels of the first control signal EMB1 and the second control signal EMB2 can remain at the low level VGL during the hold frame.

[0095] In one possible implementation, the timing waveform of the third control signal EM3 in the write frame can be the same as the timing waveform in the hold frame, the timing waveform of the fourth control signal EM1 in the write frame can be the same as the timing waveform in the hold frame, the timing waveform of the fifth control signal EM2 in the write frame can be the same as the timing waveform in the hold frame, and the timing waveform of the first scan signal S1 in the write frame can be the same as the timing waveform in the hold frame.

[0096] Figure 10 This is a schematic diagram of the signal timing of a pixel circuit in a holding frame, provided in one embodiment of this application, which can be applied to, for example... Figure 8 The pixel circuit shown in this embodiment is combined with Figure 8 and Figure 10 The working process of the pixel circuit provided in one embodiment of this application is described in detail, but it should not be construed as a limitation on the scope of the invention patent.

[0097] In one possible implementation, the hold frame may include at least a second initialization phase t21, where the level of the first control signal EMB1 is low (VGL), the level of the second control signal EMB2 is low (VGL), the level of the third control signal EM3 is high (VGH), the level of the fourth control signal EM1 is low (VGL), the level of the fifth control signal EM2 is high (VGH), and the level of the first scan signal S1 is high (VGH). The seventh transistor M7 is turned on according to the fourth control signal EM1, the ninth transistor M9 is turned on according to the fifth control signal EM2, and the remaining TFTs are turned off.

[0098] In the second initialization phase t21, after the seventh transistor M7 is turned on, the first power signal VDD transmitted on the first power line is transmitted to the first terminal D of the first transistor M1, that is, the first power signal VDD resets the first terminal D of the first transistor M1, at this time VD=VDD. After the ninth transistor M9 is turned on, the second initialization signal Vref is transmitted to the anode of the light-emitting diode D1, and the second initialization signal Vref resets the anode of the light-emitting diode D1, VAno=Vref.

[0099] In one possible implementation, after the second initialization phase t21, the holding frame may further include a third initialization phase t22, in which the level of the first control signal EMB1 is low (VGL), the level of the second control signal EMB2 is low (VGL), the level of the third control signal EM3 is low (VGL), the level of the fourth control signal EM1 is high (VGH), the level of the fifth control signal EM2 is high (VGH), and the level of the first scan signal S1 is low (VGL). The fourth transistor M4 is turned on according to the first scan signal S1, the sixth transistor M6 is turned on according to the third control signal EM3, the ninth transistor M9 is turned on according to the fifth control signal EM2, and the remaining TFTs are turned off.

[0100] In the third initialization phase t22, after the fourth transistor M4 and the sixth transistor M6 are turned on, the data signal Vdata transmitted on the data line is sequentially transmitted to the second terminal S of the first transistor M1 through the fourth transistor M4 and the sixth transistor M6, that is, VS=Vdata. After the ninth transistor M9 is turned on, the second initialization signal Vref is transmitted to the anode of the light-emitting diode D1, and the anode potential of the light-emitting diode D1 is maintained at VAno=Vref.

[0101] In one possible implementation, after the third initialization phase t22, the holding frame may further include a second light-emitting phase t23. During the second light-emitting phase t23 of the holding frame, the levels of the first control signal EMB1, the second control signal EMB2, the third control signal EM3, the fourth control signal EM1, and the fifth control signal EM2 are all low (VGL), and the level of the first scan signal S1 is high (VGH). The seventh transistor M7 is turned on according to the fourth control signal S4, the sixth transistor M6 is turned on according to the third control signal EM3, the eighth transistor M8 is turned on according to the fifth control signal EM2, and the first transistor M1 is turned on according to its gate potential and outputs a drive current. The remaining TFTs are all turned off. The drive current output by the first transistor M1 according to its gate potential is sequentially transmitted through the sixth transistor M6 and the eighth transistor M8 to the anode of the light-emitting diode D1, thereby causing the light-emitting diode D1 to emit light according to the drive current.

[0102] In the third initialization stage t22 of the holding frame, the pixel circuit provided in this application can reset point S. That is, the data signal Vdata is transmitted sequentially through the fourth transistor M4 and the sixth transistor M6 to the second terminal S of the first transistor M1, so that Vgs of the first transistor M1 is a large voltage difference, which can effectively adjust the threshold voltage of the first transistor M1. In addition, the anode of the light-emitting diode D1 is also reset by using the second initialization signal Vref, so the problem of low frequency / screen switching flicker can be effectively improved.

[0103] The present invention also provides a driving method for driving a pixel circuit as described in any of the above embodiments. The pixel circuit may include a first initialization stage t11, a threshold compensation stage t12, a data writing stage t13, and a first light emission stage t14 during the operation of a display frame. Figure 11 This is a flowchart illustrating a pixel circuit driving method in one embodiment of the present application. In one possible implementation, the pixel circuit driving method may include the following steps S100 to S400.

[0104] Step S100: In the first initialization phase, the level of the first control signal is configured to the first level, the level of the second control signal is configured to the first level, and the level of the first scan signal is configured to the first level.

[0105] In the embodiments of this application, the first level may refer to a high level VGH, and the second level may refer to a low level VGL, with the first level being greater than the second level.

[0106] During the first initialization phase t11, the level of the first control signal EMB1 is the first level (high level VGH), the level of the second control signal EMB2 is the first level (high level VGH), and the level of the first scan signal S1 is the first level (high level VGH). The second transistor M2 and the fifth transistor M5 are turned on according to the first control signal EM1, the third transistor M3 is turned on according to the second control signal EM2, and the fourth transistor M4 is turned off according to the first scan signal S1.

[0107] In one possible implementation, the level of the third control signal EM3 is high (VGH), the level of the fourth control signal EM1 is low (VGL), and the level of the fifth control signal EM2 is high (VGH). The sixth transistor M6 is turned off according to the third control signal EM3, the seventh transistor M7 is turned on according to the fourth control signal EM1, the eighth transistor M8 is turned off according to the fifth control signal EM2, and the ninth transistor M9 is turned on according to the fifth control signal EM2.

[0108] In the first initialization phase t11, the first power supply signal VDD is transmitted sequentially through the seventh transistor M7 and the second transistor M2 to the first terminal D and the gate G of the first transistor M1, resetting the first terminal D and the gate G of the first transistor M1. After the reset, VG=VD=VDD. The first initialization signal Vini is transmitted sequentially through the fifth transistor M5 and the third transistor M3 to the first node N1 and the second node N2, resetting the first node N1 and the second node N2. After the reset, VN1=VN2=Vini. The second initialization signal Vref is transmitted through the ninth transistor M9 to the second terminal of the second capacitor C2 and the anode of the light-emitting diode D1, resetting the second terminal of the second capacitor C2 and the anode of the light-emitting diode D1. After the reset, VAno=Vref. In addition, the first transistor M1 conducts according to the potential at its gate, therefore the potential at the second terminal S of the first transistor M1 is VS=VDD-Vth.

[0109] Step S200: In the threshold compensation stage, the level of the first control signal is configured to the first level, the level of the second control signal is configured to the first level, and the level of the first scan signal is configured to the first level.

[0110] During the threshold compensation stage t12, the level of the first control signal EMB1 is high (VGH), the level of the second control signal EMB2 is high (VGH), and the level of the first scan signal S1 is high (VGH). The second transistor M2 and the fifth transistor M5 are turned on according to the first control signal EM1, the third transistor M3 is turned on according to the second control signal EM2, and the fourth transistor M4 is turned off according to the first scan signal S1.

[0111] In one possible implementation, during the threshold compensation stage t12, the level of the third control signal EM3 is low (VGL), the level of the fourth control signal EM1 is high (VGH), and the level of the fifth control signal EM2 is high (VGH). The sixth transistor M6 is turned on according to the third control signal EM3, the seventh transistor M7 is turned off according to the fourth control signal EM1, the eighth transistor M8 is turned off according to the fifth control signal EM2, and the ninth transistor M9 is turned on according to the fifth control signal EM2.

[0112] During the threshold compensation phase t12, the gate G of the first transistor M1 discharges to Vini through the second transistor M2, the first transistor M1, the sixth transistor M6, and the fifth transistor M5, respectively, thus performing threshold voltage Vth compensation for the DTFT. The compensation process continues until the potential of the gate G and the first terminal D of the first transistor M1 becomes Vini + Vth, and this compensation time is adjustable. Furthermore, at this time, the potentials of the first node N1, the second node N2, and the second terminal S of the first transistor M1 are all Vini, VN1 = VN2 = VS = Vini.

[0113] Step S300: During the data writing stage, the level of the first control signal is configured to the second level, the level of the second control signal is configured to the first level, and the level of the first scan signal is configured to the second level.

[0114] During the data writing phase t13, the level of the first control signal EMB1 is low (VGL), the level of the second control signal EMB2 is high (VGH), and the level of the first scan signal S1 is low (VGL). The second transistor M2 and the fifth transistor M5 are turned off according to the first control signal EM1, the third transistor M3 is turned on according to the second control signal EM2, and the fourth transistor M4 is turned on according to the first scan signal S1.

[0115] In one possible implementation, during the data writing phase t13, the level of the third control signal EM3 is low (VGL), the level of the fourth control signal EM1 is high (VGH), and the level of the fifth control signal EM2 is high (VGH). The sixth transistor M6 is turned on according to the third control signal EM3, the seventh transistor M7 is turned off according to the fourth control signal EM1, the eighth transistor M8 is turned off according to the fifth control signal EM2, and the ninth transistor M9 is turned on according to the fifth control signal EM2.

[0116] During the data writing phase t13, the data signal Vdata is sequentially transmitted to the second node N2 and the first node N1 via the fourth transistor 4 and the third transistor M3. The data signal Vdata can also be transmitted to the second terminal S of the first transistor M1 via the sixth transistor M6. At this time, the potentials at the first node N1, the second node N2, and point S are all Vdata, i.e., VN1=VN2=VS=Vdata. The second initialization signal Vref is still transmitted to the second terminal of the second capacitor C2 and the anode of the light-emitting diode D1 via the ninth transistor M9, VAno=Vref. The potential at the second terminal of the first capacitor C1 changes synchronously with the potential at its first terminal, i.e., the potential at the gate G of the first transistor M1 becomes VG=Vth+data.

[0117] Step S400: In the first light emission stage, the level of the first control signal is configured to the second level, the level of the second control signal is configured to the second level, and the level of the first scan signal is configured to the first level, wherein the first level is greater than the second level.

[0118] During the first light-emitting stage t14, the level of the first control signal EMB1 is low (VGL), the level of the second control signal EMB2 is low (VGL), and the level of the first scan signal S1 is high (VGH). The second transistor M2 and the fifth transistor M5 are turned off according to the first control signal EM1, the third transistor M3 is turned off according to the second control signal EM2, and the fourth transistor M4 is turned off according to the first scan signal S1.

[0119] In one possible implementation, during the first light-emitting stage t14, the level of the third control signal EM3 is low (VGL), the level of the fourth control signal EM1 is low (VGL), and the level of the fifth control signal EM2 is low (VGL). The sixth transistor M6 is turned on according to the third control signal EM3, the seventh transistor M7 is turned on according to the fourth control signal EM1, the eighth transistor M8 is turned on according to the fifth control signal EM2, and the ninth transistor M9 is turned off according to the fifth control signal EM2.

[0120] In the first luminescence stage t14, The first capacitor C1 couples the data signal Vdata to the gate of the first transistor M1. The first transistor M1 can generate a drive signal based on its gate and source voltages. The drive current output by the first transistor M1 can be: I D =1 / 2*μ C OX (W / L)(Vdata-Vref) 2 The drive current I output by the first transistor M1 D The current can be transmitted sequentially through the sixth transistor M6 and the eighth transistor M8 to the anode of the light-emitting diode D1, so that the light-emitting diode D1 can be driven by the driving current I. D Glowing light.

[0121] When the aforementioned pixel circuit driving method is applied to the pixel circuit, each node in the pixel circuit is reset in the first initialization phase t11, and there are no micro-short circuits between signals, which can effectively improve image retention and reduce power consumption. In the threshold compensation phase t12, when compensating the threshold voltage Vth of the first transistor M1, the threshold voltage information Vth is stored in the first capacitor C1, and the compensation time for the threshold voltage is adjustable, enabling simultaneous compensation of multiple rows of pixel circuits, thus achieving high-frequency driving. In the data writing phase t13, the data signal Vdata is written to the second capacitor C2. The first capacitor C1 can couple the threshold-compensated data signal Vdata to the first transistor M1. Capacitive coupling enables rapid data writing without data range loss, achieving high-brightness display. In addition, the second transistor M2 and the fifth transistor M5 in the pixel circuit are both controlled by the first control signal EMB1, and the first control signal EMB1 and the second control signal EMB2 can be generated by the same set of GIP circuits. The gate drive signal required in the circuit can be generated by using 5 sets of GIP (Gate In Panel) circuits, which is more conducive to layout and to achieving narrow bezels.

[0122] In one possible implementation, the pixel circuit may further include a hold frame in one operating cycle. The hold frame may include at least a second initialization phase t21, where the level of the first control signal EMB1 is low (VGL), the level of the second control signal EMB2 is low (VGL), the level of the third control signal EM3 is high (VGH), the level of the fourth control signal EM1 is low (VGL), the level of the fifth control signal EM2 is high (VGH), and the level of the first scan signal S1 is high (VGH). The seventh transistor M7 is turned on according to the fourth control signal EM1, the ninth transistor M9 is turned on according to the fifth control signal EM2, and the remaining TFTs are turned off. The first power supply signal VDD is transmitted through the seventh transistor M7 to the first terminal D of the first transistor M1, i.e., the first power supply signal VDD resets the first terminal D of the first transistor M1, at which point VD = VDD. After the ninth transistor M9 is turned on, the second initialization signal Vref is transmitted to the anode of the light-emitting diode D1, resetting the anode of the light-emitting diode D1, VAno = Vref.

[0123] In one possible implementation, after the second initialization phase t21, the holding frame may further include a third initialization phase t22, in which the level of the first control signal EMB1 is low (VGL), the level of the second control signal EMB2 is low (VGL), the level of the third control signal EM3 is low (VGL), the level of the fourth control signal EM1 is high (VGH), the level of the fifth control signal EM2 is high (VGH), and the level of the first scan signal S1 is low (VGL). The fourth transistor M4 is turned on according to the first scan signal S1, the sixth transistor M6 is turned on according to the third control signal EM3, and the ninth transistor M9 is turned on according to the fifth control signal EM2; all other TFTs are turned off. The data signal Vdata is transmitted sequentially through the fourth transistor M4 and the sixth transistor M6 to the second terminal S of the first transistor M1, i.e., VS = Vdata. After the ninth transistor M9 is turned on, the second initialization signal Vref is transmitted to the anode of the light-emitting diode D1, and the anode potential of the light-emitting diode D1 is maintained at VAno = Vref.

[0124] In one possible implementation, the holding frame may further include a second light-emitting stage t23. During the second light-emitting stage t23 of the holding frame, the levels of the first control signal EMB1, the second control signal EMB2, the third control signal EM3, the fourth control signal EM1, and the fifth control signal EM2 are all low (VGL), while the level of the first scan signal S1 is high (VGH). The seventh transistor M7 is turned on according to the fourth control signal S4, the sixth transistor M6 is turned on according to the third control signal EM3, the eighth transistor M8 is turned on according to the fifth control signal EM2, and the first transistor M1 is turned on according to its gate potential and outputs a drive current. All other TFTs are turned off. The drive current output by the first transistor M1 according to its gate potential is sequentially transmitted through the sixth transistor M6 and the eighth transistor M8 to the anode of the light-emitting diode D1, thereby causing the light-emitting diode D1 to emit light according to the drive current.

[0125] It should be understood that although the steps in the flowcharts of the accompanying drawings are shown sequentially as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some of the steps in the flowcharts of the accompanying drawings may include multiple steps or stages, which are not necessarily completed at the same time, but may be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but may be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0126] This invention also provides a display panel that may include the pixel circuits described in any of the above embodiments. The display panel may include one or more sets of pixel circuits. The pixel circuits may be configured to generate driving signals and use these driving signals to drive the light-emitting units to emit light. This display panel can be applied to any product or component with display functionality, including but not limited to the following categories: mobile phones, televisions, digital cameras, tablet computers, laptops, desktop monitors, smart bracelets, smart glasses, automotive displays, medical devices, industrial control equipment, touch interactive terminals, etc. This invention does not impose any special limitations on these categories.

[0127] In one possible implementation, the display panel may further include multiple sets of shift register units. The first control signal EMB1 and the second control signal EMB2 input to the pixel circuit may originate from the same set of shift register units, while the third control signal EM3, the fourth control signal EM1, the fifth control signal EM2, and the first scan signal S1 input to the pixel circuit may originate from different shift register units. Therefore, the above-mentioned display panel can output the gate drive signals required to control the operation of the pixel circuit using at least 5 sets of GIP circuits, which is beneficial for achieving a narrow bezel design.

[0128] This invention also provides a display device, which may include the pixel circuit described in any of the above embodiments. The display device may include one or more sets of pixel circuits. The pixel circuits may be configured to generate driving signals and use these driving signals to drive the light-emitting units to emit light. Similarly, this display device can be applied to any product or component with display functionality, including but not limited to the following categories: mobile phones, televisions, digital cameras, tablet computers, laptops, desktop monitors, smart bracelets, smart glasses, automotive displays, medical devices, industrial control equipment, touch interactive terminals, etc. This invention does not impose any special limitations on these categories.

[0129] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0130] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0131] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A pixel circuit, characterized in that, include: The driver module is connected between the first power line and the light-emitting module and is used to output drive signals; A first storage module is connected between the first node and the control terminal of the drive module, and is used to store the voltage difference between the first node and the control terminal of the drive module; A first switch module is connected between the first end of the drive module and the control end, and is used to conduct the connection between the first end of the drive module and the control end according to the first control signal at least during the threshold compensation stage; A second switch module is connected between the first node and the second node, and is used to activate the connection between the first node and the second node at least during the threshold compensation stage and the data writing stage according to a second control signal; wherein, the second node is located on the signal transmission path from the driving module to the light-emitting module; A data writing module, connected to the second node, is used to transmit a data signal to the second node during the data writing stage according to the first scan signal; A first initialization module is connected between the second node and the first initialization signal line, and is used to conduct the connection between the second node and the first initialization signal line at least during the threshold compensation stage according to a first control signal; The second storage module has a first end connected to the first node, and a second end of the second storage module is connected to a second initialization signal at least during the threshold compensation phase and the data writing phase.

2. The pixel circuit according to claim 1, characterized in that, The driving module includes a first transistor, the gate of the first transistor serves as the control terminal of the driving module, the first electrode of the first transistor serves as the first terminal of the driving module, and the second electrode of the first transistor serves as the second terminal of the driving module. Preferably, the first switching module includes a second transistor, the gate of the second transistor serves as the control terminal of the first switching module and is connected to the first control signal, the first electrode of the second transistor serves as the first terminal of the first switching module and is connected to the first terminal of the driving module, and the second electrode of the second transistor serves as the second terminal of the first switching module and is connected to the control terminal of the light-emitting module. Preferably, the second switching module includes a third transistor, the gate of the third transistor serves as the control terminal of the second switching module and is connected to the second control signal, the first terminal of the third transistor serves as the first terminal of the second switching module and is connected to the first node, and the second terminal of the third transistor serves as the second terminal of the second switching module and is connected to the second node. Preferably, the data writing module includes a fourth transistor, the gate of the fourth transistor is connected to the first scan signal as the control terminal of the data writing module, the first electrode of the fourth transistor is connected to the data signal as the first terminal of the data writing module, and the second electrode of the fourth transistor is connected to the second node as the second terminal of the data writing module. Preferably, the first initialization module includes a fifth transistor, the gate of the fifth transistor serves as the control terminal of the first initialization module and is connected to the first control signal, the first electrode of the fifth transistor serves as the first terminal of the first initialization module and is connected to the first initialization signal line, and the second electrode of the fifth transistor serves as the second terminal of the first initialization module and is connected to the second node. Preferably, the first storage module includes a first capacitor, the first terminal of the first capacitor is connected to the first node as the first end of the first storage module, and the second terminal of the first capacitor is connected to the control terminal of the drive module as the second end of the first storage module. Preferably, the second storage module includes a second capacitor, the first terminal of the second capacitor is connected to the first node as the first end of the second storage module, and the second terminal of the second capacitor is the second end of the second storage module.

3. The pixel circuit according to claim 1, characterized in that, The pixel circuit also includes: A third switch module is connected between the second end of the drive module and the second node, and is used to conduct the connection between the second end of the drive module and the second node according to a third control signal during the threshold compensation stage and the data writing stage. Preferably, the third switching module includes a sixth transistor, the gate of the sixth transistor is connected to the third control signal as the control terminal of the third switching module, the first terminal of the sixth transistor is connected to the second terminal of the driving module as the first terminal of the third switching module, and the second terminal of the sixth transistor is connected to the second node as the second terminal of the third switching module.

4. The pixel circuit according to claim 1, characterized in that, The pixel circuit also includes: A first light-emitting control module is connected between the first power line and the first end of the driving module, and is used to conduct the connection between the first power line and the first end of the driving module according to the fourth control signal in the first initialization stage and the first light-emitting stage. Preferably, the first light-emitting control module includes a seventh transistor, the gate of the seventh transistor is connected to the fourth control signal as the control terminal of the first light-emitting control module, the first electrode of the seventh transistor is connected to the first power line as the first terminal of the first light-emitting control module, and the second electrode of the seventh transistor is connected to the first terminal of the driving module as the second terminal of the first light-emitting control module.

5. The pixel circuit according to claim 1, characterized in that, The pixel circuit also includes: A light-emitting module, connected between the second node and the second power line, is used to emit light according to the driving signal; The second light-emitting control module is connected between the second node and the first end of the light-emitting module, and is used to conduct the connection between the second node and the first end of the light-emitting module in the first light-emitting stage according to the fifth control signal; Preferably, the second light-emitting control module includes an eighth transistor, the gate of the eighth transistor is connected to the fifth control signal as the control terminal of the second light-emitting control module, the first electrode of the eighth transistor is connected to the second node as the first terminal of the second light-emitting control module, and the second electrode of the eighth transistor is connected to the first terminal of the light-emitting module as the second terminal of the second light-emitting control module. Preferably, the pixel circuit further includes: The second initialization module is connected to the first end of the light-emitting module and the second end of the second storage module, and is used to transmit the second initialization signal to the first end of the light-emitting module and the second end of the second storage module according to the fifth control signal in the first initialization stage, the threshold compensation stage and the data writing stage; Preferably, the second initialization module includes a ninth transistor, the gate of the ninth transistor is connected to the fifth control signal as the control terminal of the second initialization module, the first terminal of the ninth transistor is connected to the second initialization signal as the first terminal of the second initialization module, and the second terminal of the ninth transistor is connected to the first terminal of the light-emitting module and the second terminal of the second storage module as the second terminal of the second initialization module.

6. The pixel circuit according to claim 1, characterized in that, The pixel circuit includes a write frame in one working cycle. The write frame includes at least a first initialization phase. In the first initialization phase, the first initialization module transmits a first initialization signal to the second node according to the first control signal. The second switch module connects the connection between the first node and the second node according to the second control signal. The second initialization module transmits a second initialization signal to the second end of the first storage module according to the fifth control signal. The first light emission control module connects the connection between the first power line and the first end of the driving module according to the fifth control signal. The first switch module connects the connection between the first end of the driving module and the control end according to the first control signal. Preferably, after the initialization phase, the write frame includes a threshold compensation phase. In the threshold compensation phase, the second switch module connects the connection between the first node and the second node according to the second control signal, the first initialization module connects the connection between the first end of the driver module and the control end according to the first control signal, the second initialization module transmits the second initialization signal to the second end of the first storage module according to the fifth control signal, the first switch module connects the connection between the first end of the driver module and the control end according to the first control signal, the third switch module connects the connection between the second end of the driver module and the second node according to the third control signal, and the control end of the driver module discharges to the first initialization signal line sequentially through the second switch module, the driver module, the third switch module and the first initialization module to perform threshold compensation on the driver module. Preferably, after the threshold compensation stage, the write frame includes a data write stage. In the data write stage, the data write module transmits the data signal to the second node according to the first scan signal, the second switch module connects the connection between the first node and the second node according to the second control signal, the third switch module connects the connection between the second end of the drive module and the second node according to the third control signal, and the second initialization module transmits the second initialization signal to the second end of the first storage module according to the fifth control signal. Preferably, after the data writing stage, the write frame includes a first light-emitting stage. In the first light-emitting stage, the first light-emitting control module connects the first power line to the first end of the driving module according to the fourth control signal, the third switch module connects the second end of the driving module to the second node according to the third control signal, and the second light-emitting control module connects the second node to the first end of the light-emitting module according to the fifth control signal. Preferably, the pixel circuit includes a hold frame in one working cycle, wherein the levels of the first control signal and the second control signal are the cutoff levels of the first switching module, the second switching module and the first initialization module in the hold frame; Preferably, the timing waveform of the third control signal in the write frame is the same as the timing waveform in the hold frame, the timing waveform of the fourth control signal in the write frame is the same as the timing waveform in the hold frame, and the timing waveforms of the fifth control signal and the first scan signal in the write frame are the same as the timing waveforms in the hold frame. Preferably, the first control signal and the second control signal originate from the same set of shift register units.

7. The pixel circuit according to claim 1, characterized in that, The pixel circuit includes at least one of a metal oxide transistor and a low-temperature polysilicon transistor. Preferably, the pixel circuit includes at least one metal-oxide transistor and at least one low-temperature polysilicon transistor; Preferably, the driving module, the first switch module, the second switch module, the first initialization module and the second initialization module all include metal oxide transistors, and the data writing module, the third switch module, the first light-emitting control module and the second light-emitting control module all include low-temperature polycrystalline silicon transistors; Preferably, the driving module, the first switch module, the second switch module, the first initialization module, and the second initialization module all include N-type transistors, and the data writing module, the third switch module, the first light-emitting control module, and the second light-emitting control module all include P-type transistors.

8. A driving method for a pixel circuit, characterized in that, For driving a pixel circuit as described in any one of claims 1 to 7, wherein one working cycle of the pixel circuit includes a write frame, the write frame including at least a first initialization phase, a threshold compensation phase, a data writing phase, and a first emission phase, the driving method includes: During the first initialization phase, the level of the first control signal is configured to a first level, the level of the second control signal is configured to a first level, and the level of the first scan signal is configured to a first level. During the threshold compensation stage, the level of the first control signal is configured to a first level, the level of the second control signal is configured to a first level, and the level of the first scan signal is configured to a first level. During the data writing phase, the level of the first control signal is configured to a second level, the level of the second control signal is configured to a first level, and the level of the first scan signal is configured to a second level. During the first light emission stage, the level of the first control signal is configured to a second level, the level of the second control signal is configured to a second level, and the level of the first scan signal is configured to a first level, wherein the first level is greater than the second level.

9. The driving method for the pixel circuit according to claim 8, characterized in that, The driving method further includes: During the first initialization phase, the level of the third control signal is configured to a first level, the level of the fourth control signal is configured to a second level, and the level of the fifth scan signal is configured to a first level. During the threshold compensation stage, the level of the third control signal is configured to the second level, the level of the fourth control signal is configured to the first level, and the level of the fifth scan signal is configured to the first level. During the data writing phase, the level of the third control signal is configured to the second level, the level of the fourth control signal is configured to the first level, and the level of the fifth scan signal is configured to the first level. During the first light emission stage, the level of the third control signal is configured to the second level, the level of the fourth control signal is configured to the second level, and the level of the fifth scan signal is configured to the second level; Preferably, the pixel circuit includes a hold frame in one working cycle, and the levels of the first control signal and the second control signal are at a second level in the hold frame; Preferably, the timing waveform of the third control signal in the write frame is the same as the timing waveform in the hold frame, the timing waveform of the fourth control signal in the write frame is the same as the timing waveform in the hold frame, and the timing waveforms of the fifth control signal and the first scan signal in the write frame are the same as the timing waveforms in the hold frame. Preferably, the first control signal and the second control signal originate from the same set of shift register units.

10. A display panel, characterized in that, The display panel includes the pixel circuit as described in any one of claims 1 to 7, and further includes multiple sets of shift register units. The first control signal and the second control signal accessed in the pixel circuit originate from the same set of shift register units, and the third control signal, the fourth control signal, the fifth control signal and the first scan signal accessed in the pixel circuit originate from different sets of shift register units.

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