Pixel circuits, display panels and display devices

Abstract

A pixel circuit, a display panel, and a display device are disclosed. The pixel circuit includes a driving module and a reset module. The driving module is used to configure the voltage of the control terminal of the driving module based on a data signal in a first stage, and is also used to generate and output a driving current based on the potential of the control terminal of the driving module in a second stage; wherein the first stage includes a first reset stage. The reset module is used to transmit an alternating voltage to the control terminal of the driving module in the first reset stage; in the first reset stage, the alternating voltage is a first voltage, and in the second stage, the alternating voltage is a second voltage, the second voltage being greater than the first voltage. By providing a lower first voltage in the reset stage, the reset strength of the reset module can be enhanced, effectively repairing the bias offset caused by grain boundary defects in the low-temperature polycrystalline silicon thin-film transistor and suppressing image retention. Providing a higher second voltage in the second stage can reduce the drain-source voltage difference of the reset transistor in the reset module and reduce the leakage current.

Description

Technical Field

[0001] This application belongs to the field of display device technology, and particularly relates to a pixel circuit, display panel and display device. Background Technology

[0002] Currently, Active Matrix Organic Light Emitting Diode (AMOLED) display technology has become the mainstream display technology due to its advantages such as high contrast, fast response, and low power consumption. Low Temperature Poly-Silicon Thin Film Transistor (LTPSTFT) is widely used in the pixel circuits of AMOLED due to its high mobility.

[0003] However, low-temperature polycrystalline silicon thin-film transistors (LTSPs) have a large number of defect sites on the surface of the active layer and in the grain boundaries. When the device operates for a long time, these defects can cause the device characteristics to shift, which macroscopically manifests as image sticking after displaying the same image for an extended period of time. Summary of the Invention

[0004] To address the problems existing in the prior art, the purpose of this application is to provide a pixel circuit, a display panel, and a display device.

[0005] A first aspect of this application provides a pixel circuit, including: a driving module, configured in a first stage to configure a voltage at a control terminal of the driving module based on a data signal, and further configured in a second stage to generate and output a driving current based on a potential at the control terminal of the driving module; wherein the first stage includes a first reset stage; and a reset module electrically connected to the control terminal of the driving module, configured to transmit an alternating voltage to the control terminal of the driving module in the first reset stage; in the first reset stage, the alternating voltage is a first voltage, and in the second stage, the alternating voltage is a second voltage, wherein the second voltage is greater than the first voltage.

[0006] In one embodiment, the pixel circuit further includes a signal configuration module connected to the reset module, which is used to generate and output the alternating voltage.

[0007] In one embodiment, the pixel circuit is applied to a display panel, the display panel including multiple rows of the pixel circuit, and each of the signal configuration modules of the multiple rows of pixel circuits is cascaded in sequence; the delay between the alternating voltages output by two adjacent signal configuration modules is one row period.

[0008] In one embodiment, the pixel circuit is applied to a display panel, the display panel includes multiple rows of the pixel circuit, adjacent rows of the pixel circuit form a group, the pixel circuits in the same group share the same signal configuration module, and each of the signal configuration modules is cascaded sequentially; the delay between the alternating voltages output by two adjacent signal configuration modules is at least two row cycles.

[0009] In one embodiment, the driving module includes a first transistor, a second transistor, a third transistor, a fourth transistor, and an energy storage capacitor; the reset module includes a fifth transistor. The first terminal of the first transistor is connected to a first power supply voltage; the second terminal of the first transistor is connected to the first terminal of the second transistor and the first terminal of the third transistor; the second terminal of the second transistor is connected to the data signal; the control terminal of the second transistor is connected to the first scan signal; the second terminal of the third transistor is connected to the first terminal of the fourth transistor; the second terminal of the fourth transistor is used to output the driving current; both the control terminals of the first and fourth transistors are used to connect to a light emission control signal; the first terminal of the energy storage capacitor is connected to the first terminal of the first transistor; the second terminal of the energy storage capacitor is connected to the control terminal of the third transistor; the first terminal of the fifth transistor is connected to the control terminal of the third transistor; the second terminal of the fifth transistor is connected to the alternating voltage; and the control terminal of the fifth transistor is connected to the second scan signal.

[0010] In one embodiment, the first stage further includes a data writing stage, and the pixel circuit further includes a compensation module; the compensation module is connected between the second terminal of the third transistor and the control terminal of the third transistor, and the compensation module and the second transistor are used to conduct during the data writing stage.

[0011] In one embodiment, the first stage further includes a second reset stage, the pixel circuit further includes a conduction bias stress module, a first terminal of the conduction bias stress module is connected to a second terminal of the third transistor, the second terminal of the conduction bias stress module is used to connect to the alternating voltage, a first terminal of the reset module is connected to a control terminal of the third transistor, and a second terminal of the reset module is connected to a second terminal of the third transistor; the first voltage is the reset voltage of the control terminal of the third transistor, and the second voltage is the bias compensation voltage of the third transistor; in both the first reset stage and the second reset stage, the conduction bias stress module is turned on; in the second reset stage, the alternating voltage is the second voltage; preferably, the first stage further includes a data writing stage, in which the reset module and the second transistor are turned on, and the conduction bias stress module is turned off.

[0012] In one embodiment, the first stage further includes a third reset stage, and the first reset stage, the second reset stage, the data writing stage, and the third reset stage are performed sequentially; in the first reset stage, the first voltage is transmitted to the control terminal of the third transistor; in the second reset stage, the second voltage is transmitted to the second terminal of the third transistor; in the data writing stage, the data signal is transmitted to the control terminal of the third transistor; in the third reset stage, the second voltage is transmitted to the second terminal of the third transistor.

[0013] A second aspect of this application provides a display panel including the pixel circuit described above.

[0014] A third aspect of this application provides a display device, including the display panel as described above.

[0015] The beneficial effects of this application embodiment compared with the prior art are as follows: In the reset stage of the first stage, providing a lower first voltage to the driving module can enhance the reset strength of the reset module, effectively repair the bias offset caused by grain boundary defects in the low-temperature polycrystalline silicon thin-film transistor, and suppress image retention. In the second stage, providing a higher second voltage can reduce the drain-source voltage difference of the reset transistor in the reset module and reduce the leakage current, thereby enabling the pixel circuit to achieve both image retention improvement and leakage current suppression. Attached Figure Description

[0016] Figure 1 A schematic diagram of a pixel circuit provided in an embodiment of this application; Figure 2 A schematic diagram of a signal configuration module provided in an embodiment of this application; Figure 3 This is a schematic diagram of a cascaded signal configuration module provided in an embodiment of this application; Figure 4 Waveform diagrams of multiple alternating voltages provided in one embodiment of this application; Figure 5 A circuit diagram of a pixel circuit provided in an embodiment of this application; Figure 6 for Figure 5 The signal waveform diagram of the pixel circuit shown; Figure 7 Another circuit diagram of a pixel circuit provided in one embodiment of this application; Figure 8 for Figure 7 The signal waveform diagram of the pixel circuit is shown.

[0017] Reference numerals: 10, pixel circuit; 20, light-emitting element; 100, driving module; 200, reset module; 300, signal configuration module; 310, control module; 320, output module; 321, first switching unit; 322, second switching unit; 400, compensation module; 500, conduction bias stress module. Detailed Implementation

[0018] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0019] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0020] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0021] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0022] Figure 1 A schematic diagram of a pixel circuit according to an embodiment of this application is shown. For ease of explanation, only the parts relevant to this embodiment are shown, and the details are as follows: A pixel circuit 10 includes a driving module 100 and a reset module 200.

[0023] The drive module 100 is used to configure the voltage of the control terminal of the drive module 100 based on the data signal Data in the first stage. The drive module 100 is also used to generate and output a drive current based on the potential of the control terminal of the drive module 100 in the second stage. The first stage includes a first reset stage.

[0024] The reset module 200 is connected to the control terminal of the drive module 100. The reset module 200 is used to transmit the alternating voltage Vinit to the control terminal of the drive module 100 during the first reset phase.

[0025] In the first reset phase, the alternating voltage Vinit is a first voltage V1. In the second phase, the alternating voltage Vinit is a second voltage V2, and the second voltage V2 is greater than the first voltage V1. The specific value of the second voltage V2 can be set according to the actual voltage at the control terminal of the drive module 100 in the second phase. When the reset module 200 is off, the second voltage V2 is used to reduce the voltage difference across the reset module 200 (i.e., the voltage difference between the control terminal of the drive module 100 and the alternating voltage Vinit), thereby reducing the leakage current generated by the voltage difference across the reset module 200. In some embodiments, the first voltage V1 is a low-level signal provided by a low-level trace, and the second voltage V2 is a high-level signal provided by a high-level trace.

[0026] It is understandable that the driving current can drive the corresponding light-emitting element 20 to emit light, and the magnitude of the driving current is determined by the written data signal Data. The first stage is used to initialize the pixel circuit 10 and write the data signal Data, while the second stage is used to stably output the driving current according to the data signal Data.

[0027] By providing a lower first voltage V1 during the reset phase, the reset strength of the reset module 200 can be enhanced without increasing the number of devices in the reset module 200, effectively repairing the bias offset caused by grain boundary defects in the low-temperature polycrystalline silicon thin-film transistor and suppressing image retention. Providing a higher second voltage V2 in the second phase and in parts of the first phase other than the first reset phase reduces the drain-source voltage difference of the reset transistor in the reset module 200, thereby reducing leakage current. By employing alternating voltages Vinit with different voltages in the first and second phases, both image retention improvement and leakage current suppression can be achieved.

[0028] The alternating voltage Vinit can be transmitted to the reset module 200 through only one trace, and the multiplexing of the reset module 200 simplifies the wiring structure and improves integration. The voltage change of the alternating voltage Vinit needs to be precisely matched according to the specific operating timing of the pixel circuit 10, but this embodiment does not impose any restrictions on it.

[0029] In one embodiment, the pixel circuit 10 further includes a signal configuration module 300 connected to the reset module 200, used to generate and output an alternating voltage Vinit.

[0030] Please see Figure 2 , Figure 2 A schematic diagram of the signal configuration module 300 provided in this embodiment is shown.

[0031] In one embodiment, the signal configuration module 300 includes a control module 310 and an output module 320.

[0032] The output module 320 includes a first switch unit 321 and a second switch unit 322. The first terminal of the first switch unit 321 is used to connect to a first voltage V1, and the first terminal of the second switch unit 322 is used to connect to a second voltage V2. The second terminals of the first switch unit 321 and the second terminal of the second switch unit 322 are both connected to the output terminal of the output module 320. The control terminal of the first switch unit 321 is connected to the first output terminal of the control module 310, and the control terminal of the second switch unit 322 is connected to the second output terminal of the control module 310.

[0033] When the control module 310 receives a trigger signal at its level input terminal, it generates a first control signal and a second control signal. The first control signal is used to control the on and off of the first switch unit 321, and the second control signal is used to control the on and off of the second switch unit 322.

[0034] The first and second control signals can be complementary timing signals to ensure that the first switching unit 321 and the second switching unit 322 will not be turned on simultaneously, thereby completely avoiding abnormal output levels caused by voltage superposition. Simultaneously, the complementary timing design also avoids power path shoot-through, significantly reducing static power consumption, improving the reliability of the alternating voltage Vinit output, and adapting to long-term continuous operation scenarios. The specific voltage amplitudes and waveforms of the first and second control signals correspond to the type of switching devices used in the output module 320.

[0035] Specifically, the working logic of the signal configuration module 300 is as follows: In the first reset phase, the control module 310 controls the first switch unit 321 to be turned on and the second switch unit 322 to be turned off, and the output module 320 outputs the first voltage V1. In the second phase, the control module 310 controls the second switch unit 322 to be turned on and the first switch unit 321 to be turned off, and the output module 320 outputs the second voltage V2.

[0036] The trigger signal received by the control module 310 can be a control signal from an external clock circuit, used to indicate the start time of the signal configuration module 300 outputting the first voltage V1. Upon receiving the trigger signal, the control module 310 can, according to the received clock signal, output corresponding first and second control signals within a set time, continuously turning on the first switch unit 321 and turning off the second switch unit 322, so that the output terminal of the output module 320 stably outputs the first voltage V1. Subsequently, after a set time, it outputs corresponding first and second control signals, continuously turning off the first switch unit 321 and turning on the second switch unit 322, so that the output terminal of the output module 320 outputs the second voltage V2.

[0037] For example, in some embodiments, the first switching unit 321 includes a seventh transistor T7, and the second switching unit 322 includes an eighth transistor T8. The first terminal of the seventh transistor T7 is used to connect to a first voltage V1, and the first terminal of the eighth transistor T8 is used to connect to a second voltage V2. The second terminals of both the seventh transistor T7 and the eighth transistor T8 are connected to the output terminal of the output module 320. The control terminal of the seventh transistor T7 is connected to the first output terminal of the control module 310, and the control terminal of the eighth transistor T8 is connected to the second output terminal of the control module 310.

[0038] In some embodiments, the control module 310 can reuse the clock signal and power signal of the existing gate drive module (GIP circuit) of the display panel, without the need to add an additional drive chip channel, thereby reducing the bezel size and lowering hardware costs.

[0039] Please see Figure 3 , Figure 3 A cascaded schematic diagram of the signal configuration module 300 provided in this embodiment is shown. Please refer to [link / reference]. Figure 4 , Figure 4 The waveforms of the multiple alternating voltages (Vinit_1~Vinit_4) provided in this embodiment are shown.

[0040] In one embodiment, the pixel circuit 10 is applied to a display panel, which includes multiple rows of pixel circuits 10, and the control modules 310 of the multiple rows of pixel circuits 10 are cascaded in sequence.

[0041] The level input terminal of control module 310 is connected to the first output terminal of the previous stage control module 310, that is, the level input terminal of the nth stage control module 310 can be connected to the first output terminal of the (n-1)th stage control module 310. This enables the cascaded driving of control modules 310 and the synchronization of signal timing, ensuring that the timing of the alternating voltage Vinit is strictly aligned with the row scanning signal.

[0042] In some embodiments, the level input terminal of the first-stage control module 310 can be directly connected to the control signal SIN issued by an external clock circuit, and the control signal SIN is the trigger signal of the first-stage control module 310.

[0043] In one embodiment, when a row pixel circuit 10 uses a signal configuration module 300, the delay between the alternating voltage Vinit output by two adjacent signal configuration modules 300 is one line period. Figure 4 For example, the delay between the first alternating voltage Vinit_1 and the second alternating voltage Vinit_2 is one line period. The delay between the second alternating voltage Vinit_2 and the third alternating voltage Vinit_3 is one line period, and so on.

[0044] In some embodiments, the multiple pixel circuits 10 may share the same signal configuration module 300 to reduce system circuit complexity and manufacturing costs.

[0045] It is understandable that the alternating voltage Vinit will maintain the first voltage V1 for a set time. Therefore, when the set time is sufficient to cover the first reset phase of the multi-row pixel circuit 10, the multi-row pixel circuit 10 can share the same alternating voltage Vinit.

[0046] In one embodiment, adjacent rows of pixel circuits 10 form a group, and the pixel circuits 10 in the same group share the same signal configuration module 300. The signal configuration modules 300 are cascaded in sequence. The delay between the alternating voltage Vinit output by two adjacent signal configuration modules 300 is at least two line cycles. The delay between the alternating voltage Vinit output by two adjacent signal configuration modules 300 corresponds to the number of pixel circuits 10 in the same group of pixel circuits 10.

[0047] For example, when two adjacent rows of pixel circuits 10 share a single signal configuration module 300, the alternating voltage Vinit output by the first-level signal configuration module 300 can be simultaneously provided to the pixel circuits 10 in the first and second rows, and the alternating voltage Vinit output by the second-level signal configuration module 300 can be simultaneously provided to the pixel circuits 10 in the third and fourth rows. The delay between the alternating voltages Vinit output by the two adjacent levels of signal configuration modules 300 is two row cycles. Figure 4For example, the first alternating voltage Vinit_1 is used to simultaneously supply the pixel circuits 10 in rows 1 and 2. The second alternating voltage Vinit_2 is used to simultaneously supply the pixel circuits 10 in rows 3 and 4. The delay between the first alternating voltage Vinit_1 and the second alternating voltage Vinit_2 is two row cycles. The delay between the second alternating voltage Vinit_2 and the third alternating voltage Vinit_3 is two row cycles, and so on.

[0048] Please see Figure 5 , Figure 5 A circuit diagram of the pixel circuit 10 provided in this embodiment is shown.

[0049] In one embodiment, the driving module 100 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, and an energy storage capacitor C1, and the reset module 200 includes a fifth transistor T5.

[0050] The first terminal of the first transistor T1 is used to connect to the first power supply voltage ELVDD. The second terminal of the first transistor T1 is connected to the first terminal of the second transistor T2 and the first terminal of the third transistor T3. The second terminal of the second transistor T2 is used to connect to the data signal Data. The control terminal of the second transistor T2 is used to connect to the first scan signal S1. The second terminal of the third transistor T3 is connected to the first terminal of the fourth transistor T4. The second terminal of the fourth transistor T4 is used to output the drive current. The control terminals of the first transistor T1 and the fourth transistor T4 are both used to connect to the light emission control signal. The first terminal of the energy storage capacitor C1 is connected to the first terminal of the first transistor T1. The second terminal of the energy storage capacitor C1 is connected to the control terminal of the third transistor T3.

[0051] The first terminal of the fifth transistor T5 is connected to the control terminal of the third transistor T3, the second terminal of the fifth transistor T5 is used to connect the alternating voltage Vinit, and the control terminal of the fifth transistor T5 is used to connect the second scan signal S2.

[0052] The light-emitting element 20 includes a light-emitting diode D1, the anode of which is connected to the second terminal of the fourth transistor T4, and the cathode of which is connected to the second power supply voltage ELVSS.

[0053] In this embodiment, the driver module 100 is a 5T1C circuit (which can be expanded to a 7T1C circuit by combining with other switching transistors). Dynamic reset can be achieved simply by changing the reset voltage to an alternating voltage Vinit.

[0054] In this embodiment, the second voltage V2 can be equal to or approximately equal to the desired voltage at the first terminal of the fifth transistor T5 in the second stage, thereby minimizing the voltage difference across the fifth transistor T5 in the second stage and reducing leakage current. This improves the tolerance of the pixel circuit 10 to process fluctuations (defect density fluctuations in switching devices) and enhances the uniformity and stability of the display brightness of the display panel.

[0055] The specific voltage of the second voltage V2 can be configured according to the leakage current risk of the fifth transistor T5.

[0056] In some embodiments, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are all P-type thin-film transistors.

[0057] Please see Figure 6 , Figure 6 It shows Figure 5 The signal waveform diagram of pixel circuit 10 shown.

[0058] In the first reset phase t1, the fifth transistor T5 is turned on, writing the low-voltage first voltage V1 to the control terminal of the third transistor T3 for reset. In the second phase, the fifth transistor T5 is turned off, but since the second terminal of the fifth transistor T5 has switched to the high-voltage second voltage V2, the voltage difference across the fifth transistor T5 is significantly reduced, and the leakage current is greatly reduced.

[0059] In one embodiment, the first stage further includes a data writing stage t2, and the pixel circuit 10 further includes a compensation module 400.

[0060] The compensation module 400 is connected between the second terminal of the third transistor T3 and the control terminal of the third transistor T3. The compensation module 400 and the second transistor T2 are used to turn on during the data writing phase t2.

[0061] The compensation module 400 is used to be turned on during the data writing phase t2 to compensate for threshold voltage drift.

[0062] Specifically, in the first stage, the light-emitting control signal EM keeps the first transistor T1 and the fourth transistor T4 off, for writing the voltage to the control terminal of the third transistor T3. In the first reset stage t1 of the first stage, the second scan signal S2 can provide a corresponding level to turn on the fifth transistor T5, applying the first voltage V1 to the control terminal of the third transistor T3. The data writing stage t2 follows the first reset stage t1. In the data writing stage t2, the first scan signal S1 can provide a corresponding level to simultaneously turn on the compensation module 400 and the second transistor T2, using the data signal Data to configure the voltage at the control terminal of the third transistor T3 and complete the threshold voltage compensation of the third transistor T3. After completing the voltage writing at the control terminal of the third transistor T3, in the second stage, the light-emitting control signal EM keeps the first transistor T1 and the fourth transistor T4 on. The third transistor T3 controls the magnitude of the drive current according to the voltage at its control terminal, thereby adjusting the brightness of the light-emitting element 20.

[0063] For example, the compensation module 400 includes a ninth transistor T9, the first terminal of the ninth transistor T9 is connected to the second terminal of the third transistor T3, the second terminal of the ninth transistor T9 is connected to the control terminal of the third transistor T3, and the control terminal of the ninth transistor T9 is connected to the first scan signal S1.

[0064] Please see Figure 7 , Figure 7 Another circuit diagram of the pixel circuit 10 provided in this embodiment is shown.

[0065] In one embodiment, the first stage further includes a second reset stage t3, and the pixel circuit 10 further includes a conduction bias stress module 500. The conduction bias stress module 500 is used to realize conduction bias stress (OBS) adjustment. The first end of the conduction bias stress module 500 is connected to the second end of the third transistor T3, and the second end of the conduction bias stress module 500 is used to connect to the alternating voltage Vinit. The first end of the reset module 200 is connected to the control end of the third transistor T3, and the second end of the reset module 200 is connected to the second end of the third transistor T3.

[0066] The first voltage V1 is the reset voltage of the control terminal of the third transistor T3, and the second voltage V2 is the bias compensation voltage of the third transistor T3.

[0067] During the first reset phase t1 and the second reset phase t3, the bias stress module 500 is turned on. During the second reset phase t3, the alternating voltage is the second voltage.

[0068] It is understandable that when needed, the voltage of the first and second terminals of the third transistor T3 can be reset based on the second voltage V2 by turning on the bias stress module 500 and turning off the reset module 200, thereby improving the threshold voltage drift problem of the third transistor T3 caused by long-term operation.

[0069] The first voltage V1 and the second voltage V2 are provided in a time-division manner by the alternating voltage Vinit, and the reset module 200 is reused so that there is no need to set up power supply traces for the OBS function, which significantly simplifies the layout complexity of the metal wiring layer.

[0070] In one embodiment, the conduction bias stress module 500 includes a sixth transistor T6, the first terminal of the sixth transistor T6 is connected to the second terminal of the third transistor T3 and the second terminal of the fifth transistor T5, the second terminal of the sixth transistor T6 is used to connect to the alternating voltage Vinit, and the control terminal of the sixth transistor T6 is used to connect to the third scan signal S3.

[0071] The sixth transistor T6 is periodically turned on under the control of the third scan signal S3, so that the first voltage V1 and the second voltage V2 are alternately applied to the second terminal of the third transistor T3 at different time periods. Thus, without increasing the number of transistors, the gate reset and OBS bias adjustment can be realized through the fifth transistor T5 and the sixth transistor T6, and the time-division multiplexing of the alternating voltage Vinit can be achieved.

[0072] In one embodiment, the first stage further includes a data writing stage t2, during which the reset module 200 is turned on and the bias stress module 500 is turned off. During the data writing stage t2, when the data signal Data is written to the driving module 100, the turned-on reset module 200 can perform threshold voltage compensation for the third transistor T3. In the first reset stage t1 and the data writing stage t2, the reset module 200 is used to implement the reset function and the threshold voltage compensation function, respectively. The time-division multiplexing mechanism of the alternating voltage Vinit and the time-division multiplexing of the reset module 200 simplify the total number of transistors and wiring complexity of the pixel circuit 10, significantly compressing the layout area of ​​the pixel circuit 10.

[0073] Please see Figure 8 , Figure 8 It shows Figure 7 The signal waveform diagram of pixel circuit 10 is shown. Among them, Figure 8 Specifically, the gate voltage Vg (i.e., the voltage at the control terminal of the third transistor T3), the source voltage Vg (i.e., the voltage at the first terminal of the third transistor T3), and the gate-source voltage Vgs of the third transistor T3 are shown.

[0074] In one embodiment, the first stage further includes a third reset stage t4. In the first stage, the first reset stage t1, the second reset stage t3, the data writing stage t2, and the third reset stage t4 are performed sequentially. Transition stages can also be set between each stage to ensure precise timing matching of voltage switching between stages.

[0075] In one embodiment, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the sixth transistor T6 are all P-type thin-film transistors, and the fifth transistor T5 is an N-type thin-film transistor. By configuring appropriate waveforms for the first scan signal S1, the second scan signal S2, and the third scan signal S3 according to the type of each thin-film transistor, the conduction and turn-off of each transistor can be precisely controlled at each stage.

[0076] In the first stage, the light emission control signal EM is at a high level, and the light emission control signal EM controls the first transistor T1 and the fourth transistor T4 to remain off, so as to facilitate voltage reset and voltage writing.

[0077] During the first reset phase t1, the first voltage V1 is transmitted to the control terminal of the third transistor T3.

[0078] Specifically, in one embodiment, when in the first reset stage t1, the first scan signal S1 is high, the second scan signal S2 is high, and the third scan signal S3 is low. The second transistor T2 is turned off, and the fifth transistor T5 and the sixth transistor T6 are simultaneously turned on, applying the first voltage V1 to the control terminal of the third transistor T3. At this time, the control terminal of the third transistor T3 is strongly pulled to the first voltage V1, eliminating residual charge and completing the reset of the control terminal of the third transistor T3.

[0079] During the second reset phase t3, the second voltage V2 is transmitted to the second terminal of the third transistor T3.

[0080] Specifically, in one embodiment, when in the second reset stage t3, the first scan signal S1 is high, the second scan signal S2 is low, and the third scan signal S3 is low. The second transistor T2 is turned off, the fifth transistor T5 is turned off, and the sixth transistor T6 is turned on, applying the second voltage V2 to the second terminal of the third transistor T3 to achieve OBS regulation of the third transistor T3 and effectively suppress threshold voltage drift.

[0081] During the data writing phase t2, the data signal Data is transmitted to the control terminal of the third transistor T3.

[0082] Specifically, in one embodiment, when in the data writing stage t2, the first scan signal S1 is low, the second scan signal S2 is high, and the third scan signal S3 is high. The fifth transistor T5 is turned on, the sixth transistor T6 is turned off, and the second transistor T2 is turned on, thereby writing the data signal Data to the control terminal of the third transistor T3. At this time, the voltage at the control terminal of the third transistor T3 is equal to the sum of the voltage of the data signal Data and the transistor's turn-on threshold.

[0083] In the third reset phase t4, the second voltage V2 is transmitted to the second terminal of the third transistor T3.

[0084] Specifically, in one embodiment, when in the third reset stage t4, the first scan signal S1 is high, the second scan signal S2 is low, and the third scan signal S3 is low. The fifth transistor T5 is turned off, the sixth transistor T6 is turned on, the second transistor T2 is turned off, and the second voltage V2 is applied to the second terminal of the third transistor T3 to realize the secondary OBS regulation of the third transistor T3.

[0085] The first reset stage t1, the second reset stage t3, the data writing stage t2, and the third reset stage t4 can achieve precise reset of the control terminal potential of the third transistor T3, threshold compensation, data writing, and bias stress adjustment, thereby simultaneously realizing transistor reset and OBS adjustment.

[0086] When entering the second stage, the first transistor T1 and the fourth transistor T4 are turned on by controlling the light emission control signal EM. Based on the potential of the control terminal of the third transistor T3, a driving current corresponding to the data signal Data is generated and output. The driving current is not affected by the threshold voltage drift and stably drives the light emission element 20 to emit light.

[0087] After the data writing phase t2, the third transistor T3 is already in the conducting state. In the third reset phase t4, the first and second terminals of the third transistor T3 can be synchronously reset. By performing OBS adjustment before and after the data signal (Data) is written, better image retention optimization can be achieved on the display panel.

[0088] In some embodiments, the first stage further includes a preparation stage t5, and the preparation stage t5, the first reset stage t1, the second reset stage t3, the data writing stage t2, and the third reset stage t4 are performed sequentially. In the preparation stage t5, the initial state of each transistor can be configured. For example, the first transistor T1, the second transistor T2, the fourth transistor T4, and the sixth transistor T6 can be turned off by a clock signal, while the fifth transistor T5 is turned on, in preparation for the first reset stage t1.

[0089] In one embodiment, the pixel circuit 10 further includes a tenth transistor T10, the first terminal of which is connected to the second terminal of the fourth transistor T4, the second terminal of which is used to access the reference voltage Vref, and the control terminal of which is used to access the third scan signal S3.

[0090] The tenth transistor T10 is turned on during the validity of the third scan signal S3 to write the reference voltage Vref to the second terminal of the fourth transistor T4, which can realize the voltage reset of the output terminal of the drive module 100, ensure the initial potential of the output terminal of the drive module 100 is stable, and avoid residual charge from interfering with the subsequent driving accuracy.

[0091] This application also provides a display panel, which includes a plurality of cascaded pixel circuits 10 as described in any of the above embodiments. Since the display panel includes the pixel circuits 10 of any of the above embodiments, it possesses the beneficial effects of the pixel circuits 10 of any of the above embodiments, which will not be elaborated further here.

[0092] This application also provides a display device, which includes a pixel circuit 10 as described in any of the above embodiments or a display panel. Since the display device includes the pixel circuit 10 of any of the above embodiments, it possesses the beneficial effects of the pixel circuit 10 of any of the above embodiments, which will not be elaborated further here.

[0093] The display devices in this application include, but are not limited to, mobile phones, personal digital assistants (PDAs), tablet computers, e-books, televisions, access control systems, smart landline phones, control consoles, and other devices with display functions.

[0094] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0095] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0096] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A pixel circuit, characterized in that, include: A drive module (100) is configured to configure the voltage of the control terminal of the drive module (100) based on a data signal in a first stage, and the drive module (100) is also configured to generate and output a drive current based on the potential of the control terminal of the drive module (100) in a second stage; wherein the first stage includes a first reset stage. A reset module (200) is electrically connected to the control terminal of the drive module (100). The reset module (200) is used to transmit alternating voltage to the control terminal of the drive module (100) during the first reset phase. In the first reset phase, the alternating voltage is a first voltage; in the second phase, the alternating voltage is a second voltage, and the second voltage is greater than the first voltage.

2. The pixel circuit as described in claim 1, characterized in that, The pixel circuit also includes a signal configuration module (300), which is connected to the reset module (200) and is used to generate and output the alternating voltage.

3. The pixel circuit as described in claim 2, characterized in that, The pixel circuit (10) is applied to the display panel, which includes multiple rows of the pixel circuit (10), and each of the signal configuration modules (300) of the multiple rows of pixel circuit (10) is cascaded in sequence; The delay between the alternating voltages output by two adjacent signal configuration modules (300) is one row cycle.

4. The pixel circuit as described in claim 2, characterized in that, The pixel circuit (10) is applied to the display panel, which includes multiple rows of the pixel circuit (10). Adjacent rows of the pixel circuit (10) form a group, and the pixel circuits (10) in the same group share the same signal configuration module (300). Each signal configuration module (300) is cascaded sequentially. The delay between the alternating voltages output by two adjacent signal configuration modules (300) is at least two line cycles.

5. The pixel circuit according to any one of claims 1 to 4, characterized in that, The driving module (100) includes a first transistor, a second transistor, a third transistor, a fourth transistor, and an energy storage capacitor; the reset module (200) includes a fifth transistor. The first terminal of the first transistor is used to connect to a first power supply voltage. The second terminal of the first transistor is connected to the first terminal of the second transistor and the first terminal of the third transistor. The second terminal of the second transistor is used to connect to the data signal. The control terminal of the second transistor is used to connect to the first scan signal. The second terminal of the third transistor is connected to the first terminal of the fourth transistor. The second terminal of the fourth transistor is used to output the driving current. The control terminals of the first transistor and the fourth transistor are both used to connect to the light emission control signal. The first terminal of the energy storage capacitor is connected to the first terminal of the first transistor. The second terminal of the energy storage capacitor is connected to the control terminal of the third transistor. The first terminal of the fifth transistor is connected to the control terminal of the third transistor, the second terminal of the fifth transistor is used to receive the alternating voltage, and the control terminal of the fifth transistor is used to receive the second scan signal.

6. The pixel circuit as described in claim 5, characterized in that, The first stage also includes a data writing stage, and the pixel circuit (10) also includes a compensation module (400). The compensation module (400) is connected between the second terminal of the third transistor and the control terminal of the third transistor. The compensation module (400) and the second transistor are used to conduct during the data writing phase.

7. The pixel circuit as described in claim 5, characterized in that, The first stage also includes a second reset stage. The pixel circuit (10) further includes a conduction bias stress module (500). The first end of the conduction bias stress module (500) is connected to the second end of the third transistor. The second end of the conduction bias stress module (500) is used to connect to the alternating voltage. The first end of the reset module (200) is connected to the control end of the third transistor. The second end of the reset module (200) is connected to the second end of the third transistor. The first voltage is the reset voltage of the control terminal of the third transistor, and the second voltage is the bias compensation voltage of the third transistor; During both the first reset phase and the second reset phase, the conduction bias stress module (500) is turned on; During the second reset phase, the alternating voltage is the second voltage; Preferably, the first stage further includes a data writing stage, in which the reset module (200) and the second transistor are turned on, and the conduction bias stress module (500) is turned off.

8. The pixel circuit as described in claim 7, characterized in that, The first stage also includes a third reset stage, and the first reset stage, the second reset stage, the data writing stage and the third reset stage are performed sequentially; During the first reset phase, the first voltage is transmitted to the control terminal of the third transistor; During the second reset phase, the second voltage is transmitted to the second terminal of the third transistor; During the data writing phase, the data signal is transmitted to the control terminal of the third transistor; During the third reset phase, the second voltage is transmitted to the second terminal of the third transistor.

9. A display panel, characterized in that, Includes the pixel circuit (10) as described in any one of claims 1 to 8.

10. A display device, characterized in that, Includes the display panel as described in claim 9.

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