Light-emitting unit driving circuit and driving method, pixel circuit and display device

Abstract

This invention proposes a light-emitting unit driving circuit and driving method, a pixel circuit, and a display device. The light-emitting unit driving circuit includes a driving unit, a control switch, a coupling capacitor, and a sampling switch network. The driving unit includes at least a driving switch. The driving switch generates a test current after threshold voltage compensation and a reference driving current in the sampling frame and the display frame, respectively. The sampling switch network latches the aging voltage of the light-emitting unit in the sampling frame and applies a ramp scanning voltage in the display frame. The ramp scanning voltage is superimposed with the aging voltage and coupled to the control switch through the coupling capacitor. The control switch's conduction time is positively correlated with the aging voltage. When the aging degree of the light-emitting unit increases and the aging voltage rises, the conduction time of the control switch in the scanning cycle is correspondingly extended, compensating for the decay of luminous efficiency and achieving grayscale consistency.

Description

Technical Field

[0001] This invention belongs to the field of display technology, and particularly relates to a light-emitting unit driving circuit and method, a pixel circuit, and a display device. Background Technology

[0002] As active-matrix organic light-emitting diode (OLED) display panels evolve towards higher resolution, lower power consumption, and wider dynamic refresh rate technologies, the long-term uniformity of display image quality faces the dual degradation effects of threshold voltage drift in the driving transistors and luminous efficiency decay in the OLEDs. This image quality degradation mainly stems from the degradation of two underlying components within the pixel: the threshold voltage of the driving transistor shifts under prolonged bias stress, leading to a deviation in the driving current at the same data voltage; and the degradation of the OLED material itself, manifested as increased equivalent impedance, higher operating voltage drop, and irreversible decay of luminous efficiency, resulting in a gradual decrease in brightness under the same driving current.

[0003] In existing technologies, the mainstream solution adopts external compensation technology. This solution typically sets up a sensing branch inside the pixel, and uses the vertical blanking period between frames to lead the anode voltage of the organic light-emitting diode out of the panel through an ultra-long data line. The voltage is then sampled by a high-precision analog-to-digital converter in the source driver chip, and the timing controller uses an algorithm to calculate the compensation amount. By updating the amplitude of the analog data voltage written in the next frame, the driving current is forcibly increased to compensate for the brightness loss.

[0004] However, with the continuous improvement of panel specifications, this solution faces insurmountable physical bottlenecks: In high refresh rate mode, the vertical blanking period is extremely compressed, while the data line runs through the entire display area and has extremely large parasitic capacitance. The weak anode aging voltage is extremely difficult to establish a steady state on the data line within a limited microsecond window, resulting in a significant decrease in the sampling accuracy of the analog-to-digital converter and serious errors in compensation. At the same time, the core logic of external compensation is to compensate for the brightness loss by forcibly increasing the driving current through analog amplitude modulation. However, the luminous efficiency decay of organic light-emitting diodes at different current densities is nonlinear. Forcibly increasing the driving voltage in the low current region can easily cause severe color deflection at low gray levels and accelerate the secondary decay of the light-emitting material, forming a vicious cycle. In addition, external compensation requires the source driver chip to integrate a multi-channel high-speed analog-to-digital converter, and the timing controller needs to be configured with a memory with extremely high bandwidth and capacity to process the dual compensation data of millions of pixels on the entire screen in real time, which increases the cost of the driving system and contradicts the low power consumption requirements of mobile display panels. Summary of the Invention

[0005] The purpose of this invention is to provide a light-emitting unit driving circuit that aims to solve the problems of decreased display uniformity caused by threshold voltage drift of driving transistors and decay of luminous efficiency of organic light-emitting diodes, as well as insufficient sampling accuracy and mismatch of compensation logic in external compensation schemes.

[0006] A first aspect of this invention provides a light-emitting unit driving circuit connected to a light-emitting unit, the light-emitting unit driving circuit comprising: The drive unit includes at least a drive switch, the drive switch being used for: During the sampling frame, a test current is generated based on the test voltage after threshold voltage compensation and transmitted to the light-emitting unit; In the display frame, a reference drive current is generated based on the data voltage after threshold voltage compensation; A control switch is connected in series with the drive switch and the light-emitting unit between the anode voltage terminal and the cathode voltage terminal; A coupling capacitor, the first end of which is connected to the control terminal of the control switch; A sampling switch network is connected to the first and second terminals of the coupling capacitor, respectively. The sampling switch network is used for: During the sampling frame, a reference voltage is output to the first terminal of the coupling capacitor and the second terminal of the coupling capacitor and the input terminal of the light-emitting unit according to the first control signal, so as to latch the aging voltage formed by the test current at the input terminal of the light-emitting unit. In the display frame, the connection between the coupling capacitor and the light-emitting unit is disconnected according to the second control signal, and a ramp scan voltage is input to the second terminal of the coupling capacitor. The ramp scan voltage is superimposed with the aging voltage and coupled to the control terminal of the control switch to drive the control switch to work in the linear region and modulate the conduction time of the control switch. The conduction time of the control switch in the linear region is positively correlated with the aging voltage of the light-emitting unit.

[0007] Optionally, the sampling frame sequentially includes a test period and a sampling period, and the display frame sequentially includes a data writing period and a light emission period; The sampling switch network is used for: During the sampling period, a reference voltage is output to the first terminal of the coupling capacitor and the second terminal of the coupling capacitor and the input terminal of the light-emitting unit according to the first control signal, so as to latch the aging voltage formed by the test current at the input terminal of the light-emitting unit; During the data writing period, the connection between the coupling capacitor and the light-emitting unit is disconnected according to the third control signal, and a preset DC voltage is input to the second terminal of the coupling capacitor. The preset DC voltage is superimposed with the aging voltage and coupled to the control terminal of the control switch to drive the control switch to work in the cutoff region. During the light emission period, the connection between the coupling capacitor and the light emission unit is disconnected according to the second control signal, and a ramp scan voltage is input to the second terminal of the coupling capacitor. The ramp scan voltage is superimposed with the aging voltage and coupled to the control terminal of the control switch to drive the control switch to work in the linear region and modulate the conduction time of the control switch.

[0008] Optionally, the drive unit further includes: A light-emitting switch, wherein the control switch, the drive switch, the light-emitting switch and the light-emitting unit are sequentially connected and connected in series between the anode voltage terminal and the cathode voltage terminal, and the control terminal of the light-emitting switch is also connected to the first scan line; The optical emitting switch is used for: During the sampling period of the sampling frame, the light emission signal input from the first scan line triggers the conduction and transmits the test current to the light-emitting unit; During the light emission period of the display frame, the light emission signal triggers the conduction and transmits the reference driving current to the light emission unit.

[0009] Optionally, the drive switch includes a first transistor, a second transistor, and a third transistor; The first terminal of the first transistor is connected to the data line. The second terminal of the first transistor, the first terminal of the second transistor, and the second terminal of the control switch are connected. The first terminal of the control switch is connected to the anode voltage terminal. The control terminals of the first transistor and the third transistor are connected to the second scan line. The second terminal of the second transistor, the first terminal of the third transistor, and the input terminal of the light emission switch are connected. The second terminal of the third transistor is connected to the control terminal of the second transistor.

[0010] Optionally, the sampling frame sequentially includes a first reset period, a test period, and a sampling period, and the display frame sequentially includes a second reset period, a data writing period, and a light emission period; The drive unit further includes: The first reset switch is connected to the input terminal, reset terminal and third scan line of the light-emitting unit. The first reset switch is used to be triggered to turn on and reset the input terminal of the light-emitting unit by the reset control signal input by the third scan line during the first reset period and the second reset period. The second reset switch is connected to the reset terminal, the third scan line, and the control terminal of the second transistor. The second reset switch is used to be triggered to turn on and reset the control terminal of the second transistor by the reset control signal input by the third scan line during the first reset period and the second reset period. The sampling switch network is also used for: During the second reset period, the connection between the coupling capacitor and the light-emitting unit is disconnected according to the third control signal, and a preset DC voltage is input to the second terminal of the coupling capacitor. The preset DC voltage is superimposed on the aging voltage and coupled to the control terminal of the control switch to drive the control switch to work in the cutoff region.

[0011] Optionally, the sampling switch network includes a fourth transistor, a fifth transistor, and a sixth transistor; The first terminal of the fourth transistor is connected to the input terminal of the light-emitting unit. The second terminal of the fourth transistor, the first terminal of the fifth transistor, and the second terminal of the coupling capacitor are connected. The second terminal of the fifth transistor is connected to the first voltage terminal. The first terminal of the sixth transistor, the first terminal of the coupling capacitor, and the control terminal of the control switch are connected. The second terminal of the sixth transistor is connected to the second voltage terminal. The control terminals of the fourth transistor and the sixth transistor are connected to the fourth scan line. The control terminal of the fifth transistor is connected to the fifth scan line. The first voltage terminal receives the preset DC voltage during the second reset period and the data writing period, and writes the ramp scan voltage during the light emission period; The second voltage terminal is used to input the reference voltage.

[0012] A second aspect of the present invention provides a pixel circuit, including a light-emitting unit and a light-emitting unit driving circuit as described above, wherein the light-emitting unit driving circuit is connected to the light-emitting unit.

[0013] A third aspect of the present invention provides a display device including a driving circuit and a pixel circuit as described above, wherein the driving circuit is connected to the pixel circuit.

[0014] A third aspect of this invention provides a method for driving a light-emitting unit, applied to the light-emitting unit driving circuit described above, the method comprising: During the sampling frame, a test voltage and a first control signal are output to control the drive switch to generate a test current and to control the sampling switch network to latch the aging voltage formed by the test current at the input terminal of the light-emitting unit. During the display frame, output data voltage, ramp scan voltage, and a second control signal are used to control the drive switch to generate a reference drive current and drive the control switch to operate in the linear region and modulate the on-time of the control switch.

[0015] Optionally, the sampling frame is the moment the display panel is woken up and / or powered off; The light-emitting unit driving method further includes: At the moment of wake-up or power-down, the test voltage is output to each of the light-emitting unit driving circuits of the display panel to sample the aging voltage of the light-emitting unit corresponding to each of the light-emitting unit driving circuits; Alternatively, the sampling frame is the vertical blanking period of the display panel; The driving method for the light-emitting unit further includes: Calculate the average brightness level of the current or previous display frame; The average brightness level of the image is compared with a preset high brightness threshold and a preset low brightness threshold. When the average brightness level of the image is higher than the preset high brightness threshold, during the next vertical blanking period, aging voltage sampling operation is performed on some of the light-emitting units corresponding to the light-emitting unit driving circuit in a spatial discrete manner. When the average brightness level of the image is lower than the preset low brightness threshold, the current sampling period is skipped, and the latched aging voltage is reused for compensation.

[0016] The beneficial effects of the present invention embodiments compared with the prior art are as follows: The above-mentioned light-emitting unit driving circuit includes a driving unit, a control switch, a coupling capacitor, and a sampling switch network. The driving unit includes at least a driving switch. The driving switch generates a test current and a reference driving current after threshold voltage compensation in the sampling frame and the display frame, respectively. The sampling switch network latches the aging voltage of the light-emitting unit in the sampling frame and applies a ramp scanning voltage in the display frame. The ramp scanning voltage is superimposed with the aging voltage and coupled to the control switch through the coupling capacitor. The control switch's conduction time is positively correlated. When the aging degree of the light-emitting unit increases and the aging voltage increases, the conduction time of the control switch in the scanning cycle is correspondingly extended, compensating for the decay of luminous efficiency and achieving grayscale consistency. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the first structure of the light-emitting unit driving circuit provided in Embodiment 1 of the present invention; Figure 2 This is a waveform diagram of the on-time of the control switch and the gate voltage provided in Embodiment 1 of the present invention; Figure 3 This is a schematic diagram of a second structure of the light-emitting unit driving circuit provided in Embodiment 1 of the present invention; Figure 4 This is a schematic diagram of the signal waveform of the light-emitting unit driving circuit provided in Embodiment 1 of the present invention; Figure 5 This is a schematic diagram of a third structure of the light-emitting unit driving circuit provided in Embodiments 1 and 2 of the present invention; Figure 6 These are schematic diagrams of the signal waveforms of the light-emitting unit driving circuits provided in Embodiments 1 and 2 of the present invention; Figure 7 This is a schematic diagram of the pixel circuit provided in Embodiment 3 of the present invention; Figure 8 This is a schematic diagram of the structure of the display device provided in Embodiment 4 of the present invention; Figure 9 This is a schematic diagram of the first process of the light-emitting unit driving method provided in Embodiment 5 of the present invention; Figure 10 This is a schematic diagram of the second process of the light-emitting unit driving method provided in Embodiment 5 of the present invention.

[0018] The figures in the diagram are labeled as follows: 101. Pixel circuit; 102. Driving circuit; 10. Light-emitting unit driving circuit; 20. Light-emitting unit; 11. Driving unit; 12. Sampling switch network; 111. Driving switch; ELVDD, Anode voltage terminal; ELVSS, Cathode voltage terminal; OLED, Organic Light Emitting Diode; Da, Data line; C1, Coupling capacitor; K1, Control switch; K2, Light emitting switch; K3, First reset switch; K4, Second reset switch; S1, First scan line; S2, Second scan line; S3, Third scan line; S4, Fourth scan line; S5, Fifth scan line; T1, First transistor; T2, Second transistor; T3, Third transistor; T4, Fourth transistor; T5, Fifth transistor; T6, Sixth transistor; Vint, Reset terminal; V1, First voltage terminal; V2, Second voltage terminal; Cst, Storage capacitor; T10, Sampling frame; T20, Display frame; T11, Test period; T12, Sampling period; T13, First reset period; T21, Data writing period; T22, Light emission period; T23, Second reset period; Vt, test voltage; Vd, data voltage; V0, preset DC voltage; Vramp, ramp scan voltage. Detailed Implementation

[0019] To make the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.

[0020] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0021] Example 1 The first aspect of the present invention provides a light-emitting unit driving circuit 10 connected to a light-emitting unit 20. The light-emitting unit driving circuit 10 independently matches a single light-emitting unit 20 and forms a pixel circuit 101. The light-emitting unit 20 may be a corresponding light-emitting diode. In an optional embodiment, the light-emitting unit 20 is an organic light-emitting diode (OLED).

[0022] Among them, such as Figure 1 As shown, in this embodiment, the light-emitting unit driving circuit 10 includes: Drive unit 11, drive unit 11 includes at least drive switch 111, drive switch 111 is used for: In sampling frame T10, a test current is generated based on the test voltage Vt after threshold voltage compensation and transmitted to the light-emitting unit 20. In display frame T20, a reference drive current is generated based on the data voltage Vd after threshold voltage compensation; The control switch K1, the drive switch 111, and the light-emitting unit 20 are connected in series between the anode voltage terminal ELVDD and the cathode voltage terminal ELVSS. Coupling capacitor C1, with its first terminal connected to the control terminal of control switch K1; Sampling switch network 12 is connected to the first and second terminals of coupling capacitor C1 respectively. Sampling switch network 12 is used for: In sampling frame T10, a reference voltage is output to the first terminal of coupling capacitor C1 and the second terminal of coupling capacitor C1 is connected to the input terminal of light-emitting unit 20 according to the first control signal, so as to latch the aging voltage formed by the test current at the input terminal of light-emitting unit 20. In display frame T20, the connection between coupling capacitor C1 and light-emitting unit 20 is disconnected according to the second control signal, and ramp scanning voltage Vramp is input to the second terminal of coupling capacitor C1. The ramp scanning voltage Vramp is superimposed with the aging voltage and coupled to the control terminal of control switch K1 to drive control switch K1 to work in the linear region and modulate the conduction time of control switch K1. The conduction time of control switch K1 in the linear region is positively correlated with the aging voltage of light-emitting unit 20.

[0023] In this embodiment, the light-emitting unit driving circuit 10 can operate in sampling frame T10 and display frame T20. The sampling frame T10 can be selected during the vertical blanking period or the power-on period as needed, and the display frame T20 is the normal display light-emitting period T22 of the light-emitting unit 20.

[0024] The light-emitting unit driving circuit 10 includes a driving unit 11, a control switch K1, a coupling capacitor C1, and a sampling switch network 12. Each device is electrically connected through a fixed topology and coordinates with each other in time to complete the voltage acquisition of sampling frame T10 and the brightness compensation of display frame T20 in stages.

[0025] The driving unit 11 includes at least a driving switch 111. The driving switch 111 is the core current output device of the pixel circuit 101. It has both voltage threshold compensation and constant current output functions. It can output a stable test current and a reference driving current according to the input voltage signal of different working stages of the circuit, so as to meet the current requirements of the aging sampling of the light-emitting unit 20 and the display of the screen.

[0026] During the sampling frame T10 operation phase of the display panel, the drive switch 111 inputs the test voltage Vt, which is calibrated by the internal threshold compensation network to obtain the threshold voltage compensated test voltage Vt. Based on the threshold voltage compensated test voltage Vt, a constant amplitude test current is stably output and completely transmitted to the back-end connected light-emitting unit 20. Under the excitation of the constant test current, the light-emitting unit 20 quickly establishes a stable steady-state aging voltage, restoring the current aging state of the light-emitting unit 20 and providing a real and effective signal source for subsequent voltage sampling and data latching.

[0027] During the display frame T20 operation phase of the display panel, the drive switch 111 switches the working configuration, receives the data voltage Vd, and performs threshold voltage compensation to obtain the threshold-compensated data voltage Vd. Based on the threshold-compensated data voltage Vd, a corresponding reference drive current is output. This reference drive current is not affected by transistor threshold drift or aging of the light-emitting device, and can match the light emission requirements of the current grayscale, achieving precise control of the current amplitude dimension and ensuring the stability of the light emission brightness of the light-emitting unit 20.

[0028] The control switch K1, drive switch 111, and light-emitting unit 20 adopt a series topology. All three are connected in series between the anode voltage terminal ELVDD and the cathode voltage terminal ELVSS, forming a complete current transmission and light-emitting circuit. The control switch K1 can be a corresponding transistor. In one optional embodiment, the control switch K1 is a P-channel field-effect transistor fabricated using oxide semiconductor technology. This device is suitable for high-frequency voltage modulation scenarios and can stably switch between the linear and cutoff regions. The control switch K1 primarily performs the function of light-emitting duration modulation. By precisely controlling its own conduction time, it achieves brightness compensation in the light-emitting time dimension, forming a dual compensation mechanism of amplitude modulation and pulse width modulation together with the current amplitude regulation of the drive switch 111.

[0029] The coupling capacitor C1 is a high-stability, low-leakage surface-mount capacitor with long-term charge latching capability, making it a core component for achieving non-repeating sampling compensation. The first terminal of the coupling capacitor C1 is connected to the control terminal of the control switch K1, and the second terminal is a signal receiving terminal, which can be connected to the aging voltage and ramp scan voltage Vramp of the light-emitting unit 20, respectively. The coupling capacitor C1 can solidify the aging voltage of the light-emitting unit 20 through the charge latching effect, eliminating the need for frame-by-frame resampling, significantly reducing the frequency of circuit switching operations, and minimizing dynamic power consumption.

[0030] The sampling switch network 12 is the core module for circuit timing control and signal acquisition. It is connected to the first and second terminals of coupling capacitor C1 respectively. It can accurately switch the circuit on and off states according to different control signals output by the system, and orderly complete a series of timing operations such as voltage configuration, signal acquisition, charge latching, and voltage coupling, ensuring the orderly operation of each stage of the circuit.

[0031] During the sampling frame T10 operation phase, the sampling switch network 12 receives the first control signal output by the system and simultaneously executes two operations. The first operation is to output a reference voltage of fixed amplitude to the first terminal of the coupling capacitor C1, completing the accurate configuration of the initial voltage of the coupling capacitor C1 and unifying the initial potential reference of the coupling capacitor C1. The second operation is to conduct the electrical path between the second terminal of the coupling capacitor C1 and the input terminal of the light-emitting unit 20, enabling the coupling capacitor C1 to quickly capture the steady-state aging voltage formed at the input terminal of the light-emitting unit 20 under the action of the test current, and to complete the long-term storage of the aging voltage data through the charge latching mechanism, thus completely recording the real-time aging state of the light-emitting unit 20.

[0032] During the operation of display frame T20, the sampling switch network 12 receives the second control signal output by the system and preferentially disconnects the electrical connection between the coupling capacitor C1 and the light-emitting unit 20. This isolates the interference of the working voltage of the light-emitting unit 20 on the latched aging voltage under display frame T20, ensuring the stability and accuracy of the aging data. Subsequently, a high-frequency ramp scan voltage Vramp is continuously input to the second terminal of the coupling capacitor C1. The ramp scan voltage Vramp and the aging voltage latched by the capacitor are superimposed and coupled, and the resulting composite voltage signal is directly transmitted to the control terminal of the control switch K1 to regulate the operating range of the control switch K1.

[0033] Control switch K1 operates stably in the linear region under the drive of a composite voltage signal, and its conduction time can be flexibly modulated according to changes in the amplitude of the composite voltage. The overall circuit parameters are calibrated to ensure that the conduction time of control switch K1 in the linear region is positively correlated with the aging voltage of the light-emitting unit 20. When the light-emitting unit 20 ages after long-term operation and the aging voltage increases, the conduction time of control switch K1 automatically extends to compensate for the brightness loss caused by the degradation of the light-emitting material's efficiency. When the aging degree of the light-emitting unit 20 is relatively mild and the aging voltage is low, the conduction time of control switch K1 adaptively shortens to match the normal brightness requirements. The entire adaptive compensation is completed through pure hardware circuit logic, requiring no external algorithm calculations or data storage, completely avoiding the various defects of traditional compensation technologies.

[0034] The light-emitting unit driving circuit 10 is equipped with an oxide semiconductor switching device, which has extremely low leakage current characteristics. After sampling is completed and the switching device is completely turned off, the coupling capacitor C1 can form a completely floating charge container. In the subsequent light-emitting modulation stage, voltage coupling is completed only through a single-sided plate connected to the ramp scanning voltage Vramp, without a charge discharge circuit, which can achieve long-term latching of compensation charge. After a single sampling is completed, it can support accurate compensation work for multiple subsequent frames without frequent repeated sampling, further reducing circuit power consumption and device losses.

[0035] For example, assuming the reference voltage is -3V, the voltage at the anode voltage terminal ELVDD is 5V, the turn-off voltage of control switch K1 is -1V, the amplitude variation range of the ramp scan voltage Vramp is 0-8V, and the scan period of the ramp scan voltage Vramp is 100us, the slope of the ramp scan voltage Vramp is 0.08V / us. When the gate voltage of control switch K1 is 4V, control switch K1 is at the critical point.

[0036] When the light-emitting unit 20 is not aged, assuming that under ideal conditions, the voltage drop of the light-emitting unit 20 is normal, the detected anode voltage, i.e. the aging voltage, is 0V.

[0037] When sampling frame T10 is latched by coupling capacitor C1, the latching voltage difference ΔV of coupling capacitor C1 is ΔV = Vref - Vb = -3V -0V = -3V.

[0038] When frame T20 is coupled, the gate voltage of control switch K1 is Vramp -3V.

[0039] like Figure 2 As shown, it is turned off when the gate voltage is 4V. At a slope of 0.08V / us, it takes 87.5us, that is, within 87.5us, the ramp scan voltage Vramp changes from 0V to 4V, and the control switch K1 remains on.

[0040] When the light-emitting unit 20 has aged, the voltage drop of the light-emitting unit 20 increases to 3.5V, and the detected anode voltage increases to Vb = 0.5V.

[0041] When sampling frame T10 is latched by coupling capacitor C1, the latching voltage difference of coupling capacitor C1 is ΔV = Vref - Vb = -3V -0.5V = -3.5V.

[0042] When frame T20 is coupled, the gate voltage of control switch K1 is Vramp -3.5V.

[0043] It is turned off when the gate voltage is 4V. At the slope of 0.08V / us, it takes 93.75us, that is, when the light-emitting unit 20 ages, the light-emitting time of the light-emitting unit 20 is compensated. The light-emitting compensation time is 93.75us - 87.5us = 6.25us. Moreover, the higher the aging voltage of the light-emitting unit 20, the longer the light-emitting compensation time, which makes up for the brightness loss caused by the degradation of the light-emitting material efficiency.

[0044] In order to achieve a stable aging voltage for the anode voltage of the light-emitting unit 20 quickly in the sampling frame T10, in an optional embodiment, the test voltage Vt is greater than the data voltage Vd. In the sampling frame T10, the test current generated by the test voltage Vt is greater than the reference drive current. When the test current is output to the light-emitting unit 20, the anode of the light-emitting unit 20 can quickly obtain a stable aging voltage.

[0045] Correspondingly, sampling frame T10 needs to complete the writing of the test voltage Vt and the current output, and display frame T20 also needs to complete the data writing and light emission control. Therefore, in an optional embodiment, such as Figure 3 As shown, sampling frame T10 includes test period T11 and sampling period T12 in sequence, and display frame T20 includes data writing period T21 and light emission period T22 in sequence.

[0046] Corresponding to different time periods, the drive switch 111 and the sampling switch network 12 operate in different states.

[0047] Among them, the drive switch 111 is used for: During the test period T11, the test voltage Vt is input and threshold compensation of the test voltage Vt is performed under control. During the sampling period T12, the input test voltage Vt is cut off, and a test current is generated to the light-emitting unit 20 based on the test voltage Vt after threshold voltage compensation. During the data writing period T21, the data voltage Vd is written, and threshold compensation for the data voltage Vd is performed in a controlled manner. During the light-emitting period T22, the input data voltage Vd is cut off, and a reference drive current is generated to the light-emitting unit 20 based on the data voltage Vd after threshold voltage compensation.

[0048] Sampling switch network 12 is used for: During the sampling period T12, a reference voltage is output to the first terminal of the coupling capacitor C1 and the second terminal of the coupling capacitor C1 is connected to the input terminal of the light-emitting unit 20 according to the first control signal, so as to latch the aging voltage formed by the test current at the input terminal of the light-emitting unit 20. During the data writing period T21, the connection between the coupling capacitor C1 and the light-emitting unit 20 is disconnected according to the third control signal, and a preset DC voltage V0 is input to the second end of the coupling capacitor C1. The preset DC voltage V0 is superimposed with the aging voltage and coupled to the control end of the control switch K1 to drive the control switch K1 to work in the cutoff region. During the light emission period T22, the connection between the coupling capacitor C1 and the light emission unit 20 is disconnected according to the second control signal, and the ramp scan voltage Vramp is input to the second end of the coupling capacitor C1. The ramp scan voltage Vramp is superimposed with the aging voltage and coupled to the control terminal of the control switch K1 to drive the control switch K1 to work in the linear region and modulate the conduction time of the control switch K1.

[0049] In this embodiment, as Figure 4 As shown, the sampling frame T10 includes a test period T11, which is the aging voltage generation stage. During this period, the corresponding control unit outputs a fixed timing signal to fully turn on the drive switch 111 and perform threshold compensation for the test voltage Vt. Then, it switches to the sampling period T12. The drive switch 111 outputs a test current of a preset amplitude according to the threshold-compensated test voltage Vt and continuously transmits it to the light-emitting unit 20. Under the continuous excitation of the constant test current, the light-emitting unit 20 quickly completes the internal charge establishment and forms a stable steady-state aging voltage at the input. This voltage value can accurately reflect the current material aging degree of the pixel, providing an accurate signal basis for subsequent sampling. During the entire test period T11, the other switching devices in the circuit remain in a fixed state to prevent stray signals from interfering with the voltage establishment process.

[0050] During sampling period T12 of sampling frame T10, which is the aging voltage latching stage, the sampling switch network 12 responds to the first control signal and simultaneously completes the input of the reference voltage at the first terminal of coupling capacitor C1 and the acquisition of the aging voltage at the second terminal of coupling capacitor C1. Under the combined action of the reference voltage and the aging voltage, a fixed potential difference is formed between the two plates of coupling capacitor C1. The aging voltage data is solidified through the charge latching effect, completing the acquisition and storage of single-pixel aging features. After sampling, the data remains stable for a long period of time.

[0051] The data writing period T21 included in frame T20 is the screen data configuration and circuit initialization stage. During this period, the data voltage Vd is written to the drive switch 111, which compensates for the threshold voltage. During data writing period T21, the sampling switch network 12 receives the third control signal output by the system, completely disconnecting the electrical connection between the coupling capacitor C1 and the light-emitting unit 20, thus completely isolating the interference of the light-emitting unit 20's operating voltage on the capacitor-locked data. Simultaneously, the sampling switch network 12 inputs a preset DC voltage V0 of fixed amplitude to the second terminal of the coupling capacitor C1. The preset DC voltage V0 and the aging voltage of the capacitor-locked data are superimposed and coupled, generating a composite voltage that acts on the control terminal of the control switch K1, driving the control switch K1 into a fully off state. This configuration ensures that the control switch K1 does not mis-turn on during the data writing stage, preventing invalid light emission from the light-emitting unit 20 and unnecessary current loss, providing a clean and stable circuit state for subsequent screen data writing.

[0052] During the light emission period T22, which is the image imaging and brightness compensation stage, the sampling switch network 12 continuously responds to the second control signal, keeping the coupling capacitor C1 disconnected from the light-emitting unit 20, and continuously inputting a high-frequency sawtooth-shaped ramp scanning voltage Vramp to the second terminal of the coupling capacitor C1. The ramp scanning voltage Vramp is coupled with the latched aging voltage in real time, dynamically adjusting the gate voltage of the control switch K1, driving the control switch K1 to stably switch to the linear region. When the control switch K1 is turned on, the drive switch 111 generates a reference drive current to the light-emitting unit 20 based on the threshold-compensated data voltage Vd. At the same time, the control switch K1 adaptively modulates the on-time according to the amplitude of the aging voltage, accurately compensating for the aging brightness loss of the light-emitting unit 20, and realizing accurate brightness calibration and color correction for each frame.

[0053] By implementing independent time-sequence management, the four core actions of voltage generation, data latching, data configuration, and illumination compensation are separated into independent time slots, completely eliminating signal crosstalk between the various work steps and solving the problems of chaotic timing and unstable sampling in traditional compensation technologies. Simultaneously, the segmented timing design can adapt to dynamic working scenarios with high refresh rates, completing each operation in an orderly manner within a microsecond-level time window, significantly improving compensation accuracy and image stability in high frame rate display states.

[0054] In one alternative embodiment, in order to achieve the output of the drive current, as in one alternative embodiment, Figure 3 As shown, the drive unit 11 also includes: The light emitting switch K2, control switch K1, drive switch 111, light emitting switch K2 and light-emitting unit 20 are connected in sequence and connected in series between the anode voltage terminal ELVDD and the cathode voltage terminal ELVSS. The control terminal of the light emitting switch K2 is also connected to the first scan line S1. Optical emission switch K2 is used for: During the sampling period T12 of sampling frame T10, the light emission signal input by the first scan line S1 triggers the conduction and transmits the test current to the light-emitting unit 20; During the light emission period T22 of display frame T20, the light emission signal triggers the conduction and transmits the reference driving current to the light emission unit 20.

[0055] In this embodiment, as Figure 4 As shown, the control terminal of the optical emitting switch K2 is connected to the first scan line S1, receiving the optical emission signal output by the first scan line S1. It can perform conduction and cutoff actions according to the timing requirements of different working periods, independently controlling the current on / off state of the light-emitting branch. The optical emitting switch K2 can be a transistor device.

[0056] During sampling period T12 of sampling frame T10, the first scan line S1 outputs a valid light emission signal, triggering the light emission switch K2 to fully conduct, thus establishing the current transmission path between the drive switch 111 and the light-emitting unit 20. The test current output by the drive switch 111 can be transmitted to the light-emitting unit 20, ensuring that the light-emitting unit 20 establishes a steady-state aging voltage in a very short time, improving sampling speed and sampling accuracy, and adapting to short sampling windows under high refresh rates.

[0057] During the light emission period T22 of display frame T20, the first scan line S1 continuously outputs an effective light emission signal, triggering the light emission switch K2 to remain stably on, enabling the reference driving current output by the drive switch 111 to be transmitted to the light emission unit 20, ensuring that the light emission unit 20 emits light stably according to the preset grayscale. At the same time, the on state of the light emission switch K2 can be coordinated with the on-time modulation of the control switch K1 to accurately match the brightness compensation rhythm, ensuring that the compensated light emission brightness is uniform and stable, without brightness jumps or color jitter.

[0058] During non-light-emitting core periods such as the test period T11 of sampling frame T10 and the data writing period T21 of display frame T20, the first scan line S1 pauses the output of light emission signal, and the light emission switch K2 remains in the off state, cutting off the current path of the light-emitting branch, eliminating invalid light emission and charge accumulation caused by stray current in the circuit, ensuring the purity of the circuit at each stage of operation, and reducing image ghosting and abnormal pixel lighting problems.

[0059] The drive switch 111 can be a corresponding drive transistor, data switch, etc. In an optional embodiment, such as Figure 5 As shown, the drive switch 111 includes a first transistor T1, a second transistor T2, and a third transistor T3; The first terminal of the first transistor T1 is connected to the data line Da. The second terminal of the first transistor T1, the first terminal of the second transistor T2, and the second terminal of the control switch K1 are connected. The first terminal of the control switch K1 is connected to the anode voltage terminal ELVDD. The control terminal of the first transistor T1 and the control terminal of the third transistor T3 are connected to the second scan line S2. The second terminal of the second transistor T2, the first terminal of the third transistor T3, and the input terminal of the light emission switch K2 are connected. The second terminal of the third transistor T3 is connected to the control terminal of the second transistor T2.

[0060] In this embodiment, the driving unit 11 further includes a storage capacitor Cst. The first end of the storage capacitor Cst is connected to the anode voltage terminal ELVDD, and the second end of the storage capacitor Cst is connected to the control terminal of the second transistor T2. The storage capacitor Cst is used to store charge and stabilize the voltage of the control terminal of the second transistor T2.

[0061] The first terminal of the first transistor T1 is connected to the data line Da of the display panel, and can receive the data voltage Vd and test voltage Vt transmitted by the system in real time, serving as the input port for the circuit voltage signal. The second terminal of the first transistor T1 is interconnected with the first terminal of the second transistor T2 and the second terminal of the control switch K1, realizing the transmission and connection of voltage signal and drive current, ensuring smooth conduction of signal and current. The first terminal of the control switch K1 is directly connected to the system anode voltage terminal ELVDD to obtain a stable system power supply voltage, providing power support for the light-emitting circuit.

[0062] The control terminals of the first transistor T1 and the third transistor T3 are both connected to the second scan line S2. Both types of transistors synchronously receive the timing control signal output from the second scan line S2, achieving synchronous on / off and ensuring the timing consistency of voltage input and threshold control. The second terminal of the second transistor T2 and the first terminal of the third transistor T3 are interconnected with the input terminal of the light-emitting switch K2, completing the final output connection of the driving current and providing a stable current to the light-emitting unit 20.

[0063] The second terminal of the third transistor T3 is connected to the control terminal of the second transistor T2. The control terminal of the third transistor T3 is also connected to the second scan line S2, and the working state of the second transistor T2 can be precisely controlled according to the timing signal output by the second scan line S2.

[0064] like Figure 4As shown, during the test period T11 of sampling frame T10, the first transistor T1 and the third transistor T3 receive the timing control signal input from the second scan line S2 and turn on. At this time, the test voltage Vt is written to the second transistor T2 and undergoes threshold compensation via the third transistor T3, completing the threshold voltage extraction and compensation of the drive branch. This offsets the threshold drift caused by long-term transistor operation and ensures the constantness of the drive current output. At this time, the gate voltage of the second transistor T2 is Vt + Vth, where Vth represents the threshold voltage.

[0065] During the sampling period T12 of sampling frame T10, control switch K1 and light emission switch K2 are turned on, and the second transistor T2 acts as a driving transistor to generate a test current to the light-emitting unit 20 based on the test voltage Vt after threshold voltage compensation, so that the anode voltage of the light-emitting unit 20 can quickly reach the aging voltage.

[0066] During the data writing period T21 of display frame T20, the first transistor T1 and the third transistor T3 receive the timing control signal input from the second scan line S2 and turn on. At this time, the data voltage Vd is written to the second transistor T2 and undergoes threshold compensation via the third transistor T3. This completes the threshold voltage extraction and compensation of the drive branch, offsetting the threshold drift caused by long-term transistor operation and ensuring the constantness of the drive current output. At this time, the gate voltage of the second transistor T2 is Vd + Vth, where Vth represents the threshold voltage.

[0067] During the light-emitting period T22, control switch K1 and light-emitting switch K2 are turned on, and the second transistor T2 acts as a driving transistor. Based on the data voltage Vd after threshold voltage compensation, a reference driving current is generated to the light-emitting unit 20 so that the light-emitting unit 20 displays the corresponding gray level.

[0068] Furthermore, in order to eliminate residual charge between frames, in an optional embodiment, such as Figure 6 As shown, the sampling frame T10 sequentially includes the first reset period T13, the test period T11, and the sampling period T12, and the display frame T20 sequentially includes the second reset period T23, the data writing period T21, and the light emission period T22. like Figure 5 As shown, the drive unit 11 also includes: The first reset switch K3 is connected to the input terminal, reset terminal Vint and third scan line S3 of the light-emitting unit 20. The first reset switch K3 is used to be triggered to conduct and reset the input terminal of the light-emitting unit 20 by the reset control signal input by the third scan line S3 during the first reset period T13 and the second reset period T23. The second reset switch K4 is connected to the reset terminal Vint, the third scan line S3, and the control terminal of the second transistor T2. The second reset switch K4 is used to be triggered to conduct and reset the control terminal of the second transistor T2 by the reset control signal input by the third scan line S3 during the first reset period T13 and the second reset period T23. The sampling switch network 12 is also used for: During the second reset period T23, the connection between the coupling capacitor C1 and the light-emitting unit 20 is disconnected according to the third control signal, and a preset DC voltage V0 is input to the second end of the coupling capacitor C1. The preset DC voltage V0 is superimposed with the aging voltage and coupled to the control end of the control switch K1 to drive the control switch K1 to work in the cutoff region.

[0069] In this embodiment, during the first reset period T13 of sampling frame T10 and the second reset period T23 of display frame T20, the third scan line S3 outputs a valid reset control signal, triggering the first reset switch K3 to be fully turned on. After the first reset switch K3 is turned on, the voltage of the input terminal of the light-emitting unit 20 is directly reset, completely clearing the residual charge accumulated inside the light-emitting unit 20, forcing the light-emitting unit 20 into a deep reverse bias cutoff state, eliminating problems such as invalid light emission and voltage offset caused by residual charge, and ensuring the authenticity of voltage acquisition during the sampling stage and the purity of the image during the display stage.

[0070] The second reset switch K4 is simultaneously connected to the reset terminal Vint, the third scan line S3, and the control terminal of the second transistor T2, and responds synchronously with the first reset switch K3 to the reset control signal of the third scan line S3. During the first reset period T13 and the second reset period T23, the second reset switch K4 is synchronously turned on to reset the voltage at the control terminal of the second transistor T2, forcibly resetting the working state of the drive switch 111, eliminating the influence of the residual voltage signal from the previous working cycle, ensuring that the subsequent test voltage Vt acquisition and data voltage Vd writing can be accurately completed, and guaranteeing the accuracy of transistor threshold voltage compensation.

[0071] The voltage at the reset terminal Vint can be set accordingly, for example, 0V or a negative voltage. In an optional embodiment, the voltage at the reset terminal Vint is a negative voltage. This negative voltage reset mechanism ensures that the transistor gate is fully reset, allowing the driving transistor to enter a deep-on preparatory state, providing the optimal device operating state for subsequent threshold voltage extraction and data voltage Vd writing. At the same time, the negative voltage reset can maximize the clearing of residual charge in the light-emitting unit 20, completely eliminating the image ghosting problem.

[0072] During the second reset period T23 of display frame T20, the sampling switch network 12 synchronously responds to the third control signal, keeping the coupling capacitor C1 disconnected from the light-emitting unit 20, and inputting a preset DC voltage V0 to the second terminal of the coupling capacitor C1. The preset DC voltage V0 and the aging voltage latched by the capacitor are superimposed and coupled in real time, and the resulting composite voltage acts on the control terminal of the control switch K1, forcibly driving the control switch K1 to enter the fully cut-off state, completing the initialization preparation of display frame T20, and providing a stable circuit foundation for subsequent data voltage Vd writing and accurate light emission compensation.

[0073] Example 2 The sampling switch network 12 can select a corresponding switch and connect it to the corresponding voltage terminal. In an optional embodiment, such as... Figure 5 As shown, the sampling switch network 12 includes a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6; The first terminal of the fourth transistor T4 is connected to the input terminal of the light-emitting unit 20. The second terminal of the fourth transistor T4, the first terminal of the fifth transistor T5, and the second terminal of the coupling capacitor C1 are connected. The second terminal of the fifth transistor T5 is connected to the first voltage terminal V1. The first terminal of the sixth transistor T6, the first terminal of the coupling capacitor C1, and the control terminal of the control switch K1 are connected. The second terminal of the sixth transistor T6 is connected to the second voltage terminal V2. The control terminals of the fourth transistor T4 and the sixth transistor T6 are connected to the fourth scan line S4. The control terminal of the fifth transistor T5 is connected to the fifth scan line S5. The first voltage terminal V1 receives a preset DC voltage V0 during the second reset period T23 and the data writing period T21, and writes the ramp scan voltage Vramp during the light emission period T22. The second voltage terminal V2 is used to input the reference voltage.

[0074] In this embodiment, the first terminal of the fourth transistor T4 is connected to the input terminal of the light-emitting unit 20, and is used to collect the aging voltage signal of the light-emitting unit 20 in real time during the sampling period T12, so as to accurately capture the pixel aging state parameters. The second terminal of the fourth transistor T4 is connected to the first terminal of the fifth transistor T5 and the second terminal of the coupling capacitor C1, so that the collected aging voltage can be transmitted to the second terminal of the coupling capacitor C1 in real time, completing the input docking of the aging voltage.

[0075] The second terminal of the fifth transistor T5 is connected to the first voltage terminal V1. The first voltage terminal V1 has a multi-mode voltage output function, which can output voltage signals of different amplitudes and forms according to different working periods of the circuit, accurately adapting to the working requirements of each stage. During the second reset period T23 and the data writing period T21, the first voltage terminal V1 outputs a preset DC voltage V0 with a fixed amplitude, which is transmitted to the second terminal of the coupling capacitor C1 through the fifth transistor T5, and completes the cut-off state configuration of the control switch K1 in conjunction with the aging voltage. During the light emission period T22, the first voltage terminal V1 outputs a continuously varying high-frequency ramp scan voltage Vramp, which is input to the second terminal of the coupling capacitor C1 through the fifth transistor T5, realizing the dynamic modulation of the conduction time of the control switch K1.

[0076] The first terminal of the sixth transistor T6 is simultaneously connected to the first terminal of the coupling capacitor C1 and the control terminal of the control switch K1, enabling direct transmission of the voltage-coupled signal to the control switch K1. The second terminal of the sixth transistor T6 is connected to the second voltage terminal V2, which outputs a preset reference voltage to provide a stable initial voltage reference for the coupling capacitor C1, ensuring that the initial potential of each sampling is consistent and improving the comparability and accuracy of the sampled data.

[0077] The control terminals of the fourth transistor T4 and the sixth transistor T6 are both connected to the fourth scan line S4. Both transistors synchronously receive the timing control signal from the fourth scan line S4, achieving synchronous on / off and ensuring the timing synchronization of aging voltage acquisition and reference voltage configuration. The control terminal of the fifth transistor T5 is independently connected to the fifth scan line S5, receiving timing commands from it separately. It can independently switch between on / off states according to different operating periods, precisely matching the timing requirements of DC voltage input and ramp voltage input.

[0078] Among them, such as Figure 6 As shown, during the sampling period T12, the timing control signal is input to the fourth scan line S4, the fourth transistor T4 and the sixth transistor T6 are turned on, the aging voltage is stored at the second terminal of the coupling capacitor C1, and the reference voltage is written to the first terminal of the coupling capacitor C1. The coupling capacitor C1 latches the aging capacitor and drives the control switch K1 to turn on.

[0079] During the second reset period T23 and the data writing period T21, the fifth scan line S5 inputs a timing control signal, the fifth transistor T5 is turned on, and the preset DC voltage V0 is written to the second terminal of the coupling capacitor C1. After the preset DC voltage V0 is superimposed with the aging voltage, the drive control switch K1 is turned off.

[0080] During the light emission period T22, the fifth scan line S5 inputs a timing control signal, the fifth transistor T5 is turned on, and the ramp scan voltage Vramp is written to the second terminal of the coupling capacitor C1. The aging voltage and the ramp scan voltage Vramp are superimposed to drive the control switch K1 to work in the linear region, and the conduction time of the control switch K1 is adjusted according to the magnitude of the aging voltage.

[0081] Correspondingly, the first control signal includes the timing control signal input by the fifth scan line S5 and the preset DC voltage V0, and the second control signal includes the timing control signal input by the fourth scan line S4.

[0082] In an optional embodiment, the first transistor T1, the second transistor T2, and the third transistor T3 are P-channel field-effect transistors, and the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are N-channel field-effect transistors.

[0083] Example 3 A second aspect of the present invention provides a pixel circuit 101, such as... Figure 7 As shown, the pixel circuit 101 includes a light-emitting unit 20 and a light-emitting unit driving circuit 10. The specific structure of the light-emitting unit driving circuit 10 is as described in the above embodiments. Since this pixel circuit 101 adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be described in detail here. The light-emitting unit driving circuit 10 is connected to the light-emitting unit 20.

[0084] The light-emitting unit 20 and the light-emitting unit driving circuit 10 form a single pixel circuit 101. The pixel circuits 101 are arranged in an array to form a display module. The display module is connected to the data line Da, the scan line, the corresponding control signal terminal and the power supply terminal. Under the drive of the data voltage Vd, the scan signal, multiple control signals and the voltage signal of the power supply terminal, the corresponding image information is displayed.

[0085] Example 4 A third aspect of the present invention provides a display device, such as... Figure 8 As shown, the display device includes a driving circuit 102 and a pixel circuit 101. The specific structure of the pixel circuit 101 is as described in the above embodiments. Since this display device adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be described in detail here. The driving circuit 102 is connected to the pixel circuit 101.

[0086] The display device also includes a display panel, on which pixel circuits 101 are arrayed. The display panel is also provided with multiple data lines Da and scan lines. Each light-emitting unit driving circuit 10 is connected to a data line Da and multiple scan lines. The data lines Da and scan lines are connected to the driving circuit 102. The driving circuit 102 is used to output scanning signals line by line through multiple scan lines and to output corresponding test voltages Vt and data voltages Vd to each light-emitting unit driving circuit 10 in the pixel circuit 101 through multiple columns of data lines Da when driving each line. The light-emitting unit driving circuit 10 is triggered to work according to the received scan signal, test voltage Vt and data voltage Vd and generates a current signal to the light-emitting unit 20, and generates an aging voltage or a driving voltage to display the corresponding image information.

[0087] The driving circuit 102 may include a timing control module, a scan driving module, a multi-channel voltage output module, a signal scheduling module, etc. The driving circuit 102 is responsible for uniformly outputting various scan control signals, data voltage Vd, test voltage Vt, ramp scan voltage Vramp, reference voltage, and preset DC voltage V0, accurately controlling the timing operation status and voltage input parameters of all pixel circuits 101, and ensuring full-screen pixel synchronization, stability, and accurate operation.

[0088] Example 5 A third aspect of this invention provides a method for driving a light-emitting unit, applied to the light-emitting unit driving circuit 10 described above, such as... Figure 9 As shown, the light-emitting unit driving method includes: S10. In sampling frame T10, output test voltage Vt and first control signal to control drive switch 111 to generate test current and control sampling switch network 12 to latch the aging voltage formed by the test current at the input terminal of light-emitting unit 20. S20, in display frame T20, output data voltage Vd, ramp scan voltage Vramp and second control signal to control drive switch 111 to generate reference drive current and drive control switch K1 to work in the linear region and modulate the on-time of control switch K1.

[0089] In this embodiment, the light-emitting unit driving method is adapted to all the aforementioned light-emitting unit driving circuit 10 embodiments. It can control the timing of the driving circuit 102 process and signal output, and realize the automated and high-precision operation of pixel aging sampling and adaptive brightness compensation. The overall workflow is divided into two independent modules: the sampling frame T10 workflow and the display frame T20 workflow.

[0090] The light-emitting unit driving method strictly divides the working cycle of the display panel into two spatiotemporally decoupled working stages: sampling frame T10 and display frame T20. The two stages work together without interfering with each other. The sampling frame T10 stage is dedicated to collecting pixel aging voltage and latching charge, while the display frame T20 stage relies on the latched aging data to complete adaptive brightness compensation and normal image imaging. This ensures the accuracy of aging sampling while completely avoiding interference from the sampling operation on the image display.

[0091] During sampling frame T10 of the display panel operation, a test voltage Vt and a first control signal are output. The test voltage Vt is transmitted to the drive switch 111 of the drive circuit 102. After receiving the test voltage Vt, the drive switch 111, in conjunction with the internal threshold compensation network, completes transistor threshold voltage compensation and outputs a test current with stable amplitude. The test current is continuously transmitted to the light-emitting unit 20, enabling the light-emitting unit 20 to establish a steady-state aging voltage in a very short time, restoring the real-time aging state of the pixel. At the same time, the first control signal triggers the sampling switch network 12 to work in an orderly manner, completing the initial reference voltage configuration of the coupling capacitor C1 and the aging voltage latching of the light-emitting unit 20, completely saving the aging characteristic data of the current pixel, and completing a single sampling process.

[0092] During display frame T20 of the display panel operation, a data voltage Vd, a high-frequency ramp scan voltage Vramp, and a second control signal are output synchronously. The data voltage Vd is input to drive switch 111. After internal threshold compensation calibration, a reference drive current that accurately matches the grayscale of the current image is generated, providing stable current support for normal pixel illumination and ensuring basic image quality. The second control signal precisely regulates the switching state of the sampling switch network 12, disconnecting the aging sampling path and connecting the high-frequency ramp scan voltage Vramp. Through a voltage superposition coupling mechanism, the gate voltage of control switch K1 is dynamically adjusted, driving control switch K1 to operate stably in the linear region. Based on the latched aging voltage amplitude, the system adaptively modulates the conduction time of control switch K1 to accurately compensate for the luminous efficiency loss of the light-emitting unit 20 caused by aging, completing the brightness calibration of a single frame.

[0093] Furthermore, in order to reduce the visual interference caused by the flickering of the light-emitting unit 20 when the test voltage Vt is input, which is visible to the user, in an optional embodiment, the sampling frame T10 is the moment when the display panel is woken up and / or powered off. The light-emitting unit driving method also includes: S30. At the moment of wake-up or power-down, output test voltage Vt to each light-emitting unit driving circuit 10 of the display panel to sample the aging voltage of the light-emitting unit 20 corresponding to each light-emitting unit driving circuit 10.

[0094] The driving method sets the first type of sampling timing to the instant the display panel is woken up and the instant it is powered off. Both of these timings fall within the absolute visual blind zone, imperceptible to the human eye, enabling interference-free, high-precision sampling across the entire screen. When the display panel switches from sleep / standby mode to screen-on mode, the screen has not yet completed image formation, and the human eye cannot perceive the changes in the screen image. At this moment, a test voltage Vt is output to the driving circuit 10 of all light-emitting units on the display panel, completing the aging voltage sampling and data latching of all pixels on the entire screen in one go, achieving synchronous updates of the aging data across the entire screen.

[0095] When the display panel switches from a screen-on to a screen-off sleep state upon power-off, the screen gradually dims, remaining within the human visual blind spot. A full-screen sampling operation can be selectively performed at the moment of power-off to quickly update the aging status data of all screen pixels, providing accurate compensation baseline data for the next power-on display. The wake-up and power-off full-screen sampling modes offer high sampling efficiency, excellent data synchronization, and completely eliminate visual interference such as screen flicker or abnormal image display.

[0096] Alternatively, in another alternative embodiment, such as Figure 10 As shown, sampling frame T10 is the vertical blanking period of the display panel; The driving method for the light-emitting unit 20 also includes: S40. Calculate the average brightness level of the screen in the current display frame T20 or the previous display frame T20. S50. Compare the average brightness level of the screen with the preset high brightness threshold and the preset low brightness threshold. S60. When the average brightness level of the screen is higher than the preset high brightness threshold, the aging voltage sampling operation is performed on the light-emitting units 20 corresponding to the light-emitting unit driving circuit 10 in a spatial discrete manner during the next vertical blanking period. S70. When the average brightness level of the screen is lower than the preset low brightness threshold, skip the current sampling period operation and reuse the latched aging voltage for compensation.

[0097] In this embodiment, for scenarios where the display panel is in a low refresh rate static display state for an extended period, this driving method sets a second type of sampling timing, namely the vertical blanking period sampling mode of the display panel, to supplement and update aging data and avoid the decrease in compensation accuracy caused by long-term non-sampling. In the vertical blanking period sampling mode, the system calculates the average brightness level of the current display frame T20 or the previous display frame T20 in real time, and accurately calculates the overall average brightness value of the screen through a frame-by-frame pixel brightness statistical algorithm.

[0098] The system has pre-set high and low brightness thresholds. It compares the real-time calculated average screen brightness level with these two thresholds to determine the optimal level and executes a differentiated adaptive sampling strategy. When the average screen brightness level exceeds the pre-set high brightness threshold, it indicates that the screen is in a high-brightness state, with high pixel intensity, rapid aging rate, and frequent aging status updates, requiring timely updates to the sampling data. During the next vertical blanking period, the system uses a spatial discrete sampling method to perform local sampling operations, randomly or sequentially selecting a small number of pixel rows to activate sampling pulses, updating the aging voltage only for the local luminous units 20. This discrete sampling method avoids screen flicker caused by full-screen synchronous sampling, ensuring sampling accuracy while eliminating visual interference.

[0099] When the average brightness level of the screen is lower than the preset low brightness threshold, it indicates that the screen is currently in a dark display state, the pixel luminous intensity is extremely low, the aging rate of the organic light-emitting material is extremely slow, and the pixel aging state does not change significantly in a short period of time. The system directly skips the sampling operation of this vertical blanking period and reuses the historical aging voltage data already latched in the coupling capacitor C1 to perform brightness compensation. This will not affect the accuracy of image compensation, but also effectively reduce invalid sampling operations, reduce the dynamic power consumption loss caused by high-frequency switching of the circuit, and achieve a balance between image quality and power consumption optimization.

[0100] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0101] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A light-emitting unit driving circuit, connected to a light-emitting unit, characterized in that, The light-emitting unit driving circuit includes: The drive unit includes at least a drive switch, the drive switch being used for: During the sampling frame, a test current is generated based on the test voltage after threshold voltage compensation and transmitted to the light-emitting unit; In the display frame, a reference drive current is generated based on the data voltage after threshold voltage compensation; A control switch is connected in series with the drive switch and the light-emitting unit between the anode voltage terminal and the cathode voltage terminal; A coupling capacitor, the first end of which is connected to the control terminal of the control switch; A sampling switch network is connected to the first and second terminals of the coupling capacitor, respectively. The sampling switch network is used for: During the sampling frame, a reference voltage is output to the first terminal of the coupling capacitor and the second terminal of the coupling capacitor and the input terminal of the light-emitting unit according to the first control signal, so as to latch the aging voltage formed by the test current at the input terminal of the light-emitting unit. In the display frame, the connection between the coupling capacitor and the light-emitting unit is disconnected according to the second control signal, and a ramp scan voltage is input to the second terminal of the coupling capacitor. The ramp scan voltage is superimposed with the aging voltage and coupled to the control terminal of the control switch to drive the control switch to work in the linear region and modulate the conduction time of the control switch. The conduction time of the control switch in the linear region is positively correlated with the aging voltage of the light-emitting unit.

2. The light-emitting unit driving circuit as described in claim 1, characterized in that, The sampling frame includes a test period and a sampling period in sequence, and the display frame includes a data writing period and a light emission period in sequence; The sampling switch network is used for: During the sampling period, a reference voltage is output to the first terminal of the coupling capacitor and the second terminal of the coupling capacitor and the input terminal of the light-emitting unit according to the first control signal, so as to latch the aging voltage formed by the test current at the input terminal of the light-emitting unit; During the data writing period, the connection between the coupling capacitor and the light-emitting unit is disconnected according to the third control signal, and a preset DC voltage is input to the second terminal of the coupling capacitor. The preset DC voltage is superimposed with the aging voltage and coupled to the control terminal of the control switch to drive the control switch to work in the cutoff region. During the light emission period, the connection between the coupling capacitor and the light emission unit is disconnected according to the second control signal, and a ramp scan voltage is input to the second terminal of the coupling capacitor. The ramp scan voltage is superimposed with the aging voltage and coupled to the control terminal of the control switch to drive the control switch to work in the linear region and modulate the conduction time of the control switch.

3. The light-emitting unit driving circuit as described in claim 2, characterized in that, The drive unit further includes: A light-emitting switch, wherein the control switch, the drive switch, the light-emitting switch and the light-emitting unit are sequentially connected and connected in series between the anode voltage terminal and the cathode voltage terminal, and the control terminal of the light-emitting switch is also connected to the first scan line; The optical emitting switch is used for: During the sampling period of the sampling frame, the light emission signal input from the first scan line triggers the conduction and transmits the test current to the light-emitting unit; During the light emission period of the display frame, the light emission signal triggers the conduction and transmits the reference driving current to the light emission unit.

4. The light-emitting unit driving circuit as described in claim 3, characterized in that, The drive switch includes a first transistor, a second transistor, and a third transistor; The first terminal of the first transistor is connected to the data line. The second terminal of the first transistor, the first terminal of the second transistor, and the second terminal of the control switch are connected. The first terminal of the control switch is connected to the anode voltage terminal. The control terminals of the first transistor and the third transistor are connected to the second scan line. The second terminal of the second transistor, the first terminal of the third transistor, and the input terminal of the light emission switch are connected. The second terminal of the third transistor is connected to the control terminal of the second transistor.

5. The light-emitting unit driving circuit as described in claim 4, characterized in that, The sampling frame sequentially includes a first reset period, a test period, and a sampling period; the display frame sequentially includes a second reset period, a data writing period, and a light emission period. The drive unit further includes: The first reset switch is connected to the input terminal, reset terminal and third scan line of the light-emitting unit. The first reset switch is used to be triggered to turn on and reset the input terminal of the light-emitting unit by the reset control signal input by the third scan line during the first reset period and the second reset period. The second reset switch is connected to the reset terminal, the third scan line, and the control terminal of the second transistor. The second reset switch is used to be triggered to turn on and reset the control terminal of the second transistor by the reset control signal input by the third scan line during the first reset period and the second reset period. The sampling switch network is also used for: During the second reset period, the connection between the coupling capacitor and the light-emitting unit is disconnected according to the third control signal, and a preset DC voltage is input to the second terminal of the coupling capacitor. The preset DC voltage is superimposed on the aging voltage and coupled to the control terminal of the control switch to drive the control switch to work in the cutoff region.

6. The light-emitting unit driving circuit as described in claim 5, characterized in that, The sampling switch network includes a fourth transistor, a fifth transistor, and a sixth transistor; The first terminal of the fourth transistor is connected to the input terminal of the light-emitting unit. The second terminal of the fourth transistor, the first terminal of the fifth transistor, and the second terminal of the coupling capacitor are connected. The second terminal of the fifth transistor is connected to the first voltage terminal. The first terminal of the sixth transistor, the first terminal of the coupling capacitor, and the control terminal of the control switch are connected. The second terminal of the sixth transistor is connected to the second voltage terminal. The control terminals of the fourth transistor and the sixth transistor are connected to the fourth scan line. The control terminal of the fifth transistor is connected to the fifth scan line. The first voltage terminal receives the preset DC voltage during the second reset period and the data writing period, and writes the ramp scan voltage during the light emission period; The second voltage terminal is used to input the reference voltage.

7. A pixel circuit, characterized in that, It includes a light-emitting unit and a light-emitting unit driving circuit as described in any one of claims 1 to 6, wherein the light-emitting unit driving circuit is connected to the light-emitting unit.

8. A display device, characterized in that, It includes a driving circuit and a pixel circuit as described in claim 7, wherein the driving circuit is connected to the pixel circuit.

9. A method for driving a light-emitting unit, characterized in that, The light-emitting unit driving circuit as described in any one of claims 1 to 6, wherein the light-emitting unit driving method comprises: During the sampling frame, a test voltage and a first control signal are output to control the drive switch to generate a test current and to control the sampling switch network to latch the aging voltage formed by the test current at the input terminal of the light-emitting unit. During the display frame, output data voltage, ramp scan voltage, and a second control signal are used to control the drive switch to generate a reference drive current and drive the control switch to operate in the linear region and modulate the on-time of the control switch.

10. The light-emitting unit driving method as described in claim 9, characterized in that, The sampling frame is the moment the display panel is woken up and / or powered off; The light-emitting unit driving method further includes: At the moment of wake-up or power-down, the test voltage is output to each of the light-emitting unit driving circuits of the display panel to sample the aging voltage of the light-emitting unit corresponding to each of the light-emitting unit driving circuits; Alternatively, the sampling frame is the vertical blanking period of the display panel; The driving method for the light-emitting unit further includes: Calculate the average brightness level of the current or previous display frame; The average brightness level of the image is compared with a preset high brightness threshold and a preset low brightness threshold. When the average brightness level of the image is higher than the preset high brightness threshold, during the next vertical blanking period, aging voltage sampling operation is performed on some of the light-emitting units corresponding to the light-emitting unit driving circuit in a spatial discrete manner. When the average brightness level of the image is lower than the preset low brightness threshold, the current sampling period is skipped, and the latched aging voltage is reused for compensation.

Images