Display device

Abstract

A display device is disclosed, comprising: a frequency calculator configured to calculate a driving frequency of a previous frame and compare the driving frequency of the previous frame with a threshold driving frequency; a compensation data calculator configured to calculate compensation data based on the comparison result of the frequency calculator indicating that the driving frequency of the previous frame is lower than the threshold driving frequency; a data memory configured to provide compensation data corresponding to the calculated compensation data to an image data output unit; and an image data output unit configured to output the compensation data to a data driver.

Description

[0001] This application is a divisional application of the original invention patent application with application number 202311685893.3 (application date: December 8, 2023, invention title: display device). Technical Field

[0002] This disclosure relates to display devices. Background Technology

[0003] With the development of the information society, the demand for display devices for displaying images is increasing, and various types of display devices such as liquid crystal displays and organic light-emitting diode displays are being used.

[0004] Images displayed on a display device can include still images or moving images, and moving images can be of various types such as motion graphics, game images, and movies. The display device can operate in a variable refresh rate (VRR) mode where the drive frequency varies depending on the type of image, thereby reducing power consumption and extending the lifespan of the display device.

[0005] In such a display device, when there is little change in the input image, pixels can be driven at a low frequency (e.g., at a low speed) to reduce the refresh rate. However, when pixels are driven at a low speed, the pixel voltage is discharged, resulting in brightness differences between pixels and causing quality degradation such as image distortion or flickering. Summary of the Invention

[0006] One aspect of this disclosure is to provide a display device that prevents brightness from changing due to frequency variations.

[0007] According to one embodiment, a display device may include: a frequency calculator configured to calculate a driving frequency of a previous frame and compare the driving frequency of the previous frame with a threshold driving frequency; a compensation data calculator configured to calculate compensation data based on the comparison result of the frequency calculator indicating that the driving frequency of the previous frame is lower than the threshold driving frequency; a data memory configured to provide compensation data corresponding to the calculated compensation data to an image data output unit; and an image data output unit configured to output the compensation data to a data driver.

[0008] Details of other embodiments are included in the detailed description and accompanying drawings.

[0009] According to various embodiments, the display device has been improved in terms of brightness varying with frequency.

[0010] However, the effects that can be obtained from this disclosure are not limited to the above-described effects, and other unmentioned effects will be clearly understood by those skilled in the art to which this disclosure pertains from the following description. Attached Figure Description

[0011] Figure 1 This is a block diagram of a display device according to one embodiment.

[0012] Figure 2 This is a pixel circuit diagram of a pixel circuit in a display device according to one embodiment.

[0013] Figure 3 It is a pixel circuit diagram of a pixel circuit in a display device that has parasitic capacitors.

[0014] Figure 4 It is a waveform diagram of the signal input to the display device according to one embodiment.

[0015] Figures 5 to 7 This is a diagram illustrating the elements of a timing controller according to one embodiment.

[0016] Figure 8 It is a waveform diagram of the signal input to the display device according to one embodiment.

[0017] Figure 9 This is a diagram illustrating the elements of a timing controller according to one embodiment.

[0018] Explanation of reference numerals in the attached figures

[0019] 1: Display device

[0020] 10: Timer Controller

[0021] 20: Strobe Driver

[0022] 30: Data Driver

[0023] 40: Light-emitting driver

[0024] 50: Power supply

[0025] 60: Display panel Detailed Implementation

[0026] Hereinafter, various embodiments will be described with reference to the accompanying drawings. In this disclosure, when an element (or region, layer, portion, etc.) is referred to as being "on", "connected to", or "attached to" another element, the element may be directly on, directly connected to, or attached to the other element, or a third element may be inserted therein.

[0027] The same reference numerals denote the same elements. Furthermore, in the drawings, for efficient technical description, the thickness, scale, and dimensions of the element areas are enlarged. The term "and / or" includes any one or more combinations that can be defined by associated elements.

[0028] Although the terms first, second, etc., may be used herein to describe various elements, these elements are not limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. Unless the context clearly indicates otherwise, the singular form is intended to include the plural form as well.

[0029] The terms "below," "under," "above," "over," etc., are used to describe the relationship between the elements shown in the accompanying drawings. These terms are relative and are described with reference to the orientation shown in the drawings.

[0030] It should be understood that the terms “comprising” or “having” are intended only to indicate the presence of a feature, number, step, operation, element, component or combination thereof, and are not intended to exclude the possibility that one or more other features, numbers, steps, operations, elements, components or combinations thereof will be present or added.

[0031] Figure 1 This is a block diagram of a display device according to one embodiment.

[0032] Reference Figure 1 The display device 1 includes a timing controller 10, a gating driver 20, a data driver 30, a light-emitting driver 40, a power supply 50, and a display panel 60.

[0033] The timing controller 10 can receive image signals RGB and control signals CS from an external host system, etc. The image signal RGB may include multiple grayscale data. The control signal CS may include, for example, a horizontal synchronization signal, a vertical synchronization signal, and a master clock signal.

[0034] The timing controller 10 can process image signals RGB and control signals CS to suit the operating conditions of the display panel 60, and output image data DATA, gating drive control signal CONT1, data drive control signal CONT2, light emission drive control signal CONT3 and power supply control signal CONT4.

[0035] The strobe drive control signal CONT1 may include scan timing control signals such as strobe start pulse, strobe shift clock, and strobe output enable signal. The data drive control signal CONT2 may include data timing control signals such as source sampling clock, polarity control signal, and source output enable signal.

[0036] The timing controller 10 can be located on a control printed circuit board connected to a source printed circuit board via a connection medium such as a flexible flat cable (FFC) or a flexible printed circuit (FPC), wherein the source printed circuit board includes a data driver 30 coupled thereto. For example, the timing controller 10 can be connected to the data driver 30 via an embedded clock point-to-point interface (EPI) wiring pair to transmit and receive data.

[0037] The gating driver 20 can output gating signals sequentially in a horizontal time interval within a frame via gating lines GL in response to the gating drive control signal CONT1 received from the timing controller 10. Therefore, the pixel row connected to each gating line GL is activated for one horizontal time interval. During one horizontal time interval, a data signal can be applied to the pixel row activated by the gating line GL.

[0038] The gating driver 20 may include stage circuitry connected to multiple gating lines GL, and may be configured to be mounted to the gate in-panel (GIP) of the display panel 60. The gating driver 20 may include shift registers, level shifters, etc.

[0039] The data driver 30 converts the digital image data DATA received from the timing controller 10 into an analog data signal based on the data drive control signal CONT2. The data driver 30 can then send the analog data signal to the corresponding pixel PX via the data line DL.

[0040] The data driver 30 may include source driver circuitry or a source driver integrated circuit (IC). The data driver 30 can be connected to the bonding pads of the display panel 60 via a tape-on-board (TAB) method or a chip-on-glass (COG) method, or it can be directly mounted on the display panel 60. Depending on the requirements, the data driver 30 can be integrated and mounted on the display panel 60.

[0041] The light-emitting driver 40 can generate a light-emitting signal based on the light-emitting drive control signal CONT3 output from the timing controller 10. The light-emitting driver 40 can provide the generated light-emitting signal to the pixel PX through multiple light-emitting lines EL.

[0042] Power supply 50 can convert the external input voltage into high-level voltage ELVDD and low-level voltage ELVSS in response to the power supply control signal CONT4, serving as the standard voltages used in the internal components of display device 1. Power supply 50 outputs the generated drive voltages (ELVDD and ELVSS) to the internal components through power lines PL1 and PL2. Power supply 50 can be mounted on a control printed circuit board on which timing controller 10 is mounted. Power supply 50 can also be referred to as a power management integrated circuit (PMIC).

[0043] A plurality of pixels PX (or subpixels) are provided on the display panel 60. For example, the pixels PX can be arranged in a matrix on the display panel 60. Pixels PX arranged in a pixel row are connected to the same gate line GL, and pixels PX arranged in a pixel column are connected to the same data line DL. Pixels PX can emit light with a brightness level corresponding to the data signal provided through the data line DL.

[0044] According to one embodiment, each pixel PX can display any one of red, green, and blue. According to another embodiment, each pixel PX can display any one of cyan, magenta, and yellow. According to yet another embodiment, each pixel PX can display any one of red, green, blue, and white.

[0045] The timing controller 10, gating driver 20, data driver 30, light-emitting driver 40, and power supply 50 can each be configured as separate integrated circuits (ICs), or at least some of them can be integrated into an IC. Furthermore, at least one of the gating driver 20 and the light-emitting driver 40 can be implemented as an in-panel type integrally formed with the display panel 60.

[0046] According to one embodiment, the display device 1 can be driven in a VRR mode in which the driving frequency varies. The refresh rate can refer to the period / frequency at which data voltage is supplied (or programmed) to the pixels. For example, the display device 1 can be driven at a refresh rate higher or lower than a predetermined reference refresh rate. Operation of driving the display device 1 at a refresh rate lower than the reference refresh rate can be referred to as "low-speed operation," and operation of driving the display device 1 at a refresh rate higher than the reference refresh rate can be referred to as "high-speed operation." In low-speed operation, the display device 1 programs the data voltage to the pixels at a lower period / frequency. In high-speed operation, the display device 1 programs the data voltage to the pixels at a higher period / frequency. The refresh rate can be set according to, but is not limited to, the type of image to be displayed.

[0047] Figure 2 This is a pixel circuit diagram of a pixel circuit in a display device according to one embodiment.

[0048] For illustrative purposes, Figure 2 A pixel PX is illustrated exemplarily, and the structure of the pixel PX is not limited, as long as it can control the emission of light from the light-emitting diode (OLED). For example, the pixel PX may include additional switching TFTs, and the connection relationship of the switching TFTs or the connection position of the capacitors can be changed. For ease of description, a pixel driving circuit with "3T1C" will be described for the pixel PX.

[0049] Reference Figure 2According to one embodiment, a pixel PX may include a pixel PX having a driving transistor DT and a light-emitting diode OLED connected to the driving transistor DT.

[0050] A pixel PX can drive an OLED by controlling the driving current flowing in the OLED. A pixel PX may include a driving transistor DT, a scanning transistor T1, an initialization transistor T2, and a storage capacitor CST. Each of transistors DT and T1 to T2 may include a first electrode, a second electrode, and a gate. One of the first and second electrodes may be a source, and the other may be a drain.

[0051] Each of transistors DT and T1 to T2 can be a P-channel metal-oxide-semiconductor (PMOS) transistor or an N-channel metal-oxide-semiconductor (NMOS) transistor. The following description assumes that each of transistors DT and T1 to T2 is an NMOS transistor. Therefore, when a high-level voltage is applied to transistors DT and T1 to T2, transistors DT and T1 to T2 can be turned on.

[0052] An OLED can include an anode and a cathode. The anode of the OLED can be connected to a second node N2, and the cathode can be connected to a low potential voltage ELVSS.

[0053] The driving transistor DT may include a first electrode to which a high potential voltage ELVDD is applied, a second electrode connected to a second node N2, and a gate connected to a first node N1. The driving transistor DT may provide a driving current to the light-emitting diode OLED based on the voltage at the first node N1 (or the data voltage stored in the storage capacitor CST, which will be described later).

[0054] The first transistor T1 may include a first electrode to which a data voltage Vdata is applied, a second electrode connected to a first node N1, and a gate line GL (see...). Figure 1 The gate of any of the nodes is subject to the first scan signal SCAN1. The first transistor T1 can be turned on in response to the first scan signal SCAN1 and can transmit the data voltage Vdata to the first node N1.

[0055] The second transistor T2 may include a first electrode to which an initialization voltage Vref is applied, a second electrode connected to the second node N2, and a gate line GL (see...). Figure 1 The gate of any of the nodes is subject to the second scan signal SCAN2. The second transistor T2 can be turned on in response to the second scan signal SCAN2 and can transmit the initialization voltage Vref to the second node N2.

[0056] A storage capacitor CST can be connected between the first node N1 and the second node N2. The storage capacitor CST can store or retain a voltage corresponding to the difference between the data voltage Vdata provided to the first node N1 and the initialization voltage Vref provided to the second node N2.

[0057] In addition, refer to Figure 3 Parasitic capacitor CST1 can be formed on data line DL (see...) Figure 1 () and the first node N1.

[0058] Figure 4 It is a waveform diagram of the signal input to the display device according to one embodiment. Figures 5 to 7 This is a diagram illustrating the elements of a timing controller according to one embodiment.

[0059] Reference Figures 2 to 7 The display device may include a first frame F1 and a second frame F2.

[0060] Figure 4 The first frame F1 and the second frame F2 are illustrated by way of example, wherein the horizontal synchronization signal vsync is input before the start of each of the first frame F1 and the second frame F2.

[0061] Reference Figures 2 to 6 Each of the first frame F1 and the second frame F2 may include an effective time period, a blanking time period, and a data preparation time period. The effective time period may include the effective time period ta1 of the first frame F1 and the effective time period ta2 of the second frame F2. The blanking time period may include the blanking time period tb1 of the first frame F1 and the blanking time period of the second frame F2 (not shown). The data preparation time period may include the data preparation time period tc1 of the first frame F1 and the data preparation time period tc2 of the second frame F2.

[0062] The first frame F1 can sequentially include a first data preparation period tc1, a first active period ta1, and a first blanking period tb1. The first data preparation period tc1 begins when the horizontal synchronization signal vsync is input. The first data preparation period tc1 is essentially the same as the second data preparation period tc2 (described later), therefore the second data preparation period tc2 will be described representatively.

[0063] During the effective time periods ta1 and ta2 Figure 2 The scanning transistor T1 shown can be turned on, allowing the data voltage Vdata to be input to the first node N1. The timing controller 10 may include, for example, a frequency calculator 11, a compensation data calculator 13, and an image data output unit 15. During the effective time periods ta1 and ta2, the image data DATA (see...) Figure 1 The image data output unit 15 of the timing controller 10 can be provided to the data driver 30.

[0064] like Figure 4 and Figure 5 As shown, the first image data DATA1 can be provided during the first valid time period ta1, and the second image data DATA2 can be provided during the second valid time period ta2. The image data output unit 15 can receive image data DATA1 and DATA2 from the data memory 17 and provide image data DATA1 and DATA2 to the data driver 30.

[0065] The data driver 30 can provide analog data voltage Vdata corresponding to image data DATA1 and DATA2 to the pixel PX of the display panel via the data line DL. The data voltage Vdata, having a first voltage level Vdata1 and a second voltage level Vdata2, can be provided to the pixel PX in a first effective time period ta1 and a second effective time period ta2, respectively. Figure 4 The first voltage level Vdata1 and the second voltage level Vdata2 shown can indicate when a gate signal is applied to the gate line GL (see...). Figure 1 The applied voltage level when any of the following conditions are met. In other words, Figure 4 The magnitudes of the first voltage level Vdata1 and the second voltage level Vdata2 shown are given as examples.

[0066] In the first effective time period ta1, such as Figure 2 As shown, the voltage corresponding to the difference between the data voltage Vdata with a first voltage level Vdata1 stored in the first node N1 and the initialization voltage Vref provided to the second node N2 is stored in the storage capacitor CST.

[0067] Frequency calculator 11 can calculate the driving frequency of previous frames. For example, frequency calculator 11 can calculate the frequency of frames preceding the first frame F1 and the frequency of frames preceding the second frame F2 (i.e., the frequency of the first frame F1). Frequency calculator 11 can calculate the driving frequency of previous frames, for example, based on the duration of the previous frame. During the effective time periods ta1 and ta2, frequency calculator 11 can calculate the driving frequency of previous frames. During the effective time periods ta1 and ta2, frequency calculator 11 can compare the driving frequency of previous frames with a threshold driving frequency TH. When the driving frequency of the previous frame is lower than the threshold driving frequency TH, frequency calculator 11 can provide a signal to compensation data calculator 13 for calculating compensation data.

[0068] The compensation data calculator 13 can calculate the compensation data DATA_f based on the signal provided by the frequency calculator 11 and used to calculate the compensation data. The calculation of the compensation data DATA_f can be based on the image data DATA of the previous frame (see...). Figure 1For example, the compensation data calculator 13 can calculate the image data DATA during the effective time period of the previous frame (see...). Figure 1 The average value of the image data from the previous frame (see DATA). Figure 1 The compensation data DATA_f is calculated by taking into account the average of the image data DATA from previous frames (see [link to image data]). In some implementations, the compensation data calculator 13 can calculate the compensation data DATA_f by considering the average of the image data DATA from previous frames (see [link to image data]). Figure 1 The compensation data DATA_f is calculated by taking the average gain and / or offset of the ) ) ) ) ) ) ) ) ) ) ) ) "" ) ) " ..." ) "" " " " "" """""""""""""""""""""""""

[0069] Based on the signal provided by the frequency calculator 11 to instruct the compensation data calculator 13 to calculate the compensation data, the calculation of the compensation data DATA_f can be performed in the first effective time period ta1.

[0070] During the first blanking period tb1, the compensation data calculator 13 can provide data related to the calculated compensation data DATA_f to the data memory 17. The data memory 17 can provide the compensation data DATA_f corresponding to the calculated compensation data DATA_f to the image data output unit 15, and the image data output unit 15 can provide the compensation data DATA_f to the data driver 30. The data driver 30 can supply an analog data voltage Vdata with a third voltage level Vdata_f corresponding to the compensation data DATA_f to the data line DL (see...). Figure 1 ).

[0071] During the first blanking period tb1, the scan transistor T1 is turned off, so the data voltage Vdata does not need to be applied to the first node N1.

[0072] like Figure 4 and Figure 7 As shown, during the second data preparation period tc2 of the second frame F2, the data memory 17 can provide grayscale image data DATA_g to the image data output unit 15, and the image data output unit 15 can provide grayscale image data DATA_g to the data driver 30. The data driver 30 can supply an analog data voltage Vdata having a fourth voltage level Vdata_g corresponding to the grayscale image data DATA_g to the data line DL (see...). Figure 1 ).

[0073] During the second data preparation period tc2, the scan transistor T1 is turned off, so the data voltage Vdata does not need to be applied to the first node N1.

[0074] As described above, during the first effective time period ta1, a data voltage Vdata with a first voltage level Vdata1 is stored in the first node N1, and a voltage corresponding to the difference between the data voltage Vdata and the initialization voltage Vref provided to the second node N2 can be stored in the storage capacitor CST. Based on the voltage difference stored in the storage capacitor CST, the light-emitting diode OLED can emit light at a predetermined brightness during the first blanking time period tb1 of the first frame F1 and the second data preparation time period tc2 of the second frame F2.

[0075] As mentioned above Figure 3 The parasitic capacitor CST1 can be formed on the data line DL (see...). Figure 1 The voltage of the first node N1 can be supplied to the data line DL (see [link to data line]) during the blanking period of the frame, excluding the active period. Figure 1 The data voltage Vdata changes, and therefore the difference voltage stored in the storage capacitor CST during the first effective time period ta1 can change, thereby causing abnormal luminescence.

[0076] Typically, a frame may include an active period synchronized with the input of the horizontal synchronization signal vsync, and a blanking period in addition to the active period. During the blanking period, the image data output unit 15 may provide grayscale image data DATA_g to the data driver 30. Furthermore, the grayscale image data DATA_g may be stored in the data memory 17 and may have a value. The value of the grayscale image data DATA_g may be set such that the image data DATA in the active period of the next frame after the blanking period (see...) Figure 1 The grayscale image data DATA_g will not be overshot by the value of the grayscale image data DATA_g. In other words, when the value of the grayscale image data DATA_g is small enough that the grayscale image data DATA_g is different from the image data DATA in the effective time period of the next frame (see... Figure 1 When the difference between the two values ​​is greater than or equal to the reference value, the data from the image data DATA (see [reference value]) will be used during the effective time period of the next frame. Figure 1 The analog data voltage Vdata converted from grayscale image data DATA_g may overshoot. Therefore, the value of the grayscale image data DATA_g (or the analog data voltage Vdata converted from grayscale image data DATA_g) can be set to match the image data DATA of the next frame (see [link to image data]). Figure 1 The value of ) (or the value from the image data DATA (see Figure 1 The converted analog data voltage Vdata differs from the reference value or is lower.

[0077] However, when the value of grayscale image data DATA_g (or the analog data voltage Vdata converted from grayscale image data DATA_g) can be set and fixed to match the image data DATA of the next frame (see...) Figure 1 The value of ) (or the value from the image data DATA (see Figure 1 When the converted analog data voltage Vdata differs from the reference value or is lower, image data DATA within the valid time period may not be considered (see [reference]). Figure 1 This leads to the aforementioned abnormal luminescence.

[0078] Therefore, in the display device 1 according to one embodiment, the frequency calculator 11 can calculate the driving frequency of the previous frame, compare the driving frequency of the previous frame with a threshold driving frequency TH, and when the driving frequency of the previous frame is lower than the threshold driving frequency TH, provide a signal to instruct the compensation data calculator 13 to calculate compensation data, and the compensation data calculator 13 can, in response to the signal provided by the frequency calculator 11 and instructing the compensation data calculator 13 to calculate compensation data, calculate compensation data based on the image data DATA of the previous frame (see image data DATA). Figure 1 The image data memory 17 can provide the compensation data DATA_f corresponding to the calculated compensation data DATA_f to the image data output unit 15, and the image data output unit 15 can provide the compensation data DATA_f to the data driver 30. Therefore, during the blanking period of the frame other than the valid period, the voltage of the first node N1 can be calculated according to the voltage supplied to the data line DL (see...). Figure 1 The data voltage Vdata changes accordingly, thereby preventing abnormal light emission caused by changes in the differential voltage stored in the storage capacitor CST during the first effective time period ta1.

[0079] Figure 8 It is a waveform diagram of the signal input to the display device according to one embodiment. Figure 9 This is a diagram illustrating the elements of a timing controller according to one embodiment.

[0080] Reference Figure 4 , Figure 8 and Figure 9The frequency calculator 11 can calculate the driving frequency of the previous frame. For example, the frequency calculator 11 can calculate the frequency of the frame before the first frame F1 and the frequency of the frame before the second frame F2 (i.e., the frequency of the first frame). The frequency calculator 11 can calculate the driving frequency of the previous frame, for example, based on the duration of the previous frame. During the effective time periods ta1 and ta2, the frequency calculator 11 can calculate the driving frequency of the previous frame. During the effective time periods ta1 and ta2, the frequency calculator 11 can compare the driving frequency of the previous frame with the threshold driving frequency TH. When it is identified that the driving frequency of the previous frame is higher than the threshold driving frequency TH, the frequency calculator 11 may not provide the signal for calculating the compensation data to the compensation data calculator 13.

[0081] When the signal used to calculate the compensation data is not provided to the compensation data calculator 13, the data memory 17 can provide the grayscale image data DATA_g to the image data output unit 15, and the image data output unit 15 can provide the grayscale image data DATA_g to the data driver 30 during the first blanking period tb1. The data driver 30 can supply the analog data voltage Vdata, which has a fourth voltage level Vdata_g corresponding to the grayscale image data DATA_g, to the data line DL (see...). Figure 1 The grayscale image data DATA_g can be supplied to the data driver 30 not only during the first blanking period tb1, but also during the second data preparation period tc2 of the second frame F2, as shown below. Figure 8 As shown.

[0082] As described above, the driving frequency of the previous frame is calculated by the frequency calculator 11 and compared with the threshold driving frequency TH. When the driving frequency of the previous frame is identified as being lower than the threshold driving frequency TH, the duration of the frame may become longer, and the aforementioned luminescence anomaly may be more likely to be visible. On the other hand, when the driving frequency of the previous frame is identified as being higher than the threshold driving frequency TH, the duration of the frame may become shorter, and the aforementioned luminescence anomaly may be less likely to be visible.

[0083] For example, the display device may include: a frequency calculator configured to calculate a driving frequency of a previous frame and compare the driving frequency of the previous frame with a threshold driving frequency; a compensation data calculator configured to calculate compensation data based on the comparison result of the frequency calculator indicating that the driving frequency of the previous frame is lower than the threshold driving frequency; a data memory configured to provide compensation data corresponding to the calculated compensation data to an image data output unit; and an image data output unit configured to output the compensation data to a data driver.

[0084] For example, the previous frame can be followed by the current frame, which can include a valid time period and a blanking time period. The image data output unit can receive image data from the data memory and provide the image data to the data driver during the valid time period, and the data driver can provide the analog data voltage converted from the image data to the pixel.

[0085] For example, the frequency calculator can calculate the driving frequency of the previous frame and compare the driving frequency of the previous frame with the threshold driving frequency, which can be performed during the valid time period of the current frame.

[0086] For example, the compensation data calculator can perform calculations on compensation data during the valid time period of the current frame.

[0087] For example, the data storage unit can provide compensation data corresponding to the calculated compensation data to the image data output unit during the blanking period of the current frame.

[0088] For example, the current frame is followed by the next frame, which includes a data preparation period after the blanking period of the current frame, and the data preparation period begins in response to the vertical synchronization signal.

[0089] For example, during the data preparation period of the next frame, the data memory can provide grayscale image data to the image data output unit, and the image data output unit can provide grayscale image data to the data driver.

[0090] For example, based on the comparison result of the frequency calculator, if the driving frequency of the previous frame is higher than the threshold driving frequency, during the blanking period, the data memory can provide grayscale image data to the image data output unit, and the image data output unit can provide grayscale image data to the data driver.

[0091] For example, the compensation data calculator can perform the calculation of compensation data based on image data from the valid time period of the previous frame.

[0092] For example, the compensation data calculator can calculate the average value of image data during the effective period of the previous frame and calculate compensation data based on the calculated average value of image data from the previous frame.

[0093] Although several embodiments have been described with reference to the accompanying drawings, those skilled in the art to which this disclosure pertains will understand that different embodiments can be made without departing from the technical concept or features. Therefore, the above embodiments should be understood as illustrative rather than restrictive in all respects. Furthermore, the scope of this disclosure is defined by the appended claims rather than by the foregoing detailed description. Moreover, all modifications or variations to the concept and scope of the appended claims and their equivalents should be construed as falling within the scope of this invention.

[0094] Cross-reference to related applications

[0095] This application claims priority to Korean Patent Application No. 10-2023-0012226, filed on January 31, 2023, the entire contents of which are incorporated herein by reference for all purposes.

Claims

1. A display device, the display device comprising: A display panel, wherein pixels are arranged on the display panel; A controller configured to control the pixel at a first driving frequency in a first frame and at a second driving frequency in a second frame; as well as A data driver configured to convert image data output from the controller to generate a data voltage and output the data voltage to the pixel via a data line. The first frame and the second frame each include an effective time period and a blanking time period, and The data driver is configured to output a first grayscale data voltage, determined in response to the first drive frequency and the second drive frequency, to the data line during the blanking period.

2. The display device according to claim 1, in, The first grayscale data voltage output during the blanking period of the first frame is set such that the difference between the data voltage output during the effective period of the second frame is less than or equal to a reference value.

3. The display device according to claim 1, in, The data driver is configured to output the first grayscale data voltage to the data line during the blanking period in response to the driving frequency being greater than a preset threshold driving frequency.

4. The display device according to claim 3, in, The data driver is configured to output a second grayscale data voltage, different from the first grayscale data voltage, to the data line during the blanking period in response to the driving frequency being less than the preset threshold driving frequency.

5. The display device according to claim 4, in, The second grayscale data voltage is a voltage lower than the first grayscale data voltage.

6. The display device according to claim 4, in, The second grayscale data voltage is determined based on the average value of the data voltage output during the effective time period.

7. The display device according to claim 4, in, The first frame and the second frame each also include a data preparation period prior to the effective time period, and The data driver is configured to output the first grayscale data voltage to the data line during the data preparation period.

8. The display device according to claim 1, in, The controller includes a frequency calculator configured to calculate the first drive frequency and the second drive frequency based on the input time of the pulses of the control signal.

9. The display device according to claim 8, in, The control signal includes a first pulse synchronized with the start time of the first frame and a second pulse synchronized with the start time of the second frame, and The frequency calculator is configured to calculate the first drive frequency by counting the time from the input time of the first pulse to the input time of the second pulse.

10. The display device according to claim 9, in, The frequency calculator is configured to calculate the first drive frequency during the effective time period of the second frame.

11. The display device according to claim 10, in, The controller also includes: A calculator configured to calculate second grayscale data based on the first driving frequency; Storage device, the storage device being configured to store first grayscale data; and An image data output unit is configured to output the first grayscale data to the data driver.

12. The display device according to claim 11, in, The image data output unit is configured to output the first grayscale data to the data driver during the blanking period of the second frame.

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