Display device

Abstract

This application provides a display device whose pixels include a pixel driving circuit and a light-emitting device. The pixel driving circuit includes a first transistor, a first capacitor, and a second capacitor. The first capacitor is electrically connected to the first gate of the first transistor, the first plate of the second capacitor is electrically connected to the first capacitor, and the second plate of the second capacitor is electrically connected to the anode of the light-emitting device. The first plate of the second capacitor is located on the film layer containing the first metal layer of the display panel, and the second plate of the second capacitor is located on the film layer containing the second metal layer of the display panel. A gate insulating film layer is disposed on the first metal layer, and the second metal layer is located on the gate insulating film layer. By forming a second capacitor between the first and second metal layers, this application achieves time separation between the threshold voltage compensation process and the data signal writing process, thereby improving the threshold voltage compensation capability of the pixel driving circuit using an oxide thin-film transistor as the driving transistor within a limited pixel space.

Description

Technical Field

[0001] This application relates to the field of display technology, and more specifically to a display device. Background Technology

[0002] With the development of display technology, the pixel density of display panels is constantly increasing to meet higher requirements for display clarity and realism. This increase in pixel density leads to a reduction in the area of ​​pixel units, which in turn compresses the time available for threshold voltage compensation in the pixel driving circuit. In traditional pixel driving circuits, the threshold voltage compensation process and the data signal writing process occur within the same timeframe. When the compensation time is insufficient, inadequate compensation occurs, affecting display uniformity.

[0003] For pixel driving circuits that use indium gallium zinc oxide thin film transistors as driving transistors, the problem of insufficient compensation is particularly prominent when the compensation time is limited, due to the relatively small driving current of indium gallium zinc oxide thin film transistors, which leads to a decrease in display quality.

[0004] In high-pixel-density display panels, the available space for pixel units is limited, and the various components of the pixel driving circuit need to be rationally arranged within this limited space. Achieving a rational arrangement of these components within the limited pixel space to meet the performance requirements of threshold voltage compensation presents a technical challenge.

[0005] Therefore, it is necessary to propose a new technical solution to solve the above-mentioned technical problems. Summary of the Invention

[0006] The purpose of this application is to provide a display device that aims to improve the threshold voltage compensation capability of a pixel driving circuit using oxide thin-film transistors as driving transistors within a limited pixel space.

[0007] This application provides a display device, the display device including a display panel, the display panel including a plurality of pixels, each pixel including a pixel driving circuit and a light-emitting device, the pixel driving circuit including a first transistor, a first capacitor and a second capacitor, the first plate of the first capacitor being electrically connected to the first gate of the first transistor, the first plate of the second capacitor being electrically connected to the second plate of the first capacitor, and the second plate of the second capacitor being electrically connected to the anode of the light-emitting device; the display panel further includes an active layer, a third gate insulating layer located on the active layer and a third gate layer located on the third gate insulating layer, the first gate of the first transistor being located in the film layer of the third gate layer, the first plate of the second capacitor being located in the film layer of the first metal layer of the display panel, the second plate of the second capacitor being located in the film layer of the second metal layer of the display panel, a gate insulating film layer being disposed on the first metal layer, the second metal layer being located on the gate insulating film layer, and along a direction perpendicular to the plane of the display panel, both the first metal layer and the second metal layer are located above the film layer of the third gate layer, or both the first metal layer and the second metal layer are located below the film layer of the third gate layer.

[0008] In the above-described display device, the display panel further includes a fourth gate insulating layer located on the third gate layer, a fourth gate layer located on the fourth gate insulating layer, a fifth gate insulating layer located on the fourth gate layer, and a fifth gate layer located on the fifth gate insulating layer; the first metal layer includes the fourth gate layer, the second metal layer includes the fifth gate layer, and the gate insulating film layer includes the fifth gate insulating layer.

[0009] In the above-described display device, from a top-view perspective of the display panel, at least a portion of the fourth gate layer and at least a portion of the fifth gate layer overlap with the portion of the active layer located between the source and drain of the first transistor.

[0010] In the above-described display device, from a top-view perspective of the display panel, the fourth gate layer and the fifth gate layer overlap in a region located on at least one side of the line connecting the source and drain of the first transistor and outside the active layer of the first transistor.

[0011] In the above-described display device, the display panel further includes a second gate insulating layer, a second gate layer located on the second gate insulating layer, and a first interlayer insulating layer located on the second gate layer, wherein the active layer is located on the first interlayer insulating layer; the second metal layer includes the second gate layer, and the gate insulating film layer is located between the first metal layer and the second gate layer.

[0012] In the above-described display device, the display panel further includes a fifth gate layer located on the second gate insulating layer and a fifth gate insulating layer located on the fifth gate layer, the second gate layer being located on the fifth gate insulating layer, the first metal layer including the fifth gate layer, and the gate insulating film layer including the fifth gate insulating layer.

[0013] In the above-described display device, from a top-view perspective of the display panel, at least a portion of the fifth gate layer overlaps with the portion of the active layer located between the source and drain of the first transistor.

[0014] In the above-described display device, the display panel further includes a first gate insulating layer and a first gate layer located on the first gate insulating layer, a second gate insulating layer located on the first gate layer, a first metal layer including the first gate layer, and a gate insulating film layer including the second gate insulating layer.

[0015] In the above-described display device, from a top-view perspective of the display panel, at least a portion of the first gate layer overlaps with the portion of the active layer located between the source and drain of the first transistor.

[0016] In the above-described display device, from a top-view perspective of the display panel, a first portion of the second gate layer overlaps with the source and drain of the first transistor, as well as the portion of the active layer located between the source and drain of the first transistor.

[0017] In the above-described display device, the first electrode of the second capacitor includes a second portion of the second gate layer, and from a top view of the display panel, the second portion of the second gate layer overlaps with at least a portion of the first metal layer.

[0018] In the above-described display device, the display panel further includes a fourth gate insulating layer and a fourth gate layer located on the fourth gate insulating layer. The first electrode of the first capacitor is located in the film layer where the third gate layer is located, and the second electrode of the first capacitor is located in the film layer where the fourth gate layer is located. The second portion of the second gate layer is electrically connected to the portion of the second electrode of the first capacitor located in the film layer where the fourth gate layer is located through a switching hole.

[0019] In the aforementioned display device, the pixel driving circuit further includes a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor. The first transistor further includes a second gate. The gate of the third transistor is electrically connected to a first gate signal line. One of the source and drain of the third transistor is electrically connected to one of the source and drain of the first transistor. The other of the source and drain of the third transistor is electrically connected to the first gate of the first transistor. The second gate of the first transistor is electrically connected to the other of the source and drain of the first transistor. The gate of the second transistor is electrically connected to a second gate signal line. One of the source and drain of the second transistor is electrically connected to a data signal line. The other of the source and drain of the second transistor is electrically connected to the first plate of the second capacitor. The gate of the fourth transistor is electrically connected to the first gate signal line. One of the source and drain of the fourth transistor... The gate of the fifth transistor is electrically connected to the first light-emitting control signal line, one of the source and drain of the fifth transistor is electrically connected to the first power supply line, and the other of the source and drain of the fifth transistor is electrically connected to the source and drain of the first transistor. The gate of the sixth transistor is electrically connected to the second light-emitting control signal line, one of the source and drain of the sixth transistor is electrically connected to the other of the source and drain of the first transistor, and the other of the source and drain of the sixth transistor is electrically connected to the second plate of the second capacitor. The gate of the seventh transistor is electrically connected to the first light-emitting control signal line, one of the source and drain of the seventh transistor is electrically connected to the reset signal line, and the other of the source and drain of the seventh transistor is electrically connected to the second plate of the second capacitor.

[0020] In the above-described display device, the display device further includes a timing controller, a gate driving circuit, and a source driving chip. The timing controller is configured to control the gate driving circuit and the source driving chip to perform threshold voltage compensation on the first transistor in a first time period, and to write data voltage to the first plate of the second capacitor in a second time period, wherein the first time period is earlier than the second time period.

[0021] In the above-described display device, the first gate signal line is configured to turn on the third transistor and the fourth transistor during the first time period, and the fourth transistor is configured to transfer the voltage of the reset signal line to the first plate of the second capacitor when it is turned on; the second gate signal line is configured to turn on the second transistor during the second time period, and the second transistor is configured to transfer the data voltage of the data signal line to the first plate of the second capacitor when it is turned on.

[0022] In the display panel provided in the embodiments of this application, the first plate of the second capacitor is located on the film layer containing the first metal layer of the display panel, and the second plate of the second capacitor is located on the film layer containing the second metal layer of the display panel. A gate insulating film layer is disposed on the first metal layer, and the second metal layer is located on the gate insulating film layer. Along the direction perpendicular to the plane of the display panel, both the first and second metal layers are located above the film layer containing the third gate layer, or both the first and second metal layers are located below the film layer containing the third gate layer. The first plate of the second capacitor is electrically connected to the first capacitor, and the second plate of the second capacitor is electrically connected to the anode of the light-emitting device. During the threshold voltage compensation stage, the voltage of the first gate of the first transistor is stored through the first capacitor. The second capacitor works in conjunction with the first capacitor as an additional charge storage unit to complete the compensation of the threshold voltage of the first transistor before the data signal is written, thus separating the threshold voltage compensation process from the data signal writing process in time. When a data signal needs to be written, the threshold voltage compensation has already been completed, and the data signal writing process is not limited by the compensation time. Even when the compensation time is compressed due to high pixel density, sufficient threshold voltage compensation is still achieved, the compensation sufficiency is improved, and the display uniformity is improved. This application forms a second capacitor between a first metal layer and a second metal layer, using a gate insulating film layer as the capacitor dielectric layer. The first and second metal layers are used as gate layers in the manufacturing process of the display panel. The formation of the second capacitor is achieved without changing the existing manufacturing process, thereby reducing manufacturing costs and manufacturing difficulty.

[0023] In one embodiment of the display panel provided in this application, the first metal layer includes a fourth gate layer, the second metal layer includes a fifth gate layer, and the gate insulating film layer includes a fifth gate insulating layer. At least a portion of the fourth gate layer and at least a portion of the fifth gate layer overlap with the portion of the active layer located between the source and drain of the first transistor. The region between the source and drain of the first transistor is a relatively empty region in the pixel driving circuit when viewed from above the display panel. A second capacitor is disposed in this region, achieving the placement of the second capacitor without additionally occupying other areas of the pixel. Even with increased pixel density and reduced pixel area, sufficient capacitance area is still provided for the second capacitor to meet the charge storage requirements for threshold voltage compensation. The fourth and fifth gate layers overlap in a region located on at least one side of the line connecting the source and drain of the first transistor and outside the active layer of the first transistor, increasing the overlap area of ​​the second capacitor, improving the capacitance value of the second capacitor, enhancing the threshold voltage compensation effect, and improving display uniformity.

[0024] In another embodiment of the display panel provided in this application, the first metal layer includes a fifth gate layer, the second metal layer includes a second gate layer, and the gate insulating film layer includes a fifth gate insulating layer. At least a portion of the fifth gate layer overlaps with the portion of the active layer located between the source and drain of the first transistor. A first portion of the second gate layer overlaps with the source and drain of the first transistor and the portion of the active layer located between the source and drain of the first transistor. A second portion of the second gate layer overlaps with at least a portion of the fifth gate layer as the first electrode of the second capacitor. The first portion of the second gate layer is used as the second gate of the first transistor, and the second portion of the second gate layer is used as the first electrode of the second capacitor. By reusing the second gate layer to form the second capacitor, no additional metal layer is needed to form the second capacitor, reducing the number of film layers, simplifying the manufacturing process, and lowering manufacturing costs.

[0025] In another embodiment of the display panel provided in this application, the first metal layer includes a first gate layer, the second metal layer includes a second gate layer, and the gate insulating film layer includes a second gate insulating layer. At least a portion of the first gate layer overlaps with the portion of the active layer located between the source and drain of the first transistor. A first portion of the second gate layer overlaps with the source and drain of the first transistor and the portion of the active layer located between the source and drain of the first transistor. A second portion of the second gate layer serves as the first electrode of the second capacitor, overlapping with at least a portion of the first gate layer. The first and second gate layers are existing gate layers in the display panel. By reusing the first and second gate layers to form the second capacitor, no additional film layers are required. This achieves the setting of the second capacitor without increasing the complexity and cost of the manufacturing process, thus reducing manufacturing difficulty. The overlap between the first gate layer and the active layer fully utilizes the space of the first transistor region, providing sufficient capacitance area for the second capacitor within a limited pixel area to meet the performance requirements of threshold voltage compensation. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of a display device provided in an embodiment of this application.

[0027] Figure 2 for Figure 1 The circuit diagram of the pixel unit in the display device shown.

[0028] Figure 3 This is a schematic diagram of a first embodiment of the display panel of the display device provided in this application.

[0029] Figure 4 for Figure 3 A top view of the first embodiment of the display panel shown.

[0030] Figure 5 A schematic diagram of a second embodiment of the display panel of the display device provided in this application.

[0031] Figure 6 for Figure 5 A top view of a second embodiment of the display panel shown.

[0032] Figure 7 This is a schematic diagram of a third embodiment of the display panel of the display device provided in this application.

[0033] Figure 8 for Figure 7 A top view of the third embodiment of the display panel shown. Detailed Implementation

[0034] The specific embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0035] The terms “first,” “second,” and similar words do not indicate any order, quantity, or importance, but are merely used to distinguish different technical features. The terms “multiple,” and similar words mean two or more, unless otherwise expressly specified.

[0036] The technical solutions of different embodiments of this application can be combined with each other.

[0037] The display device provided in the embodiments of this application may be, for example, an organic light-emitting diode (OLED) display device, a miniature OLED display device, or a micro OLED display device. The embodiments of this application will be described using an organic light-emitting diode (OLED) display device as an example.

[0038] like Figure 1 As shown, the organic light-emitting diode (OLED) display device provided in the embodiments of this application includes an OLED display panel, a timing controller (TCON), and a source driver chip (SDIC). The timing controller (TCON) is electrically connected to the source driver chip (SDIC), and transmits image data and control signals to the source driver chip (SDIC). The OLED display panel includes a gate driver circuit (GOA), multiple gate signal lines (SCAN1 / SCAN2), multiple light emission control signal lines (EM1 / EM2), multiple data signal lines (DATA), and multiple pixels (PX). The gate driver circuit (GOA) generates scan signals and transmits them to the pixels (PX) through the gate signal lines (SCAN1 / SCAN2). The light emission control signal lines (EM1 / EM2) transmit light emission control signals to the pixels (PX). The source driver chip (SDIC) generates data signals and transmits them to the pixels (PX) through the data signal lines (DATA).

[0039] like Figure 2 As shown, the display panel DP of the display device provided in the embodiments of this application includes a plurality of pixels PX. Each pixel PX includes a pixel driving circuit and a light-emitting device. The pixel driving circuit is used to drive the light-emitting device to emit light. The light-emitting device is an organic light-emitting diode.

[0040] The pixel driving circuit includes seven transistors and two capacitors. The seven transistors are transistor T1, transistor T2, transistor T3, transistor T4, transistor T5, transistor T6, and transistor T7. The two capacitors are capacitor C1 and capacitor C2.

[0041] The first transistor T1 includes a first gate, a second gate, an active layer IGZO, a source, and a drain. The first gate of the first transistor T1 is electrically connected to a first node Q. One of the source and drain of the first transistor T1 is electrically connected to a second node A. The other of the source and drain of the first transistor T1 is electrically connected to a third node B. The second gate of the first transistor T1 is electrically connected to the third node B.

[0042] The gate of the second transistor T2 is electrically connected to the second gate signal line SCAN2. One of the source and drain of the second transistor T2 is electrically connected to the data signal line DATA. The other of the source and drain of the second transistor T2 is electrically connected to the fourth node P.

[0043] The gate of the third transistor T3 is electrically connected to the first gate signal line SCAN1. One of the source and drain of the third transistor T3 is electrically connected to the second node A. The other of the source and drain of the third transistor T3 is electrically connected to the first node Q.

[0044] The gate of the fourth transistor T4 is electrically connected to the first gate signal line SCAN1. One of the source and drain of the fourth transistor T4 is electrically connected to the reset signal line VI-ANO. The other of the source and drain of the fourth transistor T4 is electrically connected to the fourth node P.

[0045] The gate of the fifth transistor T5 is electrically connected to the first light-emitting control signal line EM1. One of the source and drain of the fifth transistor T5 is electrically connected to the first power supply line VDD. The other of the source and drain of the fifth transistor T5 is electrically connected to the second node A.

[0046] The gate of the sixth transistor T6 is electrically connected to the second light-emitting control signal line EM2. One of the sources and drains of the sixth transistor T6 is electrically connected to the third node B. The other of the sources and drains of the sixth transistor T6 is electrically connected to the fifth node C.

[0047] The gate of the seventh transistor T7 is electrically connected to the first light-emitting control signal line EM1. One of the source and drain of the seventh transistor T7 is electrically connected to the reset signal line VI-ANO. The other of the source and drain of the seventh transistor T7 is electrically connected to the fifth node C.

[0048] The first plate of the first capacitor C1 is electrically connected to the first node Q. The second plate of the first capacitor C1 is electrically connected to the fourth node P.

[0049] The first plate of the second capacitor C2 is electrically connected to the fourth node P. The second plate of the second capacitor C2 is electrically connected to the fifth node C.

[0050] The anode of the organic light-emitting diode (OLED) is electrically connected to the fifth node C. The cathode of the OLED is electrically connected to the second power supply line VSS.

[0051] The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the seventh transistor T7 are N-type transistors. The fifth transistor T5 and the sixth transistor T6 are P-type transistors.

[0052] The active layer IGZO of the first transistor T1 is made of indium gallium zinc oxide (IGZO) semiconductor material. The first transistor T1 is a dual-gate transistor. The first gate of the first transistor T1 is located on the active layer IGZO. The active layer IGZO is located on the second gate of the first transistor T1. The second gate of the first transistor T1 is electrically connected to the active layer IGZO through the other of the source and drain terminals of the first transistor T1.

[0053] like Figure 3 and Figure 4 As shown, the first embodiment of this application provides a display panel DP with a substrate, a first gate insulating layer GI1, a first gate layer GE1, a second gate insulating layer GI2, a second gate layer GE2, a first interlayer insulating layer ILD1, an active layer IGZO, a third gate insulating layer GI3, a third gate layer GE3, a fourth gate insulating layer GI4, a fourth gate layer GE4, a fifth gate insulating layer GI5, a fifth gate layer GE5, a second interlayer insulating layer ILD2, and a source / drain layer SD1 arranged sequentially along the thickness direction of the display panel DP.

[0054] The substrate can be a glass substrate or a flexible substrate. The flexible substrate is made of polyimide.

[0055] A first gate insulating layer GI1 is disposed on the substrate. The material of the first gate insulating layer GI1 is silicon oxide or silicon nitride.

[0056] A first gate layer GE1 is disposed on a first gate insulating layer GI1. The material of the first gate layer GE1 is at least one of molybdenum, aluminum, copper, or titanium. A portion of the first gate layer GE1 does not overlap with the active layer IGZO.

[0057] The second gate insulating layer GI2 is disposed on the first gate insulating layer GI1 and the first gate layer GE1. The material of the second gate insulating layer GI2 is silicon oxide or silicon nitride.

[0058] The second gate layer GE2 is disposed on the second gate insulating layer GI2. The material of the second gate layer GE2 is at least one of molybdenum, aluminum, copper, or titanium. The second gate layer GE2 overlaps with the active layer IGZO. The second gate layer GE2 constitutes the second gate of the first transistor T1.

[0059] The first interlayer insulating layer ILD1 is disposed on the second gate insulating layer GI2 and the second gate layer GE2. The material of the first interlayer insulating layer ILD1 is silicon oxide or silicon nitride.

[0060] The active layer IGZO is disposed on the first interlayer insulating layer ILD1, that is, the active layer IGZO is located on the first interlayer insulating layer ILD1. The material of the active layer IGZO is indium gallium zinc oxide. The active layer IGZO includes a channel region, a source region, and a drain region.

[0061] The third gate insulating layer GI3 is disposed on the first interlayer insulating layer ILD1 and the active layer IGZO, that is, the third gate insulating layer GI3 is located on the active layer IGZO. The material of the third gate insulating layer GI3 is silicon oxide or silicon nitride.

[0062] The third gate layer GE3 is disposed on the third gate insulating layer GI3, that is, the third gate layer GE3 is located on the third gate insulating layer GI3. The material of the third gate layer GE3 is at least one of molybdenum, aluminum, copper or titanium. The third gate layer GE3 constitutes the first gate of the first transistor T1. The first plate of the first capacitor C1 is located in the film layer on which the third gate layer GE3 is located.

[0063] The fourth gate insulating layer GI4 is disposed on the third gate insulating layer GI3 and the third gate layer GE3, that is, the fourth gate insulating layer GI4 is located on the third gate layer GE3. The material of the fourth gate insulating layer GI4 is silicon oxide or silicon nitride.

[0064] The fourth gate layer GE4 is disposed on the fourth gate insulating layer GI4, that is, the fourth gate layer GE4 is located on the fourth gate insulating layer GI4. The material of the fourth gate layer GE4 is at least one of molybdenum, aluminum, copper, or titanium. The fourth gate layer GE4 constitutes the second electrode of the first capacitor C1 and the first electrode of the second capacitor C2. The second electrode of the first capacitor C1 is located in the film layer where the fourth gate layer GE4 is located. The first electrode of the second capacitor C2 is located in the film layer where the fourth gate layer GE4 is located. In this embodiment, the fourth gate layer GE4 constitutes the first metal layer of the display panel DP. The third gate layer GE3, the fourth gate layer GE4, and the fifth gate layer GE5 at least partially overlap.

[0065] A fifth gate insulating layer GI5 is disposed on the fourth gate insulating layer GI4 and the fourth gate layer GE4, that is, the fifth gate insulating layer GI5 is located on the fourth gate layer GE4. The material of the fifth gate insulating layer GI5 is silicon oxide or silicon nitride. The fifth gate insulating layer GI5 constitutes the dielectric layer of the second capacitor C2. In this embodiment, a gate insulating film layer is disposed on the fourth gate layer GE4 (first metal layer), and the fifth gate insulating layer GI5 constitutes the gate insulating film layer.

[0066] A fifth gate layer GE5 is disposed on a fifth gate insulating layer GI5. The material of the fifth gate layer GE5 is at least one of molybdenum, aluminum, copper, or titanium. The fifth gate layer GE5 constitutes the second electrode of the second capacitor C2. In a direction perpendicular to the plane of the display panel, the fifth gate layer GE5 is located above the fourth gate layer GE4. The second electrode of the second capacitor C2 is located in the film layer containing the fifth gate layer GE5. In this embodiment, the fifth gate layer GE5 constitutes the second metal layer of the display panel DP, and the fifth gate layer GE5 (second metal layer) is located on the fifth gate insulating layer GI5 (gate insulating film layer).

[0067] Along the direction perpendicular to the plane where the display panel DP is located, the fourth gate layer GE4 (first metal layer) and the fifth gate layer GE5 (second metal layer) are both located above the film layer where the third gate layer GE3 is located.

[0068] The second interlayer insulating layer (ILD2) is disposed on the fifth gate insulating layer (GI5) and the fifth gate layer (GE5). The material of the second interlayer insulating layer (ILD2) is silicon oxide or silicon nitride.

[0069] The source-drain layer SD1 is disposed on the second interlayer insulating layer ILD2. The material of the source-drain layer SD1 is at least one of molybdenum, aluminum, copper, or titanium. The source-drain layer SD1 includes the source and drain of the first transistor T1.

[0070] One of the source and drain of the first transistor T1 is electrically connected to the active layer IGZO through a first contact hole penetrating the second interlayer insulating layer ILD2, the fifth gate insulating layer GI5, the fourth gate insulating layer GI4, and the third gate insulating layer GI3. The other of the source and drain of the first transistor T1 is electrically connected to the second gate layer GE2 through a second contact hole penetrating the second interlayer insulating layer ILD2, the fifth gate insulating layer GI5, the fourth gate insulating layer GI4, the third gate insulating layer GI3, and the first interlayer insulating layer ILD1. The second gate layer GE2 is electrically connected to the active layer IGZO through the other of the source and drain of the first transistor T1. One of the source and drain of the first transistor T1 is electrically connected to the active layer IGZO through a third contact hole penetrating the second interlayer insulating layer ILD2, the fifth gate insulating layer GI5, the fourth gate insulating layer GI4, the third gate insulating layer GI3, and the first interlayer insulating layer ILD1.

[0071] From a top-view perspective of the display panel DP, at least a portion of the fourth gate layer GE4 is located between the source and drain of the first transistor T1. At least a portion of the fifth gate layer GE5 is located between the source and drain of the first transistor T1. At least a portion of the fourth gate layer GE4 and at least a portion of the fifth gate layer GE5 overlap with the portion of the active layer IGZO located between the source and drain of the first transistor T1. In a direction perpendicular to the plane of the display panel, the fourth gate layer GE4 and the fifth gate layer GE5 overlap above the portion of the active layer IGZO located between the source and drain of the first transistor T1, forming the second capacitor C2. The fourth gate layer GE4 and the fifth gate layer GE5 also overlap in a region located on at least one side of the line connecting the source and drain of the first transistor T1 and outside the active layer IGZO of the first transistor T1.

[0072] In this embodiment, from the top view of the display panel DP, at least a portion of the fourth gate layer GE4 overlaps with the portion of the active layer IGZO located between the source and drain of the first transistor T1, and at least a portion of the fifth gate layer GE5 overlaps with the portion of the active layer IGZO located between the source and drain of the first transistor T1.

[0073] The line containing the first node Q is located in the film layer containing the third gate layer GE3, and the line containing the fourth node P is located in the film layer containing the fourth gate layer GE4. The fifth gate layer GE5 is electrically connected to the source-drain layer SD1 through the fifth contact hole penetrating the second interlayer insulating layer ILD2, and then electrically connected to the fifth node C. Thus, the fifth gate layer GE5 serves as the second electrode of the second capacitor C2 and is electrically connected to the fifth node C.

[0074] like Figure 5 and Figure 6 As shown, the second embodiment of this application provides a display panel DP with the following components arranged sequentially along the thickness direction: a substrate, a first gate insulating layer GI1, a first gate layer GE1, a second gate insulating layer GI2, a fifth gate layer GE5, a fifth gate insulating layer GI5, a second gate layer GE2, a first interlayer insulating layer ILD1, an active layer IGZO, a third gate insulating layer GI3, a third gate layer GE3, a fourth gate insulating layer GI4, a fourth gate layer GE4, a second interlayer insulating layer ILD2, and a source / drain layer SD1.

[0075] A first gate insulating layer GI1 is disposed on the substrate. A first gate layer GE1 is disposed on the first gate insulating layer GI1. The first gate layer GE1 does not overlap with the active layer IGZO.

[0076] The second gate insulating layer GI2 is disposed on the first gate insulating layer GI1 and the first gate layer GE1, that is, the second gate insulating layer GI2 is located on the first gate layer GE1.

[0077] The fifth gate layer GE5 is disposed on the second gate insulating layer GI2, that is, the fifth gate layer GE5 is located on the second gate insulating layer GI2. The fifth gate layer GE5 forms the second electrode of the second capacitor C2. The fifth gate layer GE5 overlaps with the active layer IGZO. The second electrode of the second capacitor C2 is located in the film layer where the fifth gate layer GE5 is located. In this embodiment, the fifth gate layer GE5 forms the first metal layer of the display panel DP.

[0078] A fifth gate insulating layer GI5 is disposed on the second gate insulating layer GI2 and the fifth gate layer GE5, that is, the fifth gate insulating layer GI5 is located on the fifth gate layer GE5. The fifth gate insulating layer GI5 constitutes the dielectric layer of the second capacitor C2. In this embodiment, a gate insulating film layer is disposed on the fifth gate layer GE5 (first metal layer), and the fifth gate insulating layer GI5 constitutes the gate insulating film layer, which is located between the fifth gate layer GE5 (first metal layer) and the second gate layer GE2.

[0079] The second gate layer GE2 is disposed on the fifth gate insulating layer GI5. The second gate layer GE2 includes a first portion GE2-1 and a second portion GE2-2. The first portion GE2-1 of the second gate layer GE2 constitutes the second gate of the first transistor T1. The second portion GE2-2 of the second gate layer GE2 constitutes the first plate of the second capacitor C2. The second portion GE2-2 of the second gate layer GE2 does not overlap with the first portion GE2-1 of the second gate layer GE2. The second portion GE2-2 of the second gate layer GE2 overlaps with the fifth gate layer GE5 to form the second capacitor C2. In a direction perpendicular to the plane of the display panel, the second gate layer GE2 is located above the fifth gate layer GE5. The first plate of the second capacitor C2 is located in the film layer on which the second gate layer GE2 is located. In this embodiment, the second gate layer GE2 constitutes the second metal layer of the display panel DP, and the second gate layer GE2 (second metal layer) is located on the fifth gate insulating layer GI5 (gate insulating film layer).

[0080] Along the direction perpendicular to the plane where the display panel DP is located, the fifth gate layer GE5 (first metal layer) and the second gate layer GE2 (second metal layer) are both located below the film layer where the third gate layer GE3 is located.

[0081] The first interlayer insulating layer ILD1 is disposed on the fifth gate insulating layer GI5 and the second gate layer GE2, that is, the first interlayer insulating layer ILD1 is located on the second gate layer GE2.

[0082] The active layer IGZO is disposed on the first interlayer insulating layer ILD1.

[0083] The third gate insulating layer GI3 is disposed on the first interlayer insulating layer ILD1 and the active layer IGZO, that is, the third gate insulating layer GI3 is located on the active layer IGZO.

[0084] The third gate layer GE3 is disposed on the third gate insulating layer GI3, that is, the third gate layer GE3 is located on the third gate insulating layer GI3. The third gate layer GE3 constitutes the first gate of the first transistor T1. The first plate of the first capacitor C1 is located in the film layer on which the third gate layer GE3 is located.

[0085] The fourth gate insulating layer GI4 is disposed on the third gate insulating layer GI3 and the third gate layer GE3, that is, the fourth gate insulating layer GI4 is located on the third gate layer GE3.

[0086] The fourth gate layer GE4 is disposed on the fourth gate insulating layer GI4, that is, the fourth gate layer GE4 is located on the fourth gate insulating layer GI4. The second plate of the first capacitor C1 is located on the film layer where the fourth gate layer GE4 is located.

[0087] The second interlayer insulating layer ILD2 is disposed on the fourth gate insulating layer GI4 and the fourth gate layer GE4.

[0088] The source-drain layer SD1 is disposed on the second interlayer insulating layer ILD2.

[0089] One of the source and drain of the first transistor T1 is electrically connected to the first portion GE2-1 of the second gate layer GE2 through a first contact hole penetrating the second interlayer insulating layer ILD2, the fourth gate insulating layer GI4, the third gate insulating layer GI3, the first interlayer insulating layer ILD1, and the fifth gate insulating layer GI5. The other of the source and drain of the first transistor T1 is electrically connected to the active layer IGZO through a second contact hole penetrating the second interlayer insulating layer ILD2, the fourth gate insulating layer GI4, the third gate insulating layer GI3, and the first interlayer insulating layer ILD1. The first portion GE2-1 of the second gate layer GE2 is electrically connected to the active layer IGZO through the other of the source and drain of the first transistor T1. One of the source and drain of the first transistor T1 is electrically connected to the active layer IGZO through a third contact hole penetrating the second interlayer insulating layer ILD2, the fourth gate insulating layer GI4, the third gate insulating layer GI3, and the first interlayer insulating layer ILD1.

[0090] The second portion GE2-2 of the second gate layer GE2 is electrically connected to the fourth gate layer GE4 through a transponder hole penetrating the first interlayer insulating layer ILD1, the third gate insulating layer GI3, and the fourth gate insulating layer GI4. The fourth gate layer GE4 includes a trace connected to the fourth node P. The second portion GE2-2 of the second gate layer GE2, through its electrical connection to the fourth gate layer GE4, enables the first plate of the second capacitor C2 to be electrically connected to the second plate of the first capacitor C1.

[0091] From a top-view perspective of the display panel DP, at least a portion of the fifth gate layer GE5 is located between the source and drain of the first transistor T1. At least a portion of the fifth gate layer GE5 overlaps with the portion of the active layer IGZO located between the source and drain of the first transistor T1. The first portion GE2-1 of the second gate layer GE2 overlaps with the source and drain of the first transistor T1 and the portion of the active layer IGZO located between the source and drain of the first transistor T1. The second portion GE2-2 of the second gate layer GE2 overlaps with at least a portion of the fifth gate layer GE5. The second portion GE2-2 of the second gate layer GE2 overlaps with the fifth gate layer GE5, forming the second capacitor C2.

[0092] In this embodiment, from a top-down view of the display panel DP, at least a portion of the fifth gate layer GE5 overlaps with the portion of the active layer IGZO located between the source and drain of the first transistor T1.

[0093] The fifth gate layer GE5 is electrically connected to the source-drain layer SD1 through the sixth contact hole that passes through the fifth gate insulating layer GI5, the first interlayer insulating layer ILD1, the third gate insulating layer GI3, the fourth gate insulating layer GI4, and the second interlayer insulating layer ILD2, and is then electrically connected to the fifth node C. Thus, the fifth gate layer GE5 serves as the second electrode of the second capacitor C2 and is electrically connected to the fifth node C.

[0094] like Figure 7 and Figure 8 As shown, the third embodiment of this application provides a display panel DP with a substrate, a first gate insulating layer GI1, a first gate layer GE1, a second gate insulating layer GI2, a second gate layer GE2, a first interlayer insulating layer ILD1, an active layer IGZO, a third gate insulating layer GI3, a third gate layer GE3, a fourth gate insulating layer GI4, a fourth gate layer GE4, a second interlayer insulating layer ILD2, and a source / drain layer SD1 arranged sequentially along the thickness direction of the display panel DP.

[0095] The first gate insulating layer GI1 is disposed on the substrate.

[0096] The first gate layer GE1 is disposed on the first gate insulating layer GI1, that is, the first gate layer GE1 is located on the first gate insulating layer GI1. The first gate layer GE1 constitutes the second electrode of the second capacitor C2. The first gate layer GE1 overlaps with the active layer IGZO. The second electrode of the second capacitor C2 is located in the film layer where the first gate layer GE1 is located. In this embodiment, the first gate layer GE1 constitutes the first metal layer of the display panel DP.

[0097] The second gate insulating layer GI2 is disposed on the first gate insulating layer GI1 and the first gate layer GE1, that is, the second gate insulating layer GI2 is located on the first gate layer GE1. The second gate insulating layer GI2 constitutes the dielectric layer of the second capacitor C2. In this embodiment, a gate insulating film layer is disposed on the first gate layer GE1 (first metal layer), and the second gate insulating layer GI2 constitutes the gate insulating film layer, which is located between the first gate layer GE1 (first metal layer) and the second gate layer GE2.

[0098] The second gate layer GE2 is disposed on the second gate insulating layer GI2. The second gate layer GE2 includes a first portion GE2-1 and a second portion GE2-2. The first portion GE2-1 of the second gate layer GE2 constitutes the second gate of the first transistor T1. The second portion GE2-2 of the second gate layer GE2 constitutes the first plate of the second capacitor C2. The second portion GE2-2 of the second gate layer GE2 does not overlap with the first portion GE2-1 of the second gate layer GE2. The second portion GE2-2 of the second gate layer GE2 overlaps with the first gate layer GE1 to form the second capacitor C2. In a direction perpendicular to the plane of the display panel, the second gate layer GE2 is located above the first gate layer GE1. The first plate of the second capacitor C2 is located in the film layer on which the second gate layer GE2 is located. In this embodiment, the second gate layer GE2 constitutes the second metal layer of the display panel DP, and the second gate layer GE2 (second metal layer) is located on the second gate insulating layer GI2 (gate insulating film layer).

[0099] Along the direction perpendicular to the plane where the display panel DP is located, the first gate layer GE1 (first metal layer) and the second gate layer GE2 (second metal layer) are both located below the film layer where the third gate layer GE3 is located.

[0100] The first interlayer insulating layer ILD1 is disposed on the second gate insulating layer GI2 and the second gate layer GE2, that is, the first interlayer insulating layer ILD1 is located on the second gate layer GE2.

[0101] The active layer IGZO is disposed on the first interlayer insulating layer ILD1, that is, the active layer IGZO is located on the first interlayer insulating layer ILD1.

[0102] The third gate insulating layer GI3 is disposed on the first interlayer insulating layer ILD1 and the active layer IGZO, that is, the third gate insulating layer GI3 is located on the active layer IGZO.

[0103] The third gate layer GE3 is disposed on the third gate insulating layer GI3, that is, the third gate layer GE3 is located on the third gate insulating layer GI3. The third gate layer GE3 constitutes the first gate of the first transistor T1. The first plate of the first capacitor C1 is located in the film layer on which the third gate layer GE3 is located.

[0104] The fourth gate insulating layer GI4 is disposed on the third gate insulating layer GI3 and the third gate layer GE3, that is, the fourth gate insulating layer GI4 is located on the third gate layer GE3.

[0105] The fourth gate layer GE4 is disposed on the fourth gate insulating layer GI4, that is, the fourth gate layer GE4 is located on the fourth gate insulating layer GI4. The second plate of the first capacitor C1 is located on the film layer where the fourth gate layer GE4 is located.

[0106] The second interlayer insulating layer ILD2 is disposed on the fourth gate insulating layer GI4 and the fourth gate layer GE4.

[0107] The source-drain layer SD1 is disposed on the second interlayer insulating layer ILD2.

[0108] One of the source and drain of the first transistor T1 is electrically connected to the first portion GE2-1 of the second gate layer GE2 through a first contact hole penetrating the second interlayer insulating layer ILD2, the fourth gate insulating layer GI4, the third gate insulating layer GI3, and the first interlayer insulating layer ILD1. The other of the source and drain of the first transistor T1 is electrically connected to the active layer IGZO through a second contact hole penetrating the second interlayer insulating layer ILD2, the fourth gate insulating layer GI4, and the third gate insulating layer GI3. The first portion GE2-1 of the second gate layer GE2 is electrically connected to the active layer IGZO through the other of the source and drain of the first transistor T1. One of the source and drain of the first transistor T1 is electrically connected to the active layer IGZO through a third contact hole penetrating the second interlayer insulating layer ILD2, the fourth gate insulating layer GI4, and the third gate insulating layer GI3.

[0109] The second portion GE2-2 of the second gate layer GE2 is electrically connected to the fourth gate layer GE4 through a switching hole that penetrates the first interlayer insulating layer ILD1, the third gate insulating layer GI3, and the fourth gate insulating layer GI4. The fourth gate layer GE4 includes the line where the fourth node P is located. The second portion GE2-2 of the second gate layer GE2, through its electrical connection with the fourth gate layer GE4, enables the first plate of the second capacitor C2 to be electrically connected to the second plate of the first capacitor C1.

[0110] From a top-view perspective of the display panel DP, at least a portion of the first gate layer GE1 is located between the source and drain of the first transistor T1. At least a portion of the first gate layer GE1 overlaps with the portion of the active layer IGZO located between the source and drain of the first transistor T1. The first portion GE2-1 of the second gate layer GE2 overlaps with the source and drain of the first transistor T1 and the portion of the active layer IGZO located between the source and drain of the first transistor T1. The second portion GE2-2 of the second gate layer GE2 overlaps with at least a portion of the first gate layer GE1, forming the second capacitor C2.

[0111] In this embodiment, from a top-view perspective of the display panel DP, at least a portion of the first gate layer GE1 overlaps with the portion of the active layer IGZO located between the source and drain of the first transistor T1. The overlap area between the first gate layer GE1 and the active layer IGZO increases the overlap area between the second capacitor C2 and the second portion GE2-2 of the second gate layer GE2, thereby increasing the capacitance value of the second capacitor C2.

[0112] The first gate layer GE1 is electrically connected to the source-drain layer SD1 through a seventh contact hole that passes through the second gate insulating layer GI2, the first interlayer insulating layer ILD1, the third gate insulating layer GI3, the fourth gate insulating layer GI4, and the second interlayer insulating layer ILD2, and is then electrically connected to the fifth node C. Thus, the first gate layer GE1 serves as the second electrode of the second capacitor C2 and is electrically connected to the fifth node C.

[0113] The three embodiments described above in this application improve the threshold voltage compensation capability within a limited pixel space by setting the second capacitor C2 at different film layer positions. The first embodiment forms the second capacitor C2 by adding a fifth gate insulating layer GI5 and a fifth gate layer GE5. The second embodiment forms the second capacitor C2 by reusing the second gate layer GE2 and adding a fifth gate layer GE5, reducing the number of film layers. The third embodiment forms the second capacitor C2 by completely reusing the first gate layer GE1 and the second gate layer GE2, eliminating the need for additional film layers and further simplifying the manufacturing process.

[0114] The timing controller TCON of the display device provided in the embodiments of this application is configured to control the gate drive circuit GOA and the source drive chip SDIC to perform threshold voltage compensation on the first transistor T1 in a first time period, and to write data voltage to the first plate of the second capacitor C2 in a second time period. The first time period is earlier than the second time period. The technical solution of this application achieves the separation of the threshold voltage compensation stage and the data signal writing stage by controlling the gate drive circuit GOA and the source drive chip SDIC to perform different operations in different time periods through the timing controller TCON.

[0115] Specifically, the first gate signal line SCAN1 is configured to turn on the third transistor T3 and the fourth transistor T4 during a first time period. The fourth transistor T4 is configured to transfer the voltage of the reset signal line VI-ANO to the first plate of the second capacitor C2, i.e., the fourth node P, when it is turned on. The third transistor T3 is configured to electrically connect one of the source and drain of the first transistor T1 to the first gate of the first transistor T1 when it is turned on, so that the first transistor T1 forms a diode and forms a threshold voltage compensation circuit. During the first time period, the first gate signal line SCAN1 controls the third transistor T3 and the fourth transistor T4 to turn on. The voltage of the reset signal line VI-ANO is transmitted to the fourth node P through the turned-on fourth transistor T4. One of the source and drain of the first transistor T1 is electrically connected to the first gate of the first transistor T1 through the turned-on third transistor T3. At this time, the first transistor T1 forms a diode connection. The voltage of the first gate of the first transistor T1 is adjusted according to the threshold voltage of the first transistor T1 and gradually stabilized to the voltage at which the first transistor T1 just turns on. The first plate of the first capacitor C1 is electrically connected to the first gate of the first transistor T1, and the second plate of the first capacitor C1 is electrically connected to the fourth node P. A voltage difference containing the threshold voltage information of the first transistor T1 is established across the first capacitor C1, thereby storing the threshold voltage compensation information of the first transistor T1 in the first capacitor C1.

[0116] The second gate signal line SCAN2 is configured to turn on the second transistor T2 during a second time period. The second transistor T2 is configured to transfer the data voltage of the data signal line DATA to the first plate of the second capacitor C2, i.e., the fourth node P, when it is turned on. During the second time period, the second gate signal line SCAN2 controls the second transistor T2 to turn on, and the data voltage of the data signal line DATA is transferred to the fourth node P through the turned-on second transistor T2, whereby the data voltage is written to the first plate of the second capacitor C2.

[0117] The technical solution of this application separates the data signal writing stage from the threshold voltage compensation stage, realizes the early performance of threshold voltage compensation, extends the threshold voltage compensation time, improves the threshold voltage compensation capability of the pixel driving circuit, solves the problem of insufficient intra-pixel compensation time under high pixel density, and improves the display effect of the display panel DP.

[0118] The embodiments of this application have been described in detail above. The content of this specification should not be construed as limiting the scope of protection of this application.

Claims

1. A display device, characterized in that, The display device includes a display panel, the display panel includes a plurality of pixels, each pixel includes a pixel driving circuit and a light-emitting device, the pixel driving circuit includes a first transistor, a first capacitor and a second capacitor, the first plate of the first capacitor is electrically connected to the first gate of the first transistor, the first plate of the second capacitor is electrically connected to the second plate of the first capacitor, and the second plate of the second capacitor is electrically connected to the anode of the light-emitting device. The display panel further includes an active layer, a third gate insulating layer located on the active layer, and a third gate layer located on the third gate insulating layer. The first gate of the first transistor is located in the film layer where the third gate layer is located. The first electrode of the second capacitor is located in the film layer where the first metal layer of the display panel is located. The second electrode of the second capacitor is located in the film layer where the second metal layer of the display panel is located. A gate insulating film layer is disposed on the first metal layer. The second metal layer is located on the gate insulating film layer. Along a direction perpendicular to the plane where the display panel is located, both the first metal layer and the second metal layer are located above the film layer where the third gate layer is located, or both the first metal layer and the second metal layer are located below the film layer where the third gate layer is located.

2. The display device according to claim 1, characterized in that, The display panel further includes a fourth gate insulating layer located on the third gate layer, a fourth gate layer located on the fourth gate insulating layer, a fifth gate insulating layer located on the fourth gate layer, and a fifth gate layer located on the fifth gate insulating layer; The first metal layer includes the fourth gate layer, the second metal layer includes the fifth gate layer, and the gate insulating film layer includes the fifth gate insulating layer.

3. The display device according to claim 2, characterized in that, From a top-view perspective of the display panel, at least a portion of the fourth gate layer and at least a portion of the fifth gate layer overlap with the portion of the active layer located between the source and drain of the first transistor.

4. The display device according to claim 3, characterized in that, From a top-view perspective of the display panel, the fourth gate layer and the fifth gate layer overlap in a region located on at least one side of the line connecting the source and drain of the first transistor and outside the active layer of the first transistor.

5. The display device according to claim 1, characterized in that, The display panel further includes a second gate insulating layer, a second gate layer located on the second gate insulating layer, and a first interlayer insulating layer located on the second gate layer, wherein the active layer is located on the first interlayer insulating layer; The second metal layer includes the second gate layer, and the gate insulating film layer is located between the first metal layer and the second gate layer.

6. The display device according to claim 5, characterized in that, The display panel further includes a fifth gate layer located on the second gate insulating layer and a fifth gate insulating layer located on the fifth gate layer, the second gate layer being located on the fifth gate insulating layer, the first metal layer including the fifth gate layer, and the gate insulating film layer including the fifth gate insulating layer.

7. The display device according to claim 6, characterized in that, From a top-down view of the display panel, at least a portion of the fifth gate layer overlaps with the portion of the active layer located between the source and drain of the first transistor.

8. The display device according to claim 5, characterized in that, The display panel further includes a first gate insulating layer and a first gate layer located on the first gate insulating layer, a second gate insulating layer located on the first gate layer, a first metal layer including the first gate layer, and a gate insulating film layer including the second gate insulating layer.

9. The display device according to claim 8, characterized in that, From a top-down view of the display panel, at least a portion of the first gate layer overlaps with the portion of the active layer located between the source and drain of the first transistor.

10. The display device according to claim 5, characterized in that, From a top-down view of the display panel, a first portion of the second gate layer overlaps with the source and drain of the first transistor, as well as the portion of the active layer located between the source and drain of the first transistor.

11. The display device according to claim 10, characterized in that, The first electrode of the second capacitor includes a second portion of the second gate layer, which overlaps with at least a portion of the first metal layer when viewed from above the display panel.

12. The display device according to claim 11, characterized in that, The display panel further includes a fourth gate insulating layer and a fourth gate layer located on the fourth gate insulating layer. The first electrode of the first capacitor is located in the film layer where the third gate layer is located. The second electrode of the first capacitor is located in the film layer where the fourth gate layer is located. The second part of the second gate layer is electrically connected to the part of the second electrode of the first capacitor located in the film layer where the fourth gate layer is located through a switching hole.

13. The display device according to claim 1, characterized in that, The pixel driving circuit further includes a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor. The first transistor further includes a second gate. The gate of the third transistor is electrically connected to a first gate signal line. One of the source and drain of the third transistor is electrically connected to one of the source and drain of the first transistor. The other of the source and drain of the third transistor is electrically connected to the first gate of the first transistor. The second gate of the first transistor is electrically connected to the other of the source and drain of the first transistor. The gate of the second transistor is electrically connected to a second gate signal line. One of the source and drain of the second transistor is electrically connected to a data signal line. The other of the source and drain of the second transistor is electrically connected to the first plate of the second capacitor. The gate of the fourth transistor is electrically connected to the first gate signal line. One of the source and drain of the fourth transistor is connected to a reset... The signal lines are electrically connected. The other of the source and drain of the fourth transistor is electrically connected to the first plate of the second capacitor. The gate of the fifth transistor is electrically connected to the first light-emitting control signal line. One of the source and drain of the fifth transistor is electrically connected to the first power supply line. The other of the source and drain of the fifth transistor is electrically connected to the source and drain of the first transistor. The gate of the sixth transistor is electrically connected to the second light-emitting control signal line. One of the source and drain of the sixth transistor is electrically connected to the other of the source and drain of the first transistor. The other of the source and drain of the sixth transistor is electrically connected to the second plate of the second capacitor. The gate of the seventh transistor is electrically connected to the first light-emitting control signal line. One of the source and drain of the seventh transistor is electrically connected to the reset signal line. The other of the source and drain of the seventh transistor is electrically connected to the second plate of the second capacitor.

14. The display device according to claim 13, characterized in that, The display device further includes a timing controller, a gate driving circuit, and a source driving chip. The timing controller is configured to control the gate driving circuit and the source driving chip to perform threshold voltage compensation on the first transistor in a first time period and to write data voltage to the first plate of the second capacitor in a second time period, wherein the first time period is earlier than the second time period.

15. The display device according to claim 14, characterized in that, The first gate signal line is configured to turn on the third transistor and the fourth transistor during the first time period, and the fourth transistor is configured to transfer the voltage of the reset signal line to the first plate of the second capacitor when it is turned on; The second gate signal line is configured to turn on the second transistor during the second time period, and the second transistor is configured to transfer the data voltage of the data signal line to the first plate of the second capacitor when it is turned on.

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