Method and device for dynamic compensation of display screen image quality under electromagnetic interference

Abstract

This invention provides a method and apparatus for dynamic compensation of display screen image quality under electromagnetic interference. The method includes: dividing source data lines into in-phase clusters based on the consistency of grayscale transition direction of adjacent columns of pixels to obtain a common-mode drive group enable signal; performing passive charge blind injection on adjacent data line pairs based on the common-mode drive group enable signal to obtain a balanced pre-charge level; applying timing misalignment drive to the data lines within the common-mode drive group based on the balanced pre-charge level to obtain a staggered charging waveform; applying directional current injection to the output stage of the source driver based on the staggered charging waveform to obtain a target voltage drive level; performing DC balance reset on the data line levels during the inter-frame vertical blanking period based on the target voltage drive level to obtain a zero-bias reference state; and maintaining the synchronous potential of the display screen pixel electrodes based on the zero-bias reference state and the target voltage drive to obtain a final drive signal. This invention improves the electromagnetic compatibility and display image quality of the display screen.

Description

Technical Field

[0001] This invention relates to the field of communication technology, and in particular to a method and apparatus for dynamic compensation of display screen image quality under electromagnetic interference. Background Technology

[0002] In LCD driving, the source driver needs to write voltage to the highly capacitive data lines within a very short line scan time. When there are large areas of high-contrast edges on the display screen, the voltage transitions of adjacent data lines are in the same direction, causing instantaneous current superposition and generating strong narrowband electromagnetic interference (EMI). This EMI can couple to sensitive reference voltage lines, causing brightness fluctuations or color crosstalk in the display.

[0003] Existing methods primarily employ global charge sharing to reduce power consumption or global spread spectrum clocking to distribute energy. While global charge sharing reduces average current, its unconditional execution introduces additional setup time overhead across all pixels, limiting high refresh rate applications. Global spread spectrum, on the other hand, causes timing jitter, affecting sampling accuracy. Therefore, existing methods lack targeted responses to electromagnetic risks associated with image content and cannot accurately suppress local electromagnetic resonance interference caused by specific high dynamic range image modes without sacrificing global refresh efficiency, thus reducing the electromagnetic compatibility and display quality of the screen in complex dynamic scenarios. Summary of the Invention

[0004] This invention provides a method and apparatus for dynamic compensation of display screen image quality under electromagnetic interference, aiming to solve the problems of existing global sharing technology sacrificing refresh efficiency or global spread spectrum technology affecting sampling accuracy, and improve the electromagnetic compatibility and display image quality of the display screen in complex dynamic scenarios.

[0005] In a first aspect, the present invention provides a method for dynamic compensation of display screen image quality under electromagnetic interference, comprising: Based on the consistency of the grayscale jump direction of adjacent columns of pixels in the current frame image data, the source data lines are divided into in-phase clusters to obtain the common mode drive group enable signal. Based on the common mode drive group enable signal, passive charge blind injection is performed on adjacent data line pairs to obtain a balanced pre-charge level. Based on the balanced pre-charge level, timing misalignment drive is applied to the data lines in the common-mode drive group to obtain a staggered charging waveform that disperses instantaneous current peaks. Based on the staggered charging waveform, directional current injection is applied to the output stage of the source driver to obtain the target voltage drive level. Based on the target voltage drive level, the data line level of the inter-frame vertical blanking period is DC balanced reset to obtain a zero bias reference state. Based on the zero-bias reference state and the target voltage driving electrode, the display pixel electrode is synchronously maintained to obtain the final driving signal.

[0006] In a second aspect, the present invention also provides a dynamic compensation device for display screen image quality under electromagnetic interference, used to implement the dynamic compensation method for display screen image quality under electromagnetic interference as described in the first aspect; the dynamic compensation device for display screen image quality under electromagnetic interference includes: The passive charge blind injection module is used to divide the source data lines into in-phase clusters based on the consistency of the gray-level jump direction of adjacent columns of pixels in the current frame image data, to obtain the common-mode drive group enable signal, and to perform passive charge blind injection on adjacent data line pairs based on the common-mode drive group enable signal to obtain a balanced pre-charge level. The directional current injection module is used to apply timing misalignment drive to the data lines in the common-mode drive group based on the balanced pre-charge level to obtain a staggered charging waveform that disperses instantaneous current peaks, and to apply directional current injection to the output stage of the source driver based on the staggered charging waveform to obtain the target voltage drive level. The DC balance reset module is used to perform DC balance reset on the data line level during the inter-frame vertical blanking period based on the target voltage drive level to obtain a zero bias reference state. The synchronization potential maintenance module is used to maintain the synchronization potential of the display pixel electrodes based on the zero bias reference state and the target voltage driving electrode to obtain the final driving signal.

[0007] Thirdly, the present invention also provides an electronic device, comprising: a memory for storing a computer program; and a processor for reading and executing the computer program, thereby realizing the dynamic compensation method for display screen image quality under electromagnetic interference as described above.

[0008] Fourthly, the present invention also provides a non-transitory computer-readable storage medium storing a computer program, which, when executed by a processor, implements the method for dynamic compensation of display screen image quality under electromagnetic interference as described above.

[0009] Fifthly, the present invention also provides a computer program product, including a computer program that, when executed by a processor, implements the dynamic compensation method for display screen image quality under electromagnetic interference as described above.

[0010] The method for dynamic compensation of display screen image quality under electromagnetic interference provided in this invention completes the division of source data line in-phase clusters and generates common-mode drive group enable signals based on the consistency of gray-level jump direction of adjacent columns of pixels in the current frame image. Based on the enable signals, passive charge blind injection is performed on adjacent data line pairs to obtain a balanced pre-charge level. This achieves targeted local identification and pre-charge balancing preprocessing for high-risk image modes such as high-contrast edges, avoiding the additional setup time overhead caused by the unconditional full-pixel execution of existing global charge sharing. Based on the balanced pre-charge level, timing misalignment drive is applied to the data lines within the common-mode drive group to generate a peak-shifting charging waveform that disperses instantaneous current peaks. Then, based on the waveform, directional current injection is performed on the driver output stage to obtain the target voltage drive level, breaking the instantaneous current superposition problem of traditional synchronous drive. This effectively weakens narrowband EMI interference in high dynamic image modes, while eliminating the need for a global spread spectrum clock and avoiding sampling accuracy loss caused by timing jitter. Based on the target voltage drive level, DC balance reset of the data line level is completed during the inter-frame vertical blanking period, constructing a zero-bias reference state and eliminating the level offset risk caused by EMI coupling to the reference voltage line. Based on the zero-bias reference state and the target voltage drive level, the synchronous potential of the display pixel electrodes is maintained and the final drive signal is generated. The entire process is precisely controlled only for local areas of high electromagnetic risk in the image, which preserves the high refresh performance of the global image. It solves the problem that existing global sharing technology sacrifices refresh efficiency or global spread spectrum technology affects sampling accuracy, and improves the electromagnetic compatibility and display quality of the display in complex dynamic scenes. Attached Figure Description

[0011] Figure 1 This is a flowchart illustrating the method for dynamic compensation of display screen image quality under electromagnetic interference provided in an embodiment of the present invention. Figure 2 This is a schematic diagram of the structure of the display screen dynamic compensation device for electromagnetic interference provided in an embodiment of the present invention; Figure 3 An embodiment diagram of the electronic device provided in this invention; Figure 4 An embodiment diagram of a computer-readable storage medium provided in accordance with the present invention. Detailed Implementation

[0012] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0013] In the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0014] In the description of this invention, the term "for example" is used to mean "used as an example, illustration, or description." Any embodiment described as "for example" in this invention is not necessarily to be construed as being more preferred or advantageous than other embodiments. The following description is provided to enable any person skilled in the art to make and use the invention. Details are set forth in the following description for purposes of explanation. It should be understood that those skilled in the art will recognize that the invention can be made without using these specific details. In other instances, well-known structures and processes will not be described in detail to avoid obscuring the description of the invention with unnecessary detail. Therefore, the invention is not intended to be limited to the embodiments shown, but is consistent with the broadest scope of the principles and features disclosed herein.

[0015] See Figure 1 , Figure 1 This is a flowchart illustrating the dynamic compensation method for display screen quality under electromagnetic interference provided by the present invention. In this embodiment of the invention, the executing entity of the dynamic compensation method for display screen quality under electromagnetic interference is a display management device. Therefore, the dynamic compensation method for display screen quality under electromagnetic interference includes: Step 10: Based on the consistency of the grayscale transition direction of adjacent columns of pixels in the current frame image data, the source data lines are divided into in-phase clusters to obtain the common-mode drive group enable signal. Based on the common-mode drive group enable signal, passive charge blind injection is performed on adjacent data line pairs to obtain a balanced pre-charge level.

[0016] Optionally, the display management device acquires the current frame image data and analyzes the grayscale transition direction of adjacent column pixels, that is, the increasing or decreasing trend of the grayscale value of the current frame pixel compared to the grayscale value of the previous frame pixel. When the grayscale transition direction of adjacent column pixels is detected to be consistent, the corresponding source data lines are divided into the same in-phase cluster, that is, the set of source data lines with consistent grayscale transition direction of adjacent column pixels.

[0017] The display management device generates a common-mode drive group enable signal, which is a trigger signal used to indicate whether the in-phase cluster needs to be controlled by common-mode drive, as shown in steps 101 to 104.

[0018] The display management device controls the adjacent data line pairs to perform passive charge blind injection based on the common mode drive group enable signal. That is, without relying on the precise target voltage value, the process of injecting charge into the data lines through the charge sharing network makes the data line voltage in the same phase cluster tend to the intermediate potential and obtain a balanced pre-charge level. Specifically, as in steps 105 to 108, the intermediate voltage state reached by the source data line after passive charge blind injection.

[0019] Step 20: Apply timing misalignment drive to the data lines in the common-mode drive group based on the balanced pre-charge level to obtain the staggered charging waveform that disperses the instantaneous current peaks, and apply directional current injection to the output stage of the source driver based on the staggered charging waveform to obtain the target voltage drive level.

[0020] Optionally, after acquiring the balanced pre-charge level, the display management device applies a timing-shifted drive to each source data line within the common-mode drive group. This involves applying time-delayed drive signals to different source data lines within the common-mode drive group. Specifically, a different drive delay time is allocated to each source data line within the common-mode drive group, causing the start times of charging from the balanced pre-charge level to the final target voltage for each source data line to be staggered. This timing shift causes the charging current, which was originally concentrated at the same moment, to be dispersed along the time axis, resulting in a staggered charging waveform. The staggered charging waveform is the voltage change curve caused by the timing-shifted drive, which disperses the instantaneous current peak along the time axis.

[0021] The display management device controls the output stage of the source driver to apply directional current injection to the corresponding source data lines based on the real-time voltage change rate of the off-peak charging waveform. That is, the output stage of the source driver provides a current of a specific direction and magnitude to the source data lines according to the real-time voltage change requirements of the off-peak charging waveform to compensate for the decrease in charging speed caused by timing misalignment. This ensures that each source data line accurately reaches the required voltage within the line scan time, thus obtaining the target voltage drive level. The target voltage drive level is the precise voltage value that the source data lines finally reach after directional current injection to drive the pixels.

[0022] For example, suppose source data lines 1, 2, and 3 are grouped into the same in-phase cluster, and a balanced pre-charge level of 5V is obtained. A timing misalignment drive is applied to these three source data lines. The drive delay time for source data line 1 is set to 0ns, the drive delay time for source data line 2 to 2ns, and the drive delay time for source data line 3 to 4ns.

[0023] Therefore, source data line 1 begins charging from 5V to the target voltage at 0ns, source data line 2 begins charging at 2ns, and source data line 3 begins charging at 4ns, thus forming a staggered charging waveform that disperses the instantaneous current peaks. Next, based on this staggered charging waveform, the output stage of the source driver is controlled to apply directional current injections to source data lines 1, 2, and 3 at the corresponding time points to maintain a predetermined charging slope, ultimately causing each of the three source data lines to reach its respective target voltage drive level.

[0024] Step 30: Perform DC balance reset on the data line level during the inter-frame vertical blanking period based on the target voltage drive level to obtain the zero bias reference state.

[0025] Optionally, after the display management device completes pixel charging for the current frame by outputting the target voltage drive level, it enters the inter-frame vertical blanking period, which is the non-display time period between the display of two adjacent frames. During this period, the display management device performs a DC balance reset on the source data line, that is, during the inter-frame vertical blanking period, it adjusts the source data line level to a specific DC reference voltage to eliminate residual charge.

[0026] Specifically, by closing a specific reset switch network, all source data lines are connected to a preset common DC reference voltage source. During the aforementioned driving process, driving voltages of different polarities may cause residual charge to accumulate on the parasitic capacitance of the data lines, forming a DC bias. Through DC balancing reset, the residual charge is released or neutralized, forcing the potential of all source data lines to converge to the common DC reference voltage, thereby eliminating the accumulated DC bias effect and obtaining a zero-bias reference state. The zero-bias reference state is the stable voltage state of the source data lines without residual DC bias after the DC balancing reset. This zero-bias reference state provides a clean and consistent initial potential condition for driving the next frame of the image, avoiding crosstalk or brightness unevenness caused by residual charge in subsequent image display.

[0027] For example, after driving source data lines 1, 2, and 3 to their respective target voltage drive levels and completing the display of the current frame, the inter-frame vertical blanking period begins. The control reset switch network closes, simultaneously connecting source data lines 1, 2, and 3 to a common DC reference voltage source, which provides a voltage of 6V. After a preset reset time, the residual charge accumulated on source data lines 1, 2, and 3 due to the previous frame's drive is completely neutralized, and the potentials of these three source data lines stabilize at 6V, achieving a zero-bias reference state, preparing for the drive of the next frame.

[0028] Step 40: Based on the zero bias reference state and the target voltage driving current, the display pixel electrodes are synchronously maintained to obtain the final driving signal.

[0029] Optionally, when the next frame starts driving, the display management device uses the zero-bias reference state as the initial potential and combines it with the target voltage driving level calculated in the current frame to maintain the synchronous potential of the display pixel electrode. That is, after the pixel electrode is charged, the final driving signal is obtained by disconnecting the connection and relying on the pixel capacitor to maintain its voltage stability. Specifically, as in steps 401 to 404, the final driving signal is used to control the display pixel electrode to display the final image.

[0030] The embodiments of the present invention improve the electromagnetic compatibility and display quality of the display screen in complex dynamic scenes.

[0031] Optionally, the processes of steps 101 to 104 include: Step 101: Extract the sign bit based on the gray level of the current column pixel in the current row and the gray level of the next adjacent column pixel to obtain the sign bit sequence of the gray level difference between adjacent columns in the current row.

[0032] Optionally, the display management device acquires the grayscale of the current column pixel in the current row and the grayscale of the adjacent next column pixel, calculates the difference between the grayscale of the adjacent next column pixel and the grayscale of the current column pixel, and obtains the grayscale difference between adjacent columns. The sign bit of the grayscale difference between adjacent columns is extracted, that is, the highest binary bit representing the positive or negative state of the difference is extracted. When the difference is positive or zero, it is extracted as a logic high level (1), and when the difference is negative, it is extracted as a logic low level (0), thus obtaining the sign bit of the grayscale difference between adjacent columns corresponding to the current column.

[0033] Traverse all columns of the current row, extract the sign bit of the grayscale difference between adjacent columns for each pair of adjacent columns, and arrange them in the order of columns to obtain the sequence of sign bits of the grayscale difference between adjacent columns of the current row.

[0034] For example, suppose the current row contains five columns of pixels with gray levels of 10, 20, 15, 15, and 30 respectively. The display management device calculates the gray level differences between adjacent columns, which are 20 minus 10 equals 10, 15 minus 20 equals -5, 15 minus 15 equals 0, and 30 minus 15 equals 15.

[0035] Extract the sign bit: 10 and 0 are extracted as logic high level 1, -5 is extracted as logic low level 0, and 15 is extracted as logic high level 1.

[0036] Therefore, the sign bit sequence of the grayscale difference between adjacent columns in the current row is 1, 0, 1, 1.

[0037] Step 102: Perform a logical XOR operation on the grayscale difference sign bit sequence of the adjacent columns of the current row and the grayscale difference sign bit sequence of the adjacent columns of the previous row to obtain the row breakpoints, and perform edge-triggered latching based on the positions where the logic level is 0 in the row breakpoints to obtain the in-phase cluster boundary index register group. Optionally, the display management device acquires the sign bit sequence of the grayscale difference between adjacent columns of the previous row, and performs a bit-by-bit logical XOR operation on the sign bit sequence of the grayscale difference between adjacent columns of the current row and the sign bit sequence of the grayscale difference between adjacent columns of the previous row. That is, the logical operation outputs a logic high level when the two input logic levels are the same and outputs a logic low level when they are different, thus obtaining the inter-row breakpoint sequence. In the inter-row breakpoint sequence, a logic high level indicates that the grayscale transition direction of the current row and the previous row is the same at that position, and a logic low level indicates that the grayscale transition direction of the current row and the previous row changes at that position. The position of the logic low level is the inter-row breakpoint, that is, the position where the grayscale transition direction changes between two adjacent rows.

[0038] The display management device performs edge-triggered latching on positions where the logic level is 0 in the row breakpoint sequence. That is, when an edge of logic level change is detected, the circuit operation that triggers and saves the data state at that position is activated, and the corresponding column index is stored in the in-phase cluster boundary index register group. The in-phase cluster boundary index register group is the set of registers used to store the column index of the in-phase cluster boundary.

[0039] For example, the sign bit sequence of the grayscale difference between adjacent columns in the current row is 1, 0, 1, 1. Assume the sign bit sequence of the grayscale difference between adjacent columns in the previous row is 1, 1, 1, 0. The display management device performs a bit-by-bit logical XOR operation: if the first bit (1 and 1) are the same, it outputs 1; if the second bit (0 and 1) are different, it outputs 0; if the third bit (1 and 1) are the same, it outputs 1; if the fourth bit (1 and 0) are different, it outputs 0, resulting in a row breakpoint sequence of 1, 0, 1, 0. The positions where the logic level is 0 are the second and fourth bits. The display management device performs edge-triggered latching on the second and fourth bits, storing column indices 2 and 4 into the in-phase cluster boundary index register group.

[0040] Step 103: Configure the path connectivity of the charge sharing switch matrix of the source driver based on the column interval range of the in-phase cluster boundary index register group to obtain the static cluster topology.

[0041] Optionally, the display management device reads the column index in the in-phase cluster boundary index register group to determine the column interval range defined by the adjacent boundary index.

[0042] The display management device configures the path connectivity of the charge sharing switch matrix of the source driver based on the range of this column, that is, controls the operation of closing or opening the switch to establish or disconnect the electrical connection. The charge sharing switch matrix is ​​a physical array composed of multiple switches for controlling charge sharing between source data lines.

[0043] Specifically, the display management device closes the switches between the corresponding source data lines within a defined column interval, so that the source data lines within the interval are electrically connected to each other, resulting in a static cluster topology, that is, a network structure in which the source data lines maintain a fixed electrical connection within a specific time period.

[0044] For example, the column indices stored in the in-phase cluster boundary index register set are 2 and 4.

[0045] The column intervals are defined as columns 1 to 2, 3 to 4, and 5. The charge-sharing switch matrix of the source drivers is configured with connectivity: the switch between the source data lines in columns 1 and 2 is closed, the switch between the source data lines in columns 3 and 4 is closed, and the other switches are opened, resulting in a static cluster topology. Specifically, the source data lines in columns 1 and 2 form one cluster, the source data lines in columns 3 and 4 form another cluster, and the source data lines in column 5 form a separate cluster.

[0046] Step 104: Based on the number of data lines in each connected cluster in the static cluster topology, the source data lines are divided into in-phase clusters to obtain the common-mode drive group enable signal.

[0047] Optionally, the display management device divides the source data lines into in-phase clusters based on the number of data lines in each connected cluster in the static cluster topology to obtain the common-mode drive group enable signal, as in steps 1041 to 1044.

[0048] This invention, through extracting the sign bit sequence of the grayscale difference between adjacent columns of pixels and performing a logical XNOR operation with the previous row, accurately locates the inter-row breakpoints where the grayscale jump direction changes in the vertical direction. Then, through edge-triggered latching and path connectivity configuration, a static cluster topology structure highly consistent with the high-contrast edges of the image is constructed at the physical level. Based on this, in-phase clusters are divided and common-mode drive group enable signals are generated. This achieves pixel-level accurate identification and hardware-level dynamic reconstruction of local electromagnetic risk areas in highly dynamic images. This ensures that subsequent passive charge blind injection and timing misalignment driving are strictly limited to the set of high-risk data lines experiencing in-phase jumps, avoiding the additional setup time overhead caused by global charge sharing. Without sacrificing global refresh efficiency, this effectively solves the problems of existing global sharing technologies sacrificing refresh efficiency or global spread spectrum technologies affecting sampling accuracy, improving the electromagnetic compatibility and display quality of the display screen in complex dynamic scenarios.

[0049] Optionally, the process of steps 1041 to 1044 includes: Step 1041: Based on the number of data lines in each connected cluster in the static cluster topology, perform parity counting to obtain the cluster drive mode selection bit; Optionally, the display management device reads the static cluster topology obtained in the aforementioned steps, counts the physical number of source data lines contained in each connected cluster, i.e., the set of source data lines that are electrically connected to each other within a defined column interval, and obtains the number of data lines.

[0050] The operation involves counting the number of data lines to determine if the number is divisible by 2. If the number is divisible by 2, it is considered even and a logic high level (1) is output to indicate an even number; if the number is not divisible by 2, it is considered odd and a logic low level (0) is output to indicate an odd number. This yields the cluster drive mode selection bit, which is a binary control bit used to indicate which drive mode the currently connected cluster should use.

[0051] For example, a static cluster topology contains three connected clusters: the connected cluster consisting of columns 1 and 2 contains 2 source data lines, the connected cluster consisting of columns 3 and 4 contains 2 source data lines, and the connected cluster consisting of column 5 contains 1 source data line. The parity of the number of data lines in these three connected clusters is counted. For the connected cluster consisting of columns 1 and 2, the number 2 is divisible by 2, so it is considered even, and a logic high level 1 is output; for the connected cluster consisting of columns 3 and 4, the number 2 is divisible by 2, so it is considered even, and a logic high level 1 is output; for the connected cluster consisting of column 5, the number 1 is not divisible by 2, so it is considered odd, and a logic low level 0 is output. Therefore, the cluster drive mode selection bits for these three connected clusters are 1, 1, and 0, respectively.

[0052] Step 1042: Perform a logical AND operation on the phase polarity of the cluster drive mode selection bit and the common-mode voltage source to obtain a unidirectional charge injection enable pulse.

[0053] Optionally, the display management device acquires a common-mode voltage source, which is a power supply providing a common-mode pre-charge voltage. The phase polarity of the common-mode voltage source at the current moment—that is, a binary representation of whether the common-mode voltage source outputs a positive or negative voltage—is shown; for example, a positive voltage is represented by a logic high level 1, and a negative voltage by a logic low level 0. The display management device performs a bit-by-bit logical AND operation between the obtained cluster drive mode selection bit and the phase polarity of the common-mode voltage source. Specifically, it outputs a logic high level 1 when both inputs are logic high level 1, and outputs a logic low level 0 if either input is logic low level 0. The high-level pulse output by this operation is the unidirectional charge injection enable pulse, which triggers a brief high-level control signal to unidirectionally inject charge into the source data line.

[0054] For example, the cluster drive mode selection bits of three connected clusters are 1, 1, and 0, respectively. Assume that the common-mode voltage source is currently outputting a positive-phase voltage with a phase polarity of logic high (1). Perform a logical AND operation between the cluster drive mode selection bits and the phase polarity of the common-mode voltage source.

[0055] For the connected clusters formed by columns 1 and 2, perform a logical AND operation between 1 and 1 to output 1.

[0056] For the connected clusters formed by columns 3 and 4, perform a logical AND operation between 1 and 1 to output 1.

[0057] For the connected clusters formed by the 5th column, perform a logical AND operation between 0 and 1 to output 0.

[0058] Thus, the unidirectional charge injection enable pulses corresponding to these three connected clusters are logic high level 1, logic high level 1, and logic low level 0, respectively.

[0059] Step 1043: Align the time window based on the unidirectional charge injection enable pulse and the row scan synchronization signal to obtain the common mode drive activation window signal within the row cycle; Optionally, the display management device acquires a line scan synchronization signal, which is a reference clock signal used to indicate that the current line pixel begins scanning and charging. The unidirectional charge injection enable pulse is aligned with the line scan synchronization signal in a time window. That is, within the effective time period of the line cycle indicated by the line scan synchronization signal, the operation that coincides with the time interval when the unidirectional charge injection enable pulse is in the logic high level 1 state is extracted to obtain the common mode drive activation window signal within the line cycle. The common mode drive activation window signal is the effective time interval control signal that allows the common mode drive circuit to actually work within a single line scan cycle.

[0060] For example, the unidirectional charge injection enable pulse for the connected clusters consisting of columns 1 and 2, and columns 3 and 4, is logic high (1), while the unidirectional charge injection enable pulse for the connected cluster consisting of column 5 is logic low (0). Assume the effective time period of the row cycle indicated by the row scan synchronization signal is 0 ns to 10 ns. The display management device performs time window alignment. For the connected clusters consisting of columns 1 and 2, and columns 3 and 4, since the enable pulse is 1, it remains effective from 0 ns to 10 ns; therefore, its common-mode drive activation window signal is a high-level signal from 0 ns to 10 ns. For the connected cluster consisting of column 5, since the enable pulse is 0, it is ineffective throughout the entire row cycle; therefore, its common-mode drive activation window signal is a low-level signal throughout the entire cycle.

[0061] Step 1044: Based on the common-mode drive activation window signal, the gate of the pre-charge switch of the source driver output stage is driven to obtain the common-mode drive group enable signal.

[0062] Optionally, the display management device applies a common-mode drive activation window signal to the gate of the precharge switch in the source driver output stage. The source driver output stage refers to the circuit portion of the source driver that is directly connected to and drives the source data line. The precharge switch refers to the switching device used to control the electrical connection between the common-mode voltage source and the source data line. The gate refers to the control electrode that controls the precharge switch to be turned on or off.

[0063] When the common-mode drive activation window signal is at a logic high level, the display management device drives the gate of the pre-charge switch through this signal, causing the pre-charge switch to enter the conducting state. This establishes an electrical connection between the common-mode voltage source and the corresponding source data line, allowing charge to flow from the common-mode voltage source to the source data line. When the common-mode drive activation window signal is at a logic low level, the display management device drives the gate of the pre-charge switch through this signal, causing the pre-charge switch to enter the off state. This disconnects the electrical connection between the common-mode voltage source and the corresponding source data line, terminating the charge injection process.

[0064] The display management device converts the common-mode drive activation window signal into a hardware drive control signal that actually controls the source data lines in the in-phase cluster to perform common-mode pre-charging by driving the pre-charge switch gate as described above. This hardware drive control signal is output to the charge sharing switch matrix of the source driver as a common-mode drive group enable signal, and is used to precisely control the start and end times of passive charge blind injection.

[0065] For example, the common-mode drive activation window signal of the connected clusters composed of columns 1 and 2 and columns 3 and 4 is high within 0 ns to 10 ns, while the common-mode drive activation window signal of the connected cluster composed of column 5 is low for the entire cycle.

[0066] The display management device applies these signals to the gates of the corresponding source data line precharge switches. During the period from 0 ns to 10 ns, the precharge switches of the source data lines in columns 1, 2, 3, and 4 are driven to turn on by the gates, generating valid common-mode drive group enable signals; while the precharge switch of the source data line in column 5 remains off, generating invalid common-mode drive group enable signals.

[0067] This invention generates a cluster drive mode selection bit by counting the number of data lines connected within a cluster in a static cluster topology based on parity. It then performs a logical AND operation with the phase polarity of the common-mode voltage source to generate a unidirectional charge injection enable pulse. This pulse is then time-window aligned with the horizontal scanning synchronization signal to generate a common-mode drive activation window signal within the horizontal cycle. Finally, this window signal is used to precisely drive the pre-charge switch of the source driver output stage to generate a common-mode drive group enable signal. Therefore, it achieves deep, multi-dimensional logical fusion of the spatial distribution characteristics of image content, the timing control of the drive circuit, and electrical characteristics. This ensures that the common-mode drive group enable signal is precisely activated only in specific high-risk in-phase clusters and under specific electrical and timing conditions. This achieves granular control of the passive charge blind injection process, avoids invalid charge injection in non-risk areas or when conditions are mismatched, effectively suppresses local electromagnetic interference at high-contrast edges, and maximizes the preservation of global screen refresh efficiency and drive timing purity. This improves the electromagnetic compatibility and display quality of the display screen in complex dynamic scenes.

[0068] Optionally, steps 105 to 108 include: Step 105: Based on the bit conduction source driver output stage with logic level 1 in the common-mode drive group enable signal, the charge sharing transmission gate between adjacent data line pairs is turned on, and a local charge connectivity network is obtained.

[0069] Optionally, the display management device reads the common-mode drive group enable signal and filters out bits with a logic level of 1, which are valid control bits indicating that the connected clusters corresponding to these bits are allowed to undergo common-mode pre-charging. For the source data lines indicated by these bits with a logic level of 1, the output control voltage turns on the charge sharing transfer gate between adjacent data line pairs in the source driver output stage.

[0070] Charge-sharing transfer gates are bidirectional switching devices made of complementary metal-oxide-semiconductor (CMOS) semiconductors used to establish low-impedance charge transfer channels between adjacent source data lines. When these transfer gates are turned on, the selected adjacent source data lines are physically connected to each other, forming a local charge connectivity network, that is, a set of source data lines that are electrically connected within a local region.

[0071] For example, the source data lines in columns 1, 2, 3, and 4 generate a valid common-mode drive group enable signal (logic level 1), while the source data line in column 5 generates an invalid common-mode drive group enable signal (logic level 0). The charge-sharing transmission gate between the source data lines in columns 1 and 2, and between the source data lines in columns 3 and 4, is turned on, while the transmission gates between columns 4 and 5, and others not mentioned, remain off.

[0072] Thus, the first and second column source data lines form the first local charge interconnection network, and the third and fourth column source data lines form the second local charge interconnection network.

[0073] Step 106: Based on the local charge interconnection network, the isolation switches between each connected data line pair and its respective digital-to-analog converter output terminal are simultaneously cut off, so that the data line pairs are in a floating interconnection state. Based on the parasitic capacitance of adjacent data line pairs in the floating interconnection state, charge distribution is performed to obtain the intermediate shared voltage after potential equalization.

[0074] Optionally, the display management device, while establishing the local charge connection network, outputs a cut-off control signal to simultaneously disconnect the isolating switches between each connected data line pair and its respective digital-to-analog converter (DAC) output. The DAC output refers to the output node within the source driver that converts digital image data into analog drive voltage. The isolating switch is a switching device used to disconnect the electrical connection between the DAC output and the source data lines during specific operating phases to prevent signal interference. After disconnecting the isolating switches, the source data line pairs within the local charge connection network are disconnected from the drive voltage source and are in a floating interconnection state. That is, the source data line pairs are neither connected to an external power supply nor to ground, but are interconnected only through charge-sharing transmission gates and store charge using their own parasitic capacitance. In the floating interconnect state, due to the initial voltage difference between adjacent data line pairs, the charge is redistributed between the parasitic capacitances of adjacent data line pairs through the charge sharing transmission gate until the potentials of the two are equal, resulting in an intermediate shared voltage after potential equilibrium. The parasitic capacitance is the equivalent capacitance formed by the physical structure of the source data line itself to ground or other conductive layers. The intermediate shared voltage is the voltage value shared by all source data lines in the local charge-connected network after the charge redistribution reaches equilibrium.

[0075] For example, simultaneously disconnect the isolating switches between the source data lines of columns 1, 2, 3, and 4 and their respective digital-to-analog converter outputs. Assume that before disconnection, the voltage of the source data line of column 1 is 8V, the voltage of the source data line of column 2 is 2V, and their parasitic capacitances are equal; the voltage of the source data line of column 3 is 6V, the voltage of the source data line of column 4 is 4V, and their parasitic capacitances are equal. After disconnecting the isolating switches, these four source data lines enter a floating interconnect state.

[0076] In the first local charge interconnection network, the charges on the source data lines in columns 1 and 2 are redistributed. Due to the equal parasitic capacitance, the potentials are eventually balanced, resulting in an intermediate shared voltage of 8 + 2 divided by 2, which equals 5V. In the second local charge interconnection network, the charges on the source data lines in columns 3 and 4 are redistributed, resulting in an intermediate shared voltage of 6 + 4 divided by 2, which equals 5V.

[0077] Step 107: Based on the polarity attribute of the intermediate shared voltage, latch the state of the corresponding polarity hold trigger to obtain the polarity lock signal, and perform an XOR logic operation on the polarity lock signal and the frame inversion control signal to obtain the phase consistency flag bit.

[0078] Optionally, the polarity attribute of the intermediate shared voltage is detected, i.e., whether the intermediate shared voltage is positive or negative relative to the common electrode reference voltage. Based on the polarity attribute, the corresponding logic level is written into and latched in a polarity hold trigger to obtain a polarity lock signal. The polarity hold trigger is a timing logic circuit used to memorize and maintain the polarity state of the source data line drive voltage within a specific time period. The polarity lock signal is a binary signal that characterizes the current polarity state of the intermediate shared voltage and is stably maintained. The frame inversion control signal is obtained, i.e., a global control signal indicating whether the polarity of the current frame image drive voltage needs to be inverted relative to the previous frame. The polarity lock signal and the frame inversion control signal are XORed, i.e., the output logic is high (1) when the two input signals are different and low (0) when they are the same, to obtain a phase consistency flag bit, i.e., a binary flag signal indicating whether the pre-charge polarity in the current local charge network is consistent with the overall drive polarity requirement of the current frame.

[0079] For example, assuming the common electrode reference voltage is 0V, and the intermediate shared voltage of the source data lines in columns 1 and 2, and columns 3 and 4 is 5V, all with positive polarity, a logic high level of 1 representing positive polarity is latched in the corresponding polarity hold flip-flop, resulting in a polarity latch signal of 1. Assuming the frame inversion control signal for the current frame indicates a polarity flip, its logic level is 1.

[0080] Perform an XOR operation between the polarity lock signal 1 and the frame inversion control signal 1. If 1 and 1 are the same, the output logic is low (0), resulting in a phase consistency flag bit of 0, indicating that the positive polarity of the current intermediate shared voltage is inconsistent with the negative polarity required by the current frame.

[0081] Step 108: Based on the phase consistency flag bit, control the on / off state of the precharge phase switching switch to achieve polarity alignment of the precharge potential, and based on the polarity-aligned precharge potential, close the switch between the data line node and the local small-capacity holding capacitor to obtain a balanced precharge level.

[0082] Optionally, the display management device controls the on / off state of the precharge phase switching switch according to the logic state of the phase consistency flag bit. The precharge phase switching switch is a multiplexer used to select the connection of a positive or negative precharge voltage source to adjust the precharge polarity of the source data line.

[0083] When the phase consistency flag indicates a polarity inconsistency, the display management device switches the precharge phase switching switch, connects the local charge connection network to the precharge voltage source with the opposite polarity to the intermediate shared voltage, performs polarity reversal compensation on the intermediate shared voltage, and achieves polarity alignment of the precharge potential, so that the polarity of the precharge potential is exactly the same as the overall driving polarity requirement of the current frame.

[0084] The switch connecting the data line node and the local small-capacity holding capacitor is closed. The data line node is the physical connection point on the source data line used to connect external capacitors. The local small-capacity holding capacitor is a small-capacity energy storage device integrated inside the source driver to maintain the node potential stability for a short period of time. After closing the switch, the local small-capacity holding capacitor is connected in parallel with the source data line, absorbing and stabilizing the pre-charge potential after polarity alignment, resulting in a balanced pre-charge level. That is, after charge sharing, potential equalization, polarity alignment, and capacitor voltage regulation, the source data line reaches a stable and correctly polarized initial voltage state before formal driving.

[0085] For example, if the phase consistency flag bits of the source data lines in columns 1 and 2, and columns 3 and 4 are all 0, it indicates that the polarity is inconsistent. The control precharge phase switching switch turns on the negative polarity precharge voltage source. Assuming that the negative polarity precharge voltage source provides a voltage of -5V, the original 5V intermediate shared voltage is pulled down to -5V, thereby achieving polarity alignment of the precharge potential (consistent with the negative polarity required by the current frame).

[0086] The switches connecting the data line nodes of the source data lines in columns 1, 2, 3, and 4 to their respective local small-capacity holding capacitors are closed. The local small-capacity holding capacitors absorb charge fluctuations, stabilizing the voltage at -5V, and ultimately all four source data lines receive a balanced pre-charge level of -5V.

[0087] This invention employs a common-mode drive group enable signal to precisely activate the charge-sharing transmission gate, constructing a local charge connectivity network. Simultaneously, the isolating switch is disconnected, allowing data line pairs to enter a floating interconnect state. Parasitic capacitance is used for charge distribution to obtain an intermediate shared voltage. Then, a polarity-holding trigger latches the polarity attribute and performs an XOR operation with the frame inversion control signal to generate a phase consistency flag. Finally, based on this flag, the pre-charge phase switching switch is controlled to complete polarity alignment and close the local small-capacity holding capacitor switch to stabilize the potential, resulting in a balanced pre-charge level. This achieves passive charge blind injection and polarity adaptive calibration for high-risk in-phase clusters. Not only does the floating charge distribution significantly reduce the initial voltage difference between adjacent data lines, thus lowering the transient current requirement for subsequent active drives, but the polarity alignment and capacitor voltage regulation mechanism also ensure an absolute match between the pre-charge level and the current frame drive polarity. This eliminates charge backflow and additional power consumption caused by polarity errors, providing a stable initial potential reference for subsequent timing misalignment drives. This maximizes charge utilization efficiency and image refresh quality while reducing local electromagnetic interference.

[0088] Optionally, the processes of steps 401 to 404 include: Step 401: Start the line scan cycle counter based on the rising edge trigger time of the horizontal synchronization signal to generate a video data window signal covering all pixel clock cycles of the current line.

[0089] Optionally, the display management device acquires a horizontal synchronization signal, which is a reference synchronization pulse signal indicating the start of a row of pixel scanning, and detects the rising edge trigger time of the horizontal synchronization signal, that is, the instant the signal jumps from a low level to a high level.

[0090] At the rising edge trigger moment, the display management device starts the line scan cycle counter, which is a digital counting circuit used to record the number of pixel clock cycles elapsed during the current line scan. The line scan cycle counter begins to accumulate the pixel clock cycles, which are the smallest time units used to synchronize the data transmission and processing of a single pixel. When the count value reaches the total number of pixels contained in the current line, a video data window signal is generated, which is a time interval control signal indicating the time interval during which effective video data transmission and processing is allowed in the current line. This video data window signal covers the entire pixel clock cycle of the current line, ensuring that the data of all pixels in the entire line can be effectively processed.

[0091] For example, assuming the current row contains five columns of pixels, it would take five pixel clock cycles to complete the data transmission. The display management device detects the rising edge of the horizontal sync signal at 0ns and then starts the row scan cycle counter at 0ns. The row scan cycle counter accumulates the pixel clock cycles, with each pixel clock cycle lasting 2ns.

[0092] When the count value accumulates from 0 to 5, that is, after 10ns, the display management device generates a video data window signal covering 0ns to 10ns, which remains at a valid high level during the period from 0ns to 10ns.

[0093] Step 402: Based on the input sampling switch between the data latch of each channel and the digital bus in the source driver closed by the start edge of the video data window signal, the grayscale data in the target voltage drive level is loaded into the grayscale code to be converted in the digital storage node of each channel.

[0094] Optionally, the display management device acquires the starting edge of the video data window signal, i.e., the moment when the video data window signal transitions from an invalid state to an valid state. At this starting edge, a control signal is output to close the input sampling switch between each channel data latch in the source driver and the digital bus. The channel data latch is a timing storage circuit within the source driver used to temporarily store the digital grayscale data of the corresponding pixels of each output channel. The digital bus is a set of multiple wires used for parallel or serial transmission of digital image data between the display management device and the source driver. The input sampling switch is an electronic switching device that controls whether data on the digital bus can enter the channel data latch.

[0095] The display management device loads the grayscale data in the target voltage drive level into the digital storage nodes of each channel via the digital bus to form the grayscale code to be converted. The grayscale data is the digital encoding information of the pixel brightness level corresponding to the target voltage drive level. The digital storage node is the circuit node inside the channel data latch used to physically store the digital logic level. The grayscale code to be converted is the digital grayscale code waiting to be converted into analog voltage by the digital-to-analog converter.

[0096] For example, the starting edge of the video data window signal is 0ns. At 0ns, the input sampling switches between the data latches of columns 1, 2, 3, 4, and 5 in the source driver and the digital bus are closed. The grayscale data in the corresponding target voltage drive level is loaded into the digital storage nodes of these five channels via the digital bus. Assuming that the grayscale data in the target voltage drive level corresponding to the pixels in columns 1 to 5 are digital codes 128, 64, 192, 255, and 0 respectively, these digital codes, after being loaded, become the grayscale codes to be converted for columns 1 to 5 respectively.

[0097] Step 403: Based on the grayscale code to be converted, control the decoding switch array in each channel digital-to-analog converter to perform tap selection, and connect the corresponding potential in the reference voltage ladder to the non-inverting input terminal of the operational amplifier.

[0098] Optionally, the display management device reads the grayscale code to be converted from the data latches of each channel, and controls the decoding switch array in each channel's digital-to-analog converter to perform tap selection based on the binary value of the grayscale code. The channel digital-to-analog converter is a circuit module that converts digital grayscale encoding into corresponding analog driving voltage. The decoding switch array is a switch network composed of multiple switches that selects a specific voltage node according to the digital encoding. Tap selection is the action of closing a specific switch in the decoding switch array to select a specific voltage node on the reference voltage ladder. The reference voltage ladder is a resistor network that provides multiple discrete step-like reference voltages generated by a series of series resistors, with multiple tap nodes at different potentials distributed on it.

[0099] By tapping, the display management device connects a specific potential in the reference voltage ladder corresponding to the grayscale code to be converted to the non-inverting input terminal of the operational amplifier. The operational amplifier is an analog amplifier circuit with high input impedance and high open-loop gain, used for buffering and driving source data lines. The non-inverting input terminal is the input terminal in the operational amplifier where the output signal phase is the same as the input signal phase.

[0100] For example, the grayscale codes to be converted for channels 1 through 5 are 128, 64, 192, 255, and 0, respectively. Based on these grayscale codes, the decoding switch array within the digital-to-analog converters of channels 1 through 5 is controlled to perform tap selection. Assume the reference voltage ladder provides a voltage range of 0 to 10V and has 256 tap nodes evenly distributed. For channel 1, the grayscale code 128 corresponds to the tap node in the middle of the reference voltage ladder; selecting this node connects a 5V potential to the non-inverting input of the operational amplifier in channel 1. For channel 2, the grayscale code 64 corresponds to a lower tap node; selecting this node connects a 2.5V potential to the non-inverting input. Similarly, channels 3, 4, and 5 select their corresponding nodes, connecting 7.5V, 10V, and 0V potentials to the non-inverting inputs of their respective operational amplifiers.

[0101] Step 404: Based on the zero bias reference state and the potential difference between the target reference potential and the feedback node connected to the inverting input of the operational amplifier, the display pixel electrode is kept synchronously to obtain the final drive signal.

[0102] Optionally, the display management device maintains the synchronous potential of the display pixel electrode based on the zero-bias reference state, that is, after DC balance reset, the source data line is in a stable voltage state with no residual DC bias, and the potential difference between the target reference potential and the feedback node connected to the inverting input terminal of the operational amplifier. That is, after the pixel electrode is charged, the final drive signal is obtained by disconnecting the connection and relying on the pixel capacitor to maintain its voltage stability. The final drive signal is the trigger control signal of the complete electrical signal used to control the display pixel electrode to display the final image, as in steps 4041 to 4044.

[0103] This invention utilizes the rising edge of a horizontal synchronization signal to trigger a line scan cycle counter, generating a video data window signal covering the entire line. The starting edge of this signal precisely closes an input sampling switch, reliably loading grayscale data from the target voltage drive level into a digital storage node to form a grayscale code to be converted. Then, based on the grayscale code, a decoding switch array is controlled to perform tap selection, connecting the precise corresponding potential in the reference voltage ladder to the non-inverting input of an operational amplifier. Finally, the potential difference between the zero-bias reference state and the feedback node is combined to maintain the synchronous potential of the pixel electrode, generating the final drive signal. This achieves seamless, high-precision conversion and stable maintenance from digital image data to the physical potential of the pixel electrode, ensuring that each pixel receives an accurate and bias-free drive voltage in complex dynamic scenes. It eliminates display defects caused by data sampling deviations or amplifier misalignment, restoring high-contrast edge image details while maintaining a high refresh rate, and improving the overall electromagnetic compatibility and ultimate display quality of the screen.

[0104] Optionally, the processes of steps 4041 to 4044 include: Step 4041: Based on the potential difference between the target reference potential and the feedback node connected to the inverting input of the operational amplifier, an analog pre-drive voltage consistent with the target reference potential is established at the feedback node through negative feedback adjustment of the operational amplifier.

[0105] Optionally, the inverting input of the operational amplifier is connected to a feedback node, which is the electrical connection point between the operational amplifier output and the inverting input. The display management device detects the potential difference between the target reference potential and the current potential of the feedback node. Based on this potential difference, the operational amplifier is controlled to perform negative feedback adjustment, that is, a mechanism that inverts a portion of the output signal and sends it back to the input through a feedback network to reduce input error. Under the action of negative feedback adjustment, the voltage at the output of the operational amplifier changes, thereby changing the potential of the feedback node, until the potential of the feedback node is completely equal to the target reference potential. At this time, an analog pre-drive voltage consistent with the target reference potential is established at the feedback node, that is, a stable analog voltage with the same amplitude as the target reference potential is formed at the feedback node after the operational amplifier has completed its internal adjustment.

[0106] For example, the target reference potentials connected to the non-inverting inputs of the operational amplifiers in columns 1 to 5 are 5, 2.5, 7.5, 10, and 0V, respectively. The potential difference between the target reference potential of each channel and the initial potential of its respective feedback node is detected, and the operational amplifiers in each channel are controlled to perform negative feedback adjustment. After adjustment, the feedback node potentials of the operational amplifiers in columns 1 to 5 stabilize at 5, 2.5, 7.5, 10, and 0V, respectively, thereby establishing an analog pre-drive voltage consistent with the target reference potential at the feedback node of each channel.

[0107] Step 4042: Generate a stable hold pulse of corresponding width based on the preset maximum setup time. During the effective period of the stable hold pulse, keep the output switches between all source data line output terminals and operational amplifier feedback nodes in the open state, so that the external source data line network is isolated and maintains a zero bias reference state.

[0108] Optionally, the display management device acquires a preset maximum setup time, which is the maximum allowable time required for the internal node potential of the operational amplifier to adjust from an initial state to a stable state. Based on this preset maximum setup time, a hold pulse with a corresponding time width is generated, which is a control signal used to indicate the time interval during which the internal potential of the operational amplifier is in a stable state. During the effective period of the hold pulse, i.e., the period during which the pulse is at a high level, the display management device keeps the output switches between all source data line output terminals and the operational amplifier feedback node open. The source data line output terminals are the physical output ports inside the source drivers that are connected to the external source data lines. The output switches are the switching devices that control the electrical connection between the internal nodes of the operational amplifier and the external source data lines, and are in the open state.

[0109] With the output switch off, the external source data line network—the physical data line set actually connected to the pixel electrodes inside the display screen—is physically isolated from the internal circuitry of the operational amplifier and is in an isolated state. In this isolated state, the external source data line network is unaffected by the internal adjustment process of the operational amplifier and continues to maintain a zero-bias reference state. The zero-bias reference state means that after DC balancing reset, the source data lines are in a stable voltage state with no residual DC bias. The stabilization hold pulse is used to define the potential stabilization window of the internal nodes of the operational amplifier, that is, the time range within which the internal potential is ensured to be completely stable before connecting to the external circuitry.

[0110] For example, assume the preset maximum settling time for each channel operational amplifier is 5ns. A stable hold pulse with a duration of 5ns is generated, assuming this pulse is validly high from 0ns to 5ns of the row scan cycle. During this valid 5ns period, the output switches between the source data line outputs of columns 1 to 5 and their respective operational amplifier feedback nodes are kept open. At this time, the external source data line networks of columns 1 to 5 are isolated from the operational amplifiers, maintaining a 6V zero-bias reference state, while the operational amplifiers internally achieve potential stabilization within the stabilization window.

[0111] Step 4043: Based on the end edge of the hold pulse, turn on the output switches of all source data lines, and instantaneously charge couple the analog pre-drive voltage with the external source data line network in the zero-bias reference state to start directional charge injection.

[0112] Optionally, the display management device detects the end edge of the hold pulse, i.e., the instant the hold pulse transitions from an effective high level to an ineffective low level. At this end edge, an on-control signal is output to turn on the output switches of all source data lines.

[0113] After the output switch is turned on, the stable analog pre-drive voltage at the operational amplifier feedback node is physically directly connected to the external source data line network, which is in a zero-bias reference state.

[0114] Because of the potential difference between the two, charge is instantaneously transferred between the analog pre-drive voltage source and the parasitic capacitance of the external source data line network. This process is called instantaneous charge coupling, which is the redistribution of charge that occurs when two capacitor networks with different potentials are connected.

[0115] Through instantaneous charge coupling, the operational amplifier begins to inject directional charge into the external source data line network. This is a process of providing a specific polarity and quantity of charge to the external network according to the direction and magnitude of the potential difference, thereby rapidly changing the potential of the external source data line network.

[0116] For example, the end edge of the hold pulse is at 5ns. At 5ns, the output switches of the source data lines from column 1 to column 5 are turned on. At this time, the analog pre-drive voltages of the operational amplifier feedback nodes of columns 1 to 5 are 5V, 2.5V, 7.5V, 10V, and 0V, respectively, while the external source data line network is at a zero-bias reference of 6V. After the output switches are turned on, instantaneous charge coupling occurs: the operational amplifiers of columns 1 and 2 inject negative charge into the external data lines; the operational amplifiers of columns 3 and 4 inject positive charge into the external data lines; and the operational amplifier of column 5 injects a large amount of negative charge into the external data lines. This initiates the directional charge injection process.

[0117] Step 4044: Based on the potential state after the charge injection process is completed, the output switch is kept on and the operational amplifier closed-loop feedback is maintained during the remaining time of the row scan cycle to combat leakage current and coupling noise, maintain the pixel electrode potential of the display screen constant, and obtain the final drive signal.

[0118] Optionally, the display management device monitors the charge injection process, and determines that the charge injection process is complete when the potential of the external source data line network reaches a potential state consistent with the simulated pre-drive voltage.

[0119] During the remaining time of the line scan cycle, which is the total time required to complete the scanning and charging of one line of pixels, the output switch is kept on, and the closed-loop feedback of the operational amplifier is maintained. That is, the operational amplifier output is kept connected to the inverting input and the negative feedback adjustment is continuously performed.

[0120] In closed-loop feedback mode, the operational amplifier can compensate for the potential decay caused by device leakage current on the external source data line network in real time. Device leakage current is the phenomenon of small current leakage in semiconductor devices when they are turned off. It can also suppress coupling noise generated by external electromagnetic interference. Coupling noise is the interference voltage induced on the data line by the external electromagnetic field.

[0121] Through this continuous dynamic compensation and suppression, the display management device maintains the constant potential of the display pixel electrodes, which are the transparent conductive electrodes in the liquid crystal panel that control the deflection of liquid crystal molecules, and obtains the final drive signal, which is the trigger control signal of the complete electrical signal used to control the display pixel electrodes to display the final image.

[0122] For example, assuming a total row scan cycle of 10 ns, the charge injection process is completed in the 7th ns. At this time, the potentials of the external source data lines in columns 1 to 5 are stable at 5, 2.5, 7.5, 10, and 0V, respectively. During the remaining time of the row scan cycle from the 7th to the 10th ns, the output switches of the source data lines in columns 1 to 5 are kept on, and the closed-loop feedback of each channel's operational amplifier is maintained. During this period, if the potential of the data line in column 3 shows a downward trend due to leakage current, its operational amplifier will immediately replenish positive charge through closed-loop feedback to maintain 7.5V; if the data line in column 2 is affected by coupling noise, its operational amplifier will also absorb or inject charge in real time to maintain 2.5V. All pixel electrode potentials remain constant, resulting in the final drive signal.

[0123] This invention utilizes the negative feedback adjustment of an operational amplifier to precisely establish an analog pre-drive voltage consistent with the target reference potential at the internal feedback node. A stable holding pulse is used to isolate the external source data line network during its effective period to ensure internal potential stability and maintain a zero-bias reference state externally. At the pulse's end edge, the output switch is instantaneously turned on, triggering instantaneous charge coupling between the analog pre-drive voltage and the external network to rapidly initiate directional charge injection. The output switch remains on and closed-loop feedback is maintained for the remainder of the horizontal scan cycle to counteract leakage current and coupling noise, thereby maintaining a constant pixel electrode potential and obtaining the final drive signal enable signal. This achieves a combination of high-precision internal voltage build-up and a pure initial external state. Instantaneous charge coupling significantly shortens the charging build-up time of large-capacitive data lines, and subsequent closed-loop feedback eliminates the influence of parasitic leakage current and electromagnetic interference on the pixel potential. This ensures that the pixel electrodes can obtain and maintain an absolutely accurate and stable drive voltage within an extremely short horizontal scan time, guaranteeing the display clarity and color accuracy of high-contrast edges in complex dynamic scenes, and achieving high electromagnetic compatibility and display image quality.

[0124] Furthermore, the display screen dynamic quality compensation device under electromagnetic interference provided by the present invention will be described below. The display screen dynamic quality compensation device under electromagnetic interference described below can be referred to in correspondence with the display screen dynamic quality compensation method under electromagnetic interference described above.

[0125] Optionally, refer to Figure 2 , Figure 2 This is a schematic diagram of the structure of the display screen dynamic quality compensation device under electromagnetic interference provided by the present invention. The display screen dynamic quality compensation device under electromagnetic interference includes: The passive charge blind injection module 210 is used to divide the source data lines into in-phase clusters based on the consistency of the gray-level jump direction of adjacent columns of pixels in the current frame image data, obtain the common-mode drive group enable signal, and perform passive charge blind injection on adjacent data line pairs based on the common-mode drive group enable signal to obtain a balanced pre-charge level.

[0126] The directional current injection module 220 is used to apply timing misalignment drive to the data lines in the common-mode drive group based on the balanced pre-charge level to obtain the staggered charging waveform of dispersed instantaneous current peaks, and to apply directional current injection to the output stage of the source driver based on the staggered charging waveform to obtain the target voltage drive level.

[0127] The DC balance reset module 230 is used to perform DC balance reset on the data line level during the inter-frame vertical blanking period based on the target voltage drive level to obtain a zero bias reference state.

[0128] The synchronization potential maintenance module 240 is used to maintain the synchronization potential of the display pixel electrodes based on the zero bias reference state and the target voltage drive to obtain the final drive signal.

[0129] The embodiments of the present invention improve the electromagnetic compatibility and display quality of the display screen in complex dynamic scenes.

[0130] Please see Figure 3 , Figure 3 An embodiment diagram of an electronic device provided in accordance with the present invention. For example... Figure 3 As shown, this embodiment of the invention provides an electronic device 300, including a memory 310, a processor 320, and a computer program 311 stored in the memory 310 and executable on the processor 320. When the processor 320 executes the computer program 311, it implements the processes of steps 10 to 40: Step 10: Based on the consistency of the grayscale transition direction of adjacent columns of pixels in the current frame image data, the source data lines are divided into in-phase clusters to obtain the common-mode drive group enable signal. Based on the common-mode drive group enable signal, passive charge blind injection is performed on adjacent data line pairs to obtain a balanced pre-charge level.

[0131] Step 20: Apply timing misalignment drive to the data lines in the common-mode drive group based on the balanced pre-charge level to obtain the staggered charging waveform that disperses the instantaneous current peaks, and apply directional current injection to the output stage of the source driver based on the staggered charging waveform to obtain the target voltage drive level.

[0132] Step 30: Perform DC balance reset on the data line level during the inter-frame vertical blanking period based on the target voltage drive level to obtain the zero bias reference state.

[0133] Step 40: Based on the zero bias reference state and the target voltage driving current, the display pixel electrodes are synchronously maintained to obtain the final driving signal.

[0134] Please see Figure 4 , Figure 4 An embodiment diagram of a computer-readable storage medium provided in accordance with an embodiment of the present invention is shown. Figure 4 As shown, this embodiment provides a computer-readable storage medium 400 on which a computer program 311 is stored. When the computer program 311 is executed by a processor, it implements the processes of steps 10 to 40. Step 10: Based on the consistency of the grayscale transition direction of adjacent columns of pixels in the current frame image data, the source data lines are divided into in-phase clusters to obtain the common-mode drive group enable signal. Based on the common-mode drive group enable signal, passive charge blind injection is performed on adjacent data line pairs to obtain a balanced pre-charge level.

[0135] Step 20: Apply timing misalignment drive to the data lines in the common-mode drive group based on the balanced pre-charge level to obtain the staggered charging waveform that disperses the instantaneous current peaks, and apply directional current injection to the output stage of the source driver based on the staggered charging waveform to obtain the target voltage drive level.

[0136] Step 30: Perform DC balance reset on the data line level during the inter-frame vertical blanking period based on the target voltage drive level to obtain the zero bias reference state.

[0137] Step 40: Based on the zero bias reference state and the target voltage driving current, the display pixel electrodes are synchronously maintained to obtain the final driving signal.

[0138] On the other hand, the present invention also provides a computer program product, which includes a computer program that can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can perform the dynamic compensation method for display screen image quality under electromagnetic interference provided by the above methods, which includes steps 10 to 40: Step 10: Based on the consistency of the grayscale transition direction of adjacent columns of pixels in the current frame image data, the source data lines are divided into in-phase clusters to obtain the common-mode drive group enable signal. Based on the common-mode drive group enable signal, passive charge blind injection is performed on adjacent data line pairs to obtain a balanced pre-charge level.

[0139] Step 20: Apply timing misalignment drive to the data lines in the common-mode drive group based on the balanced pre-charge level to obtain the staggered charging waveform that disperses the instantaneous current peaks, and apply directional current injection to the output stage of the source driver based on the staggered charging waveform to obtain the target voltage drive level.

[0140] Step 30: Perform DC balance reset on the data line level during the inter-frame vertical blanking period based on the target voltage drive level to obtain the zero bias reference state.

[0141] Step 40: Based on the zero bias reference state and the target voltage driving current, the display pixel electrodes are synchronously maintained to obtain the final driving signal.

[0142] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0143] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0144] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for dynamic compensation of display screen image quality under electromagnetic interference, characterized in that, include: Based on the consistency of the grayscale jump direction of adjacent columns of pixels in the current frame image data, the source data lines are divided into in-phase clusters to obtain the common mode drive group enable signal. Based on the common mode drive group enable signal, passive charge blind injection is performed on adjacent data line pairs to obtain a balanced pre-charge level. Based on the balanced pre-charge level, timing misalignment drive is applied to the data lines in the common-mode drive group to obtain a staggered charging waveform that disperses instantaneous current peaks. Based on the staggered charging waveform, directional current injection is applied to the output stage of the source driver to obtain the target voltage drive level. Based on the target voltage drive level, the data line level of the inter-frame vertical blanking period is DC balanced reset to obtain a zero bias reference state. Based on the zero-bias reference state and the target voltage driving electrode, the display pixel electrode is synchronously maintained to obtain the final driving signal.

2. The method for dynamic compensation of display screen image quality under electromagnetic interference according to claim 1, characterized in that, The steps for obtaining the final drive signal include: The line scan cycle counter is started at the rising edge of the horizontal synchronization signal to generate a video data window signal covering all pixel clock cycles of the current line. Based on the input sampling switch between the data latch of each channel and the digital bus in the source driver closed by the start edge of the video data window signal, the grayscale data in the target voltage driving level is loaded into the grayscale code to be converted in the digital storage node of each channel. Based on the grayscale code to be converted, the decoding switch array in each channel digital-to-analog converter is controlled to perform tap selection, and the corresponding potential in the reference voltage ladder is connected to the non-inverting input terminal of the operational amplifier; Based on the zero-bias reference state and the potential difference between the target reference potential and the feedback node connected to the inverting input of the operational amplifier, the display pixel electrodes are synchronously maintained to obtain the final driving signal.

3. The method for dynamic compensation of display screen image quality under electromagnetic interference according to claim 2, characterized in that, The process of maintaining the synchronous potential of the display pixel electrodes based on the zero-bias reference state and the potential difference between the target reference potential and the feedback node connected to the inverting input of the operational amplifier to obtain the final driving signal includes: Based on the potential difference between the target reference potential and the feedback node connected to the inverting input of the operational amplifier, an analog pre-drive voltage consistent with the target reference potential is established at the feedback node through negative feedback adjustment of the operational amplifier. A stabilization and hold pulse of corresponding width is generated based on a preset maximum setup time, and the output switches between all source data line output terminals and operational amplifier feedback nodes are kept in the open state during the effective period of the stabilization and hold pulse, so that the external source data line network is isolated and maintains a zero bias reference state; the stabilization and hold pulse is used to define the potential stabilization window of the internal nodes of the operational amplifier. Based on the end edge of the stabilized holding pulse, the output switches of all source data lines are turned on, and the analog pre-drive voltage is instantaneously charged-coupled with the external source data line network in the zero-bias reference state to start directional charge injection. Based on the potential state after the charge injection process is completed, the output switch is kept on and the operational amplifier closed-loop feedback is maintained during the remaining time of the row scan cycle to combat leakage current and coupling noise, maintain the constant pixel electrode potential of the display screen, and obtain the final driving signal.

4. The method for dynamic compensation of display screen image quality under electromagnetic interference according to claim 1, characterized in that, The step of performing passive charge blind injection on adjacent data line pairs based on the common-mode drive group enable signal to obtain a balanced pre-charge level includes: Based on the charge sharing transmission gate between adjacent data line pairs in the output stage of the source driver with a logic level of 1 in the common-mode drive group enable signal, a local charge connectivity network is obtained. Based on the local charge connectivity network, the isolation switches between each connected data line pair and its respective digital-to-analog converter output terminal are simultaneously cut off, so that the data line pair is in a floating interconnection state. Based on the parasitic capacitance of the adjacent data line pairs in the floating interconnection state, charge distribution is performed to obtain the intermediate shared voltage after potential equalization. Based on the polarity attribute latch of the intermediate shared voltage, the state of the corresponding polarity hold trigger is latched to obtain the polarity lock signal. Based on the polarity lock signal and the frame inversion control signal, an XOR logic operation is performed to obtain the phase consistency flag bit. The on / off state of the precharge phase switching switch is controlled based on the phase consistency flag bit to achieve polarity alignment of the precharge potential. The switch between the data line node and the local small-capacity holding capacitor is closed based on the polarity-aligned precharge potential to obtain the balanced precharge level.

5. The method for dynamic compensation of display screen image quality under electromagnetic interference according to any one of claims 1 to 4, characterized in that, The process of dividing the source data lines into in-phase clusters based on the consistency of grayscale transition directions of adjacent columns of pixels in the current frame image data to obtain the common-mode drive group enable signal includes: The sign bit is extracted based on the gray level of the current column pixel in the current row and the gray level of the next adjacent column pixel to obtain the sign bit sequence of the gray level difference between adjacent columns in the current row; A logical XOR operation is performed on the grayscale difference sign bit sequence of the adjacent columns of the current row and the grayscale difference sign bit sequence of the adjacent columns of the previous row to obtain the row breakpoint. An edge-triggered latch is then performed on the position where the logic level is 0 in the row breakpoint to obtain the in-phase cluster boundary index register group. Based on the column interval range of the in-phase cluster boundary index register group, the charge sharing switch matrix of the source driver is configured with path connectivity to obtain a static cluster topology. Based on the number of data lines in each connected cluster in the static cluster topology, the source data lines are divided into in-phase clusters to obtain the common-mode drive group enable signal.

6. The method for dynamic compensation of display screen image quality under electromagnetic interference according to claim 5, characterized in that, The process of dividing the source data lines into in-phase clusters based on the number of data lines in each connected cluster in the static cluster topology to obtain the common-mode drive group enable signal includes: Based on the number of data lines in each connected cluster in the static cluster topology, the parity count is performed to obtain the cluster drive mode selection bit. A logical AND operation is performed between the cluster drive mode selection bit and the phase polarity of the common-mode voltage source to obtain a unidirectional charge injection enable pulse; Based on the time window alignment of the unidirectional charge injection enable pulse and the row scan synchronization signal, the common mode drive activation window signal within the row cycle is obtained. Based on the common-mode drive activation window signal, the gate of the pre-charge switch of the source driver output stage is driven to obtain the common-mode drive group enable signal.

7. A device for dynamic compensation of display screen image quality under electromagnetic interference, characterized in that, A device for implementing the dynamic compensation method for display screen quality under electromagnetic interference as described in any one of claims 1 to 6; the dynamic compensation device for display screen quality under electromagnetic interference includes: The passive charge blind injection module is used to divide the source data lines into in-phase clusters based on the consistency of the gray-level jump direction of adjacent columns of pixels in the current frame image data, to obtain the common-mode drive group enable signal, and to perform passive charge blind injection on adjacent data line pairs based on the common-mode drive group enable signal to obtain a balanced pre-charge level. The directional current injection module is used to apply timing misalignment drive to the data lines in the common-mode drive group based on the balanced pre-charge level to obtain a staggered charging waveform that disperses instantaneous current peaks, and to apply directional current injection to the output stage of the source driver based on the staggered charging waveform to obtain the target voltage drive level. The DC balance reset module is used to perform DC balance reset on the data line level during the inter-frame vertical blanking period based on the target voltage drive level to obtain a zero bias reference state. The synchronization potential maintenance module is used to maintain the synchronization potential of the display pixel electrodes based on the zero bias reference state and the target voltage driving electrode to obtain the final driving signal.

8. An electronic device, comprising: Memory, used to store computer programs; A processor for reading and executing computer programs, characterized in that, when the processor executes the computer program, it implements the method for dynamic compensation of display screen image quality under electromagnetic interference as described in any one of claims 1 to 6.

9. A non-transitory computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements the method for dynamic compensation of display screen image quality under electromagnetic interference as described in any one of claims 1 to 6.

10. A computer program product, comprising a computer program, which, when executed by a processor, implements the method for dynamic compensation of display screen image quality under electromagnetic interference as described in any one of claims 1 to 6.

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