Gate driving circuit and display panel

Abstract

This application provides a gate driving circuit and a display panel. The gate driving circuit includes multiple gate driving units, each gate driving unit including a first pull-down sustaining circuit and a first voltage node. The first pull-down sustaining circuit includes a first switching circuit, a second switching circuit, and a pull-down switching circuit connected to the second voltage node. The first switching circuit is connected to a high-level trace, and the second switching circuit is connected to a low-level trace. Under the control of a first enable signal and a cascaded control signal, by ensuring that the first and second switching circuits are never simultaneously in a conducting state, the DC path from the high-level trace to the low-level trace is physically cut off. This significantly reduces circuit power consumption and heat generation, extends the battery life of mobile devices, and alleviates the problem of localized overheating in the display panel.

Description

Technical Field

[0001] This application belongs to the field of display panel technology, and particularly relates to a gate driving circuit and a display panel. Background Technology

[0002] Currently, the Gate Driver on Array (GOA) technology integrates the thin film transistor (TFT) in the gate driving circuit onto the array substrate to generate scanning signals to drive the pixel array.

[0003] In the gate drive circuit, the pull-down sustaining module is a crucial component. After the scan signal is output, the pull-down sustaining module typically pulls down the voltage levels of certain nodes in the gate drive circuit to release charge. Existing pull-down sustaining modules suffer from the problem of multiple transistors simultaneously conducting, causing direct connections between high-level and low-level traces connected to the module. This generates on-state current, increasing the overall power consumption and heat generation of the display panel. Summary of the Invention

[0004] The purpose of this application is to provide a gate driving circuit and a display panel, which aims to solve the problem of conduction current in the pull-down sustaining module in the conventional technology.

[0005] A first aspect of this application provides a gate driving circuit, comprising a plurality of gate driving units, each gate driving unit including a first pull-down sustaining circuit and a first voltage node; the first pull-down sustaining circuit is connected to the first voltage node; during a scanning phase, the first voltage node is at a high level; during a non-scanning phase, the first pull-down sustaining circuit is configured to set the level of the first voltage node to a low level according to a first enable signal and a cascaded control signal; the first pull-down sustaining circuit includes a first switching circuit, a second switching circuit, and a pull-down switching circuit connected to a second voltage node; the first switching circuit is configured to turn on the second voltage node when the first enable signal is received and the cascaded control signal is not received. The connection between the node and the high-level trace, and the disconnection between the second voltage node and the high-level trace upon receiving the first enable signal and the cascading control signal; the second switching circuit is used to connect the second voltage node and the low-level trace upon receiving the cascading control signal, and to disconnect the second voltage node and the low-level trace when the cascading control signal is not received; the pull-down switch circuit is used to connect the first voltage node and the low-level trace when the second voltage node is high, and to disconnect the first voltage node and the low-level trace when the second voltage node is low.

[0006] In one embodiment, the first switching circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor; a first terminal of the first transistor is connected to the high-level trace, a control terminal of the first transistor is connected to the first terminal of the first transistor, a second terminal of the first transistor is connected to the first terminal of the second transistor and the control terminal of the third transistor, a second terminal of the second transistor is connected to the low-level trace, the control terminal of the second transistor is used to receive the cascaded control signal, a second terminal of the third transistor is connected to the first terminal of the fourth transistor, a first terminal of the third transistor is connected to the high-level trace, a second terminal of the fourth transistor is connected to the second voltage node, and the control terminal of the fourth transistor is used to receive the first enable signal.

[0007] In one embodiment, the first switching circuit further includes a first capacitor, a first terminal of which is connected to a first terminal of the third transistor, and a second terminal of which is connected to a control terminal of the third transistor.

[0008] In one embodiment, the first switching circuit further includes a fifth transistor, the first terminal of which is connected to the control terminal of the third transistor, the second terminal of which is connected to the low-level trace, and the control terminal of the fifth transistor is used to receive a global reset signal.

[0009] In one embodiment, the first switching circuit further includes a sixth transistor, the first terminal of which is connected to the first terminal of the fourth transistor, the second terminal of which is connected to the low-level trace, and the control terminal of the sixth transistor is used to receive the cascaded control signal.

[0010] In one embodiment, the first switching circuit includes a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, and an eleventh transistor; the first terminal of the seventh transistor is used to receive a second enable signal, the second terminal of the seventh transistor is connected to the first terminal of the eighth transistor and the control terminal of the ninth transistor respectively, the control terminal of the seventh transistor is used to receive the cascaded control signal, the second terminal of the eighth transistor is connected to the high-level trace, and the control terminal of the eighth transistor is connected to the second terminal of the eighth transistor; the first terminal of the ninth transistor is used to receive the first enable signal, the second terminal of the ninth transistor is connected to the first terminal of the tenth transistor and the control terminal of the eleventh transistor respectively, the second terminal of the tenth transistor is connected to the low-level trace, the control terminal of the tenth transistor is used to receive the cascaded control signal, the first terminal of the eleventh transistor is connected to the high-level trace, and the second terminal of the eleventh transistor is connected to the second voltage node; the second enable signal is out of phase with the first enable signal.

[0011] In one embodiment, the second switching circuit includes a twelfth transistor, the first terminal of which is connected to the second voltage node, the second terminal of which is connected to the low-level trace, and the control terminal of which is used to receive the cascaded control signal.

[0012] In one embodiment, the second switching circuit is also connected to the first voltage node, and the second switching circuit is also used to connect the second voltage node and the low-level trace when the first voltage node is at a high level.

[0013] In one embodiment, the gate drive circuit further includes a second pull-down sustaining circuit, which is connected to the first voltage node. The second pull-down sustaining circuit is used to connect the first voltage node and the low-level trace when a second enable signal is received and the cascade control signal is not received, and to disconnect the connection between the first voltage node and the low-level trace when the cascade control signal is received.

[0014] In one embodiment, the gate driving circuit further includes a pull-up circuit and a driving switch circuit. Both the pull-up circuit and the driving switch circuit are connected to the first voltage node. The pull-up circuit is used to set the level of the first voltage node to a high level during the scanning phase according to the cascaded control signal. The driving switch circuit is used to generate and output a scanning signal when the level of the first voltage node is high.

[0015] A second aspect of this application provides a display panel including the gate driving circuit as described above, the display panel further including a pixel array, and the gate driving circuit being connected to the pixel array.

[0016] The beneficial effects of the present invention embodiment compared with the prior art are as follows: During the non-scanning stage, when the first switching circuit receives the first enable signal but does not receive the cascade control signal, the first switching circuit is turned on, pulling the second voltage node to a high level, thereby triggering the pull-down switch circuit to operate, so that the first voltage node is stably maintained at a low level, thereby effectively suppressing the potential drift and noise interference of the first voltage node, and improving the stability and reliability of the circuit in long-term operation.

[0017] During the scanning phase, the first switching circuit and the second switching circuit receive a cascaded control signal. The first switching circuit disconnects the connection between the second voltage node and the high-level trace, while the second switching circuit pulls the second voltage node to a low level, thereby turning off the pull-down switching circuit and ensuring that the first voltage node remains at a high level, so that the drive switching circuit can stably output the scanning signal.

[0018] By ensuring that the first and second switching circuits are never simultaneously on, the DC path from the high-level trace to the low-level trace is physically severed. This significantly reduces circuit power consumption and heat generation, extends the battery life of mobile devices, and alleviates localized overheating issues in the display panel. It also eliminates the stress impact of prolonged, continuous high-current short-circuit currents on the transistors in the first and second switching circuits, significantly mitigating threshold voltage drift and extending the lifespan of the entire gate drive circuit.

[0019] It eliminates the need for high on-resistance transistors to suppress short-circuit current, thus avoiding the gate drive capability degradation and signal delay issues associated with high on-resistance transistors. Attached Figure Description

[0020] Figure 1 A schematic diagram of a gate driving circuit provided in an embodiment of this application; Figure 2 A schematic diagram of the gate driving unit of the nth stage provided in an embodiment of this application; Figure 3 A detailed circuit diagram of the first pull-down sustaining circuit of the gate driving unit of the nth stage provided in an embodiment of this application; Figure 4 Another specific circuit diagram of the first pull-down sustaining circuit of the gate driving unit of the nth stage provided in an embodiment of this application; Figure 5 This is another schematic diagram of the gate driving unit of the nth stage provided in an embodiment of this application.

[0021] Specific element symbol explanations: 10, gate drive circuit; 20, gate drive unit; 100, pull-up circuit; 200, drive switch circuit; 300, first pull-down sustaining circuit; 310, first switch circuit; 320, second switch circuit; 330, pull-down switch circuit; 400, second pull-down sustaining circuit. Detailed Implementation

[0022] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0023] It should be noted that when a component is referred to as being "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0024] It should be understood that the terms "length", "width", "upper", "lower", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0025] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0026] Please see Figure 1 , Figure 1 A schematic diagram of the structure of the display panel provided in this embodiment is shown.

[0027] A gate driving circuit 10 includes multiple cascaded gate driving units 20. (See also...) Figure 2 , Figure 2 A schematic diagram of the nth-stage gate driving unit 20 provided in this embodiment is shown. At least one gate driving unit 20 includes a pull-up circuit 100, a drive switch circuit 200, a first pull-down sustaining circuit 300, and a first voltage node PU. For ease of explanation, the nth-stage gate driving unit 20 will be used as an example below.

[0028] Pull-up circuit 100, drive switch circuit 200 and first pull-down sustaining circuit 300 are all connected to the first voltage node PU. Pull-up circuit 100 is used to set the level of the first voltage node PU to high level during the scanning phase according to the cascaded control signal Tn-a. First pull-down sustaining circuit 300 is used to set the level of the first voltage node PU to low level during the non-scanning phase according to the first enable signal LC1. Drive switch circuit 200 is used to generate and output a scan signal when the level of the first voltage node PU is high.

[0029] The gate driving unit 20 is used to output a scan signal for one row of pixels. The scan signal drives the corresponding pixel unit to charge during the scanning phase and maintains a low level during the non-scanning phase to prevent crosstalk, thus achieving line-by-line scanning. During the non-scanning phase, each pixel unit maintains a stable light-emitting state based on its stored charge.

[0030] Each gate driving unit 20 is also used to output cascade control signals to realize cascade control. Specifically, the nth-stage gate driving circuit can generate the nth-stage cascade control signal Tn. The cascade control signal Tn-a received by the nth-stage gate driving unit 20 can be generated and output by the na-stage gate driving unit 20, where a is a positive integer. The specific value of a depends on the cascade delay requirements and circuit layout constraints, and a is usually 4 or 6. By transmitting the cascade control signal between each stage of the gate driving unit 20, the gate driving unit 20 can be triggered step by step without adding an additional clock signal, ensuring that the scanning signals corresponding to each row pixel unit are output sequentially according to the set timing, thus realizing line-by-line scanning.

[0031] The first enable signal LC1 can be generated by an independent control module or clock module, and the timing of the first enable signal is strictly synchronized with the scan cycle. In one embodiment, the first enable signal LC1 remains at a high level in both the scanning and non-scanning phases.

[0032] The first pull-down sustaining circuit 300 includes a first switching circuit 310, a second switching circuit 320, a pull-down switching circuit 330, and a second voltage node PD1. The first switching circuit 310, the second switching circuit 320, and the pull-down switching circuit 330 are all connected to the second voltage node PD1.

[0033] The first switching circuit 310 is used to connect the second voltage node PD1 to the high-level trace when the first enable signal LC1 is received but the cascade control signal Tn-a is not received, and to disconnect the second voltage node PD1 from the high-level trace when the first enable signal LC1 and the cascade control signal Tn-a are received.

[0034] The second switching circuit 320 is used to connect the second voltage node PD1 to the low-level trace when the cascading control signal Tn-a is received, and to disconnect the second voltage node PD1 from the low-level trace when the cascading control signal Tn-a is not received.

[0035] The pull-down switch circuit 330 is used to connect the first voltage node PU and the low-level trace when the second voltage node PD1 is high, and to disconnect the first voltage node PU and the low-level trace when the second voltage node PD1 is low.

[0036] The high-level trace is used to transmit the high-level signal VGH, and the low-level trace is used to transmit the low-level signal VSS.

[0037] It is understandable that receiving the first enable signal LC1 specifically means that the level of the first enable signal LC1 is in an active state, i.e., high level or low level (depending on the circuit logic design), and receiving the cascade control signal Tn-a specifically means that the level of the cascade control signal Tn-a is in an active state, i.e., high level or low level.

[0038] In some embodiments, the first enable signal LC1 and the cascade control signal Tn-a are both active high-level signals.

[0039] During the non-scanning phase, neither the pull-up circuit 100 nor the first pull-down sustaining circuit 300 receives the cascaded control signal Tn-a. When the first switching circuit 310 receives the first enable signal LC1, the first switching circuit 310 turns on, pulling the second voltage node PD1 to a high level, thereby triggering the pull-down switching circuit 330 to operate, so that the first voltage node PU is stably maintained at a low level, thereby effectively suppressing the potential drift and noise interference of the first voltage node PU, and improving the stability and reliability of the circuit during long-term operation.

[0040] During the scanning phase, the pull-up circuit 100 receives the cascaded control signal Tn-a, causing the potential of the first voltage node PU to rapidly rise to a high level. Simultaneously, the first switch circuit 310 and the second switch circuit 320 receive the cascaded control signal Tn-a. The first switch circuit 310 disconnects the connection between the second voltage node PD1 and the high-level trace, while the second switch circuit 320 pulls the second voltage node PD1 to a low level, thereby turning off the pull-down switch circuit 330. This ensures that the first voltage node PU remains at a high level, allowing the drive switch circuit 200 to stably output the scanning signal.

[0041] By ensuring that the first switching circuit 310 and the second switching circuit 320 are not simultaneously in a conducting state, the DC path from the high-level trace to the low-level trace is physically cut off. This significantly reduces circuit power consumption and heat generation, extends the battery life of mobile devices, and alleviates the problem of localized overheating of the display panel. It also eliminates the stress impact of prolonged, continuous high-current short-circuit current on the transistors in the first switching circuit 310 and the second switching circuit 320, significantly slowing down their threshold voltage drift and extending the lifespan of the entire gate drive circuit 10.

[0042] It eliminates the need for high on-resistance transistors to suppress short-circuit current, thus avoiding the gate drive capability degradation and signal delay issues associated with high on-resistance transistors.

[0043] Please see Figure 3 , Figure 3 A detailed circuit diagram of the first pull-down sustaining circuit 300 of the nth stage gate drive unit 20 provided in this embodiment is shown.

[0044] In one embodiment, the first switching circuit 310 includes a first transistor M1, a second transistor M2, a third transistor M3, and a fourth transistor M4.

[0045] The first terminal of the first transistor M1 is connected to a high-level trace. The control terminal of the first transistor M1 is connected to the first terminal of the first transistor M1. The second terminal of the first transistor M1 is connected to the first terminal of the second transistor M2 and the control terminal of the third transistor M3, respectively. The second terminal of the second transistor M2 is connected to a low-level trace. The control terminal of the second transistor M2 is used to receive the cascade control signal Tn-a. The second terminal of the third transistor M3 is connected to the first terminal of the fourth transistor M4. The first terminal of the third transistor M3 is connected to a high-level trace. The second terminal of the fourth transistor M4 is connected to the second voltage node PD1. The control terminal of the fourth transistor M4 is used to receive the first enable signal LC1.

[0046] Specifically, the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 can be N-type thin-film transistors. The first terminals of the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 are all the drains of the transistors, the control terminals of the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 are all the gates of the transistors, and the second terminals of the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 are all the sources of the transistors.

[0047] When the control terminal of the second transistor M2 does not receive the cascaded control signal Tn-a, the second transistor M2 is turned off, and node A is pulled up to a high level by the first transistor M1. This causes the third transistor M3 to be fully turned on, thereby transmitting the high level to the drain of the fourth transistor M4. At this time, if the first enable signal LC1 turns on the fourth transistor M4, the fourth transistor M4 will successfully pull up the second voltage node PD1.

[0048] When the control terminal of the second transistor M2 receives the cascaded control signal Tn-a, the cascaded control signal Tn-a turns on the second transistor M2, quickly pulling down the voltage at the control terminal of the third transistor M3, causing the third transistor M3 to be completely turned off, thus cutting off the power path from the high-level trace to the fourth transistor M4. Even if the first enable signal LC1 turns on the fourth transistor M4 and the second switching circuit 320 connects the second voltage node PD1 to the low-level trace, no current will flow from the high-level trace to the low-level trace, thereby preventing a shoot-through between the high-level trace and the low-level trace.

[0049] In one embodiment, please refer to Figure 3The first switching circuit 310 also includes a first capacitor C1, the first end of the first capacitor C1 is connected to the second end of the third transistor M3, and the second end of the first capacitor C1 is connected to the control terminal of the third transistor M3.

[0050] After the scanning phase ends, the circuit enters the non-scanning phase. The voltage at the control terminal of the third transistor M3 is pulled up by the first transistor M1, and the third transistor M3 begins to conduct. As the potential at the second terminal of the third transistor M3 gradually rises, the first capacitor C1, through coupling effect, actively raises the potential at the control terminal of the third transistor M3, forming a positive feedback bootstrap process. This makes the gate-source voltage of the third transistor M3 equal to the voltage of the high-level signal VGH, which is much greater than the conduction threshold of the third transistor M3. The third transistor M3 enters the deep linear region to operate, realizing the lossless transmission of the high-level signal VGH.

[0051] The first capacitor C1 effectively compensates for the voltage drop caused by the threshold voltage loss and on-resistance of the third transistor M3, achieving near-lossless voltage transmission from the high-level trace to the first terminal of the fourth transistor M4. This makes the maintenance of the high level of the second voltage node PD1 closer to the ideal value, thereby reducing the on-resistance of the pull-down switch circuit 330, enhancing its ability to maintain the low level of the first voltage node PU and the scan signal, and improving its noise immunity.

[0052] In one embodiment, please refer to Figure 3 The first switching circuit 310 also includes a fifth transistor M5. The first terminal of the fifth transistor M5 is connected to the control terminal of the third transistor M3, and the second terminal of the fifth transistor M5 is connected to a low-level trace. The control terminal of the fifth transistor M5 is used to receive the global reset signal CLR.

[0053] At the end of each frame's charging or working cycle, or in abnormal situations such as the display device, including the gate drive unit 20, being abnormally powered off, the high pulse of the global reset signal CLR controls the fifth transistor M5 to turn on, completely discharging the residual charge at the control terminal of the third transistor M3. This prevents the control terminal of the third transistor M3 from remaining in a high-level floating state for a long time, thus preventing problems such as false triggering or conduction threshold drift caused by charge accumulation.

[0054] Specifically, the fifth transistor M5 can be an N-type thin-film transistor. The first terminal of the fifth transistor M5 is the drain of the transistor, the control terminal of the fifth transistor M5 is the gate of the transistor, and the second terminal of the fifth transistor M5 is the source of the transistor.

[0055] In one embodiment, please refer to Figure 3The first switching circuit 310 also includes a sixth transistor M6. The first terminal of the sixth transistor M6 is connected to the first terminal of the fourth transistor M4, the second terminal of the sixth transistor M6 is connected to a low-level trace, and the control terminal of the sixth transistor M6 is used to receive the cascaded control signal Tn-a.

[0056] When the cascade control signal Tn-a is high, the third transistor M3 is turned off, disconnecting the high-level trace from the fourth transistor M4. Simultaneously, the sixth transistor M6 is turned on, actively pulling the voltage at the first terminal of the fourth transistor M4 down to a low level, ensuring that the second voltage node PD1 is reliably maintained at a low level, thus improving the level stability of the second voltage node PD1 during the non-scanning phase.

[0057] Specifically, the sixth transistor M6 can be an N-type thin-film transistor. The first terminal of the sixth transistor M6 is the drain of the transistor, the control terminal of the sixth transistor M6 is the gate of the transistor, and the second terminal of the sixth transistor M6 is the source of the transistor.

[0058] Please see Figure 4 , Figure 4 Another specific circuit diagram of the first pull-down sustaining circuit 300 of the nth stage gate drive unit 20 provided in this embodiment is shown.

[0059] In one embodiment, the first switching circuit 310 includes a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, and an eleventh transistor M11.

[0060] The first terminal of the seventh transistor M7 is used to receive the second enable signal LC2. The second terminal of the seventh transistor M7 is connected to the second terminal of the eighth transistor M8 and the control terminal of the ninth transistor M9, respectively. The control terminal of the seventh transistor M7 is used to receive the cascaded control signal Tn-a. The first terminal of the eighth transistor M8 is connected to the high-level trace. The control terminal of the eighth transistor M8 is connected to the first terminal of the eighth transistor M8.

[0061] The first terminal of the ninth transistor M9 is used to receive the first enable signal LC1. The second terminal of the ninth transistor M9 is connected to the first terminal of the tenth transistor M10 and the control terminal of the eleventh transistor M11. The second terminal of the tenth transistor M10 is connected to the low-level trace. The control terminal of the tenth transistor M10 is used to receive the cascade control signal Tn-a. The first terminal of the eleventh transistor M11 is connected to the high-level trace. The second terminal of the eleventh transistor M11 is connected to the second voltage node PD1.

[0062] The second enable signal LC2 is out of phase with the first enable signal LC1. Specifically, when one enable signal is high, the other enable signal is low.

[0063] Specifically, the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, and the eleventh transistor M11 can be N-type thin-film transistors. The first terminal of each of these transistors is the drain, the control terminal is the gate, and the second terminal is the source.

[0064] Since the second enable signal LC2 is out of phase with the first enable signal LC1, the second enable signal LC2 is at a low level when the first enable signal LC1 is at a high level.

[0065] Without receiving the cascade control signal Tn-a, the seventh transistor M7 and the tenth transistor M10 are turned off, the control terminal of the ninth transistor M9 is pulled up to a high level by the eighth transistor M8, and the ninth transistor M9 and the eleventh transistor M11 are turned on in sequence, thereby pulling the second voltage node PD1 to a high level.

[0066] Upon receiving the cascaded control signal Tn-a, the seventh transistor M7 and the tenth transistor M10 are turned on. The control terminal of the ninth transistor M9 is pulled down to a low level by the seventh transistor M7, and the ninth transistor M9 is turned off. At the same time, the turned-on tenth transistor M10 pulls down the control terminal of the eleventh transistor M11 to a low level, and the eleventh transistor M11 is turned off. The second voltage node PD1 is disconnected from the high-level trace.

[0067] In this embodiment, the eleventh transistor M11 is turned off by actively pulling down and latching the potential of the control terminal of the eleventh transistor M11. The interlocking logic composed of the ninth transistor M9 and the tenth transistor M10, etc., has stronger immunity to changes in the control signal, and the impact of a single control signal potential fluctuation is smaller.

[0068] In one embodiment, please refer to Figure 3 , Figure 4 The second switching circuit 320 includes a twelfth transistor M12. The first terminal of the twelfth transistor M12 is connected to the second voltage node PD1, and the second terminal of the twelfth transistor M12 is connected to the low-level trace. The control terminal of the twelfth transistor M12 is used to receive the cascaded control signal Tn-a.

[0069] When the cascading control signal Tn-a is received, the twelfth transistor M12 turns on, pulling the second voltage node PD1 down to a low level. When the cascading control signal Tn-a is not received, the twelfth transistor M12 turns off, and the voltage of the second voltage node PD1 is controlled by the first switching circuit 310.

[0070] In one embodiment, the second switching circuit 320 is also connected to the first voltage node PU, and the second switching circuit 320 is also used to connect the second voltage node PD1 and the low-level trace when the first voltage node PU is at a high level.

[0071] Specifically, the second switching circuit 320 also includes a thirteenth transistor M13. The first terminal of the thirteenth transistor M13 is connected to the second voltage node PD1, the second terminal of the thirteenth transistor M13 is connected to the low-level trace, and the control terminal of the thirteenth transistor M13 is connected to the first voltage node PU. When the first voltage node PU is at a high level, thereby controlling the thirteenth transistor M13 to conduct, the thirteenth transistor M13 stably pulls the second voltage node PD1 down to a low level, forming a redundant pull-down path with the twelfth transistor M12, thus improving the stability of maintaining the low level.

[0072] The second switching circuit 320 also includes a fourteenth transistor M14. The first terminal of the fourteenth transistor M14 is connected to the second voltage node PD1, and the second terminal of the fourteenth transistor M14 is connected to a low-level trace. The control terminal of the fourteenth transistor M14 is used to receive the second enable signal LC2. When the second enable signal LC2 is high, the first enable signal LC1 is low. At this time, the fourteenth transistor M14 is turned on, thereby stabilizing the second voltage node PD1 at a low level, ensuring that the second voltage node PD1 can still maintain a stable low-level state when the cascaded control signal Tn-a fails.

[0073] Specifically, the pull-down switch circuit 330 includes multiple transistors, the control terminal of each transistor is connected to the second voltage node PD1, the first terminal of each transistor is connected to different voltage nodes (for example, the first terminal of one transistor can be connected to the first voltage node PU), and the second terminal of each transistor is connected to a low-level trace.

[0074] It is understandable that the number of transistors in the pull-down switch circuit 330 and the connection method of each transistor can be adapted according to actual process requirements and circuit performance targets.

[0075] Please see Figure 5 , Figure 5 Another schematic diagram of the nth stage gate drive unit 20 provided in this embodiment is shown.

[0076] In one embodiment, the gate driving unit 20 further includes a second pull-down sustaining circuit 400, which is connected to the first voltage node PU. The second pull-down sustaining circuit 400 is used to connect the first voltage node PU to the low-level trace when a second enable signal LC2 is received and a cascading control signal Tn-a is not received, and to disconnect the first voltage node PU from the low-level trace when the cascading control signal Tn-a is received.

[0077] When the second enable signal LC2 is out of phase with the first enable signal LC1, the second pull-down sustaining circuit 400 can work alternately with the first pull-down sustaining circuit 300, ensuring that the two sets of pull-down sustaining circuits are in a non-working state for 50% of the time, effectively alleviating the problem of threshold voltage drift of transistors caused by long-term continuous application of bias voltage.

[0078] It is understandable that the specific circuit structure of the second pull-down sustaining circuit 400 can adopt a circuit structure symmetrical to that of the first pull-down sustaining circuit 300. The difference between the second pull-down sustaining circuit 400 and the first pull-down sustaining circuit 300 is that the control terminal of the second pull-down sustaining circuit 400 receives the second enable signal LC2, while the control terminal of the first pull-down sustaining circuit 300 receives the first enable signal LC1. The second enable signal LC2 is out of phase with the first enable signal LC1, thereby ensuring that at least one set of pull-down sustaining circuits is in an effective working state at any time.

[0079] Furthermore, to better implement the gate driving circuit 10 in any of the above embodiments, based on the gate driving circuit 10, this application embodiment also provides a display panel, which includes a pixel array and the gate driving circuit 10 described above. The gate driving circuit 10 is connected to the pixel array. The gate driving circuit 10 can provide scanning signals to each row of pixel units in the pixel array in a timing sequence, thereby ensuring that each pixel unit completes data writing and retention under precise timing.

[0080] The display panel can specifically be an LCD panel.

[0081] The pixel array includes multiple pixel units, and each gate driving unit 20 is connected to each row of scan lines in the pixel array in a one-to-one correspondence, for outputting scan signals row by row, so as to realize precise control of the charging and discharging process of each sub-pixel row by row.

[0082] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0083] The basic concepts have been described above. Obviously, for those skilled in the art, the detailed disclosure above is merely illustrative and does not constitute a limitation of this application. Although not explicitly stated herein, those skilled in the art may make various modifications, improvements, and corrections to this application. Such modifications, improvements, and corrections are suggested in this application, and therefore remain within the spirit and scope of the exemplary embodiments of this application.

[0084] Furthermore, this application uses specific terms to describe embodiments of the application. For example, "an embodiment," "one embodiment," and / or "some embodiments" refer to a particular feature, structure, or characteristic associated with at least one embodiment of the application. Therefore, it should be emphasized and noted that "an embodiment," "one embodiment," or "an alternative embodiment" mentioned twice or more in different locations in this specification do not necessarily refer to the same embodiment. In addition, certain features, structures, or characteristics in one or more embodiments of the application can be appropriately combined.

[0085] Similarly, it should be noted that, in order to simplify the description of the present application and thus aid in the understanding of one or more embodiments of the invention, the foregoing description of the embodiments of the present application sometimes combines multiple features into a single embodiment, drawing, or description thereof. However, this disclosure method does not imply that the subject matter of the application requires more features than those mentioned in the claims. In fact, the embodiments contain fewer features than all the features of the single embodiments disclosed above.

[0086] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A gate driving circuit, characterized in that, The gate driving circuit includes a plurality of gate driving units, and the gate driving unit includes a first pull-down sustaining circuit and a first voltage node; The first pull-down sustaining circuit is connected to the first voltage node; during the non-scanning phase, the first pull-down sustaining circuit is used to set the level of the first voltage node to low level according to the first enable signal and the cascaded control signal. The first pull-down sustaining circuit includes a first switching circuit, a second switching circuit, and a pull-down switch circuit connected to the second voltage node; The first switching circuit is used to connect the second voltage node and the high-level trace when the first enable signal is received and the cascade control signal is not received, and to disconnect the connection between the second voltage node and the high-level trace when the first enable signal and the cascade control signal are received. The second switching circuit is used to connect the second voltage node and the low-level trace when the cascade control signal is received, and to disconnect the connection between the second voltage node and the low-level trace when the cascade control signal is not received. The pull-down switch circuit is used to connect the first voltage node and the low-level trace when the second voltage node is at a high level, and to disconnect the first voltage node and the low-level trace when the second voltage node is at a low level.

2. The gate driving circuit according to claim 1, characterized in that, The first switching circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor; The first terminal of the first transistor is connected to the high-level trace, the control terminal of the first transistor is connected to the first terminal of the first transistor, the second terminal of the first transistor is connected to the first terminal of the second transistor and the control terminal of the third transistor, the second terminal of the second transistor is connected to the low-level trace, the control terminal of the second transistor is used to receive the cascaded control signal, the second terminal of the third transistor is connected to the first terminal of the fourth transistor, the first terminal of the third transistor is connected to the high-level trace, the second terminal of the fourth transistor is connected to the second voltage node, and the control terminal of the fourth transistor is used to receive the first enable signal.

3. The gate driving circuit according to claim 2, characterized in that, The first switching circuit further includes a first capacitor, the first end of which is connected to the first end of the third transistor, and the second end of which is connected to the control terminal of the third transistor.

4. The gate driving circuit according to claim 2, characterized in that, The first switching circuit further includes a fifth transistor, the first terminal of which is connected to the control terminal of the third transistor, and the second terminal of which is connected to the low-level trace. The control terminal of the fifth transistor is used to receive a global reset signal.

5. The gate driving circuit according to claim 2, characterized in that, The first switching circuit further includes a sixth transistor, the first terminal of which is connected to the first terminal of the fourth transistor, the second terminal of which is connected to the low-level trace, and the control terminal of the sixth transistor is used to receive the cascaded control signal.

6. The gate driving circuit according to claim 1, characterized in that, The first switching circuit includes a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, and an eleventh transistor; The first terminal of the seventh transistor is used to receive the second enable signal. The second terminal of the seventh transistor is connected to the second terminal of the eighth transistor and the control terminal of the ninth transistor, respectively. The control terminal of the seventh transistor is used to receive the cascaded control signal. The first terminal of the eighth transistor is connected to the high-level trace. The control terminal of the eighth transistor is connected to the first terminal of the eighth transistor. The first terminal of the ninth transistor is used to receive the first enable signal. The second terminal of the ninth transistor is connected to the first terminal of the tenth transistor and the control terminal of the eleventh transistor. The second terminal of the tenth transistor is connected to the low-level trace. The control terminal of the tenth transistor is used to receive the cascaded control signal. The first terminal of the eleventh transistor is connected to the high-level trace. The second terminal of the eleventh transistor is connected to the second voltage node. The second enable signal is out of phase with the first enable signal.

7. The gate driving circuit according to any one of claims 1 to 6, characterized in that, The second switching circuit includes a twelfth transistor, the first terminal of which is connected to the second voltage node, the second terminal of which is connected to the low-level trace, and the control terminal of which is used to receive the cascaded control signal. The second switching circuit is also connected to the first voltage node and is also used to connect the second voltage node and the low-level trace when the first voltage node is at a high level.

8. The gate driving circuit according to any one of claims 1 to 6, characterized in that, The gate drive circuit further includes a second pull-down sustaining circuit, which is connected to the first voltage node. The second pull-down sustaining circuit is used to connect the first voltage node and the low-level trace when a second enable signal is received and the cascade control signal is not received, and to disconnect the connection between the first voltage node and the low-level trace when the cascade control signal is received.

9. The gate driving circuit according to any one of claims 1 to 6, characterized in that, The gate driving circuit further includes a pull-up circuit and a drive switch circuit. Both the pull-up circuit and the drive switch circuit are connected to the first voltage node. The pull-up circuit is used to set the level of the first voltage node to a high level during the scanning phase according to the cascade control signal. The drive switch circuit is used to output a scanning signal when the level of the first voltage node is high.

10. A display panel, characterized in that, Including the gate driving circuit as described in claim 9, the display panel further includes a pixel array, and the gate driving circuit is connected to the pixel array.

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