A low-power buffer circuit suitable for LCD driving

Abstract

This invention discloses a low-power buffer circuit suitable for LCD driving. By setting up a current mirror unit containing a current mirror unit with a specific ratio, an output driving transistor with a negative feedback mechanism, and a buck and strong absorption branch composed of a fourth NMOS transistor and a tenth PMOS transistor, the circuit ensures that both the tenth NMOS transistor and the tenth PMOS transistor are in the subthreshold region during static operation, thereby controlling the total static power consumption current to an extremely low level. During dynamic operation, the negative feedback mechanism of the ninth NMOS transistor is used to increase its gate-source voltage difference to provide a large output current, and the change in the drain potential of the fourth NMOS transistor automatically drives the tenth PMOS transistor from the subthreshold region to the saturation region to provide a strong absorption current capability. Thus, without the need for additional complex control circuits, a perfect balance between low power consumption and large driving capability (including fast charging and strong absorption) is achieved, effectively solving the contradiction between high static power consumption and insufficient dynamic driving capability in the prior art.

Description

Technical Field

[0001] This invention relates to the field of LCD driver chip technology, and more specifically to a low-power buffer circuit suitable for LCD driving. Background Technology

[0002] Currently, most LCD driver chips on the market use a CLASS AB circuit architecture for their driver buffers. The specific circuit structure is as follows: Figure 1 As shown in the diagram, in this architecture, the PMOS transistor MPD has output current capability, and the NMOS transistor MND has current sink capability, giving it both strong output and current sink capabilities. This allows it to adapt to the voltage switching characteristics of the LCD screen's COM / SEG lines, achieving rapid voltage conversion. However, the CLASS AB architecture is complex and consumes a lot of power, making it unsuitable for driving low-power, battery-powered LCD screens. The total power consumption of the buffer circuit in this architecture is... This can be expressed as (where Ibias is the input bias current and Iset is the quiescent current of the output transistors MPD / MND):

[0003] (1)

[0004] When the total power consumption current of the buffer is required to be less than 1uA, The value should be set below 100nA. Such a small bias current will cause the stability of the CLASS AB circuit to decrease, and the DC operating point of the bias circuit will be easily disturbed, which will in turn cause disturbances in the buffer voltage output and affect the display effect of the LCD screen.

[0005] Since the LCD driver buffer needs to have the ability to both absorb and output current, traditional solutions usually adopt the CLASSAB circuit architecture. However, this architecture has the problems of circuit complexity and high power consumption, which is not conducive to the application of battery-powered LCD driver chips. Summary of the Invention

[0006] The present invention aims to provide a low-power buffer circuit suitable for LCD driving, which realizes low-power LCD driving with a simple low-power driving buffer circuit, ensuring stable driving while achieving the goal of low power consumption, and is beneficial for LCD driver chips that are powered by batteries for a long time.

[0007] To achieve the above objectives, the technical solution adopted by the present invention is: a low-power buffer circuit suitable for LCD driving, comprising:

[0008] The current mirror unit includes a first NMOS transistor MN0, a second NMOS transistor MN1, a third NMOS transistor MN2, and a fourth NMOS transistor MN3. The gate terminals of the first NMOS transistor MN0, the second NMOS transistor MN1, the third NMOS transistor MN2, and the fourth NMOS transistor MN3 are interconnected and all connected to the drain terminal of the first NMOS transistor MN0. The drain terminal of the first NMOS transistor MN0 is connected to an externally input current source.

[0009] The input stage includes a fifth NMOS transistor MN4 and a sixth NMOS transistor MN5. The drain of the second NMOS transistor MN1 is connected to the source of the fifth NMOS transistor MN4 and the sixth NMOS transistor MN5, respectively. The gate of the sixth NMOS transistor MN5 serves as the input port of the buffer and is connected to the input voltage Vin.

[0010] The first PMOS current mirror includes a seventh NMOS transistor MP0 and an eighth NMOS transistor MP1. The drain of the seventh NMOS transistor MP0 is connected to the drain of the fifth NMOS transistor MN4. The source of the eighth NMOS transistor MP1 is connected to the power supply VCC. The gates of the seventh NMOS transistor MP0 and the eighth NMOS transistor MP1 are interconnected and both are connected to the drain of the seventh NMOS transistor MP0 to form a current mirror. The drain of the eighth NMOS transistor MP1 is connected to the drain of the sixth NMOS transistor MN5.

[0011] The output driver transistor is the ninth NMOS transistor MP2. The source of MP2 is connected to the power supply VCC, its gate is connected to the drain of the eighth NMOS transistor MP1, and its drain is connected to the drain of the third NMOS transistor MN2, serving as the output port Vout of the buffer; and...

[0012] The voltage reduction and strong absorption branch includes a tenth NMOS transistor MN6 and a tenth PMOS transistor MP3. The drain of the tenth NMOS transistor MN6 is connected to the power supply VCC, and its source is connected to the drain of the fourth NMOS transistor MN3 and to the gate of the tenth PMOS transistor MP3. The source of the tenth PMOS transistor MP3 is connected to the output port Vout, and its drain is connected to ground.

[0013] Preferably, the current ratio of the first NMOS transistor MN0, the second NMOS transistor MN1, the third NMOS transistor MN2, and the fourth NMOS transistor MN3 in the current mirror unit under normal operation is 1:2:1:1.

[0014] Preferably, both the tenth NMOS transistor MN6 and the tenth PMOS transistor MP3 are in the subthreshold region when the buffer is in static operation, so that the buffer neither outputs nor absorbs current. At this time, the voltage of the output port Vout is equal to the input voltage Vin.

[0015] Preferably, when the voltage at the output port Vout is less than the input voltage Vin, the ninth NMOS transistor MP2 increases its gate-source voltage difference through negative feedback, thereby providing an output current greater than the static value to charge the output port Vout to the input voltage Vin.

[0016] Preferably, when the voltage at the output port Vout is greater than the input voltage Vin, the tenth PMOS transistor MP3 enters the saturation region from the subthreshold region. As the difference between the output port Vout and the input voltage Vin increases, its channel width-to-length ratio corresponding to its current absorption capability increases, thereby providing a strong current absorption capability to absorb external current.

[0017] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0018] This invention achieves a perfect balance between low power consumption and high driving capability (including fast charging and strong absorption) without the need for additional complex control circuitry. It incorporates a current mirror unit with a specific ratio of current mirror units, an output drive transistor with a negative feedback mechanism, and a buck and strong absorption branch composed of a fourth NMOS transistor and a tenth PMOS transistor. This ensures that during static operation, both the tenth NMOS transistor and the tenth PMOS transistor are in the subthreshold region, thus keeping the total static power consumption extremely low. During dynamic operation, the negative feedback mechanism of the ninth NMOS transistor is used to increase its gate-source voltage difference to provide a large output current. Furthermore, the change in the drain potential of the fourth NMOS transistor automatically drives the tenth PMOS transistor from the subthreshold region into the saturation region to provide a strong current absorption capability. This effectively solves the contradiction between high static power consumption and insufficient dynamic driving capability in existing technologies, without requiring additional complex control circuitry. Attached Figure Description

[0019] Figure 1 This is a circuit architecture diagram of CLASS AB in the prior art;

[0020] Figure 2 This is a circuit diagram of the LCD driver buffer of the present invention;

[0021] Figure 3 This is a schematic diagram illustrating the voltage / current changes when the buffer dynamically outputs / absorbs current according to the present invention.

[0022] Figure 4 This is a schematic diagram of the LCD driving circuit structure and voltage changes during driving according to the present invention. Detailed Implementation

[0023] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0024] It should be noted that if the embodiments of the present invention involve directional indicators such as up, down, left, right, front, back, etc., the directional indicators are only used to explain the relative positional relationship and movement of the components in a specific posture. If the specific posture changes, the directional indicators will also change accordingly.

[0025] Furthermore, if the embodiments of this invention involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the use of "and / or" or "and / or" throughout the text includes three parallel solutions. For example, "A and / or B" includes solution A, solution B, or a solution where both A and B are satisfied simultaneously. Furthermore, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by this invention.

[0026] Please see Figure 2 This invention provides a low-power buffer circuit suitable for LCD driving, comprising:

[0027] The current mirror unit includes a first NMOS transistor MN0, a second NMOS transistor MN1, a third NMOS transistor MN2, and a fourth NMOS transistor MN3. Under normal operating conditions, the ratio of their current values ​​is 1:2:1:1. The gate terminals of the first NMOS transistor MN0, the second NMOS transistor MN1, the third NMOS transistor MN2, and the fourth NMOS transistor MN3 are interconnected and all connected to the drain terminal of the first NMOS transistor MN0. The drain terminal of the first NMOS transistor MN0 is connected to an externally input current source.

[0028] The input stage includes a fifth NMOS transistor MN4 and a sixth NMOS transistor MN5. The drain of the second NMOS transistor MN1 is connected to the source of the fifth NMOS transistor MN4 and the sixth NMOS transistor MN5, respectively. The gate of the sixth NMOS transistor MN5 serves as the input port of the buffer and is connected to the input voltage Vin.

[0029] The first PMOS current mirror includes a seventh NMOS transistor MP0 and an eighth NMOS transistor MP1. The drain of the seventh NMOS transistor MP0 is connected to the drain of the fifth NMOS transistor MN4. The source of the eighth NMOS transistor MP1 is connected to the power supply VCC. The gates of the seventh NMOS transistor MP0 and the eighth NMOS transistor MP1 are interconnected and both are connected to the drain of the seventh NMOS transistor MP0 to form a current mirror. The drain of the eighth NMOS transistor MP1 is connected to the drain of the sixth NMOS transistor MN5.

[0030] The output driver transistor is the ninth NMOS transistor MP2. The source of MP2 is connected to the power supply VCC, its gate is connected to the drain of the eighth NMOS transistor MP1, and its drain is connected to the drain of the third NMOS transistor MN2, serving as the output port Vout of the buffer; and...

[0031] The buck and strong absorption branch includes the tenth NMOS transistor MN6 and the tenth PMOS transistor MP3. The drain of the tenth NMOS transistor MN6 is connected to the power supply VCC, and its source is connected to the drain of the fourth NMOS transistor MN3 and then to the gate of the tenth PMOS transistor MP3. The source of the tenth PMOS transistor MP3 is connected to the output port Vout, and its drain is connected to ground.

[0032] When the buffer is in static operation, both the tenth NMOS transistor MN6 and the tenth PMOS transistor MP3 are in the subthreshold region, meaning the buffer neither outputs nor sinks current. At this time, the voltage at the output port Vout equals the input voltage Vin, i.e., Vout = Vin. Therefore:

[0033] (2)

[0034] Ibias is the quiescent current of MP2, Iset is the input bias current, and Isub>p is the quiescent current of MP3.

[0035] Both MN6 and MP3 are in the subthreshold region.

[0036] (3)

[0037] (k is Boltzmann constant, T is thermodynamic absolute temperature, q is electron charge), δ is subthreshold swing factor (between 1.2 and 1.8). VGSN6 is the gate-source voltage difference of MN6, which is a process-dependent reference current. Therefore, for a fixed-size MP3, the Iset it flows through is only related to VGSN6. By adjusting the size of MN6 and the magnitude of the current flowing through it, the size of VGSN6 can be changed, making the quiescent current Iset small. This reduces the quiescent current power consumption of the entire buffer while ensuring a large current sinking capability during dynamic operation (when the MOSFET MP3 enters the saturation region during dynamic operation). The total power consumption current I during quiescent operation is:

[0038] (4)

[0039] When the total power consumption current I of the buffer is required to be less than 1uA The value is also nearly 200nA, and because the buffer circuit designed in this paper has a simple structure (containing only a current mirror and an amplifier tube), even Even a current of less than 100nA can ensure the stability of the buffer circuit.

[0040] In this embodiment, there are two cases when the driving buffer circuit works dynamically (Vout is the voltage magnitude connected to the buffer, Vin is the voltage magnitude output by the buffer):

[0041] 1. When the drive buffer needs to supply power to external devices, when the voltage of the output port Vout is less than the input voltage Vin, i.e. Vout < Vin, all the output current is provided by the MOS transistor MP2. The ninth NMOS transistor MP2 increases its gate-source voltage difference through negative feedback, thereby providing an output current greater than the static value to charge the output port Vout to the input voltage Vin.

[0042] Specifically, drive output current The size is ( The magnitude of the current generated by the MP2 transistor. and Same as (4):

[0043] (5)

[0044] (6)

[0045] The electron mobility of the PMOS transistor. This refers to the gate oxide capacitance per unit area of ​​the MOSFET. VTHP2 is the channel width-to-length ratio of MOSFET MP2, and VTHP2 is the threshold voltage of MP2. This represents the gate-source voltage difference of MP2. Due to the effect of negative feedback, its value will increase to a much greater extent. At this value, the driving buffer has a strong output current capability, which can quickly charge Vout to Vin and then return to steady state. At this time, the operating state of the buffer circuit is the same as that of the buffer circuit in the CLASS AB architecture. The changes in voltage and current are as follows... Figure 3 As shown: at time t1, the buffer circuit starts charging Vout, and the buffer enters the dynamic output current mode. At time t2, Vout is charged to Vin, and the buffer returns from dynamic to static, and the charging is completed.

[0046] 2. When the drive buffer needs to absorb external current, i.e., Vout > Vin, the branches that absorb external current are I_sink1 and I_sink2, and I_sink2 absorbs the vast majority of the current. (This refers to the total absorption current). The tenth PMOS transistor, MP3, enters the saturation region from the subthreshold region. As the difference between the output port Vout and the input voltage Vin increases, its channel width-to-length ratio corresponding to its absorption current capability increases, thereby providing a strong absorption current capability to absorb external current, as detailed below:

[0047] (7)

[0048] (8)

[0049] VTHP3 is the channel width-to-length ratio of MOSFET MP3, and VTHP3 is the threshold voltage of MP3. This represents the gate-source voltage difference of the MP3 file. and Same as formula (6). At this point, since Vout is greater than Vin, It will decrease as the difference between Vout and Vin increases, while I_sink1 will almost remain at its original static size. When MOSFET MP3 enters the saturation region from the subthreshold region, I_sink2 will increase as the difference between Vout and Vin increases, until the difference between the two disappears, at which point it returns to the static state. Size. Without the I_sink2 branch, the current absorption capacity of this buffer is only ( The current value is very small and cannot meet the requirements for normal LCD driving. However, the addition of the I_sink2 branch gives this buffer circuit a similar current-absorbing capability to the CLASS AB architecture buffer circuit. The voltage and current changes during its dynamic current absorption process are as follows: Figure 3 As shown.

[0050] Specifically, ultra-low power wireless system-on-a-chip chips are generally powered by batteries. In order to ensure that the chip can work for a long time (more than ten years), its power consumption requirements are very high. Naturally, the power consumption requirements of the built-in LCD driver module are also very high. If the built-in LCD driver buffer circuit still adopts the CLASS AB architecture, it will be difficult to meet its low power consumption requirements.

[0051] The drive buffer circuit in this embodiment has a simple structure and ensures drive stability while meeting low power consumption requirements. It is very suitable for chips with built-in LCD drive controllers that are powered by batteries for extended periods. A schematic diagram of the circuit structure and voltage waveforms for implementing the LCD drive are shown below. Figure 4 As shown. In Figure 4 In this circuit, VH and VL are the driving bias voltages set for the LCD screen. They are sent to the VCOM and VSEG terminals of the LCD unit (which has a structure similar to a capacitor) through the buffer circuit and switches (S1~S4), respectively.

[0052] Assuming the LCD is lit when the voltage difference across its terminals equals (VH-VL), at time t1, VP is low and VN is high. Switches S1 and S4 are on, while switches S2 and S3 are off. The VSEG terminal of the LCD unit is biased to VH, and VCOM is biased to VL. At this time, the difference between (VSEG-VCOM) across the LCD unit is (VH-VL), and it is lit. At time t3, VP becomes high and VN becomes low. Switches S2 and S3 are on, while switches S1 and S4 are off. The VSEG terminal is biased to VL, and VCOM is biased to VH. At this time, the difference between (VSEG-VCOM) across the LCD unit becomes –(VH-VL), and it is still lit. This ensures that the LCD unit can be lit normally during this time period. If the LCD unit is to be kept lit, the voltage across its terminals must be flipped periodically in this way to ensure that the LCD unit is not damaged (determined by the characteristics of the liquid crystal molecules in the LCD screen).

[0053] In summary, by setting up a current mirror unit containing a specific ratio of current mirror units, an output drive transistor with a negative feedback mechanism, and a buck and strong absorption branch composed of a fourth NMOS transistor and a tenth PMOS transistor, the present invention ensures that when the circuit is in static operation, both the tenth NMOS transistor and the tenth PMOS transistor are in the subthreshold region, thereby controlling the total static power consumption current at an extremely low level.

[0054] During dynamic operation, the negative feedback mechanism of the ninth NMOS transistor is used to increase its gate-source voltage difference to provide a large output current, and the change in the drain potential of the fourth NMOS transistor is used to automatically drive the tenth PMOS transistor from the subthreshold region to the saturation region to provide a strong current absorption capability. Thus, without the need for additional complex control circuits, a perfect balance between low power consumption and large driving capability (including fast charging and strong absorption) is achieved, effectively solving the contradiction between high static power consumption and insufficient dynamic driving capability in the existing technology.

[0055] The above description is merely an exemplary embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural transformations made using the contents of the present invention specification and drawings under the technical concept of the present invention, or direct / indirect applications in other related technical fields, are included within the patent protection scope of the present invention.

Claims

1. A low-power buffer circuit suitable for LCD driving, characterized in that, include: A current mirror unit, comprising a first NMOS transistor MN0, a second NMOS transistor MN1, a third NMOS transistor MN2, and a fourth NMOS transistor MN3, wherein the gate terminals of the first NMOS transistor MN0, the second NMOS transistor MN1, the third NMOS transistor MN2, and the fourth NMOS transistor MN3 are interconnected and all are connected to the drain terminal of the first NMOS transistor MN0. The input stage includes a fifth NMOS transistor MN4 and a sixth NMOS transistor MN5, and the drain terminal of the second NMOS transistor MN1 is connected to the source terminals of the fifth NMOS transistor MN4 and the sixth NMOS transistor MN5, respectively. The first PMOS current mirror includes a seventh NMOS transistor MP0 and an eighth NMOS transistor MP1. The drain of the seventh NMOS transistor MP0 is connected to the drain of the fifth NMOS transistor MN4. The source of the eighth NMOS transistor MP1 is connected to the power supply VCC. The gates of the seventh NMOS transistor MP0 and the eighth NMOS transistor MP1 are interconnected and both are connected to the drain of the seventh NMOS transistor MP0 to form a current mirror. The output driver transistor is the ninth NMOS transistor MP2. The source of MP2 is connected to the power supply VCC, its gate is connected to the drain of the eighth NMOS transistor MP1, and its drain is connected to the drain of the third NMOS transistor MN2, serving as the output port Vout of the buffer; and... The voltage reduction and strong absorption branch includes a tenth NMOS transistor MN6 and a tenth PMOS transistor MP3. The drain of the tenth NMOS transistor MN6 is connected to the power supply VCC, and its source is connected to the drain of the fourth NMOS transistor MN3 and to the gate of the tenth PMOS transistor MP3.

2. The low-power buffer circuit suitable for LCD driving according to claim 1, characterized in that, The current ratio of the first NMOS transistor MN0, the second NMOS transistor MN1, the third NMOS transistor MN2, and the fourth NMOS transistor MN3 in the current mirror unit under normal operation is 1:2:1:

1.

3. A low-power buffer circuit suitable for LCD driving according to claim 1, characterized in that, When the buffer is in static operation, both the tenth NMOS transistor MN6 and the tenth PMOS transistor MP3 are in the subthreshold region, so that the buffer neither outputs nor absorbs current. At this time, the voltage of the output port Vout is equal to the input reference voltage Vin.

4. A low-power buffer circuit suitable for LCD driving according to claim 1, characterized in that, When the voltage at the output port Vout is less than the input reference voltage Vin, the ninth NMOS transistor MP2 increases its gate-source voltage difference through negative feedback, thereby providing an output current greater than the static value to charge the output port Vout to the input reference voltage Vin.

5. A low-power buffer circuit suitable for LCD driving according to claim 1, characterized in that, When the voltage at the output port Vout is greater than the input reference voltage Vin, the tenth PMOS transistor MP3 enters the saturation region from the subthreshold region. As the difference between the output port Vout and the input reference voltage Vin increases, its channel width-to-length ratio corresponding to its current absorption capability increases, thereby providing a strong current absorption capability to absorb external current.

6. A low-power buffer circuit suitable for LCD driving according to claim 1, characterized in that, The drain terminal of the first NMOS transistor MN0 is connected to an externally input current source.

7. A low-power buffer circuit suitable for LCD driving according to claim 1, characterized in that, The gate terminal of the sixth NMOS transistor MN5 is connected to the input voltage Vin as the input port of the buffer.

8. A low-power buffer circuit suitable for LCD driving according to claim 1, characterized in that, The drain of the eighth NMOS transistor MP1 is connected to the drain of the sixth NMOS transistor MN5.

9. A low-power buffer circuit suitable for LCD driving according to claim 1, characterized in that, The source terminal of the tenth PMOS transistor MP3 is connected to the output port Vout, and its drain terminal is connected to ground.

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